Data Sheet

AD1030
High Precision Analog Front End with TEC/PMIC

FEATURES APPLICATIONS
► Analog input and output ► Optical networking–100G/200G/400G or higher speed optical
► Multichannel, 12-bit, 1 MSPS ADC modules
► Up to 10 external channels
GENERAL DESCRIPTION
► Power, VDAC, IDAC, and temperature monitor internal
channels The AD1030 is an analog front end (AFE) that includes a high
► Single-ended and differential mode precision analog-to-digital converter (ADC), voltage output digital-
► 0 V to VREF analog input range to-analog converters (VDACs), current output digital-to-analog con-
verters (IDACs), thermoelectric cooler (TEC) controller, and analog
► Input buffer included
comparators.
► Digital comparators
► Nine, 12-bit voltage output DACs The ADC signal chain contains two analog comparator channels,
► 4-channel, selectable output range
10 external voltage inputs, VDAC voltage and current monitor
channels, IDAC voltage and current monitor channels, a precharge
► 0 V to 2.5 V or AVDD − 0.1
buffer, and a 1 MSPS successive approximation register (SAR)
► AVDDNEG + 0.2 or −2.5 V to −0 V ADC.
► 4-channel, 0 V to 2.5 V or AVDD − 0.2 V
The AD1030 provides four IDAC channels. These are low noise,
► 1-channel, 0 V to 2.5 V
low drift current sources with programmable full-scale output ranges
► Four low noise, 12-bit IDACs (50 mA, 100 mA, or 150 mA). Each IDAC channel has 12-bit
► Configurable output range: 50 mA, 100 mA, or 150 mA resolution.
► Fast shut down with external IDACDIS pin
There are 9×, 12-bit VDAC outputs. Four of these VDACs
► 2 voltage comparators with adjustable hysteresis voltage (Channel 0 to Channel 3) support either a positive voltage range of
► TEC controller 0 V to 2.5 V or a negative range from 0 V to –2.5 V. These ranges
► Optional buck or LDO regulator mode if not using TEC can be extended to 0 V to AVDD and 0 V to AVDDNEG.
► Maximum heating and cooling current: 1.3 A
Channel 4 to Channel 7 of the VDACs support a positive voltage
► Current and voltage monitoring and protection range of 0 V to 2.5 V. VDAC Channel 8 supports a positive voltage
► Over 90% efficient range of 0 V to 2.5 V. Optionally, Channel 4 to Channel 7 of the
► Soft start function VDACs can support an output range of 0 V to AVDD.
► Digital Interface The AD1030 also integrates a TEC controller with a heating and
► 1× SPI, 3.3 V, 40 MHz cooling current up to 1.3 A, is over 90% efficient, and supports a
► 1× I2C, 3.3 V, 100 kHz, 400 kHz, and 1 MHz soft start function.
► 14x GPIO shared with analog input and output Use the 4-wire serial port interface (SPI) for up to 40 MHz or the
► Power 2-wire I2C interface for up 1 MHz to configure each functional block
► Multiple supplies, separate IDAC power supply to save power and to collect the ADC data.
► AVDDx, IOVDD, and PVDDTECx: 2.85 V to 3.63 V
Note that throughout this data sheet, multifunction pins, such as
► AVDDNEG: −1.8 V to −3.63 V VDACP0/AIN4/GPIO0, are referred to either by the entire pin name
► PVDDIDACx: 1.60 V to AVDDx or by a single function of the pin, for example, AIN4, when only that
► Packages and temperature range function is relevant.
► 3.750 mm × 3.750 mm, 0.40 mm pitch, 61-ball WLCSP
► Fully specified for TJ = –40°C to +125°C

For more information on the AD1030, contact [email protected].

Rev. SpB
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Data Sheet AD1030
NOTES

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