Signal Processing First

Lab 18: Digital Communication: FSK Modem

Pre-Lab and Warm-Up: You should read at least the Pre-Lab and Warm-up sections of this lab assignment
and go over all exercises in the Pre-Lab section before going to your assigned lab session.
Verification: The Warm-up section of each lab must be completed during your assigned Lab time and
the steps marked Instructor Verification must also be signed off during the lab time. One of the laboratory
instructors must verify the appropriate steps by signing on the Instructor Verification line. When you have
completed a step that requires verification, simply demonstrate the step to the TA or instructor. Turn in the
completed verification sheet to your TA when you leave the lab.
Lab Report: It is only necessary to turn in a report on Section 4 with graphs and explanations. You are
asked to label the axes of your plots and include a title for every plot. In order to keep track of plots, include
your plot inlined within your report. If you are unsure about what is expected, ask the TA who will grade
your report.

1 Introduction
The goal of this lab is to understand a simple modem, the Frequency Shift Keying (FSK) Modem, referred
to by the International Telecommunications Union (I.T.U.) as V.21. Here is a quick recap of the operation
of the v.21 FSK modem. The V.21 modem communicates 1’s and 0’s by sending either a 1650 Hz tone or
a 1850 Hz tone, respectively, for 1/300 sec. Thus the overall data rate is 300 bits/second (one bit is sent in
1/300-th of a second). Even though 300 bps is quite slow in comparison to the theoretical maximum of 56
kilobits per second over a phone line, the V.21 protocol is still used in almost every modem call, because
receiving it is so simple. A V.21 modem call can be received without using difficult techniques such as
equalizers, cancellers and matched filters. Furthermore, it can be received accurately even in the presence of
a significant amount of noise. For these reasons, V.21 is used to perform the initial handshake between two
modems, meaning that V.21 is a way to communicate some basic startup and control information between
the two modems. You can hear the V.21 modem tones at home when your V34, V.90, V.92 phone line
modem or fax machine starts a phone call. V.21 is also used to transmit caller ID information over the phone
line.

1.1 Modulator
In Lab 17 you built a FSK modulator for encoding text data into binary data and then into a FSK waveform.
If you were able to make this system work, you can use it to generate signals for this lab. If your system did
not work, we have provided a modulator called qdfsk that you can use in your experiments with decoding.

1.2 Demodulator
The receiver for V.21 must determine which of the two tones is present, and must make this decision every
1/300-th of a second. Furthermore, the receiver must synchronize with the bit interval, meaning that it must
learn where the starting and ending times of each bit are located. This synchronization is essential to making
reliable “0-1” decisions because the transition times must be avoided. A block diagram of the FSK V.21
demodulator is given in Fig. 1. Each of the main sections will be described in more detail below.

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 x(t) -
⊗ w(t)- Analog
LPF
y(t)
- Frequency s(t)
Estimate
- 0/1
Detect
d(t)
-
6

e−j2πfc t

Figure 1: Block diagram of the FSK V.21 demodulator.

1.2.1 Mixing
A basic operation that most modems need to perform is frequency shifting of the input signal. According to
the frequency-shifting property of the Fourier Transform, this can be done by simply multiplying the input
signal by a complex exponential.
w(t) = x(t)e−j2πfc t
This effect can best be understood by thinking of x(t) as a sum of complex exponentials and observing what
happens to each individual frequency component. In this case, x(t) is
x(t) = cos(2πf1 t) = 12 ej2πf1 t + 12 e−j2πf1 t .
When x(t) is multiplied by the given complex exponential at frequency −fc Hz, the exponents simply add
and the resulting w(t) is as follows:
w(t) = 12 ej2π(f1 −fc )t + 21 ej2π(−f1 −fc )t .
Note that the new frequencies in w(t) are simply the old frequencies shifted down (to the left on the f axis)
by fc , i.e., f1 − fc and −f1 − fc . Also note that w(t) is complex so we no longer have the condition of
complex conjugate symmetry between the two complex exponential components. This simply means that
now our signal is really two signals: a real part signal and an imaginary part signal. If we want to filter this
complex signal with a real filter, we simply filter the real part and the imaginary part separately with the
same filter. In M ATLAB, the filter( ) function does this very thing for you.
The purpose of the filter is to remove the complex exponential with frequency −f1 − fc while leaving
the other component whose frequency is f1 − fc . Thus, the filter output should be of the form
y(t) = Aej2π(f1 −fc )t ,
where A will depend on the gain of the filter in its passband. For V.21 FSK, we will choose fc so that the
original frequencies of +1650 Hz and +1850 Hz in x(t) are shifted to −100 Hz and +100 Hz respectively,
and these are the frequencies passed by the filter. This is achieved by choosing fc = 1750.

1.2.2 Discrete-Time Simulation

The M ATLAB implementation of the FSK V.21 modem is a simulation. This means that even though we
seem to have continuous-time signals such as x(t) and w(t), we actually use sampled versions in the M AT-
LAB program. For this simulation, we will choose the input sampling frequency to be

fsamp = 9000 Hz. (1)

This value is chosen to be rather high so that the input signal will appear to be continuous if we use the
M ATLAB plot() command. In Fig. 2 the continuous-time signals have been replaced with their sampled
versions, e.g., x(t) becomes x[n], w(t) becomes w[n], and so on. The complex exponential used in the
mixer must also be converted from e−j2πfc t to a discrete-time signal e−j ω̂c n . What is ω̂c ?

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 x(t) - x[n]
C/D -
⊗ w[n]- Digital
LPF
y[n]
- Frequency s[n]
Estimate
- 0/1
Detect
d[n]
-
6
6
Ts = 1/fsamp e−j ω̂c n

Figure 2: FSK system demodulator system simulated as a discrete-time system at a sampling rate of fsamp .

1.2.3 Low Pass Filter Design

The other thing that must be done in converting the block diagram of Fig. 1 to the simulation block diagram
in Fig. 2 is to replace the analog filter by a digital filter. This filter must pass the band of frequencies
equivalent to ±100 Hz, and it must remove the higher frequencies generated at the output of the mixer
which are −fc − 1650 = −3400 and −fc − 1850 = −3600 Hz.
You should already be familiar with some methods for designing FIR low pass filters with given speci-
fications on the passband and stopband edges, as well as constraints on the ripple characteristics in the pass
and stop bands. Such designs can be carried out in M ATLAB with the filtdemo GUI, or with the M-file
called hammfilt. Since the digital filter is typically used to filter signals that are sampled analog signals, it
is important to know how the bandedges of the digital filter can be expressed in terms of the desired analog
cutoff frequencies. This can be done if the sampling frequency fsamp is known. For example, if we want to
have a lowpass filter with an effective cutoff frequency of 2000 Hz, and we are using a digital filter running
at fsamp = 8000 Hz, then the digital filter must have its cutoff frequency1 at ω̂ = 2π(2000/8000) = 21 π.
The suggested design programs handle this for you.
In the FSK V.21 system, the frequency shifting of the mixer will generate spectrum lines that must be
removed by filtering. If we demand that these unwanted spectrum components must be reduced in magnitude
by a factor of 100, then we have given the specifications on the stopband ripple. A reduction by a factor of
100 means that the stopband ripple must be less than 0.01, or −40 dB. The passband, on the other hand,
must be made wide enough so that the desired frequency components will go through the LPF with little or
no change. Since the LPF’s frequency response will have a passband ripple, we will use a specification on
the passband of 1 dB, which forces the passband magnitude to lie between 0.89 and 1.12.

1.2.4 Slicing

Imag
x(t) - x[n] w[n]- Digital y[n] s[n] d[n]
C/D -
⊗ LPF
-
⊗
- - part
Im{ }
-
6 6
6
complex
Ts = 1/fsamp e−j ω̂c n - Unit - conj
Delay (y[n − 1])∗
{ }∗

Figure 3: Frequency estimation in a dual-frequency FSK system can be performed with a slicer.

Another basic operation of most modems is to measure the frequency of a received tone. This could
1
Remember that the frequency response of a digital filter, H(ej ω̂ ), is a function of the frequency variable ω̂ that runs from
ω̂ = −π to ω̂ = +π.

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be accomplished by optimal filtering algorithms such as matched filters designed to enhance the tones of
interest. However, if you are guaranteed to be looking at only one tone at a given time and the noise is
not severe (both of which are true for V.21), then there is a simpler method that can be employed to save
computation when measuring frequency.
Slicing is defined as follows:
s[n] = y[n](y[n − 1])∗ . (2)
It is a non-linear operation, but in the case where x[n] is a single cosine input, the filter output will be of the
form y[n] = Aej ω̂0 n , where ω̂0 = ∓200π/fsamp . In this case, the output of the slicer (2) reduces to

s[n] = (Aej ω̂0 n )(A∗ e−j ω̂0 (n−1) ).

After adding the exponents, the output simplifies to

s[n] = |A|2 ej ω̂0 .

If the objective were to determine the frequency ω̂0 , then it is sufficient to take the imaginary part

d[n] = =m{s[n]} = =m{|A|2 ej ω̂0 } =⇒ d[n] = |A|2 sin(ω̂0 )

and use d[n] to calculate the ArcSin(·) to get an estimate of ω̂0 . However, the FSK V.21 system is even
simpler than that, because we only need to decode two cases: a zero or a one. When ω̂0 < 0 we have a “1”,
and when ω̂0 > 0 we have a “0.” In addition, the sign of ω̂0 is the same as the sign of |A|2 sin(ω̂0 ), so we
only need to check the sign bit of d[n] to perform the decoding.
As will be seen in the final implementation of this lab, the recovery of the V.21 signal reduces to dis-
criminating between a +100 Hz tone and a −100 Hz tone. Taking the imaginary part of s[n], the slicer
output, will provide an easy way to determine whether a 1650 Hz or 1850 Hz tone was originally present.
Thus we can define b[n] as an estimate of the bit that is represented by the slicer output at time n.

when d[n] ≥ 0

0
b[n] = (3)
1 when d[n] < 0

In M ATLAB, you can use the find( ) function to implement (3) by creating a zero vector of the same
length as d[n] and then changing all locations where d[n] < 0 to 1.

foriginal fmixed |A|2 sin ω̂0 Bit Received

1650 Hz −100 Hz Negative 1
1850 Hz 100 Hz Positive 0

Table 1: FSK Decoding Rule

1.3 Decoding the Bits

Now we must extract the bit information from the output signal d[n]. To get a better understanding of
this problem, let us first describe the input signal to our demodulator system. Remember that the sampled
waveform x[n] is a variable frequency sinusoid that can switch frequency every 30 samples (assuming bit
rate of 300 bps and sampling rate of 9000 samples/sec) and the sinusoid switches between 1650 Hz to
represent a 1 and 1850 Hz to represent a 0. First of all, in any realistic simulation, the first part of the signal

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should be zero (or very small if there is noise); i.e., this part of the signal represents the time before the
modem starts sending data. Then we will have a segment of the waveform that encodes a “preamble” and
“marker flag” that will allow us to synchronize on the bits as well as the bytes. This part of the waveform
will encode the bit string [110011001100110011111111]. The next part of the waveform will encode
the bit sequence of the message data. Finally, the last part of the waveform encodes the “end marker”, which
is the bit string [1111111111111111]. This is summarized in the following table:
Sync Pattern Start Flag DATA End Flag
1100110011001100 11111111 message bits 1111111111111111
In our discrete-time simulation, the signal d[n] at the output of the slicer is either positive or negative at
each sample time, and we have just seen that the sign of this signal is an indicator of whether a 1 or a 0 is
being encoded at any particular sample time n. Now we should remember that if the bit rate is 300 bps and
the sampling rate is 9000 Hz, this means that each bit of the encoded message is actually represented by a
group of 30 consecutive samples. Since the bits are transmitted at a uniform rate, this means that we only
need to examine a sample of d[n] every 30 samples to determine the sequence of bits that is encoded in the
signal x[n] (or equivalently d[n]). The problem is to find out when the signal represents data and then to
synchronize our sampling of the b[n] sequence so that we can not only find out what the bits are, but also be
able to group the bits into 8 bit bytes so that we can decode the bit stream into ASCII characters.
Basically, there are three steps: (1) finding the preamble that marks the beginning of the message, (2)
synchronizing with the bit interval, and (3) grouping the bits into 8-bit sets to be converted into ASCII
characters. In the Lab Exercises part, you will explore these problems.

1.3.1 Bit Synchronization

The key to synchronization is that we have a known pattern of bits at the beginning of the message. We
must take advantage of this to determine where the bits change state. The preamble and marker pattern
[110011001100110011111111] begins after a period of silence (or noise). Thus we can expect an
abrupt change at the beginning of this pattern and then a sequence of transitions from 1 to 0 and then from
0 to 1. If we do not count a transition at the beginning, we can expect 8 transtions between the beginning of
the preamble and including the beginning of the marker bits [11111111]. We can use this knowledge of
the signal structure to locate this pattern and then use this to anchor our search for the message bits. Thus,
we want to begin by locating the transition points. A simple indicator of this would be

p[n] = |b[n] − b[n − 1]|. (4)

This sequence should be +1 at each transition point. For noiseless signals in our simulation, these indicator
points should be exactly 60 samples apart in the preamble part because it consists of four groups of two
consecutive ones followed by two concecutive zeros, etc. In a practical situation, there may be some “jitter”
in the locations that you might need to accomodate.
In any case, if we locate the beginning of the signal, then after about 8 × 60 = 480 samples, we should
find the eighth marker, which is the beginning of the group of eight 1s in the marker.

1.3.2 Byte Synchronization

The purpose of the marker section is to provide more reliability in grouping the bits into groups of 8 for
ultimate decoding into ASCII symbols. Since there are eight 1s, the number of samples of b[n] between
the last transition of the preamble (first transition of the marker) and the first transition of the message bits
should be 8 × 30 = 240 samples in our simulation since at 300 bps and a sampling rate of 9000 Hz, each
individual bit spans 30 samples.

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 Once the end of the group of marker bits has been found, we have achieved byte synchronization since
from that point on, groups of 240 samples of b[n] are known to represent the eight bits of one ASCII symbol.

1.3.3 Determining the Bit Sequence and forming Bytes

After we have found the end of the marker, we can determine the sequence of bits by simply looking at the
signal during each bit interval. Since each of these intervals is 30 samples long, we can find the middle
(where the answer is likely to most robust) by simply “sampling” the sequence b[n] at a point that is offset
by 15 samples from the beginning of each bit interval. Since the end of the marker interval is the beginning
of the message bits, we can use as our estimate

f [k] = b[nbeg + 15 + 30k], (5)

where nbeg is the sample location of the end of the marker bits (beginning of the message bits). The end of
the message is marked by 16 consecutive 1s, which decode to 255,255.
Finally, after we have determined the sequence of bits and grouped them into bytes, we must convert the
resulting binary number into ASCII symbols. This completes the decoding simulation. How to do this in
the M ATLAB simulation is suggested in Section 2.1.

2 Pre-Lab Exercises
2.1 Binary Stream to ASCII
The FSK decoder involves the operation of converting 8-bit patterns to ASCII. The M ATLAB functions
bin2dec and char can convert a bit stream to ASCII. Try the following example:

bb = [0,1,0,0,0,0,0,1], char(bin2dec(char(bb+abs(’0’))))

In order to understand this example, you might want to see what each char and bin2dec operator pro-
duces. Modify the example above so that it can do more than one ASCII character. Complete the loop
below:
inbits = round(rand(1,64)); %-- 64 random bits become 8 random characters
outchar = [];
for kk=1:8:length(inbits)
bb = inbits( ?? : ?? ); %<=====FILL in code here
outchar = [outchar, ???????? ]; %<=====FILL in code here
end
outchar

2.2 Mixing Moves the Spectral Lines

The input signal to the mixer is a real sinusoid, so it has spectral lines at either ±1650 Hz, or ±1850 Hz.
The mixer multiplies by a complex exponential, e−j2π(1750)t . For both input cases, determine the location
of all the spectral lines after mixing.

2.3 LPF Design

After mixing, the signal of interest is either +100 Hz or −100 Hz. Since the sampling rate is fsamp = 9000
Hz, the desired passband of the LPF can be calculated in the ω̂ domain: call the result ω̂p . The stopband of

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the digital LPF must be chosen to remove the extra spectral lines at the output of the mixer. Determine the
stopband cutoff frequency that will be needed to remove these extra spectral lines. Design the digital FIR
lowpass filter that will have these bandedges. Make the stopband ripple less than −40 dB, and the passband
ripple less than 1 dB. The FIR filter that will meet these specs is rather short — determine its length, i.e.,
number of filter coefficients.
If you use either filtdemo or the given hammfilt(), you can work directly with the analog fre-
quencies, once you enter fsamp = 9000 Hz into the GUI.

3 Warm-up
For the exercises in this warm-up, you will need the FSK encode/modulator from Lab 17. If your own t
h
k
n
version is not yet ready, then you can use the FSK encoder/modulator called qdfsk() which can be in the
CD-ROM
ZIP file called FSK Lab18.zip, which can be found at the ‘M ATLAB Files’ link. Look for the file called
FSK Lab18.zip
qdfsk.p.

3.1 Test the Mixer

First test the encoder with the mixer and the lowpass filter to be sure that the output of the filter is a complex
exponential with either +100 Hz or -100 Hz frequency.

(a) In case you did not design the filter discussed in Section 2.3, go back and do that part.

(b) Use xx = qdfsk(’Tech’,300,9000) to create an FSK signal for a bit stream. This encoder
runs at 300 bps and uses a sampling rate of 9000 Hz. If you have your own working FSK generator,
you can use that M-file instead.

(c) Process the FSK signal created in the previous part through the mixer (with fc = 1750 Hz) and the
lowpass filter that you designed in the pre-lab. Make a plot of the output signal in the time domain.
Label the horizontal axis with time in seconds. Since the output is complex-valued, plot the real part
only.
Instructor Verification (separate page)

(d) It is possible to view the spectrogram of the input and output of the lowpass filter, but some care
is needed. First of all, for the 300 bps signal, an extremely short window length is needed when
calling specgram, e.g., specgram(xx,32,fs), because the bit duration is only 30 samples at
fsamp = 9000 Hz. Secondly, the specgram plot for a complex input signal extends from 0 to fsamp ,
so negative frequency components actually show up at high frequencies. For example, −2000 Hz
would show up at 9000 − 2000 = 7000 Hz when fsamp = 9000 Hz.

3.2 Slicer Implementation

The objective of this section is to implement the slicer and show that it gives a constant output when the
input is a single-frequency complex exponential.

(a) For the input to the slicer, use the filtered output signal from the previous section. Or, if you are unsure
of that output, make a test signal by synthesizing y[n] as a single complex exponential:

y[n] = ej ω̂1 n

Find the correct value for ω̂1 from fs = 9000 Hz and f1 = 100 Hz.

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 (b) Note that y[n − 1] can easily be obtained from y[n] by with a delay of one sample. In the interest of
keeping the vectors the same size, the filter() command can be used to create y[n − 1]:

yy delayed = filter([0 1],1,yy)

(c) Now s[n] (the slicer output) can be obtained by using the conj() function in M ATLAB. Plot the
imaginary part of the slicer output ss and compare this to the predicted value which is a constant:

sin(2π(100)/9000)

Instructor Verification (separate page)

4 Lab Exercises
In the Warm-up section, you should have completed the implementation of all parts of the FSK demodulator,
so the only thing left is the “decoder” that will synchronize on the bits and group them into 8-bit bytes.

4.1 Transmitter/Modulator
For this lab, you can use your own FSK transmitter, or an FSK transmitter will be provided for you in the
M-file called qdfsk. The transmitter/modulator must be set to run at a sampling rate of 9000 Hz. A
realistic simulation would use 8000 Hz because phone lines are 8000 Hz, but 9000 Hz keeps our sampling
rate an integer multiple of 300 which is our symbol/bit rate. One useful test message is ’@U ’ because it
contains runs of consecutive zeros, consecutive ones, and also alternating zeros and ones. Note that the FSK
transmitter has an optional input parameter that will allow you to add noise to the FSK signal for a more
realistic simulation. It is probably a good idea to begin your program development and initial testing with
no noise.

4.2 Synchronize on the Bits

You should extend your simulation that you developed in the Warmup Section to included the computation
of the signal b[n] as given in (3). Use the FSK Modulator to produce a test signal for a very short message,
and run that signal through a program consisting of the mixer, LPF and slicer to produce the output b[n]
which are the detected zeros and ones obtained from d[n]. For testing the synchronization algorithm that
you will write, you will concentrate on the front end of b[n] where the preamble is found. Since b[n] is
sampled at fsamp = 9000 Hz, each bit interval lasts for 30 samples and each pair of ones and each pair of
zeros in the preamble lasts for 60 samples.
The goal here is to find the transitions (or jumps) in b[n], which also correspond to sign changes in d[n].
This could be accomplished with a for loop or a piece of smart vectorized code.2 A good starting point is
to compute the transitions in b[n] using (??) to compute a “transition” signal p[n]. Ideally these transitions
should be exactly 60 samples apart in the preamble region of p[n].
2
There are cases where for loops in M ATLAB are extremely useful. For example, when writing code that will be translated
from M ATLAB to C or Assembly for a DSP microcomputer, a M ATLAB for loop will provide an answer key for checking your
C/Assembly-code.

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4.3 M-file for Synchronization
Write an M-file called jumplast that will find the index nbeg that marks the end of the preamble and
the beginning of the marker. Remember that the beginning of the preamble will be preceded by a silence
interval, and that the preamble should produce eight transitions in p[n] after whatever occurs at the beginning
of the preamble. To get a good idea of what happens, make a stem plot of the sequence p[n] for a short test
signal generated with qdfsk.
The comments below describe the calling sequence for jumplast. Test your code with the input signal
bb = [zeros(1,70),sin(2*pi*(0:1000)/120)>0];
function nbeg = jumplast( bb, P )
%JUMPLAST: find the location of the last 0-1 jump in a group of eight pairs
% of 0s and 1s followed by eight 1s;
% i.e. 1100110011001100*this is it*11111111
%
% nbeg = jumplast( bb, P )
%
% bb = input signal consisting of bits: 0’s and 1’s
% P = number of samples per bit interval
% nbeg = index of the last transition. If the transition is from
% 0 to 1, then nbeg is at the end of the "0". Thus, you
% must add 15 to get to the middle of the next bit interval

NOTE: if you are unable to produce a working function for this module of the decoder, you can use the
M-file called qdjump.m which is in the ZIP archive FSK Lab18.zip.

4.4 Get the Message Text

The final step of the decoder is to turn the bit patterns back into text. Consult Section 2.1 for the useful
M ATLAB functions needed to do this efficiently. Recall that the FSK transmitted data is organized as follows:

Sync Pattern Start Flag DATA End Flag

1100110011001100 11111111 message bits 1111111111111111 t
h
k
n
CD-ROM
Three test messages are supplied in the ZIP file FSK Lab18.zip. For the first one (FSK1test.mat),
FSK Lab18.zip
only the data bits are given; the second one (FSK2test.mat) contains all of b[n] including the preamble.
You should be able to verify that you have correctly recovered the data for both of these. You can use the
first test to check that your “bits to ASCII” code is working. The second one will allow you to test the “baud
lock” synchronizer.
Then you are ready to run the entire FSK demodulator/decoder to recover a message from w[n] which
is an FSK signal having the same data format as shown above, but this time you will have to demodulate the
signal to get the data unlike the first two test messages that gave you the transmitted data bits. This is the
signal FSK3test.mat. Please note that the DATA portion of each message is actually text, so you should
get something that is readable as a sentence in English. If you correctly group the received data into bytes (8
bits), and convert each byte into its ASCII character (help char) you will be able to read the messages.

4.5 Others
Be sure to include the following in your lab report:
1. Plots of the specgram or sketches of the spectrum for the signals into the mixer, out of the mixer,
and after the LPF.

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 2. A stem plot of b[n] showing where the decisions will be made, based on the synchronization that
found the middle of the bit interval.

3. A description of your technique for synchronizing the bits and bytes, based on your knowledge of the
training signal and the data flags.

4. A comparison of the received bits to the transmitted pattern for a simple case. These ought to be
identical when there were no distortions, which is the (unrealistic) condition for this lab.

5. You should be prepared to your TA or instructor that your decoder works.

5 Supplementary Thoughts
In this lab we built a modem, a digital form of communication, which is generally speaking far superior to
analog communication. The magic of digital is that if the bits are recovered correctly (and there are a variety
of advanced techniques to achieve this), then all the distortions of the channel, noise, and modem imper-
fections along the way are effectively eliminated. In this lab, the digital magic occurs when the decision is
made to convert the slicer output d[n] into b[n] which is either a 0 or a 1 bit. A cell phone is a good example
of the magic of digital. In spite of the horrible channel between you and the cell tower (which is changing
as you cruise down the interstate while talking on your cell phones) and all the ambient noise, the data bits
can be heavily encoded and recovered properly, thus achieving digital quality.

McClellan, Schafer, and Yoder, Signal Processing First, ISBN 0-13-065562-7. 10

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 Lab 18
INSTRUCTOR VERIFICATION PAGE
For each verification, be prepared to explain your answer and respond to other related questions
that the lab TA’s or professors might ask. Turn this page in at the end of your lab period.

Name: Date of Lab:

Part 3.1(c): Show the output from the lowpass filter. Confirm that its frequency is either -100 Hz or +100
Hz. In addition, sketch the filter specifications (in the space below) that you used to create the filter.

Verified: Date/Time:

Part 3.2(c): Demonstrate that the slicer will give a constant output when the input is a single complex expo-
nential.

Verified: Date/Time:

McClellan, Schafer, and Yoder, Signal Processing First, ISBN 0-13-065562-7. 11

Prentice Hall, Upper Saddle River, NJ 07458. c 2003 Pearson Education, Inc.