LSI LOGIC DESIGN

CHAPTER 4
Synchronous Design

JUNE 17, 2020

PHAM TUONG HAI
QUALITY ASSESSMENT & TRAINING DEPARTMENT
RENESAS DESIGN VIETNAM CO., LTD.
RENESAS ELECTRONICS CORPORATION
CHAPTER 4. Synchronous Design

4.1. Timing Issue of Logic Data.

4.2. Synchronous Design and

Static Timing Analysis (STA)

4.3. Synchronous Design Summary

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4.1 Timing Issue of Logic Data

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Timing Issue of Logic Data
Let’s study what will comes out to output signal b when input signal a changes
while wire connections, AND, and NOT gate have delay.

1 1
a[1] 1 The difference of delay comes
b[1]
a mainly from the difference of
a[0] 2 b the length of the wire lines if
1
b[0] gate delays are the same.
4 1

Numbers in the block diagram are delay of each element, wire-delay and gate-delay.

Suppose a changes from 0 to 3, then b shall change from 1 to what ??

a[1] 0 1 b[1] 0 ?
a[0] 0 1 b[0] 1 ?

Draw the time chart for the given conditions above.

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 a[1] 1 y1 1
a[1] AND 1
b[1]
a[0] 2
1 y2
a[0] 1 NOT
y1 4 1
2 b[0]
y2 y3
4
y3
1
AND
1
NOT
1
b[1]
1
b[0]

a[1]=0 a[1]=1 time

a 0 a[0]=0 a[0]=1 3

time
b 1 1 3 2

Incorrect output for a = 3 caused by delay and hazard Correct output for a = 3

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The result shows that output b does not have a correct value corresponding
to the input a until 6 time units, the largest delay in the logic block, passes.
6 time units

a[1] a 0 Delay 3
b[1]
time
a[0] b[0] b 1 1 3 2

Incorrect output correct

output

However, delay is not an only problem we will have for timing issues.
We will have much serious problem, if input changes in a short time.
Let’s see what happens, if input changes as follows.

a[1] 0 1 0 b[1] 0 ? ?
a[0] 0 1 0 b[0] 1 ? ?

Input is 3 for just 3 time units

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 3 1
1 y1
a[1] a[1] AND 1
b[1]
2

a[0] y2
a[0] 1 NOT
1 4 1
b[0]
y1 y3
2
y2
4
y3
1
AND
NOT 1
1
b[1]
b[0] 1

0 is not a correct time

a 0 3 0 output for a = 3

time
b 1 1 3 0 1

The correct value “2” for the input “3” never appears on the output
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The result shows that if the input changes in a short time, then the correct output will never come out.

1 1
a[1] 1 For the given delay, the logic
a b[1] block on the left can not output
a[0] 2 b correct value if input changes in
1 no more than 3 time units.
b[0]
4 1

In general, we have to keep input variable stable for more than

maximum delay - minimum delay of the logic block, otherwise
the correct output will never appear at the output port.

Let’s confirm the above idea by keeping the input for 5 time units unchanged
and observe the output value.

a[1] 0 1 0 b[1] 0 ? ?
a[0] 0 1 0 b[0] 1 ? ?

Input is 3 for just 5 time units

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 5

a[1]
a[0]
1
y1
2
y2
4
y3
1
AND
NOT 1
1
b[1]
b[0] 1
time
a 0 3 0

time
b 1 1 3 2 0 1

The correct value “2” appears on the output

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The result on the previous slide can be summarized as follows.
3 3
a 0 3 0
time
b 1 1 3 2 0 1

6
correct incorrect (1) Longest path delay: The time needed for the
correct output to appear at the output.
Longest path delay = 6 (2) Shortest path delay: The correct output will go
Shortest path delay = 3 away after this time passes if the input changes.

Therefore,
(3) Longest path delay - Shortest path delay:
1 1
a[1] 1 (a) The input must be kept unchanged during
b[1] this mount of the time period, otherwise the
a[0] 2 correct output will never appear at the output.
1 (b) The time while incorrect output appears at
b[0]
4 1 the output because of the hazard.

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 For the logic block on the left, it is mandatory to
a[1] b[1] keep the input unchanged for (longest -shortest)
delay time to get the correct output.
a[0] b[0]
Placing FFs at the input of the logic block is the
most simple answer for this issue.

a[1] b[1] Now, study about the cases to build a

FF larger scale system by combining
a[0] b[0] many blocks as shown below.

clock

clock clock clock clock

This must be longer than
(longest - shortest) delay time.

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 Block1 Block2

clock1 clock2
If we are to use different clocks
such as clock1 and clock2 to
Block1 and Block2 respectively,
T1 it is almost impossible to control
t = t0 clock1
clock rise time so that T1 is
T1 must be
always longer than (longest -
longer than
shortest) delay time and T2 is
(longest -
always longer than the longest
shortest)
delay time.
delay time.
T2
t = t0 clock2

T2 must be longer than the longest delay time. Using the same clock for all the blocks is a solution.

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4.2 Synchronous Design and Static
Timing Analysis (STA)

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 Synchronous Design and STA
Synchronous design uses one clock for all the logic blocks and capture the signals
at clock rise time to make them unchanged during one cycle for the processing.

P1 P2 P3

Apply the same clock to all the logic blocks

clock

1 cycle

P1 Complete P1 before
this timing
Start P1 at
this timing
P2 Complete P2 before this timing
Start P2 at this timing

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There are several ways to use clocks in synchronous design as shown below.
However, using one clock at its rise time is recommended.

Single phase FF1 FF2

clock DQ D Q

One cycle Use only rise edges of clk

transfer a clock

Single phase FF1 FF2

clock DQ D Q

Half cycle Use both rise and fall edges clk

transfer of a clock

Two phase clk1 FF1 FF2

clock DQ D Q
clk2
clk1 clk2
Use rise edges of different
clocks having different phases.

Not recommended to use.

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 Timing constraints in synchronous design can be summarized as below.

m n Timing constraints
combin-
FF1 FF2 (1) T2 must be shorter than one cycle.
sig1 ational sig2
logic (2) sig2 must not change during Setup
clock and Hold time of FF2 to avoid
metastability of FF2.
T1: shortest path delay of the combinational logic
T2: longest path delay of the combinational logic

Setup time Hold time

sig1

sig2

T1 T2 T1

T1 > Hold time T2 + Setup time < 1 cycle

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STA is carried out several times by using various level Synthesis constraints
of accuracy of delay data.
Timing condition
(wiring model
After layout ( place and route ), we must RTL code cell library)
check the timing because delay from A to B
is very much different depending on where A Modify RTL
and B are placed and connected by which for shorter
processing
route.
time
List of
Net list available
Timing report cells
A
with temporary
? B load Dimension
Modify of the cells
place and route DR
B
constraints

Timing report
NG
Final check is done based on the actual with actual load
load, which takes account electronic
characteristics of wire lines.
OK

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Dividing a Process and Multi-Cycle Path
Next, a question may be raised that “What shall we do if an assumption
that every process can be done in one clock cycle does not hold?"

A countermeasure (1)
Divide the process into several blocks so that each
block can be completed in one clock cycle.

X Q
Y
Z Processing W
N This might be a good
solution for pipeline
type process.
X 1st 2nd 3rd Q
Y part part
Z part You may use multi cycle
of W of W N
of W path specification of DA
tool instead of dividing the
1 cycle 1 cycle 1 cycle process.

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Another countermeasure (2)
For data where processing cannot be ended within 1 clock cycle,
introduce some signal such as valid or ready to notify the block waiting
for the data that the data is ready.

X Valid
Y Process Process
Z W V This means introducing
asynchronous logic partially.
More than one cycles

Process
U

1 cycle 1 cycle

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Asynchronous Data Transfer
Synchronous design makes timing issue very simple. However, it cannot be applied to every system.
We have to introduce asynchronous design in some cases. Typical cases are:

• Connecting two system running on independent clock

System running data System running

on clock1 on clock2

clock1 independent clock2

(asynchronous)

• Getting asynchronous data, such as interrupt, from outside the chip

interrupt
Independent from
internal clock of the chip clock

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Connecting two system running on independent clock
Data transfer among the logic with different clock systems

clock1

clock2

Because clocks 1 and 2 are running without taking any synchronization, their
rise edges may collide.
Therefore, FF3 getting data from clock 1 system may fall in metastable state.

Logic driven
by clock1 FF1 FF3 Logic driven
by clock2
clock1
clock2

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Placing FFs in between clock1 system and clock 2 system as shown below is one of the known
solution for the problem.

clock1

clock2

Don't place any logic

on these line.

Logic driven
by clock1 FF1 FF2 FF3
Logic driven
clock1 by clock2
clock2
Direct output
from FF
This is to At least 2 FFs
avoid hazard. in serial

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Now let’s see how it works.
Metastability occurs because Setup, Hold condition
clock2 rises when q1 changes. OK
clock1 NG
Gate
clock2 delay

a1 1 0 1
q1
1 0 1
q2 See next page
1 1 1/0 0 0 detail
for 1 1
metastability
q3
1 1 1/0 0 0 1 1

clock1 a1 q1 q2 q3
system FF1 FF2 FF3 clock2
system
clock1
clock2

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 q1 never becomes metastable because we can
clock2 rises apply STA to clock1 system and make it sure
that a1 never changes when clock1 rises.
a1 1 0 1
q1
1 0 1
q2
1 1 1/0 0 0 1 1
metastability
q3
1 1 1/0 0 0 1 1

q1 Data sent from

1 0
clock1 system

1 1 0 0 0
Data received by
q2
1 1 1 0 0 clock2 system

Sending data's change from 1 to 0 is correctly detected by the receiving

system because q2 changes from 1 to 0 correctly even if metastability occurs.

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4.3 Synchronous Design Summary

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Implementation

All operations of one circuit block of interest are uniquely defined in

synchronous design with base clock signal.

RTL design …fully synthesizable design, configured with

single clock signal and registers (FF)

Combinational logic Combinational logic

OUT1
IN FF

clock
FF OUT2

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One Cycle Operation
Combinational logic Combinational logic
OUT1
IN FF

clock
A B
OUT2

clock

A
delay
B

must be stable
1 cycle
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Synchronous Design
Combinational logic Combinational logic

OUT1
IN FF

clock
A B
OUT2

clock

A estimated
by STA
B
input setup time input hold time

OUT2
output delay time

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Timing Requirements
Combinational logic

IN
O Requirements
FF

clock Tcyc - Tsu > Tpd > Tho

: timing margin

Timing specifications
Tcyc: clock cycle time
Tsu: input setup time
Tcyc Tho: input hold time
clock
Estimated by STA
Tpd: propagation delay time
IN
Tpd

O
Tsu
Tho

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