LSI LOGIC DESIGN

CHAPTER 5
Design for Testability (DFT)

JUNE 24, 2020

PHAM TUONG HAI
QUALITY ASSESSMENT & TRAINING DEPARTMENT
RENESAS DESIGN VIETNAM CO., LTD.
RENESAS ELECTRONICS CORPORATION
CHAPTER 5. Design for Testability (DFT)

5.1. Manufacturing Defects.

5.2. DFT and Scan Method.

5.3. DFT Design Flow.

Page 2
5.1 Manufacturing Defects

Page 3
Manufacturing Defects
Manufacturing defects are physical defects happening during the manufacturing time.

In Deep submicron era, we

have to be sensitive to this
kind of manufacturing defects
because they result in
deformation malfunction of the products.
The same level of
deformation may
result in defect.
(open or large resistance)

In former process generation, We have to apply some methods to

the deformation of the wiring check if the products are manufactured
shown above did not cause without defects or not before shipping
any problem. them to the market.

Page 4
Physical Defects
§ Abnormality in MOS Transistor
F Abnormality in Gate Oxide
F Shortage in MOS Transistor
F Abnormality in wire width, space and thickness
F Contamination due to foreign particle

§ Shortage in wiring
F Etching residuum
F Bridge due to foreign particle
F Abnormal wider width and thicker thickness

§ Disconnection in wiring
F Non-conductive via and higher resistance of via
F Abnormal narrower width and thinner thickness
F Half disconnection due to foreign particle and void

Page 5
 Gate oxide pinhole

Shortage due to foreign particle

Disconnection due to electron migration

Page 6
Purpose of Test
§ Screening of manufacturing defects
§ i.e. “last defense for LSI quality assurance”

- Test sequence Renesas Customer

- Temp., volt., freq. (System Test)
and etc. (LSI Test)

○
Tester Program

○
ＬＳＩ
LSI
ＬＳＩ
LSI Pass
ＬＳＩ
LSI Non- Shipment Non-defect
ＬＳＩ
OK
？
LSI
ＬＳＩ defect

×
LSI
Screening OK

LSI
LSI Tester
Prober
Handler
Fail ＬＳＩ ×
LSI
NG
Defect
ＬＳＩ
LSI
NG
Defect
(10～100ppm)

* ppm : 1E-6
0100HH
Test Pattern 1001XL - Failure anytime
･･･ - Failure by temperature, Failure analysis
voltage and frequency
- Big standby current
- Low reliability

Page 7
Test cost is increasing year by year
1
Purpose of test is as follows
§ Maximum quality assurance of LSI Manufacturing

Cost per Transistor

§ Adequate test cost cost
10E-2
Test Cost (tester-related cost)
§ Equipment (tester, prober, handler)
§ Operation (labor cost)
10E-4 Test
F increase of ratio to manufacturing cost Design
improve
Test cost
Test Cost (cost other than tester)
§ Test design cost (labor cost) 10E-6
§ Test circuit cost (chip area) 1980 1990 2000 2010
§ Failure analysis cost (labor test)
(Source: ITRS2002 Public Conference)

Page 8
LSI Design Flow
System spec

System design C based/System C System verification

Logic design Logic synthesis (RTL ->Gate) Logic verification

DFT
Layout verification
Layout design P&R
Timing verification

Mask making Mask data preparation Mask data verification

Manufacturing

Wafer Test Testing

Page 9
Impact of SoC Design Trend
(1) Logic size (2) Memory (3) Frequency
M gates M bits k instances MHz
50 50 1000
Mobile Mobile High-speed
40 40 800 CPU core
30 30 3 600
20 20 2 400
10 10 1 200
0 05 06 07 08 09 10 0 05 06 07 08 09 10 0 05 06 07 08 09 10

> 30% increase a year > 30% increase a year

> 30% increase a year
-> test time increases -> test time increases
-> High-speed tester
(three-halves power of size) (proportion to size)

LBIST or Compression Concurrent Enable to lower external

Test measurement using clock freq. using PLL
MBIST (around 30 MHz)
DFT reduces the increased test time and needs no tester of high specification
Page 10
Test Methodology

Functional Test Structural Test

Actual LSI operation Pay attention to defects during
= Pay attention to Function manufacturing and resulting
Concept Check whether LSI functions in the faults
same conditions to the actual condition Cover all faults by modeling faults
in use completely

Pass/Fail Decide by operating functionally or Decide the existing of defects during

Decision not manufacturing or not
Coverage Stuck-at fault Evaluating coverage quantitatively for
Measure + critical path check by manual each fault models by tools
Total Difficult to evaluate quantitatively (no Easy to evaluate quantitatively
coverage fault modeling => no definition of
capability coverage) (Summary for each fault models)

There is no scientific improvement Evaluate scientifically by quantification

Test (important to choose models)
quality because there is no quantification

Page 11
Fault Coverage

Fault Coverage: the percentage of total faults for which test patterns have
been generated

𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝑫𝒆𝒕𝒆𝒄𝒕𝒆𝒅 𝑭𝒂𝒖𝒍𝒕𝒔

𝑭𝒂𝒖𝒍𝒕 𝑪𝒐𝒗𝒆𝒓𝒂𝒈𝒆 = ×𝟏𝟎𝟎
𝑻𝒐𝒕𝒂𝒍 𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝑭𝒂𝒖𝒍𝒕𝒔 𝒊𝒏 𝒕𝒉𝒆 𝑪𝒊𝒓𝒄𝒖𝒊𝒕

Fault Coverage is also called Failure Detection Rate and can be estimated
by using Fault Models

Page 12
Modeling Faults Example: Stack-at-Fault Model
X1 X2 X3 000 001 010 011 100 101 110 111

X1 X2 X3 Y 0 1 0 0 0 1 1 1
SA0
a b c a
SA1

SA0
b
SA1

SA0
e c
SA1

SA0
d
SA1
d
SA0
f e
SA1

SA0
f
g h SA1

SA0
g
SA1

SA0
h
i SA1

Y i
SA0 0 0 0 0 0 0 0 0
SA1 1 1 1 1 1 1 1 1

Page 13
Modeling Faults Example: Stack-at-Fault Model
X1 X2 X3 000 001 010 011 100 101 110 111

X1 X2 X3 Y 0 1 0 0 0 1 1 1
0 0 0 SA0 0
a b c a
SA1
0 0 0
SA0 0
b
SA1

SA0 0
e
0
c
SA1

SA0 0
d
SA1
d
SA0 0
0 f e
SA1
1
SA0
f
g 0 0h SA1 1
SA0 0
g
SA1

SA0 0
i
h
SA1
0
Y SA0 0
i
SA1

Page 14
Modeling Faults Example: Stack-at-Fault Model
X1 X2 X3 000 001 010 011 100 101 110 111

X1 X2 X3 Y 0 1 0 0 0 1 1 1
0 0 0
SA0 0
a b c a
SA1
0 0 0
à1 SA0 0
b
SA1

SA0 0
e c
0 SA1 1
SA0 0
d
SA1
d
SA0 0
0 f e
1 SA1

SA0
f
g 0 0h SA1 1
à1 à1 SA0 0
g
SA1 1
SA0 0
i
h
SA1 1
0à 1
Y SA0 0
i
SA1 1

Page 15
Modeling Faults Example: Stack-at-Fault Model
X1 X2 X3 000 001 010 011 100 101 110 111

X1 X2 X3 Y 0 1 0 0 0 1 1 1
0 0 1
SA0 0 0
a b c a
SA1
0 0à 1 1
à0 SA0 0 0
b
SA1 1
SA0 0 0
e c
0 SA1 1 1
à1
SA0 0 0
d
SA1
d
SA0 0 0
0 f e
1 SA1 1
à0
SA0 0
f
g 0 1h SA1 1 1
à0 SA0 0 0
g
SA1 1
SA0 0 0
i
h
SA1 1 1
1à 0
Y SA0 0 0
i
SA1 1 1

Page 16
Modeling Faults Example: Stack-at-Fault Model
X1 X2 X3 000 001 010 011 100 101 110 111

X1 X2 X3 Y 0 1 0 0 0 1 1 1
SA0 0 0 0 0 0 0
a b c a
SA1 1 1 1 1 1 1
SA0 0 0 0 0 0 0 0
b
SA1 1 1 1 1 1 1 1
SA0 0 0 0 0 0 0
e c
SA1 1 1 1 1 1 1
SA0 0 0 0 0 0 0
d
SA1 1 1 1 1 1
d
SA0 0 0 0 0 0
f e
SA1 1 1 1 1 1 1
SA0 0 0 0 0 0 0
f
g h SA1 1 1 1 1 1
SA0 0 0 0 0 0 0 0 0
g
SA1 1 1 1 1 1 1
SA0 0 0 0 0 0 0 0 0
i h
SA1 1 1 1 1 1 1

Y SA0 0 0 0 0 0 0 0 0
i
SA1 1 1 1 1 1 1 1 1

Page 17
Modeling Faults Example: Stack-at-Fault Model
X1 X2 X3 000 001 010 011 100 101 110 111

X1 X2 X3 Y 0 1 0 0 0 1 1 1
SA0 0 0 0 0 0 0
aS b c a
et o SA1 1 1 1 1 1 1
100 f 4 te SA0 0 0 0 0 0 0 0
% s b
cov sin t vec SA1 1 1 1 1 1 1 1
era gle to
ge stu rs ob SA0 0 0 0 0 0 0
for e ck- t c
this at fa ains SA1 1 1 1 1 1 1
circ ult
uit SA0 0 0 0 0 0 0
d
SA1 1 1 1 1 1
d
SA0 0 0 0 0 0
f e
SA1 1 1 1 1 1 1
SA0 0 0 0 0 0 0
f
g h SA1 1 1 1 1 1
SA0 0 0 0 0 0 0 0 0
g
SA1 1 1 1 1 1 1
SA0 0 0 0 0 0 0 0 0
i
h
SA1 1 1 1 1 1 1

Y SA0 0 0 0 0 0 0 0 0
i
SA1 1 1 1 1 1 1 1 1

Page 18
5.2 DFT and Scan Method

Page 19
What is DFT?
DFT is a design technique that adds test circuits inside the LSI hardware. These
added circuits permits to easily apply tests on the designed LSI after manufacturing

DFT consists of
§ Creating test circuits
§ Inserting test circuits into LSI hardware
§ Preparing test data for physical failure analysis

Purpose of DFT
§ Guarantee the LSI product quality
§ Improve manufacture process
§ Optimize test cost

Target of DFT
§ Minimize area overhead § Minimize the test time
§ Increase test/fault coverage § Minimize the test cost

Page 20
Required Quality and Test Level

Required quality (quality level of products)

§ Zero defect

§ Guarantee of operation under warranty condition

Test level
§ Test items

§ Test conditions
(temperature, voltage, frequency/timing, etc.)

§ Test model (measure representing test sufficiency)

and target fault coverage (quantitative evaluation of test sufficiency)

Page 21
Target Quality of Renesas Products

Standardization of common quality level requested by Consumer

Quality Guaranteed Main products

Classification Lifetime
Automobile parts (Engine controller, etc.)
Q1A 20 years General traffic equipment
High
Reliability Car electronics (accessories: genuine
Q1B 10 years goods), etc.

Industry Q2 10 years Car electronics, FA equipment, etc.

PC, Consumer electronics,

Consumer Q3 10 years Mobile equipment

Custom Determine individually Game instruments,

QX for each product Ultra high reliable equipment

Page 22
 Structural Test
To check if the C1 part of an LSI shown below is manufactured without defect, we have to check wires W1,
W2, W3, W4 and W5, and gates G1 and G2 are manufactured without defect.

Usually logic designers do not know what kind of gates are created on which wire connections. Therefore, it
is almost impossible to set a specific value at the sending end of a wire such as W4 and checking the voltage
at the other end of the wire by applying test data input at the input ports of the LSI.

This means functional test is not suitable for detecting manufacturing defects.

C1 C1
FF1

output ports
FF5 FF1 W4
W1
input ports

FF2
G1 FF5
W5
FF3
W2 G2
FF2
W3

FF3
LSI_1
Page 23
However, knowing the gate net list, we can tell C1
what value must come out at W5 output when we FF1 W4
apply the values listed on the table below to FF1, W1
FF2, and FF3. G1 FF5
W5
W2 G2
By checking whether W5 output is equal to the FF2
value shown in the table, we can detect
manufacturing defects in C1. W3
FF3

Applicable input pattern and expected output

pattern FF1 FF2 FF3 W5 output

A 1 0 Patterns E and G are not
1
B 0 1 needed because they can be
1
C 1 0 covered by pattern C.
0
D 0 0
E 1 0
1
F 0 0
0
G 1 0 A, B, C, D, F, and H are enough
0 to check all the logic elements.
H 0 0

Page 24
Scan Method
For the logic block shown on the right, we can calculate what must
come out at W5 output when we apply some input patterns on W1, C1
W2, and W3, based on the net list information. FF1 W4
W1
G1 FF5
Scan is a method to use FF or latch to set input patterns on W1, W5
W2 G2
W2, and W3 and observe (memorize) the output on W5. FF2
W3
LSI_1 create inputs to C1 observe output from C1 FF3

FF1 C1
FF5

output ports
input ports

FF2 MUXscan is an idea to use FF1, FF2,

and FF3, created from the RTL code by
FF3
a synthesis tool, to set values on W1,
W2, and W3 respectively and use FF5
to observe output W5.

Page 25
 To apply MUXscan we have to replace all FFs in the LSI by “DFT ready FF”, specially designed FF suitable
for MUXscan.

scan-in scan-out
port LSI_1 port
FF1 DFT tools automatically
connects all the replaced

output ports
FF5
input ports

FF2
FFs by a scan chain.

FF3 Replacement is done by

DFT tools automatically.

MUXscan
Scan enable
D-FF
FF scan-in 1 Q output
Q output data D Q
data 0

System clock CK scan-out

replace all the FFs in the (= Scan clock)
System clock
LSI by MUXscans
rst_n
rst_n
Page 26
Scan chain created by a DFT tool works as shown below:
(1) If we prepare bit string like xxx--x101xx--xxxx at scan in port and apply clock signal to FFs, then the bit string
goes into FFs through the scan chain and as a result 1, 0, and 1 are set to FF1, FF2, and FF3 respectively.

scan-in x x x x x 1 0 1 x x x x
scan-out
port port
FF1 FF2 FF3 FF5

xxx--xx101xxx--x The bit string goes through scan chain one FF to the
next FF every clock rise time.
test pattern
(bit string) This operation is called “scan-in operation”.
x: don’t care C1
FF1 W4 FF5
W1
(2) After setting 1, 0, and 1 on FF1, FF2, and FF3 respectively, operate the W2 G1
W5
LSI for 1 clock cycle to get output W5 into FF5. FF2 G2

W3
This operation is called “capture operation”. FF3

Page 27
(3) After capture operation, the value of FF5 can be got from the scan out
port through scan chain as shown below.

scan-in x x x x x x x x x 0 x x scan-out
port port
FF1 FF2 FF3 FF5

The value of all the FFs can be read through scan xxx---xxxxxx0x--x
chain. They will come out every clock rise time.
x: don’t care

This operation is called “scan out operation”.

(4) The value of FF5 came through the scan chain is compared to the expected result of C1. If it
matches with the expected results for all the test pattern, then C1 is manufactured without defects.

Page 28
Test Point Insertion (TPI)
Because a DFT tool knows the gate net list, it can create data pattern which can test logic blocks in the LSI.
However, if the logic scale between FFs is very large, then it is difficult to create patterns to check-out all
the defects in that logic block.
many gates in between
It becomes difficult to set these value by
FF1 setting FF1, FF2, FF3, etc.
FF5
FF2
FF6
FF3 It becomes difficult to estimate this value
by observing FF5, FF6, etc.

Inserting the following logics in proper signal line, setting and observing signals become very easy. This test
point insertion improves coverage of test pattern generated by random pattern generator.
1 control 0 control observe
1 0
FF 1 FF 0
FF

Page 29
5.3 DFT Design Flow

Page 30
DFT Design Flow
Logic Design

DFT Design
DRC, Insertion of Scan and BIST logic/circuits
SCAN insertion (DFTAdviser/DFTCompiler, "Shingen", MINORI)

Layout Design
Automatic Test Pattern Generation
ATPG
(TetraMAX, FastScan, "Shingen", MINORI)

Logic Verification including inserted test circuits

Verification (Verilog_XL/NC-Verilog/Conformal-LEC)

TPG Test Program ( for tester ) Generation

Test Program
Creation Check
fault detection Check fault detection rate of the test
coverage program in a tester
(Fault simulator: Z01X!, Verifault-XL)

Page 31
SCAN Design

DRC (Design Rule Check)

DRC DRC
Library (Design Rule Check) Verify a design satisfies design constraints
for MUX scan method

Gate Level
Netlist Scan Insertion
Scan Insertion
Construct scan chain
Stitching
Library Compression and decompression circuits
are also inserted in the use of scan
Stitched Scan
Netlist Information
compression

ATPG (Test pattern generation)

ATPG
ATPG Generate test pattern
Library

Test
Pattern

Page 32
DRC (Design Rule Check)
§ A tool which can verify design constraints for MUX scan method is satisfied
§ Necessary constraints for MUX scan are covered
§ Easy error analysis by detail error report and debugging functionality

IO Configuration
Rule
Netwalker
Library

Gate Level
Design Rule Checker Result
Netlist

Constraint
Constraint: fix values for clock origins and test modes
Rule: common design rules
Result: check result / error summary

Page 33
Necessity for Highly-Compressed Pattern
§ Need more pattern generated for AC SCAN test (3 to 5 times)

§ Drastically Highly-Compressed Pattern is necessary to cope

with large scale while maintaining the high test quality

Test cost reduction

“At-Speed” Highly-Compressed
Test cost increase

Pattern
Upper limit
of pattern “At-Speed”
stored in
the tester Compressed pattern
“At-Speed”
“Stuck-at”
Compressed pattern
“Stuck-at”

Page 34
Basic Concept of Compression SCAN
0xxxx1xxxxxxxxxx01xx 0xxxx1xxxxxxxxxx01xx
xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
xxxxxx1xxxxxxxxxxxxx xxxxxx1xxxxxxxxxxxxx
Huge data
xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx0xxx
xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx0xxx
Huge data
SCAN xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxx
xxxxxx00xxxxxxxxxxxx xxxxxx00xxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxx1xxxxxxx xxxxxxxxxxxx1xxxxxxx

Compression
xxxx1xxxxxxxxxxxxxxx xxxx1xxxxxxxxxxxxxxx Compression
xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxx0xxxxx xxxxxxxxxxxxxx0xxxxx
COMPACTOR
COMPACTOR same same
Expansion Compression Software
Software 0xxxx1xxxxxxxxxx01xx 0xxxx1xxxxxxxxxx01xx 00101x1x0011010x01x1
DECOMPRESSOR

xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx x0111001x0110010x100

COMPACTOR
xxxxxx1xxxxxxxxxxxxx xxxxxx1xxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
Expectation value
00101x1x0011010x01x1
xxxxxxxxxxxxxxxx0xxx xxxxxxxxxxxxxxxx0xxx GO/NG
xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
x0111001x0110010x100 xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx
xxxxxx00xxxxxxxxxxxx xxxxxx00xxxxxxxxxxxx 00101x1x0011010x01x1

Compression xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxx1xxxxxxx
xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxx1xxxxxxx
x0111001x0110010x100

Measured value
SCAN xxxx1xxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxx0xxxxx
xxxx1xxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxx0xxxxx

Data compression/expansion circuits (DECOMPRESSOR/COMPACTOR) in a LSI for SCAN

input/output can reduce pattern data size
Page 35
Built-In Self-Test (BIST)
§ Pattern generation circuits and pass/fail judge circuits are inserted into an LSI
§ Can test an LSI using pseudo random number patterns
§ Can judge pass/fail after a test completed

Scan Test Logic BIST

Initialize clock
LSI supply
LSI
Test pattern
FF
FF Pattern
Large volume generation
of test pattern
Full scan Expectation Result Simple Tester
Large-scale
values judge (cheap)
Tester Full scan
(expensive) Read result

Page 36
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