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Quiz - Docx - Verilog

The document contains 7 multiple choice questions about digital logic design concepts such as finite state machines, boolean equations, and sequential circuits. It also includes 2 questions asking to draw state transition diagrams and implement circuits in Verilog. The questions test understanding of topics like case statements, blocking vs non-blocking assignments, and designing an FSM for a rover to follow a travel plan around a campus.

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52 views5 pages

Quiz - Docx - Verilog

The document contains 7 multiple choice questions about digital logic design concepts such as finite state machines, boolean equations, and sequential circuits. It also includes 2 questions asking to draw state transition diagrams and implement circuits in Verilog. The questions test understanding of topics like case statements, blocking vs non-blocking assignments, and designing an FSM for a rover to follow a travel plan around a campus.

Uploaded by

fiitnessbyneha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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QUIZ

Question 1: Write one line answers for the following questions (10 marks)
a)What is the difference between casex, casez and case statements?
Answer : casez treats all z values in the case expression as don't cares. casex treats all x and z
values in the case expression as don't cares.

b)What is the difference between wire and reg?


Answer : Wire is a net data type, represents connections between hardware elements. It's default
value is z. Where as reg is a register data type, which represent data storage elements. Registers
retain value until another value is placed onto them. It's default value is x.

c)What is the difference between ( = = , ! = ) and ( = = = , ! = = )?


Answer :

d)Does the order of input and output ports in the argument of module matters?

e) A net has default value : 0,1,x,z

f) A reg has default value :0,1,x,z


g)What is the difference between:
a) c = check ? a : b; and
b) if(check)
c = a;
else
c = b;
Answer :
The ?: merges answers if the condition is 'x', so if check = 1'bx, a=2'b10, and c=2'b11, then c =
2'b1x. Where as if else treats x or z as false case, so always c = b

h) What is the difference between a = #10 b; and #10 a = b; ?


Answer:
In a = #10 b; current value of "b" will be assigned to "a" after 10 units of time (like transport
delay). In #10 a = b; the simulator will execute a = b; after 10 units of time (like inertial delay).

i) Write a verilog code for implementing the functionality of a SWITCH.


-:
Whenever <enable> comes ( that is whenever the user presses the switch) the value of
the <switch> register should become high( showing that the switch has been pressed)
else <switch> should become low (showing that the switch has been switched off).

Question 2: (10 marks)


You are an engineer working for NASA. They want you to design a FSM that will test their
newest rover Fido on the IIIT campus. NASA wirelessly transmits the travel plans to Fido,
and then Fido moves according to that information. To design your FSM, you first select
the following locations around the IIIT campus and assign each location with a state in
3-bit binary representation: Killian[000], Kresge[001], ZCenter[010], Syd-Pac[011],
Student Center[100], Building 34[101], 6.111 Lab[110], and the Stata Center[111].
To simplify your test, you inform NASA to send Fido’s FSM a binary sequence for travel
plans
(e.g.‘1-0-0-0-1’ to cause Fido to move five times). In other words, Fido receives either ‘0’ or
‘1’. for each move and travels to the next destination as specified below. Fido starts off at
Killian Court for each test run, and your FSM should output Fido’s current location.
Killian [000]: If 0, stay at Killian. If 1, go to Kresge.
Kresge [001]: If 0, go to Z-Center. If 1, go to Student Center.
Z-Center [010]: If 0, go to Syd-Pac. If 1, go to Student Center.
Syd-Pac [011]: If 0, stay at Syd-Pac. If 1, go to Killian.
Student Center [100]: If 0, go to Stata Center. If 1, go to Building 34.
Building 34 [101]: If 0, go to Syd-Pac. If 1, go to 6.111 Lab.
6.111 Lab [110]: If 0, go to Stata Center. If 1, stay at 6.111 Lab.
Stata Center [111]: If 0, go to Kresge. If 1, go to Building 34.

(a) Draw the state transition diagram for this FSM.

(b) If Fido is forever given a sequence of ones (i.e. 11111…), where will it eventually
end up?

(c) If Fido is forever given a sequence of 01s (i.e. 010101…), which location(s) will
it never visit?

Question 3: (10 marks)

Let "a" be a 3 bit reg value.


initial
begin
a < = 3'b101;
a = #5 3'b000;
a < = #10 3'b111;
a < = #30 3'b011;
a = #20 3'b010;
a < = #5 3'b110;
end

What will be the value of "a" at time 0,5,10,... units till 40 units of time?

Answer :
0 - 101
5 - 000
10 - 000
15 - 111
20 - 111
25 - 010
30 - 110
35 - 011
40 - 011
(This helps in understanding the concepts of blocking and non-blocking statements).

Question 4:For function F(x, y, z) = xy’z’ + x’yz’ + x’y’z


(a) Create the truth table for function F (3 marks)

(b) Implement F by means of 8-to-1 Multiplexer (3 marks)

(c) Implement F by means of a 3-to-8 Decoder (4 marks)


Question 5 (3 marks)

There are three major courses X, Y and Z, and two minor courses A and B in a
department. A student can graduate if he or she passes:
1- All the major courses from X to Z
or
2- Two major courses and both minor courses
Write a Boolean equation to represent the graduation condition.

Hint: Use the name of the courses as the variables of your equation. i.e., X,Y, Z, A, B.
Variable X is 1 if a student passes course X, otherwise 0.

Answer:

G = XYZ + XYAB + YZAB + XZAB

Question 6

Consider the following sequential design. The D F/Fs are negative edge triggered.
1. Write out the excitation equations for F/F 1 and F/F 2, i.e., what is the logic equation
input of the inputs D1 and D2 ? (3 marks)
D1 = y1 xor y2 = Q1 xor Q2
D2 = y2’ = Q2’

2. Using the equations from 1, if the current state of the system is that y1 = 0 and y2 = 0,
what is the next state of the system on the falling clock edge? (4 marks)
Current state: Q1 = y1 = 0 Q2 = y2=0
Then the inputs D1 = 0 and D2 = 1

So on the next clock this is the value the will appear on the output and the next state is
Q1 = 0 Q2 = 1

Question 7:

Implement a 4 bit shift register in verilog. Explain its functionality in terms of frequency.

(10 marks)

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