Arka Educational & Cultural Trust (Regd.

)
Jain Institute of Technology, Davangere
(A Unit of Jain Group of Institutions, Bengaluru)
# 323, Near Veereshwara Punyashrama, Avaragere, Davangere- 577003.

Department of Electronics and Communication Engineering

Academic Year: 2023-24 Second Continuous Internal Evaluation Sem : III
Course Code: BEC306 Course Name: Computer Organization and Architecture
Max Marks: 50 Date: 06/03/2024 Time: 1.30pm–3.00pm
Answer All Questions
Q.
QUESTIONS MARKS RBTL CO
NO
PART - A
a) Define Interrupts? Briefly explain the concept of Interrupt Hardware? 5M L2 CO3
b) With a neat block diagram explain Internal organization of memory 10 M L2 CO4
1
chips?
c) Explain the concept of multiple Bus Organization? 10 M L2,L3 CO5
OR
a) Briefly explain the concept of Enabling and Disabling the Interrupt? 5M L2 CO3
b) Define virtual memory? Explain Read and write operation of Static 10 M L2,L3 CO4
2 memory cell?
c) With a neat diagram explain how registers are transferred from memory 10 M L2,L3 CO5
to processor?
PART – B
a) Explain How Interrupts are handled as a multiple device? 10 M L2 CO3
3 b) With a memory cell diagram? Explain Asynchronous DRAM? 8M L2,L3 CO4
c) Explain the concept of hardwired Control? 7M L2,L3 CO5
OR
a) With a neat block diagram explain DMA? 10 M L2,L3 CO3
b) Briefly Explain different types of ROM memory? 8M L2,L3 CO4
4 c) Explain basic Fundamental concepts of CO? 7M L2,L3 CO5
Co’s Course outcomes (Course Skill Set)
CO1 Explain the basic sub systems of a computer, their organization, structure and
operation.
CO2 Illustrate the concept of programs as sequences of machine instructions.
CO3 Demonstrate different ways of communicating with I/O devices
CO4 Describe memory hierarchy and concept of virtual memory
CO5 Illustrate organization of simple pipelined processor and other computing
systems.

Faculty Signature DQAC HOD

Mr. Sunil M Mrs. Savitra C T Dr. Santosh Herur
 Arka Educational & Cultural Trust (Regd.)
Jain Institute of Technology, Davangere
(A Unit of Jain Group of Institutions, Bengaluru)
# 323, Near Veereshwara Punyashrama, Avaragere, Davangere- 577003.

Department of Electronics and Communication Engineering

Academic Year: 2023-24 Second Continuous Internal Evaluation Sem : III
Course Code: BEC306 Course Name: Computer Organization and Architecture
Max Marks: 50 Date: 06/03/2024 Time: 1.30pm–3.00pm
Answer All Questions
Q.
QUESTIONS MARKS RBTL CO
NO
PART - A
a) Define Interrupts? Briefly explain the concept of Interrupt Hardware? 5M L2 CO3
b) With a neat block diagram explain Internal organization of memory 10 M L2 CO4
1
chips?
c) Explain the concept of multiple Bus Organization? 10 M L2,L3 CO5
OR
a) Briefly explain the concept of Enabling and Disabling the Interrupt? 5M L2 CO3
b) Define virtual memory? Explain Read and write operation of Static 10 M L2,L3 CO4
2 memory cell?
c) With a neat diagram explain how registers are transferred from memory 10 M L2,L3 CO5
to processor?
PART – B
a) Explain How Interrupts are handled as a multiple device? 10 M L2 CO3
3 b) With a memory cell diagram? Explain Asynchronous DRAM? 8M L2,L3 CO4
c) Explain the concept of hardwired Control? 7M L2,L3 CO5
OR
a) With a neat block diagram explain DMA? 10 M L2,L3 CO3
b) Briefly Explain different types of ROM memory? 8M L2,L3 CO4
4 c) Explain basic Fundamental concepts of CO? 7M L2,L3 CO5
Co’s Course outcomes (Course Skill Set)
CO1 Explain the basic sub systems of a computer, their organization, structure and
operation.
CO2 Illustrate the concept of programs as sequences of machine instructions.
CO3 Demonstrate different ways of communicating with I/O devices
CO4 Describe memory hierarchy and concept of virtual memory
CO5 Illustrate organization of simple pipelined processor and other computing
systems.

Faculty Signature DQAC HOD

Mr. Sunil M Mrs. Savitra C T Dr. Santosh Herur