Laboratory Manual

Course Title: HDL Laboratory

20EC407 (0-0-2-1)
4th SEMESTER

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

MALNAD COLLEGE OF ENGINEERING

HASSAN-573202

Syllabus
EC407 HDL Laboratory

Course Objective: The students will have hands-on experience to simulate and debug combinational
and sequential circuits using Xilinx.

Course Outcomes (COs) {with mapping shown against the Program Outcomes (POs)}
Upon completion of the course, students shall be able to:

COs Statement POs

1. Simulate combinational and sequential circuit using ISE simulator. PO1,PO2

2. Target the designed circuits onto CPLD/FPGA chips. PO2

3. Do functional simulation on target chips and Place and route (back end
PO2
design) of the designs on to programmable chips.
Exp Experiment Title
4. Implement peripheral device interfacing. PO2
No.
I Programming
1. Verilog code to realize all the logic gates.
2. Verilog program for Encoder and Decoder without priority and with priority.
3. Verilog code for Multiplexer, Demultiplexer, Comparator, Code converters.
4. Verilog code to describe a Half Adder/Half Subtractor using different modeling styles.
5. Verilog code to describe a Full adder/Full Subtractor using different modeling styles.
6. Verilog code for a) 4-bit parallel adder b)4-bit ALU.
7. Verilog code for SR, D, JK, T-flip-flops.
8. Designing 4-bit Binary counter, BCD counter (Synchronous reset) and any arbitrary
sequence counter.
9. Designing 4-bit Binary counter, BCD counter (Asynchronous reset) and any arbitrary
sequence counter.
10. Modeling of Universal shift registers.
II Interfacing
1. Seven segment display.
2. Stepper Motor.
3. DC Motor.
4. DAC interface.
Reference Books:
1. Nazeih M. Botors –“HDL Programming (VERILOG and Verilog)”, Dream tech publication New Delhi.
2. J Bhaskar, “VERILOG Primer”, Pearson/PHI, New Delhi 2003.

HDL BASICS

HDL stands for Hardware Description Language. HDL can describe a digital system at
several different levels- Behavioral, Data-flow and Structural.
A. Behavioral description: A digital circuit can be described at the behavioral level in
terms of its function or behavior, without giving any implementationdetails.

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B. Data-flow description: A digital circuit can be described at the data-flow level by

giving the logic equation of thatcircuit.
C. Structural description: A digital circuit can be described at the structural level by
specifying the interconnection of the gates or flip-flops that comprise thecircuit.
The basic design units used in HDL are entity and architecture.

Entity:
Entity is the basic design unit used in HDL.It describes the external boundary of the hardware.
General syntax of the entity is
entity entity-name is

port (list of ports: mode

type; list of ports:
mode type;
end [entity-name];

List of ports: which includes all input and output ports

Mode type: which specifies the type of ports such as in, out & input.

Architecture:
It describes the functionality/behavior of the entity.
General syntax of the architecture is
architecture architecture-name of entity-name is

[ declarations ]
begin
architecture body
end [architecture-name];

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Note: 1. [ ]- square brackets indicates optional.

2. Signals and components are declared in the declaration part of thearchitecture.
3. The architecture body contains concurrent or sequentialstatements.

Process:
A common way of modeling sequential logic in HDL uses a process.
General syntax of the processis
process (sensitivity-list)

begin
sequential-statements;
end process;
Sensitivity list contains list of signals. Whenever one of the signals in the sensitivity list changes
the sequential statements in the process body are executed in sequence one time.

If statement:
It is commonly used sequential statement.

The basic IF statement has the form

if condition then

sequentialstatements1
else sequentialstatements2
end if;
The condition is a Boolean expression, which evaluates to TRUE or FALSE. If it is TRUE
sequential statements1 are executed otherwise sequential statements2 are executed.
Elsif statement:
Which is alternative way of writing nested IF statements.
The most general form of the ELSIF statement is
if condition then

sequential statements
{ elsif condition then sequential statements }

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-- 0 or more elsif clauses may be included.

[ else sequential statements ]
end if;
The curly brackets indicate that any number of elsif clauses may be included, and the square
brackets indicate that the else clause is optional.

Conditional assignment statement:

This statement has the form
signal-name <= expression1 when condition1
else expression2 when condition2

…
[ else expressionN ];

This concurrent statement is executed whenever an event occurs on a signal used in one of the
expressions or conditions.If condition1 is true, signal_name is set equal to the value of the
expression1, else if condition2 is true, signal_name is set equal to the value of expression2, etc.,

Case statement:
The case statement has the general form
case expression is

when choice1 => sequentialstatements1

when choice2 => sequentialstatements2
…
[ when others => sequential statements]
end case;
The expression is evaluated first. If it is equal to “choice1”, then “sequential statements1” are
executed. If it is equal to “choice2”, then “sequential statements2” are executed, etc.,
Note:
All the possible values of the expression must be included in the choices. If all the values are not
explicitly given, a “ when others” clause is required in the case statement.

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Variable:
Variable is a HDL object and must be declared with in the process in which they are used and
are local to that process.
The variable declaration has the form
variable list_of_variable_names : type_name [ := initial value ];

Signal:
Signal is a HDL object and it is declared in the declaration part of the architecture.
The signal declaration has the form
signal list_of_signal_names : type_name [ := initial value ];

Array:
The array type and array object declarations have the general forms
type array_type_name is array index_range of element_type;

signal array_name: array_type_name [ :=

initial_values ]; element_type: Which specifies integer or bit or
bit_vectoretc.

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EC407 HDL Laboratory

HDL XILINX PROJECT NAVIGATOR TOOL TUTORIAL

1. Double click on Project Navigator.

2. Select File -> New Project. The New Project dialog box willappear.
3. In the Project line, type in a name for your project. The name example (encoder) is shown
above. Then select a directory for the project files. You may type in the path, or you may
click the browse button to find a directory to place thefiles.
4. Select the Top-Level Module Type value box. For VHDL, Verilog, orABEL designs,
select Verilog. Click Next.

5. The dialog changes to allow you to select device and design flowmethod.
6. AfteryouclickNextfromtheDeviceandDesignFlowdialogbox,theNewSource dialog box
will appear.

7. Create a source file. Click New Source. The New source type dialog box appears. Select
the type of source file you wish to create. Select Verilog Module as the type of our main
design source. Next, enter the name and location for the new sourcedesign.
8. Click Next >. The Define Module dialog willappear.
9. Type the name of each port of your source module into the Port Name column. Specify
whether each port is an input or output by clicking in the Direction column and pulling
down the selectionlist.
10. Click the Next button and the New Source Information dialog box willappear.
11. Examine the information, then click Finish. The Create a New Source dialog box will
appear with your new source file listed.
12. Click Next. Click Next, Click Finish. The first new module is automatically added to
the project as the top-level module of the project. You will now use the HDL Editor
window to define the contents of your design. When complete, Save your design source.
You can repeat the above procedure to create additional design sources in your
projecthierarchy.
13. With the module name (encoder) selected in the Sources window, double-click Check
Syntax (found under Synthesize) to check the VHDL syntax. The transcript on the
Project Navigator will let you know if the syntax is correct and places a green check next
to Check Syntax. If the syntax check fails, a red x willappear.

To Assign Package Pins

1. Select the design module in the Sources window for which you want to assign a pin
package.
2. Double-click the Assign Package Pins process in the Processes for Source window.
14. Select the input and output pins by looking into the ucffile.
15. Enable input pins from switches on FPGA board, observe the output LEDsglowing.

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16. Close the xilinx pacewindow

17. Double click on Generate Programming File then it will show completed process
”Generate Programming File” in ‘consolewindow’
18. Connect the Xilinx JTAG Parallel Download Cable to your PC. Then connect the cable
to your target device JTAG pins as specified in the device data sheet (and turn on the
power to your targetdevice).
19. After you have successfully implemented your design, double-click Configure Device
[IMPACT] in the Processes window under Generate Programming File. This will
generate a JEDEC file and bring up the iMPACT interface. A dialog will appear. Select
Boundary-Scan Mode and clickNext.
20. The Boundary Scan selection mode dialog box will then ask if you want to automatically
connect, or just enter a boundary-scan chain (manually). If you have a demo board,
select the automatic mode, otherwise manually create a boundary-scan chain using Enter
a Boundary-ScanChain.
21. Click Finish. The program automatically detects the chain. When it finds a device, it
brings up a file dialog and the program queries you for a JED or BIT file for the device.
Locate the *.hex file for your design and click OK.
22. Start the iMPACT programming operation by highlighting the device (click on it once).
23. Right click on the device and click on program. The program will be successfully loaded
onto the device.
Simulation using Isim Simulator:
1. After Syntax check, in Source window select the verilog code and change sources for
Behavioral Simulation. Then in processes window double click on Simulate Behavioural
Model.
2. Isim Simulator window pops out.
3. Set the input value through force constant.
4. In waveform window run the simulation. And Verify the output with desired truthtable.

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EC407 HDL Laboratory

PART A (using Xilinx Tool)

PROGRAM 1: Write Verilog code to realize all the logic gates

AIM: To implement and realize the basic gates using Xilinx ISETool.

THEORY: The gate is a digital circuit with one or more input voltages but only one output voltage.
By connecting the different gates in different ways, we can build circuits that perform arithmetic
and other functions.
Logic gates are the basic elements that make up a digital system. The electronic gate is a
circuit that is able to operate on a number of binary inputs in order to perform a particular logic
function. The types of gates available are the NOT, AND, OR, NAND, NOR, EXCLUSIVE-OR,
and EXCLUSIVE-NOR.

TRUTH TABLE FOR ALL GATES:

Input Output
A B op_and op_or op_xor op_not op_nand op_nor op_xnor
0 0 0 0 0 1 1 1 1
0 1 0 1 1 1 1 0 0
1 0 0 1 1 0 1 0 0
1 1 1 1 0 0 0 0 1
VERILOG CODE:

module all_ gates (A, B, op_not, op_or, op_and, op_nor, op_nand, op_xor, op_xnor);
input A, B;
output op_not,op_or,op_and,op_nor ,op_nand ,op_xor, op_xnor;
assign op_not = ~ A;
assign op_or = ~ A | B;
assign op_and = A & B;
assign op_nor = ~(A | B);
assign op_nand = ~( A &B);
assign op_xor = A ^ B;
assign op_xnor = ~( A ^B);
endmodule

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EC407 HDL Laboratory

PROGRAM 2a(i): Write a HDL code to implement the functionality of 8:3 encoder
withoutpriority.

AIM: To implement and realize the 8:3 encoder using Xilinx ISE Tool. And hence verify its truth
table by using on board logic inputs & outputLED’S.

THEORY: An encoder is a digital function that produces a reverse operation from that of decoder.
An encoder has 2n (or less) input lines and n output lines. The output lines generate the binary code
for 2n input variables. The encoder assumes that only one input line can be equal to 1 at any time.
Otherwise the circuit has no meaning. If the encoder has 8 inputs and could have 28
= 256 possible input combinations.

BLOCK DIAGRAM:
8:3
8
ENCODER 3

I Y

TRUTH TABLE:
Input Output
I[7] I[6] I[5] I[4] I[3] I[2] I[1] I[0] Y[2] Y[1] Y[0]
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

VERILOG CODE:
module ENC83(I, Y);
input [7:0] I;
output [2:0] Y;
reg [2:0]Y;
always@ (I)
begin
case(I)
8'b00000001: Y =3'b000;
8'b00000010: Y =3'b001;
8'b00000100: Y =3'b010;

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EC407 HDL Laboratory

8'b00001000: Y =3'b011;
8'b00010000: Y =3'b100;
8'b00100000: Y =3'b101;
8'b01000000: Y =3'b110;
8'b10000000: Y =3'b111;
default: Y = 3'b ZZZ;
endcase
end
endmodule

PROGRAM 2a(ii): Write a HDL code to implement the functionality of 8:3 encoder with
priority.
AIM: To implement and realize the 8:3 encoder using Xilinx ISE Tool. And hence verify its truth
table by using on board logic inputs & outputLED’S.
THEORY: These encoders establish an input priority to ensure that only the highest priority line is
encoded. For example 8-to-3-line priority encoder the inputs are I(0) ,I(1) ,…….I(7).If the priority is
given to an input with higher subscript number over one with a lower subscript number , then if both
I(2) and I(5) are logic-1 simultaneously , the output will be 101 because I(5) has higher priority
overI(2).
TRUTH TABLE:
Input Output
d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] b[2] b[1] b[0]
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 x 0 0 1
0 0 0 0 0 1 x x 0 1 0
0 0 0 0 1 x x x 0 1 1
0 0 0 1 x x x x 1 0 0
0 0 1 x x x x x 1 0 1
0 1 x x x x x x 1 1 0
1 x x x x x x x 1 1 1

VERILOG CODE:
Module penc83(d, b);
input [7:0] d;
output [2:0] b;
reg [2:0] b;
always@ (d)
begin
casex(d)
8'b00000001 : b =3'd0;
8'b0000001x : b =3'd1;
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EC407 HDL Laboratory

8'b000001xx : b = 3'd2;
8'b00001xxx : b = 3'd3;
8'b0001xxxx : b = 3'd4;
8'b001xxxxx : b = 3'd5;
8'b01xxxxxx : b = 3'd6;
8'b1xxxxxxx : b = 3'd7;
default: b = 3'dZ;
endcase
end
endmodule

PROGRAM 2b: Write a Verilog code for implementing 2:4 decoder.

AIM: To implement and realize the 2:4 decoder-using Xilinx ISE Tool. And hence verify its truth
table by using on board logic inputs & output LED’S.

THEORY: Decoder is a logic circuit that accepts a set of inputs which represents a binary number
and activates only the output that corresponds to the input number. In other words, a decoder circuit
looks at its inputs, determines which binary number is present there, and activates the one output
that corresponds to that number – all other outputs remain inactive. For a given input code, the only
output that is active (HIGH) is the one corresponding to the decimal equivalent of the binary input
code. Some of the applications are as follows:
1) Can be used for generating timing or sequencing signals to turn devices ON or OFF at specific
times.
2) Used in memory system of a computer where they respond to the address code generated
by the microprocessor to activate a particular memorylocation.
3) Used in computers for selection of external devices that include printers, modems, scanners,
keyboards, video, monitoretc.,
For selecting one out of ‘n’ inputs for connection to the output, a set of m select inputs are
required.
2m = n
(n = Number of inputs, m = Number of select lines )
Depending upon the code applied at the select inputs one out of 8 data sources is selected &
transmitted to a single output Channel.

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EC407 HDL Laboratory

BLOCK DIAGRAM:

2 2:4 4
DECODER
I Y

TRUTH TABLE:
Input Output
I[1] I[0] Y[3] Y[2] Y[1] Y[0]
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

VERILOG CODE:

module decoder24(I,
Y); input [1:0]I;
output [3:0]Y;
reg [3:0]Y;
always@(I)
begin
case (I)
2'b 00 : Y = 4'b 0001;
2'b 01 : Y= 4'b 0010;
2'b 10 : Y = 4'b0100;
2'b 11 : Y = 4'b1000;
endcase
end
endmodule

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EC407 HDL Laboratory

PROGRAM 2c: Write a HDL code to implement the functionality of 8:1 Multiplexer.

AIM: In this lab you will learn to implement and realize the 8:1 Multiplexer using Xilinx ISE Tool.
And hence verify its truth table by using on board logic inputs & output LED’S.

THEORY: A digital multiplexer is a combinational circuit that selects binary information from one
of many input lines and directs it to a single output line. A multiplexer is also called as data selector,
since it selects one of many inputs and steers the binary information to the output line. The selection
of particular input line is controlled by a set of selection lines. Normally there are 2n input lines and
n selection lines whose bit combinations determine which input isselected.

BLOCK DIAGRAM:

VERILOG CODE:
module mux81(i, sel, y);
input [7:0] i;
input [2:0] sel;
output y;
regy;
always @ ( sel or i )
begin
case (sel)
3' b 000: y = i[0];
3' b 001: y = i[1];
3' b 010: y = i[2];
3' b 011: y = i[3];
3' b 100: y = i[4];
3' b 101: y = i[5];
3' b 110: y = i[6];
3' b 111: y = i[7];
endcase
end
endmodule
PROGRAM 2e(i): Write a HDL code to implement the functionality of 1:4 demux.

AIM: To implement and realize the 1:4 Demux using Xilinx ISE Tool. And hence verify its truth

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EC407 HDL Laboratory

table by using on board logic inputs & output LED’S.

THEORY: A demultiplexer is a circuit that receives the information on a single line and transmits
this information on one of 2n possible output lines. The selection of specific output lines is controlled
by the values of n selection lines. For 1: 4 demultiplexers, the single input variable has a path to all
the four outputs, but the input information is directed to only one of the 4 output lines.

BLOCK DIAGRAM:

TRUTH TABLE:
Select line Output
s[1] s[0] y[3] y[2] y[1] y[0]
0 0 0 0 0 i
0 1 0 0 i 0
1 0 0 i 0 0
1 1 i 0 0 0
VERILOG CODE:
module Demux14(i, s, y);
input i;
input [1:0] s;
output [3:0] y;
reg [3:0]y;
always@ (s)
begin
y = 4'b0000;
case (s)
2'b00:y[0] =i;
2'b01:y[1] =i;
2'b10:y[2] =i;
2'b11:y[3] =i;
endcase
end
endmodule

PROGRAM 2d: Write a HDL code to implement the functionality of 4 bit binary to gray
and gray to binary code converter.
AIM: To implement and realize the Binary to Gray code converter using Xilinx ISE Tool. And

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EC407 HDL Laboratory

hence verify its truth table by using on board logic inputs & output LED’S.

THEORY: A Gray code represents each number in the sequence of integers as a binary string of
length N in an order such that adjacent integers have Gray code representations that differ in only
one bit position. The advantage of the gray code is that only one bit will change as it proceeds from
one number to the next. To obtain gray code, one can start with any bit combination by changing
only one bit from 0 to 1 or 1 to 0 in any desired random fashion, as long as two numbers do not have
identical code assignments.
Simplified equations for binary to gray code are
G0 = B0 B1
G1 = B1 B2
G2 = B2 B3
G3 =B3

Simplified equations for gray to binary code are

B3 = G3
B2 = G3 G2
B1 = B2 G1
B0 = B1 G0

BLOCK DIAGRAM:

TRUTH TABLE:
Binary Gray
B[3] B[2] B[1] B[0] G[3] G[2] G[1] G[0]
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
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1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
VERILOG CODE:
Binary to Gray code conversion
Module B2G(B, G);
input [3:0]B;
output [3:0]G;
assign G[3] = B[3];
assign G[2] =B[2]^B[3];
assign G[1] =B[2]^B[1];
assign G[0] = B[1]^B[0];
endmodule

Gray to Binary code conversion

Module G2B(B, G);
input [3:0]G;
output [3:0]B;
assign B[3] = G[3];
assign B[2] =G[2]^G[3];
assign B[1] =B[2]^G[1];
assign B[0] = B[1]^G[0];
endmodule

PROGRAM 2e(ii): Write a HDL code to implement the functionality of 4-bit comparator.

AIM: To implement and realize the 4- bit Comparator using Xilinx ISE Tool. And hence verify
its truth table by using on board logic inputs & outputLED’S.
THEORY: A comparator is a combinational circuit that compares two numbers, A and B, and
then determines their relative magnitudes. The comparison of two numbers is an operation that
determines if one number is greater than, less than or equal to the other number. The outcome of
the comparison is specified by three binary variables that indicate whether A > B, A = B, A < B.

BLOCK DIAGRAM:

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TRUTH TABLE:

Input Output
a[3] a[2] a[1] a[0] b[3] b[2] b[1] b[0] equ less grt
0 0 0 0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1 0 1 0
1 0 0 0 1 0 0 0 1 0 0
VERILOG CODE:

module comp4(a, b, equ, less, grt);

input [3:0]a,b;
output equ,less,grt;
reg less,equ,grt;
always @(a,b)
begin
less = 0;
equ = 0;
grt = 0;

if (a<b)
less = 1 ;
else if (a == b)
equ = 1 ;
else if (a > b)
grt = 1;
end
endmodule

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PROGRAM 3: Write a VHDL and Verilog code to describe the functions of half adder/ full
adder using Dataflow, Behavioral and Structural modeling style.

AIM: To implement and realize the Full adder using Xilinx ISE Tool. And hence verify
its truth table by using on board logic inputs & outputLED’S.

THEORY: A combinational circuit that performs the addition of two bits is called a half
adder. One that performs the addition of three bits (two significant bits and a previous
carry) is a Full adder. The most basic arithmetic operation is the addition of two binary
digits. This simple addition consists of four possible elementary operations namely 0 + 0
= 0, 0 + 1 = 1, 1 + 0 = 1, 1 + 1 = 10.The first three operations produce a sum whose length
is one digit, but when both augend and addend bits are equal to 1,the binary sum consists
of two digits. The higher significant bit is called carry.
𝑠𝑢𝑚 = 𝐴 ⊕ 𝐵 ⨁𝐶 Carry = AB + BC+CA

TRUTH TABLE:
A B SUM COUT Input Output
0 0 0 0 x y cin sum cout
0 1 1 0 0 0 0 0 0
1 0 1 0 0 0 1 1 0
1 1 0 1 0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

BLOCK DIAGRAM:

VERILOG CODE
Half Adder
Behavioural modelling
module HA(a,b,sum,cout);
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input a,b;
output sum,cout;
always@(a,b)
begin
sum = a^b;
cout = a & b;
end
endmodule

Data Flow modelling

module HA(a,b,sum,cout);
input a,b;
output sum,cout;
sum = a^b;
cout = a & b;
endmodule

Full adder
Behavioural modelling
module FA(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
always@(a,b,cin)
begin
sum = a^b^cin;
cout = (a & b) ^ (b&cin) ^ (a&cin);
end
endmodule

Data Flow modelling

module HA(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
sum = a^b^cin;
cout = (a & b) ^ (b&cin) ^ (a&cin);
endmodule
Structuralmodelling
module fa(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire t1,t2,t3;
begin
HA ha1(a,b,t1,t2);
HA ha2(t1,cin,sum,t3);
OR or(t2,t3,cout);
endmodule

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module HA(x,y,s,co);
input x,y;
output s,co;
s = x^y;
co = x & y;
endmodule

module or(x,y,z);
input x,y;
output z;
z = x|y;
endmodule

PROGRAM 4: Write a VHDL and Verilog code to describe the functions of half Subtractor/
full Subtractor using Dataflow, Behavioral and Structural modeling style.
AIM: To implement and realize the Half Subtractor using Xilinx ISE Tool. And hence
verify its truth table by using on board logic inputs & outputLED’S.

Theory:The subtraction of 2 binary digits produces two outputs termed

as difference and borrow. The simplest possible subtraction of 2-bit binary digits consists of four
possible operations, they are 0-0 = 00, 0-1 = 11, 1-0 = 10 and 1-1 = 00. The operations 0-0, 1-
0 and 1-1 produces a subtraction of 1-bit output whereas, the remaining operation 0-1 produces
a 2-bit output. They are referred as difference and borrow bit respectively. This borrow bit is
used for subtraction of the next higher pair bit.The full subtractor is a combinational circuit
which is used to perform subtraction of three input bits: the minuend, subtrahend , and borrow in
. The full subtractor generates two output bits: the difference and borrow out.

BLOCK DIAGRAM:

TRUTH TABLE:
Half Subtractor:

X Y diff bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

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Full Subtractor: Input Output

x y bin diff Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
VERILOG CODE
Half Subtractor
Structuralmodelling
module hs (a,b,d,br);
input a,b;
output d,br,;
wire a_;
xor_g xor 1(a,b,d);
not_g not1(a,a_);
and_g and1(a_,b,br);
endmodule

module xor_g(a,b,d);
input a,b;
output d;
assign d=a^b;
endmodule

module not_g(a,a_);
input a;
output a_;
assign a_=~a;
endmodule

module and_g(a_,b,br);
input a_,b;
output br;
assign br=(a_)&b;
endmodule

Data Flow
Module hs (a,b,d,br);
Input a,b;
Output d,br;
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Assign d=a^b;
Assign br=~a&b;
endmodule

Behavioral
Module hs (a,b,d,br);
Input a,b;
Output d,dr;
reg d,br;
Always @(a,b)
begin
d=a^b;
br=~a & b;
end
endmodule

Full subtractor

Dataflow model
Module fs(a,b,c,d,br);
Input a,b,c;
Output d,br;
assign d=a^b^c;
assign br=(~a&c)|(~a&b)|(b&c);
endmodule

Behavioral
Module fs(a,b,c,d,br);
Input a,b,c;
Output d,br;
Reg d,br;
always @(a,b,c)
Begin
d=a^b^c;
br=(~a&c)|(~a&b)|(b&c);
end
endmodule

Structural:
Module fs(a,b,c,d,br);
Input a,b,c;
Output d,br;
Wire u,v,w,a1;
xor_g xor1(a,b,c,d);
not_g not1(a,a1);

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and1 and1(a,b,u);
and1 and2(b,c,v);
and1 and3(a1,c,w);
or_g or1(u,v,w,br);
endmodule

module xor_g(a,b,c,d);
input a,b,c;
output d;
assign d = a ^ b ^ c;
endmodule

module not_g(a,a1);
input a;
output a1;
assign a1 = ~a;
endmodule

module and1(x,y,z);
input x,y;
output z;
assign z = x & y;
endmodule

module or(x,y,z);
input x,y;
output z;
assign z = x | y;
endmodule

PROGRAM 5: Write a VHDL and Verilog code to parallel adder using Structural
modeling style.

THEORY: Parallel adder is a combinatorial circuit (not clocked, does not have any memory
and feedback) adding every bit position of the operands in the same time. Thus it is requiring
number of bit-adders(full adders+ 1 half adder) equal to the number of bits to be added.

BLOCK DIAGRAM:

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VERILOG CODE:

4-Bit Parallel Adder:

Module PA(A,B,Cin,S,Co);
Input [3:0]A, [3:0]B, Cin;
Output [3:0]S, Co;
Wire x,y,z;
FA fa_1(A0,B0,Cin,S0,x);
FA fa_2(A1,B1,x,S1,y);
FA fa_3(A2,B2,y,S2,z);
FA fa_4(A3,B3,z,S3,Co);
Endmodule

Module FA(a,b,cin,sum,cout);
Input a,b,cin;
Output sum,cout;
Assign sum = a ^ b ^ cin;
Assign cout = (a & b) | (b & cin) | (a & cin);
endmodule

PROGRAM6: Write a Verilog code to model 4 bit ALU.

• ALU should use combinational logic to calculate an output based on the four bit op-codeinput.

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• ALU should pass the result to the out bus when enable line in high, and tri-state the out
bus when the enable line islow.
• ALU should decode the 4 bit op-code according to the example givenbelow.
OPCODE ALU Operation
1. A+B
2. A-B
3. A Complement
4. A*B
5. A AND B
6. A OR B
7. A NAND B
8. A XOR B

AIM: To implement and realize the 4-bit ALU using Xilinx ISE Tool.

THEORY: The arithmetic logic unit (ALU) is a digital circuit that calculates an
arithmetic operation (like an addition, subtraction, etc.) and logic operations (like XOR,
AND, NOT etc.,) between two numbers. The ALU is a fundamental building block of the
central processing unit of a computer. Many types of electronic circuits need to perform
some type of arithmetic operation, so even the circuit inside a digital watch will have a tiny
ALU that keeps adding 1 to the current time, and keeps checking if it should beep the
timer,etc.

VERILOG CODE:

module alu32(A, B, Opcode, Enable, Output);

input [31:0]A;
input [31:0]B;
input [3:0]Opcode; input Enable;
output reg [63:0]Output;
always@( A, B, Opcode, Enable)
begin
op = 64'd0;
if ( Enable == 0)
Output = 64'bz;
Else
case(Opcode)
4'd1: Output [32:0] = A + B;
4'd2: Output [31:0] = A - B;
4'd3: Output [31:0] = ~A;

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4'd4: Output = A * B;
4'd5: Output [31:0] = A & B;
4'd6: Output [31:0] = A | B;
4'd7: Output [31:0] = ~(A & B);
4'd8: Output [31:0] = A ^ B; endcase
End
endmodule

PROGRAM 7a: Develop the verilog code for SR flip flop.

AIM: To implement and realize the SR-flip-flops using Xilinx ISE Tool. And hence verify
its truth table by using on board logic inputs & outputLED’S.
THEORY: The basic flip-flop is an asynchronous sequential circuit. The RS flip-flop
consists of a basic NOR flip-flop and two AND gates. The outputs of the two NAND gates
remain at ‘0’ as long as the clock pulse is ‘0’, regardless of the S and R input values.
When the clock pulse goes to ‘1’, the information from the S and R inputs is allowed to
reach the basic flip-flop. The set state is reached with S = 1 and R = 0 and Clock pulse = 1.
To change it to clear state the inputs must be S = 0, R = 1 and Clock pulse = 1. When both
S = R = 1, the occurrence of the clock pulse causes both outputs to go to0.

BLOCK DIAGRAM:

TRUTH TABLE:
Input Output
SR[1] SR[0] Q+ ACTION
0 0 Q No Change
0 1 0 Reset
1 0 1 Set
1 1 z Illegal
VERILOG CODE:

module srff(SR, clk, reset,Q, Qb);

input [1:0] SR;
input clk, reset;

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output Q,Qb;
reg Q,Qb;
// All commented lines are to be uncommented to implement on FPGA
// wire clkd;
// reg [22:0] divider;
// always@ (posedge clk)
// begin
// divider = divider +1;
//end
// assign clkd = divider[20];
always@ (posedgeclk)
if ( reset == 0 )
begin
case (SR)
2'b00 : Q = Q ;
2'b01 : Q = 0;
2'b10 : Q = 1;
2'b11 : Q = 1'bZ ;
endcase
end
else
Q = 1'b0;
Qb = ~Q;
end
endmodule

PROGRAM 7b: Develop the Verilog for JK flip flop.

AIM: To implement and realize the JK-flip-flops using Xilinx ISE Tool. And hence verify
its truth table by using on board logic inputs & outputLED’S.

THEORY: A JK flip-flop is a refinement of the RS flip-flop in that the indeterminate state

of the RS flip-flop is defined in the JK flip-flop. Inputs J and K behave like inputs S and R
to set and clear the flip- flop. The JK flip-flop behaves like an RS flip-flop except when
both J and K are equal to 1. When both J and K are 1, the clock pulse is transmitted through
one AND gate only-the one whose Q=1, the output of upper AND gate becomes 1, upon
application of clock pulse, and the flip-flop is cleared. If Q’ is 1, the output of lower AND
gate becomes a 1, and the flip-flop is set.

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BLOCK DIAGRAM:

TRUTH TABLE:
Input Output
J K Q+ ACTION
0 0 Q No Change
0 1 0 Reset
1 0 1 Set
1 1 ~Q Toggle
VERILOG CODE:
module jkff(jk,
clk, reset, q, qb);
input [1:0]jk;
input clk,reset; output reg q,qb;
// All commented lines are to be uncommented to implement on FPGA
// wire sclk;
// reg [22:0] divider;
// always@ (posedge clk)
// begin
// divider <=divider+1;
// end
// assign sclk = divider[20];
always@(posedgeclk) // to implement on FPGA replace clk bysclk
begin
if(reset == 0)
begin
case(jk)
2'b00: q = q;
2'b01: q = 0;
2'b10: q = 1;
2'b11: q = ~q;
endcase
end
else
q = 1'b0;
qb = ~q; end

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endmodule

PROGRAM 7c: Design the verilog code for D flip flop.

AIM: To implement and realize the D-flip-flops using Xilinx ISE Tool. And hence verify its
truth table by using on board logic inputs & output LED’S.

THEORY: A flip-flop is a binary cell capable of storing one bit of information. A flip-flop
circuit has two outputs, one for the normal value and one for the compliment of bit stored in
it. A flip-flop circuit can maintain a binary state indefinitely until directed by an input signal
to switch states. The major difference between various flip-flops is in number of inputs they
possess and in the manner in which the inputs affect the binary state.
The D flip-flop receives the designation from its ability to transfer data into a flip-flop.
It’s basically an RS flip-flop with an inverter in the R input. This type of flip-flop sometimes
called as D- latch.

BLOCK DIAGRAM:

TRUTH TABLE:

Input Output
D Q+ Action
0 0 No Change
1 1 Set

VERILOG CODE:
Module dff(d,clk,reset, q,qb);
input d,clk,reset;
output q,qb;
reg q,qb;
// All commented lines are to be uncommented to implement on FPGA
// wire clkd;
// reg [22:0] divider;
// always@ ( posedge clk)
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//begin
//divider = divider +1;
//end
//assign clkd = divider[20];

always@ ( posedgeclk ) // to implement on FPGA

//replace clk byclkd begin
if ( reset == 0)
begin
q= d;
end
else
q = 1'b0;
qb = ~q;

endmodule

PROGRAM 7d: Develop the Verilog code for T flip flop.

AIM: To implement and realize the T-flip-flops using Xilinx ISE Tool. And hence verify its
truth table by using on board logic inputs & output LED’S.
THEORY: The T flip-flop is a single input version of the JK flip-flop. The T flip-flop is
obtained from JK flip-flop if both the inputs are tied together. The designation T comes from
the ability of the flip-flop to toggle. Regardless of the present state, it assumes the complement
state when the clock pulse occurs while input T is logic is 1.
BLOCK DIAGRAM:

TRUTH TABLE:

Input Output
T Q+ Action
0 Q No Change
VERILOG CODE: 1 ~Q Toggle

module tff(t,clk,reset, Q,Qb);

input t,clk,reset;

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output q,qb;
reg q,qb;
// All commented lines are to be uncommented to implement on FPGA
//wireclkd;
//reg[20:0]divider;
//always@ ( posedge clk)
//begin
//divider = divider +1;
//end
//assign clkd = divider[20];
always@ (posedgeclk) // to implement on FPGA replace clk by clkd
begin
if ( reset == 0 )
begin
if ( t == 1)
Q = ~Q;
else
Q = Q;
end
else
Q = 1'b0;
Qb = ~Q;
end
endmodule

PROGRAM 8a: Design a 4 bit binary counter (up down counter) using Verilog Code.

AIM: To implement and realize the 4 bit binary counter using Xilinx ISE Tool. And hence
verify its truth table by using on board logic inputs & output LED’S.

THEORY: Binary counters are the simplest form of counters. An N-bit binary counter counts from
0 to (2N - 1) and back to 0 again. A binary counter can be constructed from J-K flip-flops by taking
the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to
1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle
is produced in the second cell, and so on down to the fourth cell. This device is sometimes called
a "ripple through"counter.
BLOCK DIAGRAM:

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TRUTH TABLE:

UP COUNTING SEQUENCE :FOR ud=1 DOWN COUNTING SEQUENCE: FOR ud=0

CLK q(3) q(2) q(1) q(0) CLK q(3) q(2) q(1) q(0)
↑ 0 0 0 0 ↑ 1 1 1 1
↑ 0 0 0 1 ↑ 1 1 1 0
↑ 0 0 1 0 ↑ 1 1 0 1
↑ 0 0 1 1 ↑ 1 1 0 0
↑ 0 1 0 0 ↑ 1 0 1 1
↑ 0 1 0 1 ↑ 1 0 1 0
↑ 0 1 1 0 ↑ 1 0 0 1
↑ 0 1 1 1 ↑ 1 0 0 0
↑ 1 0 0 0 ↑ 0 1 1 1
↑ 1 0 0 1 ↑ 0 1 1 0
↑ 1 0 1 0 ↑ 0 1 0 1
↑ 1 0 1 1 ↑ 0 1 0 0
↑ 1 1 0 0 ↑ 0 0 1 1
↑ 1 1 0 1 ↑ 0 0 1 0
↑ 1 1 1 0 ↑ 0 0 0 1
↑ 1 1 1 1 ↑ 0 0 0 0

VERILOG CODE:
module unvcnt(d, clk,reset,ld,ud, q);
input [3:0]d;
input clk,reset,ld,ud;
output [3:0]q;
reg [3:0]q;
// All commented lines are to be uncommented to implement on FPGA
// wire clkd;
// reg [22:0] divider;
// always@( posedge clk)
// begin
// divider = divider+1;
// end
// assign clkd = divider [20];
always@ ( posedge clk) // to implement on FPGA replace clk by clkd
begin
if (reset)
q = 4'd0;
else if (ld == 1)
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q = d;
else if (ud == 1)
q = q + 1;
else
q = q - 1;
end
endmodule

PROGRAM 8b: Design a 4 bit BCD counter (0 – 9) (synchronous reset).

AIM: To implement and realize the 4 bit BCD counter using Xilinx ISE Tool. And hence verify its
truth table by using on board logic inputs & output LED’S.

THEORY: A counter is a register capable of counting the number of clock pulses arriving at its
clock input. There are two types of counters, synchronous and asynchronous. In synchronous
counter the common clock input is used to connect all the flip-flops and they are clocked
simultaneously. In Asynchronous counters the external clock pulse clocks the first flip-flop and
then each successive flip-flop is clocked by the output of previous flip-flop. BCD stands for Binary
Coded Decimal. A BCD counter has four outputs usually labeled A, B, C, D. By convention A is
the least significant bit, or LSB. In other words, the counter outputs follow a binary sequence
representing the decimal numbers 0-9.... this is why its called as binary coded decimal counter.

BLOCK DIAGRAM:

TRUTH TABLE:

UP COUNTING SEQUENCE : FOR ud=1 DOWN COUNTING SEQUENCE: FOR ud=0

CLK q(3) q(2) q(1) q(0) CLK q(3) q(2) q(1) q(0)
↑ 0 0 0 0 ↑ 1 0 0 1
↑ 0 0 0 1 ↑ 1 0 0 0
↑ 0 0 1 0 ↑ 0 1 1 1
↑ 0 0 1 1 ↑ 0 1 1 0
↑ 0 1 0 0 ↑ 0 1 0 1
↑ 0 1 0 1 ↑ 0 1 0 0

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↑ 0 1 1 0 ↑ 0 0 1 1
↑ 0 1 1 1 ↑ 0 0 1 0
↑ 1 0 0 0 ↑ 0 0 0 1
↑ 1 0 0 1 ↑ 0 0 0 0

VERILOG CODE:
module BCD_counter(din, clk,ld,ud,reset, q);
input [3:0] din;
input clk,ld,ud,reset;
output reg [3:0]q;
// All commented lines are to be uncommented to implement on FPGA
// wire clkd;
// reg [22:0] divider;
// always@ ( posedge clk ) begin
// divider = divider + 1;
// end
// assign clkd = divider[20];
always@(posedge clk)
begin // to implement on FPGA replace clk by clkd
if (~ reset)
begin
if ( ld == 1 )
q = din;
else if ( ud == 1)
if ( q == 4'b1001)
q = 4'b0000;
else
q = q+1;
else if ( ud == 0) begin
if ( q == 4'b0000)
q = 4'b1001;
else
q = q - 1;
end
end
else
q = 4'b0000;
end
endmodule

PROGRAM 8c: Write a Verilog code for 4 bit any sequence counter Example: 0,1,2,3,6,5,7 and
repeats.
AIM: To implement and realize the 4 bit BCD counter using Xilinx ISE Tool. And hence verify its
truth table by using on board logic inputs & output LED’S.
VERILOG CODE:
module arb_counter(clk, reset, count);
input clk;
input reset;
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output [3:0] count;

reg [3:0] count;
reg [3:0] state;
// All commented lines are to be uncommented to implement on FPGA
// wire clkd;
// reg [22:0] divider;
// always@ ( posedge clk ) begin
// divider = divider + 1;
// end
// assign clkd = divider[20];
always @ (posedge clk or posedge reset) // to implement on FPGA replace clk by clkd
begin
if (reset == 1)
begin
count <= 0;
state <= 0;
end
else
case (state)
0: begin
count <= 0;
state <= 1;
end
1: begin
count <= 1;
state <= 2;
end
2: begin
count <= 2;
state <= 3;
end
3: begin
count <= 3;
state <= 4;
end
4: begin
count <= 6;
state <= 5;
end
5: begin
count <= 5;
state <= 6;
end
6: begin
count <= 7;
state <= 0;
end

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EC407 HDL Laboratory

default: state <= 0;

endcase
end
endmodule

Part – B (Interfacing using VHDL/Verilog)

PROGRAM 1: Write a HDL code to interface Hex key pad and display the key code on seven
segment display.

AIM: To implement VHDL Code to interface Hex keypad and to have display on seven segment
display.

THEORY:
In this lab we will learn how to interface keyboard, seven-segment display and Input Output LEDs
to FPGA using Xilinx ISE Tool. Write the functionality in Xilinx Project Navigator, synthesize the
design with XST, and take the synthesized design through the Xilinx implementation tools.
Download the bit stream file into VTU kit and see the scrolling display using keyboard.

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OBJECTIVE:
After completing this lab, you will be able to
Use the keyboard, Input / Output LEDs to perform various functions that can be implemented
using FPGA.
Observe the output on the display / LEDs.

STEPS TO IMPLEMENT THE KEYDISPLAY:
Step 1: Generate the bitstream for seven segment display and download it.
Step 2: Apply input through SW1-SW4 switches. Observe input/output LEDs. LEDs should glow
with proper brightness.
Step 3: Observe the scrolling of hexadecimal numbers by pressing respective keys (k1-k16).

EXPERIMENTAL SET UP:

VHDL CODE:
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity GKBDSP3 is
Port (clk: in std_logic;
rst: in std_logic;
row: out std_logic_vector (3 downto 0);
col: in std_logic_vector ( 3 downto 0);
En1,En2,En3,En4,En5,En6 : out std_logic;
seg_dis: out std_logic_vector (6 downto 0));
end GKBDSP3;

architecture behave of GKBDSP3 is

type state is (s0, s1, s2, s3);
signal st:state:= s0;
signal clkdiv: std_logic;
signal col1, col2: std_logic_vector (3 downto 0);
signal clk_div: std_logic_vector (15 downto 0);
begin
En1 <= '0'; En2 <= '0'; En3 <= '0';

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En4 <= '0'; En5 <= '0'; En6 <= '0';

clkdiv <= clk_div (15);

process (clk, rst)
begin
if rst<='0'then
if clk' event and clk = '1' then
clk_div <= clk_div + '1';
else
null;
end if;
end if;
end process;

process (clkdiv)
begin
if clkdiv' event and clkdiv = '1' then
col1 <= col;
col2 <= col1;

case st is
when s0 => row <= "1110";
case col2 is
when "1110" => seg_dis <= "0111111";
when "1101" => seg_dis <= "0000110";
when "1011" =>seg_dis <= "1011011";
when "0111"=> seg_dis <= "1001111";
when "1111" => st <= s1;
when others => null;
end case;
when s1 => row <= "1101";
case col2 is
when "1110" =>seg_dis <= "1100110";
when "1101" =>seg_dis <= "1101101";
when "1011" => seg_dis <= "1111101";
when "0111"=> seg_dis <= "0000111";
when "1111" => st <= s2;
when others => null;
end case;

when s2 =>row <= "1011";

case col2 is
when "1110" => seg_dis <= "1111111";
when "1101" =>seg_dis <= "1101111";
when "1011" => seg_dis <= "1110111";
when "0111"=> seg_dis <= "1111100";
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EC407 HDL Laboratory

when "1111" =>st <= s3;

when others =>null;
end case;

when s3 =>row <= "0111";

case col2 is
when "1110" =>seg_dis <= "0111001";
when "1101" => seg_dis <= "1011110";
when "1011" => seg_dis <= "1111001";
when "0111"=>seg_dis <= "1110001";
when "1111" => st <= s0;
when others => null;
end case;
end case;
end if;
end process;
end behave;

PROGRAM 2: Write a HDL code to Control speed and direction of DC motor

AIM: To implement VHDL Code to Control speed and direction of DC motor by interfacing DC
motor with FPGA board.

THEORY: The DC motor provided onboard interface with the following specification-
• DC MOTOR Interface: Input Voltage – 12 VDC
• DC Motor Connector Details: By giving control signals to these pins the Speed and
Direction of Rotation of DC Motor can be controlled.
Table 1: DC motor ConnectorJ12

Coil_A0 Coil_A1
1 2
VHDL CODE:
library ieee;
use ieee.std_logic_1164.all;

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use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity DCMOTORSP3 is
port(start,dir,clk:in std_logic;
pwm_out:out std_logic;
out_dc:out std_logic_vector(1 downto 0)
);
end DCMOTORSP3;

architecture dcmotor_a of DCMOTORSP3 is

signal clk1: std_logic;
signal div: std_logic_vector(22 downto 0);
begin
process(clk,start)
begin
if(start='0') then
div<="00000000000000000000000";
elsif(clk' event and clk='1')then
div<= div+1;
end if ;
clk1<=div(14);
end process;
process(clk1)
begin
if(clk1' event and clk1='1')then
if start='0' then
out_dc<="00";
elsif start='1' and dir='1' then
out_dc<="10";
pwm_out<='1';
elsif start='1' and dir='0' then
out_dc<="01";
pwm_out<='1';
end if;
end if;
end process;
end dcmotor_a;

PROGRAM 3: Write a HDL code to control speed and direction of stepper motor.

AIM: To implement VHDL Code to Control speed and direction of DC motor by interfacing DC
motor with FPGA board.

THEORY: The stepper motor is an electrical motor, which converts digital electric input into a
rotary motion. Stepper Motor is the one that revolves through a fixed angle for each pulse applied

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EC407 HDL Laboratory

to the logic sequences. By controlling pulse rate stepper motor speed can be controlled. Stepper
Motor is also called as a Single Stack Variable Reluctance Motor. If the switching is carried out
in a sequence, the rotor will rotate with stepped motion. The unipolar stepper motor, both
permanent magnet and hybrid stepping motors with 5 or 6 wires has two coils, simple lengths of
wound wire. Each coil has a centre tap - a wire coming out from the coil that is midway in length
between its two terminals. Because of the long length of the wound wire, it has a significant
resistance (and inductance). You can identify the center tap by measuring resistance with a
suitable ohm-meter. The resistance from a terminal to the center tap is half the resistance from the
two terminals of a coil. As shown in the figure, the current flowing from the center tap of winding
1 to terminal A1 causes the top stator pole to be a north pole while the bottom stator pole is a
south pole. This attracts the rotor into the position shown. If the power to winding 1 is removed
and winding 2 is energised, the rotor will turn 30 degrees, or one step.

OBJECTIVE:

To Implement a Stepper Motor Controller in an FPGA 

To verify & change speed of Stepper Motor by varying input frequency.
To verify & change the direction of rotation of Motor.
SPECIFICATIONS OF MOTOR:
Voltage Rating – 12 V DC
Step Angle –1.80.
Steps/Revolution-200.

PROCEDURE:

Step 1: Double click on Configure Device to download the bitstream.

Step 2: Connect stepper motor to the protoboard as shown below.

Step 3: Set the DIP switch IL0 to change the direction of rotation.
For clockwise rotation : IL0 = 0.

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For anticlockwise rotation : IL0 = 1.

Step 4: Set the DIP switches IL1 and IL2 to change the speed of motor.

EXPERIMENTAL SET UP:

VHDL CODE:
Library IEEE; -- library declaration
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity STEPPERSP3 is -- entity declaration

Port (clk1: in STD_LOGIC;
rst: in STD_LOGIC; --start, stop:in std_logic;
dir: in std_logic; -- dir1, dir2: in std_logic;
out_stm: out STD_LOGIC_vector (3 downto 0));
end STEPPERSP3;

architecture stm_st_a of STEPPERSP3 is -- architecture declaration

type state_type is (s0,s1,s2,s3);
signal state: state_type; -- signal assignment
signal div: std_logic_vector (20 downto 0);
signal Clk, clkwise, start: std_logic;

begin
process (clk1, rst)
begin
if (rst='1') then
div<= (others=>'0');
elsif (clk1' event and clk1 = '1') then
div <= div + 1;
end if;
end process;
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Clk <=div(19);

process (Clk, dir) -- direction control

begin
if Clk='1' and Clk' event then
if dir='1' then
clkwise<=not clkwise;
end if;
end if;
end process;
process (Clk, rst, clkwise)
begin
if (rst='1') then
state <=s0;
elsif Clk' event and Clk='1' then
if clkwise='0' then
case state is
when s0=> state<=s1;
when s1=> state<=s2;
when s2=> state<=s3;
when s3=> state<=s0;
when others=>null;
end case;
elsif clkwise='1' then
case state is
when s3=> state<=s2;
when s2=> state<=s1;
when s1=> state<=s0;
when s0=> state<=s3;
when others=>null;
end case;
end if;
end if;
end process;

with state select

out_stm<= "0110" when s0,
"1011" when s1,
"1001" when s2,
"0101" when s3;
end stm_st_a;

PROGRAM 4a: Write a VHDL code to generate Sine wave using DAC.

AIM: To implement VHDL Code to generate Sine wave using DAC and to change the frequency.

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THEORY:Analog signals represent real physical parameters with accuracy, but it is difficult to process
or store them. It is necessary to translate an Analog signal into a digital signal. Similarly, a digital signal
needs to be translated into an analog signal to represent a physical quantity. Quite often it is also necessary
to decode any digital signal, the most obvious method is to use D/A converter for each signal. DAC-
Digital to analog conversion involves translation of digital signal into equivalent analog signal.
Applications of DAC’s include digital voltmeters, peak detectors, panel meters, programmable gain and
attenuation, and stepping motor drive.

Specifications of DAC TLV5619:

• Resolution - 12 bits
• Conversion time - 100 ns
• Settling time – 600 nSec
• Output Range - 0 to 5 Volts, Single ended (Unipolar)

The two important aspects of the D/A converter are the Resolution & Accuracy of the conversion.
• Accuracy is a measure of how close the actual output voltage is to the theoretical output voltage.
• Resolution is the smallest increment in output voltage and is determined by the LSB.

OBJECTIVE:
After completing this lab you will be able to
• Perform the basic design flow for generating Counter
• It will help you to understand the behavior of a DAC it should show a proper RAMP signal at
the output.
• Synthesize a design using Xilinx Too
• Implement a design using the Xilinx implementation tools.

DESIGN DESCRIPTION:

You can design a counter, which will give you a ramp waveform of Amplitude: 5V at the output of
DAC. Hence a counter, that is applied as an input to get equivalent analog (ramp) signal at the output.
If the full scale Analog voltage is 5 V, the smallest unit or the LSB is equivalent to 1/2n of 5 V. This
is defined as resolution. In this example, DAC is 12 bit so that (5V/212)

Note:- Full scale voltage is 5V

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For 5 V, LSB = 5/212

MSB = ½ full scale = 2.5V
Full scale output = (Full scale Value – (1 LSB))
= 5V-(5V/212). ------For TLV5619
= 4.988V.
EXPERIMENTAL SET UP:

PROCEDURE:
Step 1: Generate the bitstream for DAC counter project and download it.
Step 2: Connect the CRO probe to the DAC Out terminal to observe “Ramp waveform” as shown in
figure below. Thus the digital input applied (counter) is converted into an analog ramp waveform.

VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sinewave is
Port ( clk,rst : in std_logic;
dac_out : out std_logic_vector(0 TO 7));
end sinewave;

architecture Behavioral of sinewave is

signal c1:std_logic_vector(7 downto 0);
signal i: integer range 0 to 179;
type sine is array(0 to 179) of integer range 0 to 255;
constant value: sine:=(128,
132,136,141,154,150,158,163,167,171,175,180,184,188,192,195,199,203,206,210,213,216,
220,223,226,228,231,234,236,238,241,243,244,246,247,248,249,250,251,252,253,254,255,
255,255,255,255,254,254,253,252,251,249,246,244,243,241,238,236,234,231,228,226,223,
220,216,213,210,206,203,199,195,192,188,184,180,175,171,167,163,158,154,150,145,141,
136,132,128,123,119,114,110,105,101,97,92,88,84,80,75,71,67,64,60,56,52,49,45,42,39,35
,32,29,27,24,21,19,17,14,12,11,9,7,6,4,3,2,1,1,0,0,0,0,0,0,0,0,1,1,2,3,4,5,6,7,9,11,12,14,17,
19,21,24,27,29,32,35,39,42,45,49,52,56,60,64,67,71,75,80,84,88,92,97,101,105,110,114,11
9,123,128);
begin

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process(clk, rst)
begin
if(rst='1') then
c1<=(others=>'0');
elsif(clk' event and clk='1') then
c1<= c1+1;
end if;
end process;
process(c1(3))
begin
if(c1(3)' event and c1(3)='1') then
dac_out<= conv_std_logic_vector(value(i), 8);
i<=i+1;
if(i=179) then
i<= 0;
end if;
end if;
end process;
end behavioral;

PROGRAM 4b: Write a VHDL code to generate Square wave using DAC.

AIM: To implement VHDL Code to generate Square wave using DAC and to change the frequency.

VHDL CODE :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DACSQR is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dac : out STD_LOGIC_VECTOR (7 downto 0));
end DACSQR;

architecture Behavioral of DACSQR is

signal temp:STD_LOGIC_VECTOR (3 downto 0);
signal cnt:STD_LOGIC_VECTOR (0 to 7);
signal en:STD_LOGIC;
begin
process(clk)
begin
if rising_edge(clk) then
temp<=temp+'1';

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end if;
end process;
process(temp(2))
begin
if rst='1' then cnt<="00000000";
elsifrising_edge(temp(2)) then
if cnt<255 and en='0' then
cnt<=cnt+1;
en<='0';
dac<="00000000";
elsif
cnt=0 then en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
end if;
end process;
end Behavioral;

PROGRAM 4c: Write a VHDL code to generate Triangle wave using DAC.

AIM: To implement VHDL Code to generate Triangle wave using DAC and to change the frequency.

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DACTRI is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dac : out STD_LOGIC_VECTOR (7 downto 0));
end DACTRI;

architecture Behavioral of DACTRI is

signal temp:STD_LOGIC_VECTOR (3 downto 0);
signal cnt:STD_LOGIC_VECTOR (0 to 8);
signal en:STD_LOGIC;
begin
process(clk)
begin
if rising_edge(clk) then
temp<=temp+'1';
end if;

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end process;
process(temp(3))
begin
if rst='1' then cnt<="000000000";
elsif
rising_edge(temp(3)) then
cnt<=cnt+'1';
if cnt(0)='1' then
dac<=cnt(1 to 8);
else
dac<=not(cnt(1 to 8));
end if;
end if;
end process;
end Behavioral;

PROGRAM 4d: Write a VHDL code to generate Ramp wave using DAC.

AIM: To implement VHDL Code to generate Ramp wave using DAC and to change the frequency.

VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity rampwave is
Port ( rst,clk : in STD_LOGIC;
dac : out STD_LOGIC_vector(7 downto 0));
end rampwave;
architecture Behavioural of rampwave is
signal temp:std_logic_vector(7 downto 0);
signal cnt:std_logic_vector(0 to 7);
begin
process(clk)
begin
if clk='1' and clk' event then
temp<=temp+'1';
end if;
end process;
process(temp(7))
begin
if rst='1' then
cnt<=(others=>'0');
elsif(temp(7)='1' and temp(7)' event) then
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cnt<=cnt+15;
end if;
end process;
dac<=cnt;
end Behavioural;

PROGRAM 4e: Write a VHDL code to generate Sawtooth wave using DAC.

AIM: To implement VHDL Code to generate Sawtooth wave using DAC and to change the frequency.

VHDL CODE:

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SAWTOOTH is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dac : out STD_LOGIC_VECTOR (7 downto 0));
end SAWTOOTH;
architecture Behavioral of SAWTOOTH is
signal temp:STD_LOGIC_VECTOR (3 downto 0);
signal cnt:STD_LOGIC_VECTOR (0 to 8);
begin
process(clk)
begin
if rising_edge(clk) then
temp<=temp+'1';
end if;
end process;
process(temp(3))
begin
if rst='1' then cnt<="000000000";
elsif
rising_edge(temp(3)) then
cnt<=cnt+'1';
end if;
end process;
dac<=cnt(1 to 8);
end Behavioral;

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