MODULE 3: MEMORY SYSTEM

5.1 BASIC CONCEPTS:

The maximum size of the Main Memory (MM) that can be used in any computer is determined
by its addressing scheme. For example, a 16-bit computer that generates 16-bit addresses is capable of
addressing upto 216 =64K memory locations. If a machine generates 32-bit addresses, it can access upto
232 = 4G memory locations. This number represents the size of address space of the computer.
If the smallest addressable unit of information is a memory word, the machine is called
word-addressable. If individual memory bytes are assigned distinct addresses, the computer is called
byte-addressable. Most of the commercial machines are byte-addressable. For example in a byte-
addressable 32-bit computer, each memory word contains 4 bytes. A possible word-address assignment
would be:
Word Address Byte Address

0 1 2 3

4 5 6 7

8 9 10 11

. …..

With the above structure a READ or WRITE may involve an entire memory word or it may involve
only a byte. In the case of byte read, other bytes can also be read but ignored by the CPU. However,
during a write cycle, the control circuitry of the MM must ensure that only the specified byte is altered.
In this case, the higher-order 30 bits can specify the word and the lower-order 2 bits can specify the
byte within the word.

CPU-Main Memory Connection – A block schematic: -

Data transfer between CPU and MM takes place through the use of two CPU registers,
usually called MAR (Memory Address Register) and MDR (Memory Data Register). If MAR is K bits
long and MDR is „n‟ bits long, then the MM unit may contain upto 2k addressable locations and each
location will be „n‟ bits wide, while the word length is equal to „n‟ bits. During a “memory cycle”, n
bits of data may be transferred between the
MM and CPU. This transfer takes place over the processor bus, which has k address lines (address
bus), n data lines (data bus) and control lines like Read, Write, Memory Function completed (MFC),
Bytes specifiers etc (control bus). For a read operation, the CPU loads the address into MAR, set R/W
to 1 and sets other control signals if required. The data from the MM is loaded into MDR
and MFC is set to 1. For a write operation, MAR, MDR are suitably loaded by the CPU,R/W is set to
0 and other control signals are set suitably. The MM control circuitry loads the data into appropriate
locations and sets MFC to 1. This organization is shown in the following block schematic.

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Memory Access Time: It is the time that elapses between
→ initiation of an operation &
→ completion of that operation.
Memory Cycle Time: It is the minimum time delay that required between the initiation of the two
successive memory operation.
RAM (Random Access Memory): In RAM, any location can be accessed for a Read/Write-
operation in fixed amount of time.
Cache Memory
Ø It is a small, fast memory that is inserted between
→ Larger slower main-memory and processor.
Ø It holds the currently active segments of a program and their data.
Virtual Memory
Ø The address generated by the processor is referred to as a virtual/logical address.
Ø The virtual-address-space is mapped onto the physical-memory where data are actually
stored.
Ø The mapping-function is implemented by MMU. (MMU = memory management unit).
Ø Only the active portion of the address-space is mapped into locations in the physical-
memory.
Ø The remaining virtual-addresses are mapped onto the bulk storage devices such as
magnetic disk.
Ø As the active portion of the virtual-address-space changes during program execution the
MMU.
MMU(memory management unit)
→ changes the mapping-function &
→ transfers the data between disk and memory.
Ø During every memory-cycle, MMU determines whether the addressed-page is in the
memory. If the page is in the memory. Then, the proper word is accessed and execution
proceeds. Otherwise, a page containing desired word is transferred from disk to memory.
• Memory can be classified as follows:
1) RAM which can be further classified as follows:
i) Static RAM ii) Dynamic RAM (DRAM) which can be further classified as
synchronous & asynchronous DRAM.
2) ROM which can be further classified as follows:
i) PROM ii) EPROM iii) EEPROM & iv) Flash Memory which can be
further classified as Flash Cards & Flash Drives.

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5.2 SEMICONDUCTOR RAM MEMORIES
5.2.1 Internal Organization of Memory Chips

Memory cells are usually organized in the form of an array, in which each cell is capable of storing
on bit of information. Each row of cells constitutes a memory word, and all cells of a row are
connected to a common line referred to as the word line, which is driven by the address decoder on
the chip. The cells in each column are connected to a Sense/Write circuit by two bit lines. The
Sense/Write circuits are connected to the data I/O lines of the chip. During the read operation, these
circuits‟ sense, or read, the information stored in the cells selected by a word line and transmit this
information to the output data lines. During the write operation, the Sense/Write circuits receive the
input information and store in the cells of the selected word.

Fig 5.2:Organization of bit cells in a memory chip

The above figure is an example of a very small memory chip consisting of 16 words of 8 bits each.
This is referred to as a 16×8 organization. The data input and the data output of each Sense/Write
circuit are connected to a single bidirectional data line that can be connected to the data bus of a
computer. Two control lines, R/W (Read/ Write) input specifies the required operation, and the CS
(Chip Select) input selects a given chip in a multichip memory system.

Example: For 1k*1 Memory chip

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The memory circuit given above stores 128 and requires 14 external connections for address, data
and control lines. Of course, it also needs two lines for power supply and ground connections.
Consider now a slightly larger memory circuit, one that has a 1k (1024) memory cells. For a 1k×1
memory organization, the representation is given next. The required 10-bit address is divided into
two groups of 5 bits each to form the row and column addresses for the cell array. A row address
selects a row of 32 cells, all of which are accessed in parallel. However, according to the column
address, only one of these cells is connected to the external data line by the output multiplexer and
input demultiplexer.

5.2.2 Static Memories

Memories that consist of circuits capable of retaining their state as long as power is
applied are known as static memories.

Fig 5.4 A static RAM cell

• Two inverters are cross connected to form a latch (Figure 5.4).

• The latch is connected to 2-bit-lines by transistors T1 and T2.
• The transistors act as switches that can be opened/closed under the control of the word-line.
• When the word-line is at ground level, the transistors are turned off and the latch retain its
state.

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Read Operation
• To read the state of the cell, the word-line is activated to close switches T1 and T2.
• If the cell is in state 1, the signal on bit-line b is high and the signal on the bit-line b’ is low.
• Thus, b and b‟ are complement of each other.
• Sense/Write circuit
→ monitors the state of b & b‟ and
→ sets the output accordingly.

Write Operation
• The state of the cell is set by
→ placing the appropriate value on bit-line b and its complement on b’ and
→ then activating the word-line. This forces the cell into the
corresponding state.
• The required signal on the bit-lines is generated by Sense/Write circuit.

Example: CMOS Cell

• Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch (Figure 8.5).
• In state 1, the voltage at point X is high by having T5, T6 ON and T4, T5 are OFF.
• Thus, T1 and T2 returned ON (Closed), bit-line b and b‟ will have high and low signals
respectively.

• Advantages:
1) It has low power consumption „.‟ the current flows in the cell only when the cell is
active.
2) Static RAM‟s can be accessed quickly. It access time is few nanoseconds.
• Disadvantage: SRAMs are said to be volatile memories their contents are lost when power is
interrupted.

ASYNCHRONOUS DRAM
Information is stored in a dynamic memory cell in the form of a charge on a capacitor,
and this charge can be maintained for only tens of milliseconds. Since the cell is required to store

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information for a much longer time, its contents must be periodically refreshed by restoring the
capacitor charge to its full value. An example of a dynamic memory cell that consists of a capacitor,
C, and a transistor, T, is shown below:

A sense amplifier connected to the bit line detects whether the charge stored on the capacitor is
above the threshold. If so, it drives the bit line to a full voltage that represents logic value 1. This
voltage recharges the capacitor to full charge that corresponds to logic value 1. If the sense amplifier
detects that the charge on the capacitor will have no charge, representing logic value 0.
ASYNCHRONOUS DRAM DESCRIPTION
• The 4 bit cells in each row are divided into 512 groups of 8 (Figure 5.7).
• 21 bit address is needed to access a byte in the memory. 21 bit is divided as follows:
1) 12 address bits are needed to select a row.
i.e. A8-0 → specifies row-address of a byte.
2) 9 bits are needed to specify a group of 8 bits in the selected row.
i.e. A20-9 → specifies column-address of a byte.
• During Read/Write-operation,
→ row-address is applied first.
→ row-address is loaded into row-latch in response to a signal pulse on RAS’ input of chip.
(RAS = Row-address Strobe CAS = Column-address Strobe)
• When a Read-operation is initiated, all cells on the selected row are read and refreshed.
• Shortly after the row-address is loaded, the column-address is
→ applied to the address pins & → loaded into CAS’.
• The appropriate group of 8 Sense/Write circuits is selected.
R/W’=1(read-operation) Output values of selected circuits are transferred to data-lines D0-D7.
R/W’=0(write-operation) Information on D0-D7 are transferred to the selected circuits.
• RAS‟ & CAS‟ are active-low so that they cause latching of address when they change from high
to low.
• To ensure that the contents of DRAMs are maintained, each row of cells is accessed periodically.
• A special memory-circuit provides the necessary control signals RAS‟ & CAS‟ that govern the
timing.
• The processor must take into account the delay in the response of the memory.
Fast Page Mode
Ø Transferring the bytes in sequential order is achieved by applying the consecutive
sequence of column-address under the control of successive CAS‟ signals.
Ø This scheme allows transferring a block of data at a faster rate.
Ø The block of transfer capability is called as fast page mode.

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5.2.4 Synchronous DRAMs

In these DRAMs, operation is directly synchronized with a clock signal. The below given
figure indicates the structure of an SDRAM.

Fig 5.8:Synchronous DRAM.

Ø The output of each sense amplifier is connected to a latch.
Ø A Read operation causes the contents of all cells in the selected row to be loaded into these
latches.
Ø But, if an access is made for refreshing purpose only, it will not change the contents of these
latches; it will merely refresh the contents of the cells.
Ø Data held in the latches that correspond to the selected column(s) are transferred into the
output register, thus becoming available on the data output pins.
Ø SDRAMs have several different modes of operation, which can be selected by writing
control information into a mode register. For example, burst operations of different lengths
are specified.

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 Ø The burst operations use the block transfer capability described before as fast page mode
feature.
Ø In SDRAMs, it is not necessary to provide externally generated pulses on the CAS line to
select successive columns. The necessary control signals are provided internally using a
column counter and the clock signal. New data can be placed on the data lines in each clock
cycles. All actions are triggered by the rising edge of the clock.

The above figure shows the timing diagram for a burst read of length 4.
Ø First, the row address is latched under control of the RAS signal.
Ø Then, the column address latched under control of the CAS signal.
Ø After a delay of one clock cycle, the first set of data bits is placed on the data lines.
Ø The SDRAM automatically increments the column address to access next three sets of the
bits in the selected row, which are placed on the data lines in the next clock cycles.

Latency and Bandwidth

¡ Memory latency is the time it takes to transfer a word of data to or from memory

¡ Memory bandwidth is the number of bits or bytes that can be transferred in one second.

¡ DDRSDRAMs- Cell array is organized in two banks.

Double Data Rate- Synchronous DRAMs (DDR- SDRAMs)

To assist the processor in accessing data at high enough rate, the cell array is organized in two
banks. Each bank can be accessed separately. Consecutive words of a given block are stored in
different banks. Such interleaving of words allows simultaneous access to two words that are
transferred on the successive edges of the clock. This type of SDRAM is called Double Data Rate
SDRAM (DDR- SDRAM).
5.2.5 Structure of larger memories

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 Ø Implementing a memory unit of 2M words of 32 bits each.
Ø Using 512x8 static memory chips. Each column consists of 4 chips. Each chip implements
one byte position.
Ø A chip is selected by setting its chip select control line to 1. Selected chip places its data on
the data output line, outputs of other chips are in high impedance state.
Ø 21 bits to address a 32-bit word. High order 2 bits are needed to select the row, by activating
the four Chip Select signals.
Ø 19 bits are used to access specific byte locations inside the selected chip.

Dynamic Memory System

• The physical implementation is done in the form of memory-modules.
• If a large memory is built by placing DRAM chips directly on the Motherboard, then it will
occupy large amount of space on the board.
• These packaging consideration have led to the development of larger memory units known as
SIMM‟s & DIMM‟s.
1) SIMM Single Inline memory-module
2) DIMM Dual Inline memory-module
¡ SIMM/DIMM consists of many memory-chips on small board that plugs into a socket
on motherboard. Memory modules are an assembly of memory chips on a small board
that plugs vertically onto a single socket on the motherboard.

§ Occupy less space on the motherboard.

§ Allows for easy expansion by replacement.
Recall that in a dynamic memory chip, to reduce the number of pins, multiplexed addresses are
used.
Address is divided into two parts:
§ High-order address bits select a row in the array.
§ They are provided first, and latched using RAS signal.
§ Low-order address bits select a column in the row.
§ They are provided later, and latched using CAS signal.

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5.2.6 Memory System Considerations

• To reduce the number of pins, the dynamic memory-chips use multiplexed-address inputs.
• The address is divided into 2 parts:
1) High Order Address Bit
Select a row in cell array.
It is provided first and latched into memory-chips under the control of RAS signal.
2) Low Order Address Bit
Selects a column.
They are provided on same address pins and latched using CAS signals.
• The Multiplexing of address bit is usually done by Memory Controller Circuit (Figure 5.11).

• The Controller accepts a complete address & R/W‟ signal from the processor.
• A Request signal indicates a memory access operation is needed.
• Then, the Controller
→ forwards the row & column portions of the address to the memory.
→ generates RAS & CAS signals &
→ sends R/W & CS signals to the memory.

5.2.7 RAMBUS MEMORY

• The usage of wide bus is expensive.
• Rambus developed the implementation of narrow bus.
• Rambus technology is a fast signaling method used to transfer information between chips.
• The signals consist of much smaller voltage swings around a reference voltage Vref.
• The reference voltage is about 2V.
• The two logical values are represented by 0.3V swings above and below Vref.
• This type of signaling is generally is known as Differential Signalling.
• Rambus provides a complete specification for design of communication called as Rambus
Channel.
• Rambus memory has a clock frequency of 400 MHz.
• The data are transmitted on both the edges of clock so that effective data-transfer rate is
800MHZ.
• Circuitry needed to interface to Rambus channel is included on chip. Such chips are called
RDRAM. (RDRAM = Rambus DRAMs).
• Rambus channel has:
1) 9 Data-lines (1st-8th line ->Transfer the data, 9th line>Parity checking).
2) Control-Line &
3) Power line.
• A two channel rambus has 18 data-lines which has no separate Address-Lines.
• Communication between processor and RDRAM modules is carried out by means of packets
transmitted on the data-lines.

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• There are 3 types of packets:
1) Request 2) Acknowledge & 3) Data.

5.3 READ ONLY MEMORY (ROM)

• Both SRAM and DRAM chips are volatile, i.e. They lose the stored information if power is
turned off. • Many application requires non-volatile memory which retains the stored
information if power is turned off.
• For ex:
OS software has to be loaded from disk to memory i.e. it requires non-volatile memory.
• Non-volatile memory is used in embedded system.
• Since the normal operation involves only reading of stored data, a memory of this type is called
ROM.
5.3.1 ROM
At Logic value ‘0’
Transistor(T) is connected to the ground point (P).
Transistor switch is closed & voltage on bit-line nearly drops to zero (Figure 5.12).
At Logic value ‘1’
Transistor switch is open. The bit-line remains at high voltage.

• To read the state of the cell, the word-line is activated.

• A Sense circuit at the end of the bit-line generates the proper output value.

TYPES OF ROM
• Different types of non-volatile memory are
1) PROM
2) EPROM
3) EEPROM &
4) Flash Memory (Flash Cards & Flash Drives)

5.3.1 PROM (PROGRAMMABLE ROM)

• PROM allows the data to be loaded by the user.
• Programmability is achieved by inserting a „fuse‟ at point P in a ROM cell.
• Before PROM is programmed, the memory contains all 0‟s.
• User can insert 1‟s at required location by burning-out fuse using high current-pulse.
• This process is irreversible.

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• Advantages:
1) It provides flexibility.
2) It is faster.
3) It is less expensive because they can be programmed directly by the user.

5.2.2 EPROM (ERASABLE REPROGRAMMABLE ROM)

• EPROM allows
→ stored data to be erased and
→ new data to be loaded.
• In cell, a connection to ground is always made at „P‟ and a special transistor is used.
• The transistor has the ability to function as
→ a normal transistor or
→ a disabled transistor that is always turned „off‟.
• Transistor can be programmed to behave as a permanently open switch, by injecting charge into
it.
• Erasure requires dissipating the charges trapped in the transistor of memory-cells.
This can be done by exposing the chip to ultra-violet light.
• Advantages:
1) It provides flexibility during the development-phase of digital-system.
2) It is capable of retaining the stored information for a long time.
• Disadvantages:
1) The chip must be physically removed from the circuit for reprogramming.
2) The entire contents need to be erased by UV light.

5.2.3 EEPROM (ELECTRICALLY ERASABLE ROM)

• Advantages:
1) It can be both programmed and erased electrically.
2) It allows the erasing of all cell contents selectively.
• Disadvantage: It requires different voltage for erasing, writing and reading the stored data.

5.3.4 FLASH MEMORY

• In EEPROM, it is possible to read & write the contents of a single cell.
• In Flash device, it is possible to read contents of a single cell & write entire contents of a block.
• Prior to writing, the previous contents of the block are erased.
Eg. In MP3 player, the flash memory stores the data that represents sound.
• Single flash chips cannot provide sufficient storage capacity for embedded-system

• Advantages:
1) Flash drives have greater density which leads to higher capacity & low cost per
bit.
2) It requires single power supply voltage & consumes less power.
• There are 2 methods for implementing larger memory:
1) Flash Cards & 2) Flash Drives
1) Flash Cards
Ø One way of constructing larger module is to mount flash-chips on a small card.
Ø Such flash-card have standard interface.
Ø The card is simply plugged into a conveniently accessible slot.
Ø Memory-size of the card can be 8, 32 or 64MB.
Ø Eg: A minute of music can be stored in 1MB of memory. Hence 64MB flash cards can
store an hour of music.
2) Flash Drives

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 Ø Larger flash memory can be developed by replacing the hard disk-drive.
Ø The flash drives are designed to fully emulate the hard disk.
Ø The flash drives are solid state electronic devices that have no movable parts.
Advantages:
1) They have shorter seek & access time which results in faster response.
2) They have low power consumption, they are attractive for battery driven
application.
3) They are insensitive to vibration.
Disadvantages:
1) The capacity of flash drive (<1GB) is less than hard disk (>1GB).
2) It leads to higher cost per bit.
3) Flash memory will weaken after it has been written a number of times (typically
at least 1 million times).

5.4 SPEED, SIZE COST

• The main-memory can be built with DRAM (Figure 5.13)

• Thus, SRAM‟s are used in smaller units where speed is of essence.
• The Cache-memory is of 2 types:
1) Primary/Processor Cache (Level1 or L1 cache)
It is always located on the processor-chip.
2) Secondary Cache (Level2 or L2 cache)
It is placed between the primary-cache and the rest of the memory.
• The memory is implemented using the dynamic components (SIMM, RIMM, DIMM).
• The access time for main-memory is about 10 times longer than the access time for L1 cache.

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Fastest access is to the data held in processor registers. Registers are at the top of the memory
hierarchy. Relatively small amount of memory that can be implemented on the processor chip.
This is processor cache. Two levels of cache. Level 1 (L1) cache is on the processor chip. Level 2
(L2) cache is in between main memory and processor. Next level is main memory, implemented
as SIMMs. Much larger, but much slower than cache memory. Next level is magnetic disks. Huge
amount of inexpensive storage. Speed of memory access is critical, the idea is to bring instructions
and data that will be used in the near future as close to the processor as possible.

5.5 Cache memories

• The effectiveness of cache mechanism is based on the property of “Locality of Reference”.
Locality of Reference
• Many instructions in the localized areas of program are executed repeatedly during some time
period
• Remainder of the program is accessed relatively infrequently (Figure 5.14).
• There are 2 types:
1) Temporal
Ø The recently executed instructions are likely to be executed again very
soon.
Ø 2) Spatial
Ø Instructions in close proximity to recently executed instruction are also
likely to be executed soon.
• If active segment of program is placed in cache-memory, then total execution time can be
reduced.
• Block refers to the set of contiguous address locations of some size.

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• The cache-line is used to refer to the cache-block

• The Cache-memory stores a reasonable number of blocks at a given time.

• This number of blocks is small compared to the total number of blocks available in main-
memory.
• Correspondence b/w main-memory-block & cache-memory-block is specified by mapping-
function.
• Cache control hardware decides which block should be removed to create space for the new
block.
• The collection of rule for making this decision is called the Replacement Algorithm.
• The cache control-circuit determines whether the requested-word currently exists in the cache.
• The write-operation is done in 2 ways: 1) Write-through protocol & 2) Write-back protocol.

Write-Through Protocol
Ø Here the cache-location and the main-memory-locations are updated
simultaneously.
Write-Back Protocol
Ø This technique is to
→ update only the cache-location &
→ mark the cache-location with associated flag bit called Dirty/Modified
Bit.
Ø The word in memory will be updated later, when the marked-block is
removed from cache.
During Read-operation
• If the requested-word currently not exists in the cache, then read-miss will occur.
• To overcome the read miss, Load–through/Early restart protocol is used.
Load–Through Protocol
Ø The block of words that contains the requested-word is copied from the memory
into cache.
Ø After entire block is loaded into cache, the requested-word is forwarded to
processor.
During Write-operation
• If the requested-word not exists in the cache, then write-miss will occur.
1) If Write Through Protocol is used, the information is written directly into main-
memory.
2) If Write Back Protocol is used,
→ then block containing the addressed word is first brought into the cache &
→ then the desired word in the cache is over-written with the new information.

5.5.1 MAPPING-FUNCTION
• Here we discuss about 3 different mapping-function:

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 1) Direct Mapping
2) Associative Mapping
3) Set-Associative Mapping
DIRECT MAPPING
• The block-j of the main-memory maps onto block-j modulo-128 of the cache (Figure 5.16).
• When the memory-blocks 0, 128, & 256 are loaded into cache, the block is stored in cache-
block 0. Similarly, memory-blocks 1, 129, 257 are stored in cache-block 1.
• The contention may arise when
1) When the cache is full.
2) When more than one memory-block is mapped onto a given cache-block position.
• The contention is resolved by allowing the new blocks to overwrite the currently resident-block.
• Memory-address determines placement of block in the cache.

Fig 5.15 Direct-Mapped cache

• The memory-address is divided into 3 fields:

1) Low Order 4 bit field
Selects one of 16 words in a block.
2) 7 bit cache-block field
7-bits determine the cache-position in which new block must be stored.
3) 5 bit Tag field
5-bits memory-address of block is stored in 5 tag-bits associated with cache-location.
• As execution proceeds,
5-bit tag field of memory-address is compared with tag-bits associated with cache-location.
If they match, then the desired word is in that block of the cache.
Otherwise, the block containing required word must be first read from the memory.
And then the word must be loaded into the cache.

ASSOCIATIVE MAPPING
• The memory-block can be placed into any cache-block position. (Figure 5.17).

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• 12 tag-bits will identify a memory-block when it is resolved in the cache.
• Tag-bits of an address received from processor are compared to the tag-bits of each block of
cache.
• This comparison is done to see if the desired block is present.

Fig 5.16 Associative-mapped cache

• It gives complete freedom in choosing the cache-location.

• A new block that has to be brought into the cache has to replace an existing block if the cache is
full.
• The memory has to determine whether a given block is in the cache.
• Advantage: It is more flexible than direct mapping technique.
• Disadvantage: Its cost is high.
SET-ASSOCIATIVE MAPPING
• It is the combination of direct and associative mapping. (Figure 5.18).
• The blocks of the cache are grouped into sets.

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• The mapping allows a block of the main-memory to reside in any block of the specified set.
• The cache has 2 blocks per set, so the memory-blocks 0, 64, 128…….. 4032 maps into cache set
„0‟.
• The cache can occupy either of the two block position within the set.
6 bit set field
Determines which set of cache contains the desired block.
6 bit tag field
The tag field of the address is compared to the tags of the two blocks of the set.
This comparison is done to check if the desired block is present.

Fig 5.17 Set-associative-mapped cache with two blocks per set

• The cache which contains 1 block per set is called direct mapping.
• A cache that has „k‟ blocks per set is called as “k-way set associative cache‟.
• Each block contains a control-bit called a valid-bit.
• The Valid-bit indicates that whether the block contains valid-data.
• The dirty bit indicates that whether the block has been modified during its cache residency.
Valid-bit=0 à When power is initially applied to system.
Valid-bit=1 à When the block is loaded from main-memory at first time.
• If the main-memory-block is updated by a source & if the block in the source is already exists in
the cache, then the valid-bit will be cleared to “0‟.
• If Processor & DMA uses the same copies of data then it is called as Cache Coherence
Problem.
• Advantages:
1) Contention problem of direct mapping is solved by having few choices for block
placement.
2) The hardware cost is decreased by reducing the size of associative search.

5.5.2 REPLACEMENT ALGORITHM

• In direct mapping method, the position of each block is pre-determined and there is no need of
replacement strategy.
• In associative & set associative method, The block position is not pre-determined.

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 If the cache is full and if new blocks are brought into the cache, then the cache-
controller must decide which of the old blocks has to be replaced.
• When a block is to be overwritten, the block with longest time w/o being referenced is over-
written.
• This block is called Least recently Used (LRU) block & the technique is called LRU algorithm.
• The cache-controller tracks the references to all blocks with the help of block-counter.
• Advantage: Performance of LRU is improved by randomness in deciding which block is to be
over- written.

Eg:
Consider 4 blocks/set in set associative cache.
Ø 2 bit counter can be used for each block.
Ø When a ‘hit’ occurs, then block counter=0; The counter with values originally lower than
the referenced one are incremented by 1 & all others remain unchanged.
When a ‘miss’ occurs & if the set is full, the blocks with the counter value 3 is removed,
the new block is put in its place & its counter is set to “0‟ and other block counters are
incremented by 1.

5.6 PERFORMANCE CONSIDERATION

• Two key factors in the commercial success are 1) performance & 2) cost.
• In other words, the best possible performance at low cost.
• A common measure of success is called the Pricel Performance ratio.
• Performance depends on
→ how fast the machine instructions are brought to the
processor & → how fast the machine instructions are
executed.
• To achieve parallelism, interleaving is used.
• Parallelism means both the slow and fast units are accessed in the same manner.

5.6.1 INTERLEAVING
Divides the memory system into a number of memory modules. Each module has its own
address buffer register (ABR) and data buffer register (DBR). Arranges addressing so that
successive words in the address space are placed in different modules. When requests for memory
access involve consecutive addresses, the access will be to different modules.

Since parallel access to these modules is possible, the average rate of fetching words from the Main
Memory can be increased

Methods of address layout:

1)

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 (a)Consecutive words in a module
Consecutive words are placed in a module. High-order k bits of a memory address determine the
module. Low-order m bits of a memory address determine the word within a module. When a block
of words is transferred from main memory to cache, only one module is busy at a time.

2)

(b)Consecutive words in consecutive modules

Consecutive words are located in consecutive modules. Consecutive addresses can be located in
consecutive modules. While transferring a block of data, several memory modules can be kept busy
at the same time.

• This results in both

→ faster access to a block of data and
→ higher average utilization of the memory-system as a whole.
• To implement the interleaved-structure, there must be 2k modules;
Otherwise, there will be gaps of non-existent locations in the address-space.

5.6.2 Hit Rate & Miss Penalty

• The number of hits stated as a fraction of all attempted accesses is called the Hit Rate.
• The extra time needed to bring the desired information into the cache is called the Miss Penalty.

20
• High hit rates well over 0.9 are essential for high-performance computers.
• Performance is adversely affected by the actions that need to be taken when a miss occurs.
• A performance penalty is incurred because of the extra time needed to bring a block of data from
a slower unit to a faster unit.
• During that period, the processor is stalled waiting for instructions or data.
• We refer to the total access time seen by the processor when a miss occurs as the miss penalty.
• Let h be the hit rate, M the miss penalty, and C the time to access information in the cache. Thus,
the average access time experienced by the processor is
tavg = hC + (1 − h)M
5.6.3 Caches on the processor chips

§ In high performance processors 2 levels of caches are normally used.

§ Avg access time in a system with 2 levels of caches is
§ T ave = h1c1+(1-h1)h2c2+(1-h1)(1-h2)M

h1- hitrate of Cache 1, h2- hit rate of Cache 2, M – miss penalty, c1- time to access info from
cache1, c2- time to access info from cache2.

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 MODULE 3
Memory System

Questions Year
1 Define: Memory Latency and Memory bandwidth. (2marks) June17
2 Explain synchronous DRAMS with block diagram. Jan19(17s)
3 With a diagram, explain the internal organisation of 2M X 8 asynchronous DRAMchip. June18, Jan17
June 17
4 With diagram, describe the internal organisation of a 128 X 8 memory chip. June19
5 With a neat diagram, explain the design of 2M X 32 memory module using 1M X 8memory Jan19
chips.
6 Draw and explain the working of 16 Mega Bit DRAM chip configured as 2M X 8. Jan18
7 Describe organisation of a 2M X 32 memory using 512K X 8 memory chips. Jan18
8 With diagram of basic SRAM (Static RAM) and DRAM (Asynchronous DRAM) chip(cell), June19
explain the read and write operations on each of them.
9 Define ROM. Explain various types of ROMs. Jan19(17s)
10 Write a short note on Flash memories (4marks) June17
Jan17,19(17s)
11 Explain ‘Hit Rate and Miss Penalty’.
June17
12 Define cache memory, explain various types of it with neat block diagram. Jan19(17s)
13 Define the following with respect to cache memory: Jan18
■ Valid bit ■ Dirty data ■ Stale data ■ Flush the cache
14 Describe any 2 mapping functions in cache. (with diagram) June18, 19
Jan17
15 Explain Associative mapping technique and set associative mapping technique. June17
16 Explain in detail the working of set associative mapped cache with 2 blocks per setwith Jan18
relevant diagram.
In a given system
(i) hit rate (n) = 0.5
17 (ii) miss penalty (M) = 100 ns June19
(iii) Time to access cache memory (c) = 100 ns.
Calculate the average access time (tavg) experienced by the processor.
18 Calculate the average access time experienced by processor if miss penalty is 17clock Jan19 (4m)
cycles and Miss rate is 10% and cache access time is 1 clock cycle.
Consider a cache consisting of 256 blocks of 16 words each, for a total of 4096 words and
assume main memory is addressable by 16 bit address and it consists of 4K blocks. How
19 many bits are there in each of Tag, block/set and word fields for Jan19 (9m)
different mapping techniques?
A block-set associative cache consists of a total of 64 blocks divided into 4 blockssets. The
main memory contains 4096 blocks, each consisting of 128 words.
20 (i) How many bits are there in a main memory address? Jan18
(ii) How many bits are there in each of the TAG, SET and WORD fields?
21 Analyze the working mechanism of Asynchronous DRAMS. Sep18(5M)

22 What is Cache memory? Analyze the three mapping function of cache memory Sep18(10M)

23 Analyze how data are written into Read Only Memories(ROM). Discuss different types of Sep18(10M)
Read Only Memories
18CS34 - COMPUTER ORGANISATION | QUESTION BANK
24 What is memory interleaving? Explain. Jan18

25 Calculate the average access time experienced by a processor, if a cache hit rate is 0.88, Jan18
miss penalty is 0.015 millisecond and cache access time is 10 microsecound.
26 What is ‘Locality of Reference’? Explain Direct mapping and set-associative mapping Jan2020(17
techniques. Scheme)

18CS34 - COMPUTER ORGANISATION | QUESTION BANK

18CS34 - COMPUTER ORGANISATION | QUESTION BANK
18CS34 - COMPUTER ORGANISATION | QUESTION BANK