POPULAR PUBLICATIONS AMPLIFIERS @ Chapter at a Glance © Power Amplifiers are large signal avplifiers, which are designed to give power gain with reasonable efficiency. There are three typvs of power amplifiers: (i) Class A , (ii) Class B, (iii) (Class AB and (iv) Class C. © Feedback Feedback means transfer of a fraction of a output quantity of a system to its input, It can be of two types 2. Positive feedback: positive feedback enhances the output and is required for oscillation while negative feedback reduces the output. b. Negative feedback: Negative feedback circuits are used for increasing stability, reducing distortion, increasing bandwidth and error correction. j © Oscillators: any circuit which is used to generate a.c voltage without a.c input signal is called ‘an oscillator. Oscillation means gain * feedback fraction = 1. For a positive feedback system the overall gain can be written as, A, = A/ 1 ~ AB where, A is the gain of the intemal amplifier, B is the feedback ratio, and -AB is the loop gain. © Phase shift: An example of an oscillator circuit that follows the basic development of a feedback circuit is the phase-shift oscillator. The operational amplifier provides a phase shift of 180° as it is used in the inverting mode and remaining 180° phase shift is produce by three RC network. This form of RC layout is usually referred to as ladder network. Thus the total phase shift around the loop is 360°(or 0°). If 46 is greater than unity at this particular ENEMES* gid ahaa a Rall RL aa 1+2rc+ 8 RC + oro ss s Let, 5 = jo; 1 1 2 ______ where, = TeS(GIAY OUI 2 2a © Wein-Bridge oscillators: The circuit consists of two state RC coupled amplifier -wi provides the phase shift of 360° or 0°. A balanced bridge is used as the feedback network which has no need to provide any additional phase shift © Multivibrators are classified as: a. Astable multivibrators: Astable multivibrator is a multivibrator in which neither state is stable. These are two quasi-stable (temporary) states: b. Monostable multivibrators: It has one stable state and one quasi stable state. when a pulse is applied to the input circuit, the circuit state changes to unstable state for a predetermined time. ‘*, Schmitt Trigger Circuits: The Schmitt trigger is a comparator application which switches the output negative when the input passes upward through a positive reference voltage. It then uses negative feedback to prevent switching back to the other state until the input passes through a lower threshold voltage, thus stabilizing the switching against rapid triggering by noise as it passes the trigger point. : A&D-2 Scanned with CamScanner ol,‘Multiple Choice Typ 4, A class B push-pull power amplifier has an a.c. output of 10 watts. The d.c. jer drawn from the power supply under ideal condition is [BUT 2007] '2) 10 watts 6) 12.75 watts ¢) 15 watts 4) 20 watts ‘Answer: (b) 2. Astable multivibrator may be used as [WeUT 2010, 2014] a) frequency to voltage converter b) voltage to frequency converter ¢) squaring circuit ) comparator circuit Answer: (C) 3. Schmitt trigger is also known as [weur 2010) a) squaring circuit b) blocking oscillator c) sweep circuit d) astable multivibrator Answer: (a) 4, For a wide range of oscillations in the audio range, the preferred oscillator is [WBUT 2010] a)Hartley b) Phase shift c)Wien-bridge _d) Hartley and Colpitt Answer: (c) 5. If the input of a Schmitt trigger is a sawtooth wave, the output is (weuT 2010) ) si 4 2) puledHES - -> RANI BBE SAS ue Feb Answer: (b) ae 6. The net phase shift of Wien-bridge oscillator around the loop is [WBUT 2010, 2017] a) 90° b) 180° ¢) zero d) 360° ‘Answer: (4) 7. Maximum efficiency of transformer coupled class A power amplifier is a) 78.5% b) 50% ) 25% d) 100% [WBUT 2011} Answer: (b) ' 8. A 2transistor class B power amplifier is commonly called [WBUT 2011, 2012) a) push-pull b) dual c) differential d) none of these Answer: (a) 9. Class C amplifiers are used as © [WBUT 2011) a) AF amplifiers b) detectors c) RF amplifiers _d) none of these Answer: (c) A&D-3 Scanned with CamScannerPOPULAR PUBLICATIONS 10, A bistable multivibrator circult has Dy owe take cisieg (eur 2011) a) two unstable states d) none of the ¢) quasi-stable states Answer: (b) 11. A Wien-bridge oscillator has @ frequency ee DWBUT 2011, 2012, 2014) a) 1/22 JRC by VRC eee 4) none of those Answer: (c) 12. Which of the following oscillators is used at audio truancy oe f : 20 2) Crystal Oscillators Senn teat "1, 20124 ©) RC Phase-shift Oscillator 4) Colpitt's Oscillator Answer: (c) 13. Astable multivibrator has by one stable state BUT 2012) 4 No stable state d) none of these o stable 5 Answer: (c) 14. Schmitt trigger circuit generates by square wave BUT 2012, 2014) @) Triangular wave d) none of these 7 ¢) saw tooth wave “PRIEMIES - ->RANWAN_MAHATO Rife aor 15. Negative feedback in an am “b) increased noiss a) reduced gain d) reduced bandwidth ©) increased frequency & Phase Answer: (c) ion at all times is 16. rates in the linear reg DWBUT 2043) : arplir tat one ee c) Class AB d) Classe Answer: (a) A power amplifier is 17, | efficiency of Class. (Bur 204: . Areas theo ot c) 75% d) 98% 31 Answer: (a) nk for 18. Crossover distortion is 2 problem! Cag amptiners BUT 2013) caer dies hein Answer: (by ually called 18. A 2-transistor class-B amplifier be aed b) inverting amplifier mwauT 2014] 4 gual ample eer d) push-pull amplifier Answer: swer: (4) A&D-4 Scanned with CamScannerNc ONKK [WBUT 2014) £20. The gain of an amplifier in ean is ¢) reat d) none of these ; inary) complex Answer: (d) , 21. For etitial modulation the value of modulation index Is hour 2014) 2) 0.5 by aan : Answer: (d) 22. The Q point in a voltage amplifier is selected in the middle of the active region aesie [BUT 2014] a) It gives better stability ® the circuit then needs less number of resistors ¢) the circuit needs a small d.c. voltage 4) it gives a distortion less output Answer: (a) 23. The output voltage of the circuit [BUT 2014] os v valv 10a 200 1 2Vv d3v a 1v r AnwVEMIES - ->RANJAN_MAHATO_RKM 24. A 24transistor class B power amplifier is cyauatt ae BUT 2015) a) push-pull ” d) none of these ¢) differential Answer: (a) a ee ¢) two stable states qa) fone these Answer: (a) : 26. Schmitt trigger circuit generates b) square wave BUT 2015) 3 wienouter ve d) none of these Answer: (b) : 27. A Wien-bridge oscillator has afrequency = BUT 2015) 1 a —- qd Se a6 2aRC None of these Answer: (c) A&D-5 a Scanned with CamScannerPOPULAR PUBLICATIONS 28, Which of the following oscillators is used at audio frequency? [WBUT 2018) a) Crystal oscillator b) Hartley oscillator c) RC phase-shift oscillator d) Colpitts oscillator Answer: (c) 29. Negative feedback in an amplifier is , (eur 2015) a) reduced gain b) increased noise c) increased frequency and phase d) reduced bandwidth Answer: (c) 30. Cross-over distortion occurs in [WBUT 2016, 2018) a) Class A amplifier b) Class AB amp! . ¢) Class C amplifier 4) Push pull ampli { Answer: (6) ‘ 31. The minimum distortion during amplification is obtained in DWBUT 2016) a) Class A amplifier b) Class B amplifier "i ¢) Class C amplifier d) Class AB amplifier Answer: (b) 32. A class C amplifier conducts for [WBUT 2016) © az b) 27 ocx 4) 0-7 Answer: (d) 33. A pure sine wave output is possible with [WBUT 2016) a) Hartley oscillators b) Wien bridge oscillators ince 7 EREQESS SSRRNJAN_RABATCRKM 34. The Barkhausen criterion for sustained oscillation is, (WBUT 2016) a) 4B=1 by [4plz1 ¢) | 4B|<1 d) NOT, Answer: (b) 35. Multivibrators : [WBUT 2016, 2018) a) Generate square wave b) Convert sine to square wave c) Convert triangular to sine wave d) Convert triangular to square wave Answer: (a) 36. The output pulse width for a monostable multivibrator using IC 855 where external resistance and capacitance are 20 kQ and 0.1 pF is. [WBUT 2016, 2018] a)21s |b) 2ms ¢) 2.5 ms d) 2.2 us Answer: (d) 37. In order to generate a square wave form a sinusoidal input signal one can use f [WBUT 2016] a) monostable multivibrators b) clipper and amplifiers 3 ¢) Schmitt trigger circuit d) both (b) and (c) a Answer: (4) ; A&D-6 Scanned with CamScanner& DIGITAL ELECTRONI 38. The efficiency of Class A amplifier is. [WBUT 2017] a) 0.8 b)4 ¢) 0.25 40.4 ‘Answer: (a) : 39. If the Q of a single stage single turned amplifier is doubled, then bandwidth will a) romain the same b) become half [WBUT 2017) c) become double d) become four times ‘Answer: (a) 40. Which of the following mode of BJT can be used as an amplifier? [WBUT 2018] a) CB bycc °) CE ) None of these Answer: (c) 41. A pure sine wave output is possible with [WBUT 2018] a) Hartley oscillators b) Wien-bridge oscillators. c) RC phase shift oscillators 4) Colpitt oscillators Answer: (b) 42. How is a conducting diode biased? [WBUT 2019] a) Forward b) Inverse ¢) Poorly d) Reverse Answer: (a) 43. The current gain of a p-n-p transistor is BNET 2019) atebbiedlitelenantaahinN MAHATO b) the collector current divided by the emitter current = c) near zero d) none of these Answer: (d) 44, The contro! terminal in a BJT transistor is, [WBUT 2019] a) The collector b) The base ¢) The emitter d) none of these Answer: (a) 48. For the operation as an amplifier the base of an n-p-n transistor must be [WBUT 2019] a) +ve with respective to emitter b) ~ve with respect to the emitter c)ov ) +ve with respect to collector Answer: (a) 46. The input resistance of a common base amplifier is [WBUT 2019) a) very low b) very high ¢) same as CE d) same as CC Answer: (a) Scanned with CamScanner47. A certain common-emitter amplifier has véltage gain 100. If the emitter bypagg cepecitor Is removed, [WEUT 2018) 2) clroult will become unstable by voltage gain will decrease ©) voltage pain will Inereaee @) gepotnt will shift Answer: (b) 48. b SFET dittere trom BUT mainty because of (WEUT 2019) 8) power rate b) high frequency performance: ¢) higher input impedence @) higher speed Answer: (c) BIT in CC mode can be used es (WEUT 2019) 2) Amplifier ) Butter ¢) Intermediate stage Amewer: (6) ‘1. Draw ane explain the operation of astable multivibrator using $5 Timer. (BUT 2014) Amewer: The following figure shows the $55 timer IC that is operated ir astable mode eee: “SHAAN [3. the ostpa of resiswr of the comparator undergoes 2 change in sign of their output, which i negative and therefore logic 0. If the capacitor is charging and is voltage tends tw rise ebove 21’, /3, comparator 1 output jump to positive saturation value, ic. itis logic | at R input of flip-flop. Similarly when capacitor i discharging and its voltage tends to fall below V,,/3 and comparator 2 output jumps to Positive saturation value or logic | at $input of flip-flop. ; 2 Define upper threshold, lower threshold, hysteresis voltage and centre voltage related to 2 Schmitt trigger circuit. [WBUT 2011] Answer: Upper threshold voltage: It is the voltage for low to high transition. Lower threshold voltage: It is the voltage for high to low transition. Hysteresis voltage: [tis the difference of two voltages Centre voltage: It is the imermediate to V," and Vy. 2. Draw and explain the operation of Monostable multivibrator using 656 Timer. [WBUT 2012, 2015, 2017, 2019] A&D-B Scanned with CamScannerSALOG & DIGITAL ELECTRONICS Anower: The monietable qmiftivibeator axing 555 timer is shown in figure 1. When a negative. going polse js connected th trigger input (pit 0.2) the output goes high. The terminal 7 is shorted by capacitor C, When the voltage across the capacitor C comes or. then the upper comparator in figute | changes the output fom high voltage value to low voltage value. The three internal resistance in figure | act ae volrage dividers and it provides the bias voltages of (2/3)V-- to the upper comparator and (1/3)V-r to the lower comparator. Since these two voltages fix the necessary comparator threshold voltages, they also aids in determining the timing interval, The input output voltage waveform is shown in figure 1 Negmve oe” ta Fig: 1 Monostable Operation The FobEAPHEUS cxertolFQAhiihd aN | Mata @> RIC foo is given by, “URAC Ve=Vecli-e J AY attimet =T, Therefore, when the output is high, the time interval becomes, tugs Therefore, IR,C (3) Figure 2 shows the wide range of output pulses that are obtained from the values of Ra and C. Since the changing rate and comparator thresholds are both proportional to the A&D-9 Scanned with CamScannerPOPULAR PUBLICATIONS supply voltage, the timing interval given by equation (2) is independent of the supply. voltage. 3 Functional Block diagram 4. Draw and explain the Schmitt trigger circuit. (WBUT 2012, 2015, 2019) Answer: Symbol The Schmit trigger is a comparator application which switches the output negative when the input passes upward through a positive reference voltage. It then uses negative feedback to prevent switching back to the other state until the input passes through a A&D-10 Scanned with CamScannerNALOG & DIGITAL ELE ICS lower threshold voltage, thus stabilizing the switching against rapid triggering by noise as it passes the trigger point. ‘Application: - ‘Schmitt trigger devices are typically used in open loop configurations for noise immunity and closed loop negative feedback configurations to implement bistable regulators, triangle/square wave generators, etc. 5. What is the basic principle of oscillation? [WBUT 2014) What is Barkhausen criterion? [WBUT 2014, 2017] Answer: Oscillation means gain feedback fraction = 1 A For a positive feedback system the overall gain can be written as, A iy 1-AB Where, 4 is the gain of the intemal amplifier, B is the feedback ratio, and—AB is the loop gain. If AB = 1, from this equation A, tends to infinity. The amplifier then gives an output voltage without requiring any externally applied input voltage. In other words, the amplifier becomes an oscillator. This condition of unity loop gain, i.e. AB = 1 is called the Barkhausen Criterion. ‘This condition means that |43|=1, and the phase angle of AB is zero or an integral multiplé of 360°. Therefore, the basic conditions for oscillation in a feedback amplifier re (i) the feedback must be regenerative, and (ii) the loop gain must be unity. o. wit MHEAhA HES ace ER vate Poh ellnGyA Mb PE oF EGA iit is called 50” a UT 2014] Answer: J push-pull amplifier possesses the following advantages: 1. There is no DC saturation of the core of the output transformer because th DC plate * currents flow through the output transformer in opposite directions due to the two transistors. This reduces the size of the output tramsformer. 2, As the AC signal frequency current does not pass through the common supply, the push-pull amplifier has no regenerative effect on other stages. The common emitter resistor for the two transistors doies not require a bypass capacitor. ide distortion in the output due to cancellation of all even order (2"4, 4" etc.) harmonics. 4. Any AC hum or ripple currents from the DC power supply sources balance out in the + Circuit and there is no hum in the output. 5, A Class B push-pull amplifier without input signal draws very litle collector or plate * Current resulting in great economy in battery power. The system is, therefore, suitable for battery operated equipment including transistor radio receivers. A&D-11 * Scanned with CamScannerPOPULAR PUBLICATIONS: 2 Part: A push-pull amplifier is a combination of two Class A or Class B amplifiers so connected . that one amplifier amplifies the positive half and the other apmplifies the negative half of, the input signal and the amplified replica of the input voltage, Push-pull amplifiers give higher output with less distortion than a single ended amplifier. In transistors, push-pull! amplifiers having complementary symmetry with one PNP and the other NPN transistor are used which do not need any transformers 7. AWien bridge oscillator has a frequency of 1000 Hz and a capacitance of 100 oF 7 Fine the resistance,. If the amplifier gain is 10, obtain the ratio of the resistances In the other arms. * WBUT 2016) Answer: . f= A=10, R=? 1 __01s9 : 2CR 10H 10" x10" x R= 0.159 (10? x10") F .1s9x10°Q &. Draw and explain Schmitt trigger circuit using 585 timer.» [WBUT 2016, 2018) Fig. shows timer 1C55S as a Schmitt Trigger Input and output where forms A&D-12 Scanned with CamScannerANALOG & DIGITAL ELECTRONICS The input of two compilation threshold input (6) and trigger input (2) are connected together and externals biased at ¥,, /2 therefore a voltage divider formed by R, and Ry. ‘As upper comparator will trip at 1/3¥,, and lower comparator (2) at 1/3¥,,, the bias provided by resistances A, and R, is cantered within there too thresholds. The circuit can convert wave form of shape. 9. Calculate the width of the gene ‘Answer: Following formula or equation is used for Monostable multivibrator pulse width. Monostable multivibrator pulse width: Tp= Ll *RI* Cl Where Cl = Capacitance and RI = Resistance. ed pulse. [WBUT 2019] Long Answer Ty] 4, a) Draw the circuit diagram of a transformer coupled Class A power amplifiers and explain its operation. b) Calculate the total efficiency of this amplifier. ¢) What is cross-over distortion found in Class B power amplifiers? How it can be eliminated? [WBUT 2011] Answer: 4a) Transformer coupling becomes necessary when the load impedance is smaller than the one rieeded in the collector for matching or, when'the load is to be isolated and cannot carry the de collector current. ENEMIES - -> wp ATATO REM Re we Fig: 1. Transformer coupled class A amplifier Fig. 1. shows a class A amplifier circuit with transformer coupling. Since it is a class A amplifier and same fixed biasing scheme is used, the operation is similar to the normal class A amplifier as described previously. The only difference is, here load is coupled with a transformer. b) Maximum conversion efficiency : 7 100% = 50% A&D-13 Scanned with CamScannerPOPULAR PUBLICATIONS: NUMBER SYSTEMS _—_— = Chapter at a Glance + Acnumber system is a framework where a set of rumbers are represented by numerals in @ consistent manner Ex: Decimal Number System, Binary Number System, + Compliments of a number: Complement is used in digital computers for simplifying the subtraction operation and for logical manipulation. There are two types of complements for seach bese-r-cystem: . 1.78 complement 2. (1's complement ID's Complement of Binary Number it The 1's complement of binary number can be found by changing all 1 (one) to 0 (zero) and alt. | {zero} to i (one), 2S Complement of Binary Number 2's complement of a binary number can be found ty adding 1 to I's complement of bins number Example: Find 1°s and 2's complement of ( 1011010); Changing all 110 02nd 010 1. ° 1 1 0 1 0 ENEMIES - -RANJAN! MAHATG_RKM i 2’scomplement 0100110 binary oumber tation with I's and 2's complement method: First, we convert § and | to binary. : Now we add 2 sign bit to each one. Notice that we have padded '' with zeros so it 4 will have four bts. e001 (1) To make our binary numbers negative, we simply change our sign bit from ‘0'to'l'. 1101 (-5) 1001 (1 Here is 2 quick summary of how to find the I's complement representation of any decimal - umber x. j 1. If xis positive, simply convert x to binary. 2. Mfxis negative, writ the positive value of x in binary 3. Reverse each bit. 1. First, we write the positive value of the number in binary 0101 (5) 2._Next. we reverse each bit ofthe number so I's become 's and U's become I's_1010 (-5) A&D-30 Scanned with CamScannerANALOG & DIGITAL ELECTRONICS Here is a quick summary of how to find the 2's complement representation of any decimal number x. Notice the first three steps are the same as I's complement. 1, If xis positive, simply convert x to binary. 2. If xis negative, write the positive value of x in binary 3. Reverse each bit. 4. Add 1 to the complemented number. First, we write the positive value of the number in binary. O101 (+5) Next, we reverse each bit to get the I's complement. 1010 Last, we add | to the number. tort (-5) Mul many 1's are present in the binary representation of decimal number Choice di x512+7 x 6445 x 8+3)? IWSUT 2007, 2018] a) 8 b)9 ©) 10 on ‘Answer: (b) = (23) 19 where xs base (+ ve integer), then the value of xis 2. I (212) x PWBUT 2007, 2008] gs 92 bs "9s ‘Answer: (b) at FREES FERARIAN 3 MAHATO_ aK" Answer: (c) ivatent of (1111100100), is (WBUT 2011] 4 eee soe b) 568 c) $96 d) none of these Answer: (c) : suivalent of (AOF9.0EB)ss is [WBUT 2011] : Tae sar 0867 nap) 67902.8796 ¢) 41209.0572 d) none of these Answer: (4) ilaittia lent of the binary no. 1011101000114 is [WBUT 2013] 6. onset cava ETA ¢) 2F3B 4) 1E9D Answer: (a), Two 4-bit 2's complements of binary numbers 1011 and 0110 are added. Then 7. Two 4-bit [WBUT 2013] the rent be by do10 ‘ ¢) 1101 . d) 0001 a) Answer: (4) which (211)X = (0.52)8 Is [WBUT 2014) 8 ae cate of base X a <16 Pai Answer: (d) hap Scanned with CamScannerPOPULAR PUBLICATIONS 9.1f (S4),, = (.1),, then the value of X Is MBUT 2047) a) 123 by 312 o) 213 d) 132 Answer: (b) q { 1. Find out the 7's complement of (- 756): MBUT 2007) Answer: For base R system, with word length = n bits, for a positive number N then Rs complement is N” = R* - Nand (R=1)'s complementis (R* ~1)-N. Here R=8(octal),n=3,then the &'s complement of 756, is1000, - 756, = 22,and the 7's complement is (1000, -1)- 756, =777-756= 21, 2. Subtract 111001, from (101011), using 2's complement method. = [WBUT. 2013); Answer: ‘ 111001, = 000110+1=000111 101011, = 010100+1 = 010101 011000 3. Carry out the following operation in binary using 1's complement arithmetic: ENEMIES - ->RANYAN_MAHATO_RETPT 20191 (8):0 = (1000) (9)i0o= (1001): = (9)yo in 2's complement = (0110) +1 = O11 (8):0 ~ (9)s0 = (10002 — (0111): 1000 ol 7 (0001 [0-1 = 19 (* = borrow) 2. (000I))=(-1) Proved Scanned with CamScannerANALOG & DIGITAL ELECTRONICS CODES Chapter ata Qn Chapter at a Glance « BCD (Binary Coded Decimal): Bina i E Decimal): Binary-coded decimal (BCD) is a digit it In BCD, a numeral i Sean ae OncaN ." Usually represented by four bits which, in general, represent the decimal Sap Begaul 0001 0010 oo1L 0100 101 0110 Olt 1000 1001 = « ASCII (American Standard code for information interchange): ASCII is the American Standard Code for Information Interchange, also known as ANSI X3.4. It is quite clegant in the way it represents characters and it is very easy to write code to manipulate upper/lowercase and check for valid data ranges. It is essentially a 7-bit code which owe ie fo Hare FN he et hd FR Pe computer systems tend to use ASCII values of 128 and above for extended charaeter sets. EBDIC code: EBCDIC (Extended Binary Coded Decimal Interchange Code) is a character encoding set used by IBM mainframes. It uses the full 8 bits available to it, so parity checking cannot be used on an 8 bit system. It has a wider range of control characters than ASCII. ‘* Gray Code: The reflected binary code is known as gray code. Scanned with CamScannerPOPULAR PUBLICATIONS 1. An example of weighted code Is [WBUT 2009, 2019) a) Excess-3 b) ASCII c)Hamming coded) 8421 . Answer: (4) q 2. Which of the following is reflected code? [WBUT 2009, 2014). a) 8421 b) Excess.3 ¢) Gray d) ASCII Answer: (c) 3. Which of the following codes is not a BCD code? (WBUT 2019) 2) Gray b)Xs3 ¢) 8421 4d) all of these Answer: (2) 4. (14011), in BCD 8421.c0de is [WBUT 2010) 2) 00014014 b) 00100114 ) 11011001 4) 01104100 Answer: (a) : 5. In which code do the successive code characters differ in only one position? [WBUT 2010] 2) Gray b)Xs3 ¢) 8424 d) Hamming code Answer: (a) 6.8421 isa [WBUT 2012, 2015) 2) Weighted code : b) non- weighted code ENRMIBS “2 RANJAN MARATO_RKM 7. What is Gray equivalent of the binary 1101? [WBUT 2014) a) 1104 b) 1011 cont d)none of these Answer: (d) ‘ 1. Why gray code is called reflected code? (WBUT 2016} Answer: In this code, a decimal number is represent in binary form in such a way such that each grey code number differs from the preceding and succeeding number by a single bit Then it is called refleetd code. Long Answer 1. Write short note on Gray code. (WBUT 2016, 2018] Answer: It is a non-weighted code. In this code a decimal number is represented in Binary form in such a way such that each gray code number differs from the preceding and succeeding number by a single bit. This code is a reflected code. A&D-34 Scanned with CamScanner‘ANALOG & DIGITAL ELECTRONICS BOOLEAN ALGEBRA @ Chapter at a Glance ¢ Boolean Algebra: Boolean algebra is an algebraic logic which deals with logic variable. This logic variable having only two values | and 0 alternatively “TRUE” or FALSE”. * Boolean Theorem and Identification: 1. Commutative law A+tB=BtA AB= BA Binary operation is commutative if changing the order of A@B= BOA fhe operands does not change the end result. A@B-BOA . A binary operation is associative if the order in whicl 2 ecearet hs = (BRE e operations are performed does not matter as long aq ‘A(B.C)=(A.B).C A® (BEC )= (A@B) ® C 3. Distributive law (B+) = A.BEA.C Bobs 6. Redundancy law AtAB=A ACASB) + Venn diagéam: Graphical representation of logical function i called Venn diagram. 1) A+B: First take B completely. A&D-35 Scanned with CamScannerENEMIES Sasa MAPA TORIC O. Ars ‘+ Representation of SOP (Sum of Product) form: £(A.B,C)=A B C+ C+ B Cisknown to bein sum of product form. For a n function. if each product term contains all the variables (complemented ‘uncomplemerted) the function is sudo bein Standard Sum of Product Form and each product is known as a “minterm” (denoted by m), eg. £(A, B, C)= ABC+ ABC+ABC ‘This Function isin standard SOP form and it consists of 3 minterms ABC, A BC and A\ Ina standard SOP form, for each minterm an un-complemented variable or literal is treat “I” and a complemented literal is treated as ‘0". Itis denoted by 1 + Representation of POS (Product of sum) form: q FIA,B, C)=(A +B +0)(A+C).(B +C ) is known to be in product of sum form. For a variable function, if each sum term conti complemented), the function is said to be i ‘sum is known 2s a “maxterm” (denoted by M), eg. F(A.B,C)=(A+BHC).(A+B+C)(A +B +C) Standard product of sum form and each sy and (A+B+O). Ina standard POS form, for cach maxterm an un-complemented variable or literal is “0° and a complemented literals treated as ‘I*.Itis denoted by TT. 1..A+ A'B +B" is equal to [WBUT 2012, 2016 aja b)B . oO do Answer: (c) 2 A+AB+ ABC's ABCDS. equals. (WBUT 2017 a) A+B+C+D b) A+ B+C'4D' lt do Answer: (c) 3. [AB'(C+BD)+ ABC is [WBUT a) AB b) BC ) BC 4d) AB Answer: (c) 4. Simplify A'B+ A+ BC [WBUT 2018] a)A+BC b)A+B QaeBC d) None of these ‘Answer: (a) A&D-36 Scanned with CamScannerANALOG & DIGITAL ELECTRONICS 4. Simplify the following Boolean function into 1) Sum of product form 1) Product of form: F(A, B.C,D) = ¥(0,1,2,5,8,9:10). Answer: ) [WBUT 2011] it) £(4, B,C, D)= Ym (0,112.5, 8,9,10) cD heme. wad oe AB oo ol tl 10 oo |fo [fo 0 2 o1 0 ; u w {foto} fe (A,B,C,D)=(B+C)(B+D)(4+C+B) A&D-37 Scanned with CamScannerPOPULAR PUBLICATIONS LOGIC GATES a 2 Chapter ata Glance a tt i ee ot complement ofthe sum of variable fs equal fo the product of the | complements of the variable. Proof: i¢ Ae B=AB — a. 3 ; B AB | ASB AB 0 1 1 q foro ee . | r i 7 1 0 0 ‘ t i i T 0 0 oe 7 T 0 0 From the truth table we see that, A+B =A : ‘Statement 2 : It states that the complement of the product of variable is equal to the sum of the complements ofthe variable, Proof: ie. AB = A+B A |B A 5 A+B | AB A+B a 1 0 1 i L ENEMIES Es 1 1 0 jell i) 0 From the truth table we see that, AB=A+B ‘© Universal logic gates: By this gate all the Boolean function can be implemented i.e. all the digital system can be implemented. NAND and NOR gate are two universal gates, 4 ‘* NAND Gate as a universal logic gate: - z NOT Gate using NAND Gate - : a ‘Y=A AND gate using NAND Gate, iB ‘ 2! OR Gate using NAND Gate B Using Demorgan's theorem Y=A.B AtB = AtB A&D-38 Scanned with CamScannerEXOR Gate using NAND Gate B Using Demorgan’s 2 theorem, Y= or, Y=A.AB+B.AB (A+B)+B(A+B) =AA+AB+BA+BB AB+AB =AGB Multiple Choice Type Questions 4. The aH number of NAND gates required to design one XOR gate is EMIES$ ; ->RANJAN I, MAHAT@RSERPRIO! hee @) 2. The operation which is commutative but not associative is [WBUT 2007, 2008, 2009, 2013] a) AND b) XOR c) NAND/NOR d) NOT Answer: (c) 3. The number of XOR gates required for conversion of 11011 to its equivalent grey code is [WBUT 2009, 2019] a)2 - bys 3 as Answer: (b) 4. The output of a logic gate is “1” when all its ip are at logic ‘0. The gate is either [WBUT 2009, 2019] 'a) NAND or XOR gate b) NOR or XOR gate c) AND or XNOR gate d) NOR or XNOR gate Answer: (d) : 5. How many minimum NOR gates is required to implement NAND gate? weur 2012, 2015] a)3 bys os a2 Answer: (b) 3 A&D-39 Scanned with CamScannerPOPULAR PUBLICATIONS. 6. Minimum number of NAND gates required to implement the XOR gate of two variables is [WBUT 2013) a)§ by? 4 a3 5 Answer: (c) 7. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates? (WBUT 2017] | a) OR gates only b) AND gates, OR gates and NOT gates © | c) OR gates and NOT gates d) none of these Answer: (b) 8. The minimum number of NAND gates required to implement an EX-OR gate is [WBUT 2017) a)2 b)3 Qa Oy Answer: (c) ‘8. A 32:1 MUX can be designed using {WBUT 2018] 2) two 16:1 MUXs and one two input OR gate 'b) two 16:1 MUXs and one two input AND gate c) two 16:1 MUXs and 2 two input OR gate 4) two 16:1 MUXs only Answer: (2) ENEMIES - --RSSGRRORRSFS! RKM 4. Implement 2- input XOR function using minimum number of 2-input NAND gates. [WBUT 2009) Answer: . EX —OR Gate using NAND Gate * a el } Y=A0B Scanned with CamScanner& DIGITAL ELECTRONICS KARNAUGH MAP eee @ Chapter ata Glance. 7 « K-map: The Karnaugh map is a tool to facilitate management of Boolean algebraic expressions. A Kamaugh map is unique in that only one variable changes value between squares, in other words, the rows and columns are ordered according to the principles of Gray code. «Functions of K-map: (@ Minimization of Boolean expression. To obtaining the minimal expression function require extensive calculations. Karnaugh map reduce the complexity. (iiy Kemaps permit the rapid identification and elimination of potential race hazards, something that Boolean equations alone cannot do. of a Boolean Two variable k map: B A o 1 aw 2. 1 ee of ase | a a 1] jp | a8 . iT : Mint Maxterms ENERIES -SRANJAN, MAHATO_RKM DH 00 ol HH _! io Asc | ABC I ABC | ABC Minterms Four variable k map: cD Z AB 00 o1 rh 00 ABCD ABCD ol ABCD | ABCD ABCD | ABCD " | 10| abcd | aBcp | ABCD Minterms A&D-41 Scanned with CamScannerPOPULAR PUBLICATIONS le Choice iestior 4. The maxterm corresponding to decimal 15 is [WBUT 2008) a) ABCD b) ABCD’ At Bt CHD d)A'B'C' DY Answer: (b) 2ASAB+ABC+ABCDS.... (WBUT 2010) A)ASBOCe... BA EB EC HDS. et go Answer: (c) 3. A code used for labeling the cells of a K-map is. [WBUT 2010) a) 8-4-2-4 binary _b) Hexadecimal ¢) Gray d) Octal 5 Answer: (a) 4. The minimized expression for the K-map is shown below [WBUT 2010) = Ti¥ a) ABCD4ACD ») ABCD +ACD+ABC c) BCD+CD+ABC 4) BCD+CD+ABC Answer: (b) 1. Minimize the following expression using K-map and realize the simplified ENEMIES SRANTSAN MALI TOMRRR 14 Answer: G(AB,C,D) = ¥(1,2,3,5,6,11,12) + D(7,8,10,14) Scanned with CamScannerDIGITAL ELECTRO? Sin =CD+AD+AB+8C=C(5+3)+(A@D) A B c D 2. Simplify the Boolean function using K-map FW,X,Y,Z)= ¥\m(0,4,5,6,8,9)+ (10, 11, 12, 13, 14, 15). Anew MEMIES - ->RANJAN_MAHATO_RKM F(W,X,Y,2) = Ym(0,4,5,6,8,9)+ Yrd(10,11,12,13;14,15) : The function is defined in terms of minterms and don’t care conditions. K — map representation of the given function is fig. below. [WBUT 2007] YZ 00 o no 10 wx) Soin =W 4¥Z +WZ+X¥ =W+¥(Z+X)4WZ A&D-43 Scanned with CamScannerEQEVRAR PUBLICATIONS 3. Simphity the following function using Kemah. D F=PPmaLas i [Tate BM B FTW e210 18) LAMA Answer: OFT] m(arasiars)[]A(Uan) &,=(A+C)(a+B+D)(B+C+D) F=Yn(a7,91515)- Faun) Sm =ACD+ATD+ BCD =C(AD+AD)+BcD =C(A@D)+BCD 4. Simplify the followir ing expressic i 2201456891211) oP A&D-44 Scanned with CamScannerAnswer! 5. Simplify the following functions by means of K-map: [WBUT 2008] F=Em(0,4,7,9,13,15)+d5(3,5) Answer: AAHATO_RKM F = ABC + BD+ ABC 6. Minimize the following expression using Karnaugh Map. [WBUT 2013] 1) F(A,B,C,D) = 11M (0,1,3,8,10,15) + T14(11,13,14) Ml) F(A,B,C,D) = ¥m(0,1,2,5,8,14) + Yd(4,10,13) Answer: i) Refer to Question No. | Short Answer Type Questions. » apre2oo_ol 1110 oop qi i o boo Ml x mA Snin = AC +BD + ACD * A&D-45 Scanned with CamScannerPOPULAR PUBLICATIONS 7. Simplify the following functions using K-map: 8) F(A. BC. D)=T (7.9.10, 11.1214 13) Ww b) F(A.B,C.D) =, (0,2.3,6,7) #2, (8,10,11 18). Answer: (a) F(A, B,C. D)=F(7,9.10,11,12,13, 14,15) f= AB+AD+AC+BCD ®) F(4, B,C, D)=s, (0,2,3,6,7)+%,(8,10,11, 15) cD AB\ Ds cD cds CD ENEMIES - ->RANJANE aB AB 4a f=(B+D}(A+e) ‘e eo) all 8. Obtain the minimal POS expression of the following function and implemer ‘same using only NOR gates. F(A, B, C, D) = Em(1, 4, 7,8, 9, 11) + £d(0,3,5) (BUT! Answer: F(A, B, C, D) = Zmi(1, 4, 7, 8, 9, 11) + £4(0,3,5) Realize the following expression using k map and implement the simplified exy using NOR gates only. Scanned with CamScanner(AD+AC+CD+B) 4. Realize the following expression using K- map and implement the simplified expression using NOR gates only: F(A, B,C,D) = >, (041,4,6,7,10,1112,13,15) +4 (2,5,9,14) [WBUT 2008, 2019] Answer: Realize the following expression. using K map and implement tte simplified expression using NOR gates only. F(A,B,C.D) = 5,(0,1,4,6,7,10,11,12,13,15) +4(2,5,9,14) A&D-47 Scanned with CamScanner+ Demnttipterer: The demultiplexer performs the reverse operation of multiplexer. It acc 4 signal input and distributes it over several cutpats, Demultiplexer is a combinational circuit, which transmit a single fine signal over multiple line information signals + Comparator: 4 disital comparator circuit is a combinational circuit which compare two ‘input digital signal and gives the output as per result.eg. Let A and Bare two input signals + the circuit compare with A and B POPULAR PUBLICATIONS ' { Ie ASB output =1 4 A=B output =1 i ARANJAN._MAHATO_RKM vill te Mle ly Tange requirements ix) flexibilities available. 3. Implement the function F(4,B,C) =) m(1,3,5,6)using decoder. What is the difference between combinational circuit and sequential circuit? [WBUT 2012, 2013, 2015] Answer: Given function: F (4, B,C) = Y°m(1,3,5,6) K-Map: Bc BC. Bc BC BC FF =AC+BC + ABC =C(4+B)+ ABC =C(4B)+ ABC = ABC + ABC = AB®C A&D-61 Scanned with CamScannerPUBLICAT Implementation using decoder: A Xp Be ¢ A circuit in which output depends up on the present state of the inputs is called! § combinational circuit. A logic circuit whose output depends not only on the present input but also on the history of the inputs is called sequential circuit. 4. 2) Implement the following function using 4:1 multiplexer: [BUT 2013) F(A,B,C)=¥ mi.3,5,6). 'b) Write the application of multiplexer. a) As 4:1 multiplexer is used to implement Boolean function F(4,2,C) =)" m(1,3,5,6) Iwo select address lines. ENEMIES: >RARUAN MARATO_RKM Truth table of 4:1 MUX: ef Inputs ‘Outputs FE Scanned with CamScannerANALOG & DIGITAL ELECTRONICS b) It operates as controlled switch with n inputs at one bit data output. It selects one of the inputs according to binary signals applied on select pins of combinational circuit passes the information to output. 5. Design a 6:32 decoder using 2:4 and 3:8 decoders. [weurT 2017] Answer: Let us consider 5 input lines are ABCDE here A is the MSB & E is the LSB. 1" we have to use 2:4 decoder whose inputs are A & B and output D,D,D;D; are enable j signals of 4 3x8 decoder respectively. CDE are the 3 input line of the 3x8 decoder, each | of the decoder produces 8 output lines. are the 3 input line of the 3x8 decoder, each of the decoder produces 8 output lines. ENEMIES|- - 6. Design NAND and NOR logic gate using COMS technology, [WBUT 2018) Answer: 2 input NAND Gate: : ‘Truth Table Va] Ve | Vous LOW LOW HIGH ioe HIGH HIGH LOW HIGH Linge agi} LOW A&D-63 Scanned with CamScannerCircait ve Vax Gat ‘The above drawn circuit is a 2 input CMOS Nand gate. 2 input NOR Gate: ae Trath Table i7 ¥ TOW | HIGH Low | HIGH | LOW HIGH. LOW. a ii ENEMIES - RAEN HETO HMESATO_RKM Bach el [est a i NMOs2 MOST gil A&D-64 Scanned with CamScannerANALOG & DIGITAL.LECTRONICS 7. Explain the working principle of 4:1 MUX with a truth table. Reaze it using NAND gates only. (BUT 2019) Answer: fe {lo RENE ->RANJAN_MAHATO_RKM A, B are control 11 Output is, 1,4B-1,4B-1,AB-1,AB = I,4B + 1,4B+J,AB+1,AB which is the output f MUX. ; Truth Table [Selact Inputs] Enable Inputs Input 2 a HY i ><] ><] ><] >«] Lo] ><] >¢]>4] 8. Explain the working principle of 1:4 DEMUX with truth table. Realize it using basic gates. [WBUT 2019] =|—|=|-lololola}>|er —|-lolol—|-lololay lolelo}e}o}o|o}o}—lm ><] ><] =o] ><] ><] ><] >¢] >< ho =|] >| ><] ><] ><] >| ><] >= —|e|—le]—lo|-|o}o}-< ><] ><] ><] >¢] ><} ><] —| | A&D-65 Scanned with CamScannerPOPULAR PuBICATIONS Answer: j . mation from one input The process o getting info many outputgs called demultiplexing, A ‘that receives/he information on 3 single ‘one of 2n pssible output lines. The bit co" selection ofipecific output line figure illusties the basic idea of any one ofhe four outputs is poss! as data digibutors, since they trans different dstinations. Thus. 2 demultiplexer is an N-tcl device. The figure below shows simply a fEMUX. The bela figure shows the block diagram single injut D, three select inputs S2. SI and line to ge of 4 output lines depending on >. ENEMI Je input & bination to be connect’ exer. i : te Ge instant. Demultiplexers are also mit the same dat is ofa 14o-4 demultiplexer that consists 4, input lines. It distributes one j F to three select input lines. It S One in, also cll as Ito demulipee it 0 inputs, Put Outputs and transmitting the same Ver one: yltiplexer is @ combinational logic é rd transmits the same information uit ns of the select lines contryy tt ito the input at given instant, The the in which the switching of the in, 3 pa fa which is received at the inl Mm -o-N device where as the multipy the block diagram of a demultiplexer « $0 and eight outputs from YO to Y3 1, ‘e = 7 Yo = DS2S150 Y1=DS25iS0 Y2=DS2S1S0 Y3=DS2S1S0 OO & SS Data Input Select Inputs Outputs D sls [siul% | YT Yo | D 0 0 o 0 o 0 D D 0 0 1 0 o D 0 D 0 1 o 0 D 0 0 D 0 1 1 D o 0 0 D 1 0 o 0 o oO oO D 1 0 1 0 o oO 0 D Try eoyoj;ololo i ‘ruth table shows the equation: A&D-66 Scanned with CamScannerANALOG & DIGITAL ELECTRONICS 4, Implement the following function usin, 9 ail 4: 1 multi : F=Sm(0D3 ultiplexers. 9,12,14) [WBUT 2007, 2010, 2018] Answer: To implement F = Y'm(0,2,3,6,8,9,12,14),one 16:1 multiplexer is required. As the circuit will be designed by 4:1 MUX, 16:1 multi MUX as shown in Fi iplexer can be implemented using five 4:1 ig.- Consequently to implement F = DX7(0, 2, 3, 6,8, 9, 12, 14), input signals JovTartyoTuryslost;,and J,,are connected with SV and other input signals I tatsTrtortirts,and l,, are grounded. lo i 4:1 MUX : ae fe ENEMIES F=SRANJAN. MAHATO_RKM 4:1 MUX ; Si_ So A&D-67 Scanned with CamScannerPOPULAR PUBLICATIONS anrrunencore’™ ymbers: A = wo ie binary MAMA, | + arate binary adder: CEE BRR The eddition of A & B wil G Column 1 and Cy is carry igen ee s two deter binary mdse called paralie! binary 68 Circuit diagram rn Fig: Block diagram of full adder circuit using half adder circuit. A&D-88 LSS _ Scanned with CamScannerANALOG & DIGITAL ELECTRONICS Cirenit diagram D> ———__ c Boolean expression S=A®BOC, oe) C, SAB+(A@D)C, C, = AB+(AB+ ABYC, = AB(1+C,)+(AB+ AB)C, = AB+ ABC, + ABC, + ABC, + ABC, = AB+ BC,(A+A)+AC,(B+B) = AB + BC, + AC, vee (2) ‘The equation 1 & 2 are representing the sum (S) Carry (C,) of a full adder circuit. 1. The carry output ofa full adder i thre input [WBUT 2007} An ENEMIES. A NGARE RAHAT: PERT 2. How many full adders are required to construct m bit parallel adder? [WBUT 2010, 2011] a) mi/2 ° by)m=1 c)m djm+1 Answer: (b) 3. Acarry look ahead adder is frequently used for addition because, it [WBUT 2010) a) is faster b) is more accurate c) uses fewer gates 4d) costs less Answer: (a) 4, The minimum no. of NAND gates required to design one full adder circuit is ‘ [WBUT 2011] a6 b)5 ¢) 10 a9 Answer: (a) A&D-89 - Scanned with CamScannerPOPULAR PUBLICATIONS ‘BCD sum using binary adde, pan waur som’ Ww points: ‘9° or when a cary ig 1. Design a lopie circuit which #66 receaar loge guts, Expat Answer: in mil w ising two BCD sos, sh epi i) Whatever the value of bit together exceeds the “6° should be added ie. (0110) inbinaty: S,asthe cupet after addition Correction Required This gives us the correction — circuit va Scanned with CamScannerBB: BB, | AYASAAy nol MIS, acoRANNANMALATQ. RKM OR, Implement a full adder circuit using a 3-to-8 decoder and other logic gates. [WBUT 2014] Answer: S(x,y, = Yo m(1,2,4,7) = sum C(x y.2)= mGB5,6,7) = carry Since there are 3 inputs and a total of 8 minterms and we need a 3 to 8 decoder. The implementation is shown in figure below. ; * no» Jy . y 2, decoder z cm - “A&D-91 Scanned with CamScannerAnswer: The serial adder accepts as input two serial strings of digits of arbitrary length, starting with the low order bits, and produces the sum ofthe two bit streams as its output. (The input bit streams could come from, say, two shift registers clocked simultancously.) This device can be easily described as a state machine. We first decide what must be “remembered” ~ in the case of an adder, this is easy; ‘that must be remembered is whether or not there is a carry to be aC) into. the-n eel outputs, also: el in Figure shown below, inpuvoutput 000 ol 0 010 ©=——=6) * 101 oon iW ‘We can derive a state table from the state diagram as follows: Present state | laputs [Next state | Output & [ojo] & | o G Joli] % | ENEMIES - >-AanpaNlahAGAtO Rkw G [ojo] & 1 G foli] & 0 G& fifol & 0 Ge ula erales 4 cae Full-adder circuit using two Half-adders. Write the truth table of [WBUT 2012, ante 2017], ine Full Adder Circuit from Half Adder Circuit Fig: Block diagram of fll adder circuit using half adder circuit A&D-92 Scanned with CamScannerTruth table of Half subtractor 6. Draw a BCD adder circult to add two BCD numbers maximum up to 9. The output of this address should be in BCD. [WBUT 2013] Answi ‘i Refer to Question No. 1 of Long Answer Type Questions. -o-ox co-on 6. Implement the following using 3 to 8 line decoder. Use active low decoder outputs: ‘YO (A, B, C)=Zm (0, 1, 2, 4). [WBUT 2013} Answer: ENE D{A,B,C) =Lm(0,1,2,4) 7 7 Since there are 3- inputs and a total of 8 minterms, we need a 3-to-8 decoder. The implementation is as shown in figure below: o i 38 2 a] cater 3 > ; c s 7 é > Fig: 3 to 8 decoder ; A&D-93 Scanned with CamScannerPOPULAR PUBLICATIONS FLIP-FLOP. mi © Chapter ata Glance ‘The sequential circuits, the output na nly depend on the present state but also depend on the [past state ofthe system. There are two types of flip-flops. (i) Edge-triggered flip-flop, (ii) level- triggered fip-Nop, ‘An Edge triggered Flip Flop responds only during the brief instant the clock switches fro ‘one voltage level to another when triggering occurs onthe positive going edge of the clo is called Positiveedge triggering and when triggering occurs in the negative edge, it is,¢ Negative-edge triggering A Level triggered Flip Flop responds only a particular stage i.e. cither high or low sit for atime. Ex: Flip Flop can be divided into RS Flip Flop, D Flip Flop, JK Flip Flop and Master IK Flip Flop. Latch: A latch isthe most basic type of fipfop circuit. It can be constructed using Ni NOR gates. There are two types of latches. (i) NAND gate latch (ii) NOR gate latch. RS Flip-lop: RS Flip-lop sed as restoring information. It has two stable states, whi be achieved by giving proper inpats to R and S inputs. The flip-flop will assume one two stable sates depending upon any asymmety inthe circuit jon which is called an universal flip-flop beea ENEMIES aoe SNEARAIATO” BRM D Mip-flop: D Flip-Flop is a flip-flo With a delay (D) equal to exattly one cycle of the’ In D flip-flop input to R gh inet S50 at int to R is al a ofS and never same. " the flip-optogeles on every new clock pus. 1. Flip-flop that makes output equals to input after clock is wi 2) JK flipflop —b) Dfiplop ¢) T flip-flop 4) none of ti Answer: (b) ‘ constructed from these Flip-Flop and still operate upto 10MHz is © [WBUT 2008] a) 255 b) 265 8 . 410 Answer: 256 . " ‘ 3. The characteristics equation of the T-FIFis given by a) Qt=TQ+T@ b)Qt=TQ+Qr ) Q= TQ a) Q+= Ta Answer: (b) A&D-100 Scanned with CamScanner