Busitema University Faculty of Engineering : : , Department of Computer Engineering Pursuing Excellence yW) Ph UNIVERSITY EXAMINATIONS Semester TWO 2019/2020 ‘Course Code: ect 1202 Course Name: Introduction to Digital Logic Program of Study: B. Computer Engineering ‘Year of Study: I ‘Date of Examinations: 16/2/2021 ‘Time of Examinations: 11:30am — 2:30pm: INSTRUCTIONS: ‘This paper consists of TWO sections, A and B ‘Answer all questions in section A and choose any three from section B. «Section A carries 25 marks and each multiple-choice question carries two marks except for the last question which carries one mark © All questions in section B carry equal marks (25 MARKS) Observe all instructions written on your answer booklets Please turn aver for the questionsSECTION A. 1. The output of an AND gate 1s LOW A. when any input ts LOW 8. when all inputs are HIGH when any input 1s HIGH D. Alithe time The Boolean expression for 2 3-input AND gate a A. X= ABC Cc. X= AB B. X=A+B4C D. X= ABHC 5. The format used to present the logic output for the various ‘combinations of logic inputs to a gate is called 2 A. Input logic function B, C. Boolean variable D. 4, The universal gate is .. A. NAND gate c. B. AND gate D. 5. The inverter is . Truth table . Boolean constant 4 . OR gate - |. None of the above ‘A. NOT gate C. OR gate B. AND gate D. None of the above 6. The binary number 10101 is equivalent to decimal number Ag B12 .27 D.21 7. The inputs of a NAND gate are connected together. The resulting circuit is A. OR gate C. AND 8. NOT gate srt D. None of the above 8. The circuit of the given figure realizes the function e ABE CID + EY2 digital s system :¢ Filpflop. Cc. Counte B. Encoder (e nom 4 14 1011 0113 4.67 D =i ae = p-flop is said to be transparent when The output is HIGH C. The out; 8. The output follow input D. The our s clock s The boolean algebra is mostly based on A. De Morgans theorem C. De Mors br B. Standard theorem D. Boolear. 13. The time required for a Gate to change its outpi~ A. Decay tirne B. Run tim ©. Propagation time O. Start t: lioSECTION B & Question 2 (25 Marks) _ Dé igit i ee advantage: a a), Differentiate between digital and analog systems and give any thr ie —e) Vaf, techniques over their analog counterparts. of digital igi (b) Perform the following conversions: ks (i) 14.125: to its binary equivalent. (4 marks) (ii) FAD4ys to its decimal equivalent. (3 marks) (ii) 10110110012 into its octal equivalent. (3 marks) ©) Simplify the following expressions using Boolean algebra and draw the simplified logic circuit diagrams. LoXe ‘A+B)A+C)B+C) (4 marks) (S marks) QUESTION 3 (25 MARKS) @) Distinguish between the following; i, Combinational logic circuits and sequential circuits (3 marks) C7; Synchronous and asynchronous digital systems ii, (3 marks) 2 ¢ b) Explain the typical advantage of JK flip flops over the SR flip flops. ©) Draw the symbol and truth table of a clocked 3-k by @ positive-going transition (PGT) of the clock (2 marks) flipflop that is edge- triggered pulse, (3 marks) i) Determine the output waveform given the following 3-K inputs and clock-pulse signal. (4 marks) ———~ time 4) Explain the followin flops. ee, illustrations) Se tagers (c ‘9 terms digital pulses and Edge trigger as applied to flip (Ro,0 : (6 marks) Ce) Gita hitQuestion 4 (25 marks) uo / Aonsider a logic circuit with four inputs A, B, C and D. The logic circuit output Xis HIGH whenever two or more inputs are HIGH. i) Draw the truth table for the circuit described in question (3 marks) ii) Express the output in terms of its Minterms and Maxterms. (4 marks) b) Illustrate the circuits of a NAND latch and a NOR latch (4 marks) ) Mustrate the internal circuitry of the SR Flip-flop using NAND gates. Show how this circuitry is modified to achieve the JK Flip flop. (8 marks) 4) Given the truth table below, express the output in terms on their Minterms and Max terms. (6 marks) A |B 0 | o o | o o [i [0 [1 1 oO 1 [0 1 1 11 (2y/ Question 5 (25 marks) ZY. wa a) The output of a logic circuit is given as x=C(ADB + D) + ACBD + D. i) Implement the logic circuit output in question above. (4 Marks) ii) Given that A=0 and B=C=D=1, evaluate the logic output. (3 Marks) b) Draw a truth table for the logic cirguit above, (6 Marks) ©) Determine the output of the logic gates in the figure Q.5 below in terms of the (9, Boolean expression (2 Marks) 7 Ao | Be [>e 7 bY cad figure Q.5 port JY” Show that the output in (c) above when simplified will be equal to Fe(A+€).(C+D) (4 Marks) /ii) Write short notes on the following logic famili Ai rite short nate 9 log) lies as used in Pee Ae@ + E-DHone! 2 ® UNIVERSITY gra 2 aon eet Mf BCT RR Inbedatione ae CT 1202 - Introduction to Digitat Logic and t DCE 1203 - DIGITAL ELECTRONICS oie CAT 1 a i a 4 2) Time: 1Hr 45 mins (OxVIGe aK ie Attempt ALL Questions ats Question 1 2) Differentiate between digital and analog systems and give any three advantages of digital techniques over their analog counterparts. (6 marks) (0) Perform the following conversions: e (14.125. to its binary equivalent, (4 marks) ~ (FAD As to its decimal equivalent, (3 marks) (ii) 1011011901, into its octal equivalent, (3 marks) wo Question 2 2) The ouput of a logic circuit is given as x=ABC¥D). Implement this logic Circuit . b) Given chat A=0 and B=: 4, evaluate ihe iogic output, rm ©) Draw a truth table for the logic circuit above. ~ d) Determine the output of the logic gates in the figure 2 beiow in terms of the Boolean expression ——_—— (4 Marks) 1 (wee eR) 2 A tb 2 8 fF u . — vb I ee eS 8 : iS y D Bi figure 2 ®) Show that the output in (4) above when simplified will be equal to FE(+ 8).(C4.D) (4 Marks) > 1) Hence draw the above Simplified logic circuit in ey (4 Marks) vs) Peau” fein PRES 2