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Pavan Updated Resume 2yr

The document provides a summary of Pavan Kumar's experience as a Hardware Engineer, including over 2 years working in physical design and STA. Some of his key experiences include working on blocks in 8nm, 16nm and 28nm nodes, performing physical design flows, floorplanning, placement and routing, timing closure, fixing violations, using CAD tools like ICC, Primetime and Innovus, and scripting in TCL and Linux. He has experience with three projects involving block implementation for AMD in 8nm and 16nm nodes and another in a 28nm node.

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119 views3 pages

Pavan Updated Resume 2yr

The document provides a summary of Pavan Kumar's experience as a Hardware Engineer, including over 2 years working in physical design and STA. Some of his key experiences include working on blocks in 8nm, 16nm and 28nm nodes, performing physical design flows, floorplanning, placement and routing, timing closure, fixing violations, using CAD tools like ICC, Primetime and Innovus, and scripting in TCL and Linux. He has experience with three projects involving block implementation for AMD in 8nm and 16nm nodes and another in a 28nm node.

Uploaded by

RA NDY
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PAVAN KUMAR.

R
Pavanrandy619@gmailcom | +91-8142150715
EXPERIENCE SUMMARY
 Having 2 years of work experience in --- through --- as a Hardware Engineer [PD]
 Experience in Physical Design & STA.
 Experience of working in the latest technology nodes like 8nm, 16nm, and 28nm.
 Experience in block-level Physical Design. Well-known about ASIC design flow
from Specifications to GDSII. Good knowledge of Timing and Congestion fixes.
 Experience in STA sanity checks & manual ECO flow and STA Sign-Off closure.
 Basic Knowledge of writing scripts using TCL & Linux shell.
 Basic Electronics and Debugging Techniques Fundamentals of Digital, CMOS
Theory and Low Power Design,
 Working Knowledge of STA/Timing ECO Flow, Net delay calculations, Skew,
Timing Exceptions (Half cycle paths, Multicycle paths), Back Annotation, PVT
Variations, Setup and hold time violations

TECHNICAL SKILLS:

TOOLS: ICC, ICC2, PRIMETIME, FUSION COMPILER & INNOVUS (CADENCE)


Scripting: Basics of TCL, vim, grep, sed, awk.
Technology node: 8nm, 16nm, 28nm,

PROFESSIONAL EXPERIENCE:

PROJECT DETAILS

PROJECT 1: (Client: AMD )

• Title : Block-Level PNR Implementation


• Technology : 8 nm
• Frequency : 525MHz / TP: 1.9 ns
• No of Clocks : 7
• Macro : 8
• Instance Count : 0.4 M
• Metal Layer :11
Responsibilities:
• Responsible for block-level PNR Implementation.
• Performed sanity checks and did various iterations of Floorplanning.
• Reduced congestion by using blockages.
• Created path groups and defined routing layers for routing.
• Fixed timing and DRC, DRV, LVS violations, and sanity checks are performed.
• Analyzed the logs after optimization techniques were utilized.
• Clock tree analysis and meeting skew and latency.
PROJECT 2: (Client: AMD )
• Title : Block-Level PNR Implementation
• Technology : 16 nm
• Frequency : 465MHz / TP: 2.1ns
• No of Clocks :9
• Macro : 80
• Instance Count :2M
• Metal Layer : 13
Responsibilities:
• Responsible for block-level PNR Implementation.
• Did placement and applied various strategies to control congestion.
• Fixed timing violations after placement and clock tree synthesis (CTS).
• Fixed trans and timing violations across various corners.
• Sanity checks are also performed.
• Analyze the logs before & after iterations.

PROJECT 3:

• Title : Block-Level PNR Implementation


• Technology/Metal Layer : 28 nm / 11 Metal Layers
• Instant Count : 0.5 M
• Macros : 20
• Clocks :5
• Frequency : 565 MHz/ 1.7 ns
Responsibilities:
• Place and Route and timing closure
• Performed sanity checks and did various iterations of Floor planning.
• Pin placement was done with the help of guidelines provided by top-level
• Multiple iterations of floor plan to achieve acceptable congestion.
• Congestion fixing, Timing fixing DRV Fixing.
• Clock tree analysis and meeting skew and latency
• Performed signoff for RC extraction and closed the timing using primetime
• DRCs (Shorts and opens) and LVS.

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