ELEC 370: Electronic Circuits

Lecture 1: MOSFETs

Fall 2023
Dr. Amine El Moutaouakil
Department of Electrical Engineering
E-mail: [email protected]
Outline
• Warming up,
• pMOS vs nMOS,
• CMOS,
• DC operation,
• Q point and biasing,
• AC operation,
• Reviews

Lecture 1 - MOSFETs 2
MOSFET
• Figure 5.1. shows general structure of the n-channel enhancement-
type MOSFET

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view, (b) cross-
section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the thickness of the oxide
layer (tox) is Lecture
in the 1range of 1 to 10nm.
- MOSFETs 3
nMOS I-V Summary
• Shockley 1st order transistor models

Lecture 1 - MOSFETs 4
Example 5.1: NMOS MOSFET
• Example 5.1. Problem Statement: Consider an NMOS process
technology for which Lmin = 0.4mm, tox = 8nm, mn = 450cm2/Vs, Vt =
0.7V.
• Q(a): Find Cox and k’n.
• Q(b): For a MOSFET with W/L = 8mm/0.8mm, calculate the values of
vOV, vGS, and vDSmin needed to operate the transistor in the saturation
region with dc current ID = 100mA.
• Q(c): For the device in (b), find the values of vOV and vGS required to
cause the device to operate as a 1000ohm resistor for very small vDS.

Lecture 1 - MOSFETs 5
The p-Channel MOSFET

• Figure 5.9(a) shows cross-

sectional view of a p-channel
enhancement-type MOSFET.
• structure is similar but
“opposite” to n-channel
• complementary devices – two
devices such as the p-channel
and n-channel MOSFET’s.

Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor
shown in Figure 5.1(b), except that all semiconductor regions are reversed in polarity. (b) A negative
voltage vGS of magnitude greater than |Vtp| induces a p-channel, and a negative vDS causes a current iD
to flow Lecture
from source to drain.
1 - MOSFETs 7
The p-Channel MOSFET

• Q: What are main differences

between n-channel and p-channel?
• A: Negative (not positive) voltage
applied to gate “closes” the
channel
• allowing path for current flow
• A: Threshold voltage (previously
represented as Vt) is represented
as Vtp
• |vGS| > |Vtp| to close channel

Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor
shown in Figure 5.1(b), except that all semiconductor regions are reversed in polarity. (b) A negative
voltage vGS of magnitude greater than |Vtp| induces a p-channel, and a negative vDS causes a current iD
to flow Lecture
from source to drain.
1 - MOSFETs 8
The p-Channel MOSFET

• Q: What are main differences

between n-channel and p-channel?
• A: Process transconductance
parameters are defined
differently
• k’p = mpCox
• kp = mpCox(W/L)
• A: The rest, essentially, is the
same, but with reverse polarity...

Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor
shown in Figure 5.1(b), except that all semiconductor regions are reversed in polarity. (b) A negative
voltage vGS of magnitude greater than |Vtp| induces a p-channel, and a negative vDS causes a current iD
to flow Lecture
from source to drain.
1 - MOSFETs 9
The p-Channel MOSFET

• PMOS technology originally dominated the MOS field

(over NMOS). However, as manufacturing difficulties
associated with NMOS were solved, “they” took over
• Q: Why is NMOS advantageous over PMOS?
• A: Because electron mobility mn is 2 – 4 times greater
than hole mobility mp.
• complementary MOS (CMOS) technology – is technology
which allows fabrication of both N and PMOS transistors
on a single chip.

Lecture 1 - MOSFETs 10
The p-Channel MOSFET

Lecture 1 - MOSFETs 11
The p-Channel MOSFET

Lecture 1 - MOSFETs 12
Complimentary MOS/CMOS
• CMOS employs MOS transistors of both polarities.
• more difficult to fabricate
• more powerful and flexible
• now more prevalent than NMOS or PMOS

Lecture 1 - MOSFETs 13
Figure 5.10: Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-
type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n
device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the
latter functions as the body terminal for the p-channel device.

p-type semiconductor n-well is added to allow

provides the MOS body generation of p-channel
(and allows generation of
SiO2 is used to isolate
n-channel)
Lecture 1NMOS
- MOSFETs from PMOS 14
Current-Voltage Characteristics

• Figure 5.11. shows an n-channel enhancement

MOSFET.
• There are four terminals:
• drain (D), gate (G), body (B), and source (S).
• Although, it is assumed that body and source
are connected.

Figure 5.11 (a): Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with
an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n
channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect
of the body on device
Lectureoperation
1 - MOSFETsis unimportant. 15
Current-Voltage Characteristics
• Although MOSFET is symmetrical
device, one often designates
terminals as source and drain. the potential at drain (vD) is
• Q: How does one make this always positive with respect to
designation? source (vS)
• A: By polarity of voltage applied.
• Arrowheads designate “normal”
direction of current flow
• Note that, in part (b), we
designate current as D→S.
• No need to place arrow with B.

Figure 5.11 (a): Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with
an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n
channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect
of the body on device
Lectureoperation
1 - MOSFETsis unimportant. 16
The iD-vDS Characteristics
• Q: When MOSFET’s are employed to design
amplifier, in what range will they be
operated?
• A: saturation
• In saturation, the drain current (iD) is… ’

• dependent on vGS
• independent of vDS
• In effect, it becomes a voltage-controlled
current source.
• This is key for amplification.

Figure 5.13: The iD – vDS characteristics

for an enhancement-type NMOS
transistor
Lecture 1 - MOSFETs 17
equation (5.14) as vGS increases, so do the (1) saturation current
and (2) beginning of the saturation region

Figure 5.13: The iD – vDS characteristics for an enhancement-type NMOS transistor

Lecture 1 - MOSFETs 18
 • Q: What is one problem with (5.21)?
• A: It is nonlinear w/ respect to
5.2.2. The iD-vGS Characteristic vOV … however, this is not of
concern now.

• In effect, it becomes a voltage-controlled

current source.
• This is key for amplification.
• Refer to (5.21).

2
vOV
1 W 
(eq5.21) iD = kn   ( vGS − Vtn )
2

2  L 
this relationship provides
basis for application of
MOSFET as amplifier

Figure 5.14: The iD-vGS characteristic of an NMOS transistor operating in the saturation region. The iD-vOV
characteristic can be obtained by simply re-labeling the horizontal axis, that is, shifting the origin to the point
vGS1=- MOSFETs
Lecture Vtn. 19
The iD-vDS Characteristics
• The view of transistor as VCCS is exemplified
in figure 5.15.
• This circuit is known as the large-signal
equivalent circuit.
• Current source is ideal.
• Infinite output resistance represents
independent, in saturation, of iD from
vDS..

note that, in this circuit, iD is Figure 5.15: Large-signal equivalent-circuit model

of an n-channel MOSFET operating in the
completely independent of vDS saturation
(because no shunt resistor
exists)
Lecture 1 - MOSFETs 20
Example 5.2: NMOS Transistor
• Example 5.2. Problem Statement: Consider an NMOS transistor
fabricated in an 0.18-mm process with L = 0.18mm and W = 2mm. The
process technology is specified to have Cox = 8.6fF/mm2, mn =
450cm2/Vs, and Vtn = 0.5V.
• Q(a): Find VGS and VDS that result in the MOSFET operating at the
edge of saturation with ID = 100mA.
• Q(b): If VGS is kept constant, find VDS that results in ID = 50mA.
• Q(c): To investigate the use of the MOSFET as a linear amplifier, let it
be operating in saturation with VDS = 0.3V. Find the change in iD
resulting from vGS changing from 0.7V by +0.01V and -0.01V.

Lecture 1 - MOSFETs 21
Finite Output Resistance in Saturation

• In previous section, we assume (in saturation) iD is

independent of vDS.
• Therefore, a change DvDS causes no change in iD.
• This implies that the incremental resistance RS is
infinite.
• It is based on the idealization that, once the n-channel
is pinched off, changes in vDS will have no effect on iD.
• The problem is that, in practice, this is not completely
true.

Lecture 1 - MOSFETs 24
Finite Output Resistance in Saturation

• Q: What effect will increased vDS have on n-channel once

pinch-off has occurred?
• A: It will cause the pinch-off point to move slightly
away from the drain & create new depletion region.
• A: Voltage across the (now shorter) channel will
remain at (vOV).
• A: However, the additional voltage applied at vDS will
be seen across the “new” depletion region.

Lecture 1 - MOSFETs 25
 this is the most important
point here
Finite Output Resistance in Saturation

• Q: What effect will increased vDS have on n-channel once

pinch-off has occurred?
• A: This voltage accelerates electrons as they reach the
drain end, and sweep them across the “new”
depletion region.
• A: However, at the same time, the length of the n-
channel will decrease.
• Known as channel length modulation.

Lecture 1 - MOSFETs 26
 Finite Output Resistance in Saturation

• Q: How do we account for “this effect” in iD?

Figure 5.16: Increasing vDS beyond vDSsat causes the
• A: Refer to (5.23). channel pinch-off point to move slightly away from
the drain, thus reducing the effective channel
length by DL
valid when vDS vOV

1 W 2
(eq5.17) iD = ( mnCox ) vOV in A
2 L
1 W 2
(eq5.23) iD = ( mnC ox ) vOV (1 + vDS ) in A
2 L
• A: Addition of finite outputvalid
resistance
when v v (r ).
o DS OV

Figure 5.18: Large-Signal Equivalent Model of the

n-channel MOSFET in saturation, incorporating the
output resistance ro. The output resistance
models the linear dependence of iD on vDS and is
Lecture 1 - MOSFETs
given by (5.23) 27
Finite Output Resistance in Saturation  i 
−1

(eq5.24) ro =  D 
 vDS  vGS =constant
−−−−−−−−−−−−−−−−−−−−−−−−−−−−
• Q: How is ro defined?  (5.23)

• step #1: Note that ro is the iD  1 W 2 
(eq5.23) =  ( m C ) v ( 1 +  v )
DS 
vDS vDS  2
n ox OV
1/slope of iD-vDS L 
characteristic.  
• step #2: Define relationship  (5.23)

iD  1  W 2 
between iD and vDS using (eq5.23) =  ( n ox )
m C v OV ( 1 + v DS ) 
vDS vDS  2 L 
(5.23).  
• step #3: Take derivative of iD 1 W 2
this function. (eq5.23) = ( mnC ox ) vOV 
vDS 2 L
• step #4: Use above to define −−−−−−−−−−−−−−−−−−−−−−−−−−−−
ro.
−1
1 W 2 
• Note that ro may be defined in (eq5.25) ro =  ( mnC ox ) vOV 
2 L  vGS =constant
terms of iD, where iD does not take
in to account channel length 1 VA
(eq5.24) ro = =
modulation…
Lecture 1 - MOSFETs  iD iD 28
Finite Output Resistance in Saturation
• Q: What is ?
• A: A device parameter with the units of V
-1, the value of which depends on

manufacturer’s design and

manufacturing process.
• much larger for newer tech’s
• Figure 5.17 demonstrates the effect of
channel length modulation on vDS-iD curves
• In short, we can draw a straight line
between VA and saturation. Figure 5.17: Effect of vDS on iD in the
saturation region. The MOSFET
parameter VA depends on the process
technology and, for a given process, is
proportional to the channel length L.

Lecture 1 - MOSFETs 29
MOSFET Circuits at DC

• We move on to discuss how

MOSFET’s behave in dc circuits.
• We will neglect the effects of

DC
channel length modulation
(assuming  = 0).
• We will work in terms of
overdrive voltage (vOV), which
reduces need to distinguish
between PMOS and NMOS.

Lecture 1 - MOSFETs 30
Example 5.3: NMOS Transistor

• Problem Statement:
Design the circuit of Figure
5.21, that is, determine the
values of RD and RS – so
that the transistor operates
at ID = 0.4mA and VD =
+0.5V. The NMOS
transistor has Vt = 0.7V,
mnCox = 100mA/V2, L = 1mm,
and W = 32mm. Neglect
the channel-length
modulation effect (i. e. Figure 5.21: Circuit for Example
assume that  = 0). Lecture 1 - MOSFETs 5.3. 31
Example 5.4:
• Refer to textbook…

Lecture 1 - MOSFETs 33
Example 5.5: MOSFET

• Problem Statement:
Design the circuit in Figure
5.23 to establish a drain
voltage of 0.1V. What is
the effective resistance
between drain and source
at this operating point? Let
Vtn = 1V and k’n(W/L) =
1mA/V2.
Figure 5.23: Circuit for Example
5.5.
Lecture 1 - MOSFETs 34
Example 5.6: MOSFET
• Problem Statement: Analyze the circuit shown in Figure 5.24(a) to
determine the voltages at all nodes and the current through all
branches. Let Vtn = 1V and k’n(W/L) = 1mA/V2. Neglect the channel-
length modulation effect (i.e. assume  = 0).
Figure 5.24: (a) Circuit for

circuit with some of the

analysis details shown.
Example 5.6. (b) The

Lecture 1 - MOSFETs 37
Example 5.7: PMOS Transistor

• Problem Statement: Design the

circuit of Figure 5.25 so that
transistor operates in saturation
with ID = 0.5mA and VD = +3V. Let
the enhancement-type PMOS
transistor have Vtp = -1V and
k’p(W/L) = 1mA/V2. Assume  = 0.
• Q: What is the largest value that
RD can have while maintaining
saturation-region operation?
Figure 5.25: Circuit for
Example 5.7.
Lecture 1 - MOSFETs 39
Exercise 5.8: CMOS Transistor

• Problem Statement: The

NMOS and PMOS transistors
in the circuit of Figure 5.26(a)
are matched, with k’n(Wn/Ln)
= k’p(Wp/Lp) = 1mA/V2 and Vtn
= -Vtp = 1V. Assuming  = 0
for both devices.
• Q: Find the drain currents iDN
and iDP, as well as voltage vO
for vI = 0V, +2.5V, and -2.5V.
Figure 5.26: Circuits for Example
Lecture 1 - MOSFETs 5.8. 40
 example of transconductance
amplifier
Obtaining a Voltage Amplifier

• In section 1.5 of text, we learned that

voltage controlled current source
(VCCS) can serve as
transconductance amplifier.
• the following slides (with blue tint) are a
review
• Q: How can we translate current
output to voltage?
• A: Measure voltage drop across load
function
resistor.v supply
of input
v
out G
Figure 5.27: (a) simple MOSFET
(eq5.Lecture DS = vDD − iD RD
30)1 - vMOSFETs amplifier with input vGS and output vDS 41
 • voltage transfer characteristics (VTC
– plot of out voltage vs. input
Voltage Transfer Characteristic • three regions exist in VTC
• vGS < Vt → cut off FET
• vOV = vGS – Vt < 0
• ID = 0
• vDS ??? vOV
• vout = vDD
• Vt < vGS < vDS + Vt → saturation
• vOV = vGS – Vt > 0
• ID = ½ kn(vGS – Vt)2
• vDS >> vOV
• vout = VDD – IDRD
• vDS + Vt < vGS < VDD → triode
• vOV = vGS – Vt > 0
• ID = kn(vGS – Vt – vDS)vDS
• vDS > vOV
Figure 5.27: (b) the voltage transfer
characteristic (VTC) of the amplifier • vout = VDD – IDRD
from previous slide Lecture 1 - MOSFETs 42
 cutoff FET cutoff AMP

Voltage Transfer Characteristic • Q: What observations may be

drawn?
• A: Cutoff FET represents
transistor blocking, cutoff
AMP represents vout = 0
• A: As vGS increases…
• vDS (effectively)
decreases
• iD increases
• vout decreases
nonlinearly
• gain (G) decreases
• A: Once vDS > vDD, all power
Figure 5.27: (b) the voltage transfer is dissipated by resistor RD
characteristic (VTC) of the amplifier
from previous slide Lecture 1 - MOSFETs 43
Voltage Transfer Characteristic
Q: How do we define vDS in terms of
vGS for saturation?
this is equation is simply ohm's law / KVL

1 2
(eq5.32) vDS = VDD −  kn ( vGS − Vt )  RD
2 
iD

2kn RDVDD + 1 − 1
(eq5.33) VGS B = Vt +
kn RD

Q: How do we define point B –

boundary between saturation and
Figure 5.27: (b) the voltage transfer triode regions?
characteristic (VTC) of the amplifier
Lecture 1 - MOSFETs
from previous slide 44
 Biasing the MOSFET to Obtain Linear Amplification this equation is simply ohm's law

1 2
(eq5.34) VDS = VDD −  kn (VGS − Vt )  RD
2 
• Q: How can we linearize VTC? Vsource −ID RD

• A: Appropriate biasing technique

• A: Dc voltage vGS is selected to obtain
operation at point Q on segment AB
• Q: How do we choose vGS?
• A: Will discuss shortly…

This equation differs from (5.32) because

it considers dc component only.
Figure 5.28: biasing the MOSFET
Lecture 1 - MOSFETs amplifier at point Q located on 45
segment AB of VTC
 Biasing the MOSFET to Obtain Linear Amplification this equation is simply ohm's law

1 2
(eq5.34) VDS = VDD −  kn (VGS − Vt )  RD
2 
• bias point / dc operating pt. (Q) – Vsource −ID RD

point of linearization for MOSFET

• Also known as quiescent point.
• Q: How will Q help us?
• A: Because VTC is linear near Q, we
may perform linear amplification of
signal << Q

Figure 5.28: biasing the MOSFET

Lecture 1 - MOSFETs amplifier at point Q located on 46
segment AB of VTC
• bias point / dc operating pt. (Q) = point of linear amplification
linearization for MOSFET around Q in
• also known as quiescent point
saturation region
• Q: how will Q help us?
• because VTC is linear near Q, we may perform
linear amplification of signal << Q

Figure 5.28: biasing the MOSFET amplifier at

Lecture 1 - MOSFETs point Q located on segment AB of VTC 47
Biasing the MOSFET to Obtain Linear Amplification

• Q: How is linear gain achieved?

• step #1: Bias MOSFET with dc
voltage VGS as defined by (5.34)
• step #2: Superimpose amplifier vGS (t ) = VGS + vgs (t )
input (vgs) upon VGS. −−−−−−−−−−−
• step #3: Resultant vds should be vds (t )  vgs (t )
linearly proportional to small-
signal component vgs.

Lecture 1 - MOSFETs 48
 Figure 5.29: The MOSFET amplifier with a small
time-varying signal vgs(t) superimposed on the dc
bias voltage vGS. The MOSFET operates on a short
Q: How is linear gain achieved? almost-linear segment of the VTC around the bias
point Q and provides an output voltage vds = Avvgs

As long as vgs(t) is small, its effect

on vDS(t) will be linear –
facilitating linear amplification.

Lecture 1 - MOSFETs 49
Q: How is linear gain achieved?

dvDS
(eq5.35) Av =
• step #4: Note if vgs dvGS
v V GS GS
is small, output vds means that
vgs is small
will be nearly action: replace v with (5.32)
DS
linearly
proportional to it.
(eq5.35) Av =
d ( VDD − 2 n ( GS
1
k v − Vt ) RD )
2

• Slope will be dvGS

constant. v GS VGS

action: simplify

(eq5.36) Av = −kn (VGS − Vt ) RD

action: replace
with VOV

Lecture 1 - MOSFETs (eq5.37) Av = −knVOV RD 50

Small-Signal Voltage Gain

• Q: What observations can dvDS

(eq5.35) Av =
be made about voltage dvGS vGS VGS
gain? means that
vgs is small

• A: Gain is negative. action: replace vDS with (5.32)

• A: Gain is proportional to:

(eq5.35) Av =
(
d VDD − 12 kn ( vGS − Vt ) RD
2
)
• load resistance (RD) dvGS
• transistor conductance vGS VGS
action: simplify
parameter (kn)
• overdrive voltage (vOV) (eq5.36) Av = −kn (VGS − Vt ) RD
action: replace
with VOV

(eq5.37) Av = −knVOV RD
Lecture 1 - MOSFETs 51
 Small-Signal Voltage Gain

• Equation (5.38) is another version of

(5.37) which incorporates (5.17).
• It demonstrates that gain is ratio of: (eq5.37) Av = −knVOV RD
• voltage drop across RD action:
incorporate
(5.17) iD = 12 kn vOV
2
• half of over voltage
 ID RD 
(eq5.38) Av = −  
 VOV /2 

Lecture 1 - MOSFETs 52
Example 5.9: MOSFET Amplifier

• Problem Statement: Consider the

amplifier circuit shown in Figure 5.29(a).
The transistor is specified to have Vt =
0.4V, k’n = 0.4mA/V2, W/L = 10, and  =
0. Also, let VDD = 1.8V, RD = 17.5kOhms,
and VGS = 0.6V.
• Q(a): For vgs = 0 (and hence vds = 0), find
VOV, ID, VDS, and Av.
• Q(b): What is the maximum
symmetrical signal swing allowed at the
drain? Hence, find the maximum
allowable amplitude of a sinusoidal vgs. Figure 5.29:
Lecture 1 - MOSFETs 53
 Determining the VTC via Graphical Analysis
VDD vDS
(eq5.39) iD = −
RD RD
• Graphical method for determining
VTC is shown in Figure 5.31
• Rarely used in practice, b/c difficult
to draw vi-relationship.
• Based on observation that, for each
value of vGS, circuit will operate at
intersection of iD and vDS.

Figure 5.31: Graphical construction to determine the voltage transfer characteristic

Lecture 1 - MOSFETs 57
of the amplifier in Fig. 5.29(a).
 Points A (open) and C (closed) are
suitable for switch applications
Determining the VTC via Graphical Analysis

• point A – where vGS = Vt

• point Q – where MOSFET
may be biased for
amplifier operation
• vGS = VGS, vDS = VDS
• point B – where MOSFET
leaves saturation / enters
triode
• point C – where MOSFET is
Point Q is suitable for amplifier
deepLecture
in1triode region and
- MOSFETs applications
vGS = VDD 58
Determining the VTC via Graphical Analysis

Figure 5.32: Operation of the MOSFET in Figure 5.29(a) as a switch: (a) Open,
corresponding to point A in Figure 5.31; (b) Closed, corresponding to point C in
Figure 5.31. The closure resistance is approximately equal to rDS because VDS is
Lecture 1 - MOSFETs 59
usually very small.
Locating the Bias Point Q

• bias point (Q) – is determined by value of vGS and load

resistance RD.
• Two considerations in deciding Q:
• Required gain.
• Allowable signal swing at output.

Lecture 1 - MOSFETs 60
Locating the Bias Point Q

• Q: How is Q for VTC defined

(assuming RD is fixed)?
• A: As point Q approaches B:
• gain increases
• maximum vgs swing
decreases

Lecture 1 - MOSFETs 61
Locating the Bias Point Q
Note that a trade-off between
gain and linear range exists.
linear range is large

linear range is small

gain is low

gain is high

Lecture 1 - MOSFETs 62
 The objective is to prevent vDS from
“clipping” or entering triode region
Locating the Bias Point Q

• To define load resistance RD,

one should refer to the iD - vDS
plane.
• Two examples of RD are shown
to right for illustration:
• Q2: too close to triode
• not enough legroom Figure 5.33: Two load lines and
• Q1: too close to VDD corresponding bias points. Bias point Q1
does not leave sufficient room for
• not enough headroom positive signal swing at the drain (too
• Ideally, we want to be close to VDD). Bias point Q2 is too close
somewhere in the middle. to the boundary of the triode region
and might not allow for sufficient
Lecture 1 - MOSFETs 63
negative signal swing.
 input voltage to dc bias
output voltage
be amplified voltage
Small-Signal Operation and Models
• Previously it was stated that linear
amplification may be obtained from
MOSFET via…
• Operation in saturation region
• Utilization of small-input
• This section will explore small-signal
operation in detail
• Note the conceptual amplifier
circuit to right

Figure 5.34: Conceptual circuit utilized

to study the operation of the MOSFET
Lecture 1 - MOSFETs as a small-signal amplifier. 64
 The DC Bias Point

• Q: How is dc bias current ID defined?

only applies in saturation where VDS VOV

1 1
(eq5.40) ID = kn (VGS − Vt ) = knVOV
2 2

2 2
(eq5.41) VDS = VDD − RD ID

Figure 5.34: Conceptual circuit utilized

to study the operation of the MOSFET
Lecture 1 - MOSFETs as a small-signal amplifier. 65
The Signal Current in the Drain Terminal
(eq5.42) vGS = VGS + vgs
−−−−−−−−−−−−−−−−−−−−−−−
• Q: What is effect of vgs action: state (5.17)

on iD?  
2

1 
• step #1: Define vGS as in (eq5.17) iD = kn VGS + vgs − Vt 
2  
(5.42).  v GS 
vOV

• step #2: Define iD, action: expand the squared

term via VGS −Vt and vgs

separate terms as
1 (VGS − Vt ) + 
2

function of VGS and vgs (eq5.43) iD = kn  

2  + 2 (VGS − Vt ) vgs + vgs 
2

(VGS +vgs −Vt )

action: simplify

1
iD = kn (VGS − Vt ) +
2
Note that this differs from previous 2
(eq5.43)
analyses - because of attempt to 1
+ kn (VGS − Vt ) vgs + knvg2s
isolate the effect of vgs from VGS.
Lecture 1 - MOSFETs 2 66
 Note that to minimize nonlinear
Q: What is effect of vgs on iD? distortion, vgs should be kept small.
½knvgs2 << kn(VGS-Vt)vgs
• step #3: Classify terms. vgs << 2(VGS-Vt)
• dc bias current (ID). vgs << 2vOV
• linear gain – is desirable.
• nonlinear distortion – is undesirable, because rep. distortion.

1 1 2
(eq5.43) iD = kn (VGS − Vt ) + kn (VGS − Vt )vgs + knvgs
2

2 2
linear
dc bias current ( ID ) gain nonlinear
term distortion
term
Lecture 1 - MOSFETs 67
Q: What is effect of vgs on iD?

• step #4: Adapt (5.43) for small-signal condition.

• If vgs << 2vOV , neglect distortion.

1 1 2
(eq5.43) iD = kn (VGS − Vt ) + kn (VGS − Vt )vgs + knvgs
2

2 2
linear
dc bias current ( ID ) gain nonlinear
term distortion
term

vgs
(eq5.47) MOSFET transconductance gm = = kn (VGS − Vt )
id
Lecture 1 - MOSFETs
68
Figure 5.35: Small-signal operation
Lecture 1 - MOSFETsof the MOSFET amplifier. 69
Biasing in MOS Amplifier Circuits
1) Biasing by fixing VGS

Bad biasing!

Figure 5.51 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2 represent extremes among
units of the same type.
Lecture 1 - MOSFETs 70
Biasing in MOS Amplifier Circuits
2) Biasing by fixing VG and Connecting RS

𝐼𝐷1 ≈ 𝐼𝐷2 , 𝑉𝑂𝑉1 ≈ 𝑉𝑂𝑉2

𝑽 𝑽
𝑽𝑮 = 𝑪𝒐𝒏𝒔𝒕𝒂𝒏𝒕 = 𝑽𝑮𝑺 + 𝑽𝑹𝑺 = 𝑽𝑮𝑺 +𝑰𝑫 𝑹𝑺 ⇒ 𝑰𝑫 = 𝑹𝑮 − 𝑹𝑮𝑺
𝑺 𝑺

Figure 5.52 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic arrangement; (b) reduced variability
in ID; (c) practical implementation using a single supply; (d) coupling Lecture 1 -source
of a signal MOSFETs
to the gate using a capacitor CC1; (e) practical implementation using two 71
supplies.
Biasing in MOS Amplifier Circuits
2) Biasing by fixing VG and Connecting RS
Example 6.11, p. 437

Design Rule of thumb :

RD, RS chosen so that: VRD=VRS=VDS=VDD/3

Lecture 1 - MOSFETs 72
Biasing in MOS Amplifier Circuits
3) Biasing using Drain-to-Gate feedback resistor

𝑉𝐷𝑆 = 𝑉𝐺𝑆 = 𝑉𝐷𝐷 − 𝑅𝐷 𝐼𝐷

𝑉𝐷𝐷 = 𝑉𝐺𝑆 + 𝑅𝐷 𝐼𝐷

Figure 5.54 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.
Lecture 1 - MOSFETs 73
 The Voltage Gain

• Q: How is voltage gain (Av) defined?

• step #1: Define vDS for circuit of
Figure 5.34 using KVL.

action: apply
small-signal
condition

vDS = VDD − RD iD = VDD − RD ( ID + id )

action: regroup terms action: simplify

vDS = VDD − RD ID − RD id = VDS − RD id Figure 5.34: Conceptual circuit utilized

to study the operation of the MOSFET
dc comp vds
Lecture 1 - onent
MOSFETs as a small-signal amplifier.
(VDS ) 74
 Q: How is voltage gain (Av) defined?

• step #2: Isolate vds component of action: isolate vds

vDS. (eq5.50) vds = −RD id

• step #3: Solve for gain (Av). action: insert (5.47)

(eq5.50) vds = −RD ( gmvgs )

( 5.47)

−−−−−−−−−−−−−−−
action: solve for gain

vds
Figure 5.34: Conceptual circuit utilized (eq5.51) Av = = −gm RD
to study the operation of the MOSFET
Lecture 1 - MOSFETs
vgs
as a small-signal amplifier. 75
The Voltage Gain

• Output signal is shifted

from input by 180O.
• Input signal vgs << 2(VGS –
Vt).
• Operation should remain in
MOSFET saturation region
• vDS > vGS – Vt (legroom)
• vDS < VDD (headroom)
Figure 5.36: Total instantaneous
voltage vGS and vDS for the circuit in
Lecture 1 - MOSFETs Figure 5.34. 76
Basic MOSFET Amplifier Configurations

Important note:
The more general definition for the amplifier
category is based on the connection of the
“concerned” terminal to a Constant voltage:
Example:
CS-Amplifier: is where the source terminal is
connected to a constant voltage (ground or
else)
Lecture 1 - MOSFETs 77
This means the terminal (Source in this case)
Small-Signal Equivalent Models

• From signal POV, FET behaves

as VCCS.
• Accepts vgs between gate
and source
• Provides current (iD) at
drain
• Input resistance is high
• b/c gate terminal draws
Figure 5.37: Small-signal models for the
iG = 0 MOSFET: (a) neglecting the dependence
• Output resistance is high of iD on vDS in saturation (the channel-
length modulation effect) and (b)
including the effect of channel length
Lecture 1 - MOSFETs modulation 78
 Note that this resistor (ro)
takes on value 10kOhm to
Small-Signal Equivalent Models 1MOhm and represents
channel-length modulation.

Figure 5.37: Small-signal models for the MOSFET: (a) neglecting the dependence of
iD on vDS in saturation (the channel-length modulation effect) and (b) including the
effect of channel
Lecture 1length
- MOSFETsmodulation 79
More Observations

• Model (b) is more accurate

than model (a)
less accurate, b/c does not consider
• ro = VA / ID channel length modulation

• Small signal parameters (eq5.51) Av =

vds
= −gm RD
(gm, ro) both depend on dc vgs
bias point vds
(eq5.54) Av = = −gm ( RD ||ro )
• If channel-length vgs
modulation is considered, more accurate, b/c does consider
channel length modulation
(5.51) becomes (5.54).
Lecture 1 - MOSFETs 80
The Transconductance gm

• Observations from (5.47) vgs

• gm is proportional to mn, Cox, (eq5.47) gm = = kn (VGS − Vt )
id
ratio W/L, dc component VOV. action: make some
• MOSFET with short / wide substitutions

channel provides maximum W

gain. (eq5.47) gm = kn (VGS − Vt )
L
• Gain may be increased via VGS, kn
but not without reducing action: simplify
allowable swing of vgs. W
(eq5.55) gm = kn VOV
L

Lecture 1 - MOSFETs 81
 1 W 2
(eq5.40) ID = kn VOV
The Transconductance gm 2 L
action: solve
(5.40) for VOV

2ID
• Observations from (5.47) (eq5.40) VOV =
kn W / L
• gm is proportional to square
root of dc bias current (ID) −−−−−−−−−−−−−−−−
• For given ID, gm is proportional W
to (W/L)1/2 
(eq5.55) gm = kn VOV
L
• This behavior is sharp contrast action: substitute for
VOV as defined above
to the bipolar junction
W 2ID
transistor (BJT). (eq5.56) gm = kn
• For which, gm is proportional to L knW / L
gm alone (not size or geometry). action: simplify

(eq5.56) gm = 2kn W / L ID
Lecture 1 - MOSFETs 82
 The Transconductance gm

• Figure 5.38 illustrates the

relationship defined in (5.57).
W
(eq5.55) gm = kn VOV
L
W
action: replace kn
L

 2ID 
(eq5.56) gm =  VOV
 (V − V )2 
 GS t 
action: simplify
Figure 5.38: The slope of the tangent at
2ID 2ID
(eq5.57) gm = = the bias point Q intersects the vOV axis
VGS − Vt VOV
Lecture 1 - MOSFETs at 1/2VOV. Thus gm = ID/(1/2VOV). 83
The Transconductance gm

• In summary, there are

three relationships for
determining gm:
• (5.55), (5.56), and W
(eq5.55) gm = kn VOV
(5.57) L
• These relationships are (eq5.56) gm = 2kn W / L ID
dependent on three 2ID
design parameters: (eq5.57) gm =
VOV
• W/L, VOV, ID

Lecture 1 - MOSFETs 84
Example 5.10: MOSFET Amplifier

• Example 5.10 Problem Statement: Figure 5.39(a) shows a

discrete common-source MOSFET amplifier utilizing a drain-
to-gate resistance RG for biasing purposes. Such a biasing
arrangement will be studied in Section 5.7. The input signal vI
is coupled to the gate via a large capacitor, and the output
signal at the drain is couppled to the load resistance RL via
another large capacitor. The transistor has Vt = 1.5V, k’n(W/L)
= 0.25mA/V2, and VA = 50V. Assume the coupling capacitors
to be sufficiently large so as to act as short circuits at the
signal-frequencies of interest.
• Q: We wish to analyze this amplifier circuit to determine its
(a) small-signal voltage gain, its (b) input resistance, and the
largest allowable input signal.
Lecture 1 - MOSFETs 85
 note: capacitors block dc
signals completely, but
have no effect on small-
signal

Lecture 1 - MOSFETs 86
The T Equivalent-Circuit Model
• Through circuit transformation,
it is possible to develop
alternative circuit models
• T-Equivalent-Ckt Model is
shown to right.

Figure 5.40: Development of the T

equivalent-circuit model for the
MOSFET. For simplicity, ro has been
omitted; however, it may be added
between D and S in the T model of (d).
Lecture 1 - MOSFETs 90
 ro

Figure 5.40: Development of the T equivalent-circuit model for the MOSFET. For
simplicity, ro has been omitted; however, it may be added.
Lecture 1 - MOSFETs 91
Lecture 1 - MOSFETs 92
Lecture 1 - MOSFETs 93
Characterizing Amplifiers

𝒗𝒊
𝑹𝒊𝒏 ≡ : Input Resistance
𝒊𝒊
𝒗𝒐
𝑨𝒗𝒐 ≡ ቤ : Open-circuit Voltage-gain
𝒗𝒊 𝑹 =∞(𝒐𝒑𝒆𝒏−𝒄𝒊𝒓𝒄𝒖𝒊𝒕)
𝑳
𝒗𝒙
𝑹𝒐 = ቤ : Output Resistance
𝒊𝒙 𝒗 =𝟎
𝒊
𝒗𝒐 𝑹𝑳
𝑨𝒗 ≡ = 𝑨𝒗𝒐 : Voltage-gain
𝒗𝒊 𝑹 𝑳 + 𝑹𝒐
𝑹𝒊𝒏
𝒗𝒊 = 𝒗𝒔𝒊𝒈
𝑹𝒊𝒏 + 𝑹𝒔𝒊𝒈
𝑹𝒊𝒏 𝑹𝑳
𝑮= 𝑨𝒗𝒐 : Overall-Voltage-gain
𝑹𝒊𝒏 + 𝑹𝒔𝒊𝒈 𝑹𝑳 + 𝑹𝒐

Lecture 1 - MOSFETs 94
Characterizing Amplifiers: CS-Amplifier
𝑹𝒊𝒏 = ∞ : Input
Resistance
𝒗𝒐 = − 𝒈𝒎 𝒗𝒈𝒔 𝑹𝑫 ԡ𝒓𝒐
𝑨𝒗𝒐 = อ = −𝒈𝒎 𝑹𝑫 ԡ𝒓𝒐
𝒗𝒊 = 𝒗𝒈𝒔
𝑹𝑳 =∞(𝒐𝒑𝒆𝒏−𝒄𝒊𝒓𝒄𝒖𝒊𝒕)

𝒗𝒙
𝑹𝒐 = ቤ = 𝑹𝑫 ԡ𝒓𝒐 ≅ 𝑹𝑫 , 𝒂𝒔 𝑹𝑫 ≪ 𝒓𝒐
𝒊𝒙 𝒗 =𝟎
𝒊

𝒗𝒊 = 𝒗𝒔𝒊𝒈

𝑣𝑜 −𝒈𝒎 𝑣𝑖 𝑹𝑫 ԡ𝒓𝒐 ฮ𝑹𝑳

𝑮𝒗 = =
𝑣𝑠𝑖𝑔 𝑣𝑖

Lecture 1 - MOSFETs 95
Characterizing Amplifiers: CS-Amplifier

Figure 5.46 Performing the analysis directly on the circuit diagram with the MOSFET model used implicitly.

Lecture 1 - MOSFETs 96
Characterizing Amplifiers: CS-Amplifier with RS

• What are the

Characteristics of this
Amplifier 𝑹𝒊𝒏 , 𝑨𝒗𝒐 , 𝑹𝒐 and
𝑮𝒗 ?

Lecture 1 - MOSFETs 97
Characterizing Amplifiers: CG-Amplifier
Ignoring channel modulation:
1
𝜆 = 0 𝑎𝑛𝑑 𝑟𝑜 = ∞, (𝑟𝑜 = )
𝜆𝑖𝐷

𝑣𝑖 1
𝑅𝑖𝑛 = = : 𝑟𝑒𝑙𝑎𝑡𝑖𝑣𝑒𝑙𝑦 𝑙𝑜𝑤
𝑖𝑖 𝑔𝑚
𝑣0 𝑖𝑖 1
𝐴𝑣𝑜 = = 𝑅𝐷 = 𝑔𝑚 𝑅𝐷
𝑖𝑖 𝑣𝑖 1ൗ
𝑔𝑚
𝑅𝑜 = 𝑅𝐷
𝑣𝑜 𝑣𝑖 𝑣𝑜 (𝑖𝑛𝑐𝑙. 𝑅𝐿 ) 1ൗ 𝑅𝐷 ԡ𝑅𝐿 𝑹@𝒅𝒓𝒂𝒊𝒏
𝑔
𝐺𝑣 = = = Lecture𝑚1 - MOSFETs
𝑔𝑚 𝑅𝐷 ԡ𝑅𝐿 = = 98
𝑣𝑠𝑖𝑔 𝑣𝑠𝑖𝑔 𝑣𝑖 1ൗ + 𝑅 1ൗ + 𝑅 𝑹@𝒔𝒐𝒖𝒓𝒄𝒆
𝑔𝑚 𝑠𝑖𝑔 𝑔𝑚 𝑠𝑖𝑔
Characterizing Amplifiers: CD-Amplifier also called:
Source-follower
Application: voltage buffers (Active Pixel Sensors)
The need for Voltage Buffers (Unity Gain 𝑨𝒗𝒐 = 𝟏 Amplifiers)

Lecture 1 - MOSFETs 99
Figure 5.49 Illustrating the need for a unity-gain buffer amplifier.
Characterizing Amplifiers: CD-Amplifier also called:
Source-follower
Application: voltage buffers (Active Pixel Sensors)

𝑅𝐿
𝑅𝑖𝑛 = ∞ 𝐴𝑣0 = lim 𝐺𝑣 = 𝐴𝑣 = =1
𝑅𝐿 →∞ 𝑅𝐿 + 1/𝑔𝑚

𝑅𝐿
𝑅𝑜 = 1/𝑔𝑚 𝐺𝑣 = 𝐴𝑣 =
𝑅𝐿 + 1/𝑔𝑚 , because 𝑅𝑖𝑛 = ∞ (remember the voltage divider ☺)➔𝑣𝑖 = 𝑣𝑠𝑖𝑔 ⇒ 𝐴𝑣 = 𝐴𝑣𝑜
Lecture 1 - MOSFETs 100
Characterizing Amplifiers: CD-Amplifier also called:
Source-follower
Application: voltage buffers (Active Pixel Sensors)

Lecture 1 - MOSFETs 101

Summary and Comparison

Lecture 1 - MOSFETs 102

Review 1
• Draw DC and AC equivalent circuits

Lecture 1 - MOSFETs 103

Review 2
The NMOS transistor has Vt = 0.7 V.
a) What type of amplifier is it?
b) Draw the DC equivalent circuit,
c) If ID = 0.5 mA and VOV = 0.3 V, what is the mode of operation of the MOSFET?
d) Draw the AC equivalent circuit,
e) Find the input resistance Rin.
f) Determine the voltage gain of the amplifier proper Av
g) Find the overall voltage gain Gv
h) Find the maximum allowable value of vsig for which the transistor remains in
saturation. What is the corresponding amplitude of the output voltage?

Lecture 1 - MOSFETs 104

Thank you!

Lecture 1 - MOSFETs 105