MC34060A, MC33060A

Fixed Frequency, PWM,

Voltage Mode Single Ended
Controllers
The MC34060A is a low cost fixed frequency, pulse width
modulation control circuit designed primarily for single−ended http://onsemi.com
SWITCHMODEt power supply control.
The MC34060A is specified over the commercial operating
temperature range of 0° to +70°C, and the MC33060A is specified MARKING
over an automotive temperature range of −40° to +85°C. DIAGRAMS
14
Features SOIC−14 MC3x060ADG
• Complete Pulse Width Modulation Control Circuitry 14 D SUFFIX AWLYWW
CASE 751A
• On−Chip Oscillator with Master or Slave Operation 1 1
• On−Chip Error Amplifiers
• On−Chip 5.0 V Reference, 1.5% Accuracy
14
• Adjustable Dead−Time Control PDIP−14
MC3x060AP
• Uncommitted Output Transistor Rated to 200 mA Source or Sink P SUFFIX
AWLYYWWG
14 CASE 646
• Undervoltage Lockout
1
• These are Pb−Free and Halide−Free Devices 1

x = 3 or 4
A = Assembly Location
WL = Wafer Lot
PIN CONNECTIONS
Y, YY = Year
WW = Work Week
G = Pb−Free Package
Noninv Noninv
1 + + 14 Input
Input
Error Error
Amp 1 2 Amp ORDERING INFORMATION
Inv Inv See detailed ordering and shipping information in the package
2 - - 13 Input
Input VCC dimensions section on page 14 of this data sheet.

Compen/PWM 5.0 V
3 12 Vref
Comp Input ref
0.1V
Dead-Time
4 11 N.C.
Control

CT 5 10 VCC
Oscillator
RT 6 9 C
Q1
Ground 7 8 E

(Top View)

© Semiconductor Components Industries, LLC, 2011 1 Publication Order Number:

March, 2011 − Rev. 7 MC34060A/D
 MC34060A, MC33060A

MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.)
Rating Symbol Value Unit
Power Supply Voltage VCC 42 V
Collector Output Voltage VC 42 V
Collector Output Current (Note 3) IC 500 mA
Amplifier Input Voltage Range Vin −0.3 to +42 V
Power Dissipation @ TA ≤ 45°C PD 1000 mW
Operating Junction Temperature TJ 125 °C
Storage Temperature Range Tstg −55 to +125 °C
Operating Ambient Temperature Range TA °C
For MC34060A 0 to +70
For MC33060A −40 to +85
ESD Capability
Machine Model 200 V
Human Body Model 2.0 kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1– 14: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.
Pins 1– 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A.
2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.

THERMAL CHARACTERISTICS
P Suffix D Suffix
Characteristics Symbol Package Package Unit
Thermal Resistance, Junction−to−Ambient RqJA 80 120 °C/W
Derating Ambient Temperature TA 45 45 °C

RECOMMENDED OPERATING CONDITIONS

Condition/Value Symbol Min Typ Max Unit
Power Supply Voltage VCC 7.0 15 40 V
Collector Output Voltage VC − 30 40 V
Collector Output Current IC − − 200 mA
Amplifier Input Voltage Vin −0.3 − VCC −2 V
Current Into Feedback Terminal Ifb − − 0.3 mA
Reference Output Current Iref − − 10 mA
Timing Resistor RT 1.8 47 500 kW
Timing Capacitor CT 0.00047 0.001 10 mF
Oscillator Frequency fosc 1.0 25 200 kHz
PWM Input Voltage (Pins 3 and 4) − −0.3 − 5.3 V
3. Maximum thermal limits must be observed.

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 MC34060A, MC33060A

ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted. For typical values TA = 25°C,
for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit

REFERENCE SECTION
Reference Voltage (IO = 1.0 mA, TA 25°C) Vref 4.925 5.0 5.075 V
TA = Tlow to Thigh − MC34060A 4.9 − 5.1
TA = Tlow to Thigh − MC33060A 4.85 − 5.1
Line Regulation (VCC = 7.0 V to 40 V, IO = 10 mA) Regline − 2.0 25 mV
Load Regulation (IO = 1.0 mA to 10 mA) Regload − 2.0 15 mV
Short Circuit Output Current (Vref = 0 V) ISC 15 35 75 mA

OUTPUT SECTION
Collector Off−State Current (VCC = 40 V, VCE = 40 V) IC(off) − 2.0 100 mA
Emitter Off−State Current (VCC = 40 V, VCE = 40 V, VE = 0 V) IE(off) − − −100 mA
Collector−Emitter Saturation Voltage (Note 4) Vsat(C) − 1.1 1.5 V
Common−Emitter
(VE = 0 V, IC = 200 mA)
Emitter−Follower Vsat(E) − 1.5 2.5
(VC = 15 V, IE = −200 mA)

Output Voltage Rise Time (TA = 25°C) tr ns

Common−Emitter (See Figure 12) − 100 200
Emitter−Follower (See Figure 13) − 100 200
Output Voltage Fall Time (TA = 25°C) tr ns
Common−Emitter (See Figure 12) − 40 100
Emitter−Follower (See Figure 13) − 40 100

ERROR AMPLIFIER SECTION

Input Offset Voltage (VO[Pin 3] = 2.5 V) VIO − 2.0 10 mV
Input Offset Current (VC[Pin 3] = 2.5 V) IIO − 5.0 250 nA
Input Bias Current (VO[Pin 3] = 2.5 V) IIB − −0.1 −2.0 mA
Input Common Mode Voltage Range VICR 0 to − − V
(VCC = 40 V) VCC −2.0

Inverting Input Voltage Range VIR(INV) −0.3 to − − V

VCC−2.0

Open−Loop Voltage Gain AVOL 70 95 − dB

(DVO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kW)
Unity−Gain Crossover Frequency fc − 600 − kHz
(VO = 0.5 V to 3.5 V, RL = 2.0 kW)
Phase Margin at Unity−Gain φm − 65 − deg.
(VO = 0.5 V to 3.5 V, RL = 2.0 kW)
Common Mode Rejection Ratio CMRR 65 90 − dB
(VCC = 40 V, Vin = 0 V to 38 V))

Power Supply Rejection Ratio PSRR − 100 − dB

(DVCC = 33 V, VO = 2.5 V, RL = 2.0 kW)
Output Sink Current (VO[Pin 3] = 0.7 V) IO− 0.3 0.7 − mA
Output Source Current (VO[Pin 3] = 3.5 V) IO+ −2.0 −4.0 − mA
4. Low duty cycle techniques are used during test to maintain junction temperature as close to ambient temperatures as possible.
Tlow = −40°C for MC33060A Thigh = +85°C for MC33060A
= 0°C for MC34060A = +70°C for MC34060A

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 MC34060A, MC33060A

ELECTRICAL CHARACTERISTICS (continued) (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.
For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit

PWM COMPARATOR SECTION (Test circuit Figure 11)

Input Threshold Voltage VTH − 3.5 4.5 V
(Zero Duty Cycle)

Input Sink Current II 0.3 0.7 − mA

(V[Pin 3] = 0.7 V)

DEAD−TIME CONTROL SECTION (Test circuit Figure 11)

Input Bias Current (Pin 4) IIB(DT) − −1.0 −10 mA
(Vin = 0 V to 5.25 V)

Maximum Output Duty Cycle DCmax %

(Vin = 0 V, CT = 0.01 mF, RT = 12 kW) 90 96 100
(Vin = 0 V, CT = 0.001 mF, RT = 47 kW) − 92 −
Input Threshold Voltage (Pin 4) VTH V
(Zero Duty Cycle) − 2.8 3.3
(Maximum Duty Cycle) 0 − −

OSCILLATOR SECTION
Frequency fosc kHz
(CT = 0.01 mF, RT = 12 kW, TA = 25°C) 9.7 10.5 11.3
TA = Tlow to Thigh − MC34060A 9.5 − 11.5
TA = Tlow to Thigh − MC33060A 9.0 − 11.5
(CT = 0.001 mF, RT = 47 kW) − 25 −

Standard Deviation of Frequency* σfosc − 1.5 − %

(CT = 0.001 mF, RT = 47 kW)
Frequency Change with Voltage Dfosc(DV) − 0.5 2.0 %
(VCC = 7.0 V to 40 V)

Frequency Change with Temperature Dfosc(DT) %

(DTA =Tlow to Thigh) − 4.0 −
(CT = 0.01 mF, RT = 12 kW) − − −

UNDERVOLTAGE LOCKOUT SECTION

Turn−On Threshold (VCC increasing, Iref = 1.0 mA) Vth 4.0 4.7 5.5 V
Hysteresis VH 50 150 300 mV

TOTAL DEVICE
Standby Supply Current ICC mA
(Pin 6 at Vref, all other inputs and outputs open)
(VCC = 15 V) − 5.5 10
(VCC = 40 V) − 7.0 15
Average Supply Current IS − 7.0 − mA
(V[Pin 4] = 2.0 V, CT = 0.001 mF, RT = 47 kW). See Figure 11.

*Standard deviation is a measure of the statistical distribution about the mean as derived from the formula; σ = Σ (xn −x)2
n−1
N −1

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 MC34060A, MC33060A

6
Reference 10
Oscillator Regulator VCC
5
RT
CT Dead-Time Undervoltage
Comparator Lockout 12
- - Ref Out
4 0.12V
Dead-Time + +
Control
0.7V VTH
-
+ 9 Collector
PWM.
Comparator Q1 8
≈ 0.7mA
Emitter
+ +
1 2
- -

1 2 3 13 14 7 GND
Error Amp Feedback/PWM Error Amp
1 Comparator Input 2
This device contains 46 active transistors.

Figure 1. Block Diagram

Description Output pulse width modulation is accomplished by

The MC34060A is a fixed−frequency pulse width comparison of the positive sawtooth waveform across
modulation control circuit, incorporating the primary capacitor CT to either of two control signals. The output is
building blocks required for the control of a switching power enabled only during that portion of time when the sawtooth
supply (see Figure 1). An internal−linear sawtooth oscillator voltage is greater than the control signals. Therefore, an
is frequency−programmable by two external components, increase in control−signal amplitude causes a corresponding
RT and CT. The approximate oscillator frequency is linear decrease of output pulse width. (Refer to the Timing
determined by: Diagram shown in Figure 2.)
fosc ^ 1.2
RT • CT
For more information refer to Figure 3.

Capacitor CT
Feedback/P.W.M.
Comparator

Dead-Time Control

Output Q1,
Emitter

Figure 2. Timing Diagram

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 MC34060A, MC33060A

APPLICATIONS INFORMATION

The control signals are external inputs that can be fed into pin varies from 0.5 V to 3.5 V. Both error amplifiers have a
the dead−time control, the error amplifier inputs, or the common mode input range from −0.3 V to (VCC −2.0 V), and
feed−back input. The dead−time control comparator has an may be used to sense power supply output voltage and
effective 120 mV input offset which limits the minimum current. The error−amplifier outputs are active high and are
output dead time to approximately the first 4% of the ORed together at the noninverting input of the pulse−width
sawtooth−cycle time. This would result in a maximum duty modulator comparator. With this configuration, the
cycle of 96%. Additional dead time may be imposed on the amplifier that demands minimum output on time, dominates
output by setting the dead time−control input to a fixed control of the loop.
voltage, ranging between 0 V to 3.3 V. The MC34060A has an internal 5.0 V reference capable
The pulse width modulator comparator provides a means of sourcing up to 10 mA of load currents for external bias
for the error amplifiers to adjust the output pulse width from circuits. The reference has an internal accuracy of ±5% with
the maximum percent on−time, established by the dead time a typical thermal drift of less than 50 mV over an operating
control input, down to zero, as the voltage at the feedback temperature range of 0° to +70°C.

500 k 120

A VOL , OPEN LOOP VOLTAGE GAIN (dB)

110 VCC = 15 V
f osc , OSCILLATOR FREQUENCY (Hz)

VCC = 15 V DVO = 3.0

θ , EXCESS PHASE (DEGREES)

100
100 k 0.001 mF V
90 RL = 2.0 kW 0
80 AVOL -20
70 -40
60 q -60
10 k CT = 0.01 mF 50 -80
40 -100
30 -120
1.0 mF 20 -140
1.0 k -160
10
500 0 -180
1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 1.0 10 100 1.0 k 10 k 100 k 1.0 M
RT, TIMING RESISTANCE (W) f, FREQUENCY (Hz)
Figure 3. Oscillator Frequency Figure 4. Open Loop Voltage Gain and Phase
versus Timing Resistance versus Frequency

100
% DT, PERCENT DEAD‐TIME, Q1 OUTPUT

20
18
16 80 VCC = 15 V
PERCENT DUTY CYCLE (%)

CT = 0.001
14 RT = 47 k
12 CT = 0.001 mF 60
10
8.0 40
6.0 0.01 mF
4.0 20
2.0
0 0
500 1.0 k 10 k 100 k 500 k 0 1.0 2.0 3.0 3.5
fosc, OSCILLATOR FREQUENCY (Hz) DEAD-TIME CONTROL VOLTAGE (V)
Figure 5. Percent Deadtime versus Figure 6. Percent Duty Cycle versus
Oscillator Frequency Dead−Time Control Voltage

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 MC34060A, MC33060A

1.9 2.0
VCE(SAT) , SATURATION VOLTAGE (V)

VCE(SAT) , SATURATION VOLTAGE (V)

1.8 1.8

1.7 1.6

1.6 1.4

1.5 1.2

1.4 1.0

1.3 0.8
1.2 0.6

1.1 0.4
0 100 200 300 400 500 0 100 200 300 400 500
IE, EMITTER CURRENT (mA) IC, COLLECTOR CURRENT (mA)
Figure 7. Emitter−Follower Configuration Figure 8. Common−Emitter Configuration
Output Saturation Voltage versus Output Saturation Voltage versus
Emitter Current Collector Current

10
VTH, UNDERVOLTAGE LOCKOUT THRESHOLD (V)
6.0
9.0
8.0
I CC, SUPPLY CURRENT (mA)

5.5
7.0
6.0
Turn On
5.0 5.0
4.0
3.0 Turn Off
4.5
2.0
1.0
0 4.0
0 5.0 10 15 20 25 30 35 40 0 5.0 10 15 20 25 30 35 40
VCC, SUPPLY VOLTAGE (V) IL, REFERENCE LOAD CURRENT (mA)
Figure 9. Standby Supply Current Figure 10. Undervoltage Lockout Thresholds
versus Supply Voltage versus Reference Load Current

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 MC34060A, MC33060A

VCC = 15V

Dead- VCC 150W

Time 2W
Error Amplifier Test
+ Under Test Inputs Feedback
Vin RT C Output
- CT E
(+)
Feedback (-)
Terminal Error
(+)
(Pin 3)
(-)
Ref
+ 50kW Out
Gnd
Vref - Other Error
Amplifier

Figure 11. Error Amplifier Characteristics Figure 12. Deadtime and Feedback Control

15V
15V
RL C
68W
VC Output
C Transistor

Output CL VE
E
Transistor 15pF CL
RL
68W 15pF
E

90% 90% 90% 90%

VC VE
10% 10% 10% 10%

tr tf tr tf

Figure 13. Common−Emitter Configuration Figure 14. Emitter−Follower Configuration

and Waveform and Waveform

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 MC34060A, MC33060A

VO
To Output
Voltage of Vref
System
R1
1 1
+ + R2
3 3
Vref - -
2 Error Error 2
Amp Amp
R2
R1
Positive Output Voltage Negative Output Voltage To Output
Voltage of
R1 R1 System
VO = Vref (1 + ) VO = -Vref (1 + ) VO
R2 R2

Figure 15. Error Amplifier Sensing Techniques

Vref R1
4
Output Q DT
+
RT CT
R2 R1 CS
6 5 Vref -
4
Output Q DT

47k 160 R2
0.001 Max % On Time ≈ 92 - R
1+ 1
R2

Figure 16. Deadtime Control Circuit Figure 17. Soft−Start Circuit

Vref

6
RT
Master
5
CT

RT CT
Vref

6
RT
Slave (Additional
5 Circuits)
CT

Figure 18. Slaving Two or More Control Circuits

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 MC34060A, MC33060A

150mH @ 2.0A
Vin = 8.0V to 40V Vout
Tip 32
5.0V/1.0A
47

4.7k
10
VCC 75
0.01 1
+
47k
2 9
- C
1.0M
3
Comp
+ MC34060A +
50/50 14 MR850
+ 1000
0.01 6.3V
13 8
- E
12 7
4.7k Vref GND
DT CT RT
4 5 6
10/16V
+ 0.001
4.7k 4.7k 47k

150 390

0.1

Test Conditions Results

Line Regulation Vin = 8.0 V to 40 V, IO = 1.0 A 25 mV 0.5%
Load Regulation Vin = 12 V, IO = 1.0 mA to 1.0 A 3.0 mV 0.06%
Output Ripple Vin = 12 V, IO = 1.0 A 75 mV p−p P.A.R.D.
Short Circuit Current Vin = 12 V, RL = 0.1 W 1.6 A
Efficiency Vin = 12 V, IO = 1.0 A 73%

Figure 19. Step−Down Converter with Soft−Start

and Output Current Limiting

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 MC34060A, MC33060A

150mH @ 4.0A 20mH @ 1.0A

Vin = 8.0V to 26V MR850 Vout
*
28V/
0.5A
22k

10
0.05 VCC
1
+
33k
2 9
4.7k - C
2.7M
3
Comp
+ + +
50/35V 14 MC34060A *
+
470/ 470/
13 8 300 35V 35V
3.9k - E Tip 111
12 7
Vref GND
DT CT RT 0.1

4 5 6
4.7k
0.001 470
47k
390

Test Conditions Results

Line Regulation Vin = 8.0 V to 26 V, IO = 0.5 A 40 mV 0.14%
Load Regulation Vin = 12 V, IO = 1.0 mA to 0.5 A 5.0 mV 0.18%
Output Ripple Vin = 12 V, IO = 0.5 A 24 mV p−p P.A.R.D.
Efficiency Vin = 12 V, IO = 0.5 A 75%
*Optional circuit to minimize output ripple

Figure 20. Step−Up Converter

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 MC34060A, MC33060A

Vin = 8.0V to 40V Tip 32C MR851 Vout

20mH * -15V/
@ 1.0A 0.25A
47
30k

10

0.01 VCC 75
1
+
47k
2 9
7.5k - C
1.0M
+ 3
Comp
50/50V *
14 MC34060A 150mH 330/ 330/
+ @ 2.0A + 16V + 16V
0.01 13 8
- E
12 7
Vref GND
10k DT CT RT

10/16V 4 5 6

0.001
47k 4.7k 47k

3.3k 820

1.0

Test Conditions Results

Line Regulation Vin = 8.0 V to 40 V, IO = 250 mA 52 mV 0.35%
Load Regulation Vin = 12 V, IO = 1.0 to 250 mA 47 mV 0.32%
Output Ripple Vin = 12 V, IO = 250 mA 10 mV p−p P.A.R.D.
Short Circuit Current Vin = 12 V, RL = 0.1 W 330 mA
Efficiency Vin = 12 V, IO = 250 mA 86%
*Optional circuit to minimize output ripple

Figure 21. Step−Up/Down Voltage Inverting Converter

with Soft−Start and Current Limiting

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 L1
1N4003 T2 1N5824 5.0V/3.0A
+ +
3 each 2200/10V 100/10V
0.0047 UL/CSA 3/200
Vac L2
1N4934 1N4934 12/075A
* + +
* T1 1N4001 47/25V +
1000/25V 10/35V Common
* 22k
10 + L3 +
+ 1000/25V 10/35V
* 180/200V VCC
1 9
1N4742 + C 1N4934 -12/0.75A
1N4937
2
1.0A -
T 15Ω 2.2M 33k
Cold 0.01 3
Comp
MPS
115 Vac 7.5k 1N4687 6.8k MC34060A
14 A05
± 20% +
10/25V
13 8 MJE
- E
+ 13005
12 7 MPS
Vref GND A55
8.2k

13
DT CT RT
*Optional R.F.I. Filter
4 5 6
+ 200 47
0.001

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Vout Pout 10 47k
1.5k
5.0k 25k
27k
11k 1.0
MC34060A, MC33060A

0.01

1N4148 2.7k

Test Conditions Results

T1 − Coilcraft W2961
Line Regulation 5.0 V V in = 95 Vac to 135 Vac, IO = 3.0 A 20 mV 0.40% T2 − Core: Coilcraft 11−464−16,
Line Regulation ±12 V V in = 95 Vac to 135 Vac, IO = ±0.75 A 52 mV 0.26% 0.025″ gap in each leg.
Bobbin: Coilcraft 37−573
Load Regulation 5.0 V V in = 115 Vac, IO = 1.0 A to 4.0 A 476 mV 9.5%
Windings:
Load Regulation ±12 V V in = 115 Vac, IO = ±0.4 A to ±0.9 A 300 mV 2.5% Primary, 2 each, 75 turns #25 Awg Bifilar wound
Output Ripple 5.0 V V in = 115 Vac, IO = 3.0 A 45 mV p−p P.A.R.D. Feedback: 15 turns #26 Awg
Output Ripple ±12 V V in = 115 Vac, IO = ±0.75 A 75 mV p−p P.A.R.D. Secondary, 5.0 V, 6 turns @33 Awg Bifilar wound
Secondary, 2 each, 14 turns #24 Awg Bifilar wound
Efficiency V in = 115 Vac, IO 5.0 V = 3.0 A 74% L1 − Coilcraft Z7156, 15 μH @ 5.0 A
IO ±12 V = ±0.75 A
L2, L3 − Coilcraft Z7157, 25 μH @ 1.0 A

Figure 22. 33 W Off−Line Flyback Converter with Soft−Start and Primary Power Limiting
 MC34060A, MC33060A

ORDERING INFORMATION
Operating
Shipping†
Device Temperature Range Package
MC34060ADG SOIC−14
55 Units / Rail
(Pb−Free)

MC34060ADR2G SOIC−14
TA= 0° to +70°C 2500 / Tape & Reel
(Pb−Free)

MC34060APG PDIP−14
25 Units / Rail
(Pb−Free)

MC33060ADG SOIC−14
55 Units / Rail
(Pb−Free)

MC33060ADR2G SOIC−14
TA= −40° to +85°C 2500 / Tape & Reel
(Pb−Free)

MC33060APG PDIP−14
25 Units / Rail
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 MC34060A, MC33060A

PACKAGE DIMENSIONS

SOIC−14
CASE 751A−03
ISSUE H

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−A− 2. CONTROLLING DIMENSION: MILLIMETER.
14 8 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B− 5. DIMENSION D DOES NOT INCLUDE
P 7 PL DAMBAR PROTRUSION. ALLOWABLE
0.25 (0.010) M B M DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.

G MILLIMETERS INCHES
R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
−T− F 0.40 1.25 0.016 0.049
K M J
SEATING D 14 PL G 1.27 BSC 0.050 BSC
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

SOLDERING FOOTPRINT*
7X
7.04 14X
1.52
1
14X
0.58

1.27
PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MC34060A, MC33060A

PACKAGE DIMENSIONS

PDIP−14
CASE 646−06
ISSUE P

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
F L C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
N C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
−T− J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING L 0.290 0.310 7.37 7.87
PLANE
K J M −−− 10 _ −−− 10 _
H G D 14 PL N 0.015 0.039 0.38 1.01
M
0.13 (0.005) M

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