The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

2
The scaling of MOSFETs, Moore’s law, and ITRS

For the last three decades, the microelectronic industry has benefited
enormously from the MOSFET miniaturization. The shrinking of transistors to
dimensions below 100 nm enables hundreds of millions transistors to be placed on a
single chip. The increased functionality and reduced cost of large variety of integrated
circuits and systems has brought its own benefit to the end users and above all the
semiconductor industry. A low cost of manufacturing, increased speed of data transfer,
computer processing power and the ability to accomplish multiple tasks simultaneously
are some of the major advantages gained as a result of transistor scaling.
This chapter has four main sections. The first section deals with the Moore’s law
and its impact on the overall development of semiconductor technology and on
MOSFET scaling in particular. Then the contributions made by the International
Technology Roadmap for Semiconductors (ITRS) to the advancement of
microelectronics technology from the MOSFET point of view are briefly discussed. At
the same time the influence of the ITRS on the current priorities and directions related
to the scaling of transistors will be discussed.
Section two describes the two basic forms of scaling considered by industry and
research communities. Some of the fundamental limitations that that will eventually
limit the scaling of conventional MOSFETs are examined in section three. The chapter
ends with a summary presented in section four.

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

2.1 The impact of Moore’s law and ITRS on device scaling

Moore’s ‘law’ and the ITRS have been complimenting each other since the first
edition of the roadmap in the early 90’s. The former has been cast as a law from
engineering observation made by G. Moore in the mid sixties [2:1]. It was initially a
forecast on the number of transistors that can be integrated into a microchip for the next
ten years (1965-1975), but the trend remained almost unchanged over the next three
decades. The ITRS on the other hand is a comprehensive guide that enables the
semiconductor industry to transform this observation into reality. At this stage,
however, one has to be careful when interpreting “Moore’s law”, as a physical or
mathematical law. Despite the efforts made by Meindle [2.2] to formulate the “compact
mathematical formulation of the Moore’s law” ( N = F −2 D 2 PE where N is the number of
transistors per chip, F is the minimum feature size, D is the chip area, and PE is
transistor packaging efficiency measured per minimum feature area), it remains simply
an empirical observation on the rate of growth of semiconductor technology [2.3]
originating from the forecast depicted inset to figure 2:1. Therefore, in order to clarify
its role on the growth of semiconductor industry, in the following sub sections Moore’s
law is discussed briefly together with the ITRS mainly from the MOSFET scaling point
of view.

2.1.1 Moore’s Law

Back in time when Gordon Moore published his article, “Cramming more
components onto integrated circuits” in 1965 [2:1], he was probably not aware of its
impact on the remarkable progress of semiconductor technology in the years to come. In
this publication he made an observation that it will be possible to integrate 6.5 × 10 4
components into a single chip by 1975, provided that the number of active transistor per
chip doubled roughly every year. As illustrated in figure 2:1 the advances of the
semiconductor technology have been able to follow this predicted trend.
When G. Moore made his prediction, the number of transistors in a single chip
was roughly 32 and today there are approximately half a billion transistors integrated on
a single microprocessor (figure 2:1). This phenomenal growth has demonstrated how

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

visionary his prediction was, and how vital has it been to the technology enabling the
shrinking of individual transistors. The scaling of MOSFETs, which are the key
components in digital technology, has revolutionized the semiconductor industry and
has also enabled the realization of the immensely complex devices and systems we rely
on at present.
Although the “Moore’s law” has been interpreted differently at the different
stages of the semiconductor technology industry’s development, the formulation that
has been accepted as a general consensus states that: “the number of components per
chip doubles every 18 months” [2.4]. Note that the original assumption made by Moore,
according to the inset in figure 2.1, was that the number of components per chip will be
doubled every 12 months. Indeed the originally stated rate of development was
maintained in the seventies, as shown by Moore himself in 1975 [2.5], and continued to
the early eighties. The present 18 months period of doubling of the chip components is a
modification in line with the past and present (2003) ITRS editions and the real state of
the industry.

109 1b transistors o
o
o
(2007) o
o
108
Transistors / processor

410m Transistors 16
1958 1960 1962 1964 1966 1968 1970 1972 1974
7 2 65536
10 (2003) 14
2 16384

12
per

2 4096

10 6 1m Transistors 10
2 1024
integrated function
Number of Components

8
2 256

5 6
10 2
4
64

2 16

104 2 4

0
2 1
1958 1960 1962 1964 1966 1968 1970 1972 1974
3 2500 Transistors Yeay of production
10
1970
1975
1980
1985
1990
1995
2000
2005
2010

Year of introduction

Figure 2:1 Visualization of Moore’s Law: The number of transistors integrated in a commercially
available processor and the outlook towards a billion transistors in a single processor due in year 2007
(Intel). The inset graph: Projection made by Moore on his original paper on the number of components
per integrated device [2.1]

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

2.1.2 Implication of Moore’s law

Moore’s law has had various implications on the microelectronics

manufacturing industry and user applications in general over the last 30 years. As a
result, increasing functionality [2.6], cost per function reduction, and better
performance, have all been achieved for every new generation of integrated circuits.
According to the ITRS, the functionality is defined as the number of bits in a
DRAM chip or the number of logic transistors in a microprocessor unit. With the
integration of more individual components in a single chip the functionality per chip
increases (figure 2:2) together with the increase in the density of functions
(functions/area). The increase in functionality minimizes the delay of data flow that
occurs due to the isolation of individual functions on separately integrated systems
[2.7]. More functionality also means an increase in overall physical density of useable
transistors per total chip area. Figure 2:2 shows according to the ITRS, that in both the
near-term (2003-2009) and the long-term (20010-2018) functionality will be increasing
by roughly 100% in every technology nodes.

Functionality per Chip 4

100 Cost-Performance MPU 3.0x10
High-Performance MPU 2.5x10
4
80
Micro cent / transistor

Transistors

4
2.0x10
60
4
1.5x10
40 4
1.0x10
× Million

20 3
5.0x10
0 0.0
2001

2004

2007

2010

2013

2016

2019

Year of Introduction

Figure 2:2 Cost – performance of Microprocessor Unit (MPU), cost of high speed performance MPU and
functionality (functionality is often associated with the number of bits or unit devices in MPU) against the
year of introduction of technology nodes: data ITRS 2004 update.

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

The second important feature associated with the Moore’s law is cost. It is a
general rule that the goal of every manufacturing community is maximizing the profit
while minimizing the cost of production. The electronics industry is not unique in this.
In fact the primary implication of the Moore’s law is the reduction of manufacturing
cost per function and at the same time to increase the functionality per chip. As it can be
seen from figure 2:2 the reduction in cost-per-function according to the latest ITRS
edition, is roughly 50% in about two years.
The third important implication of Moore’s law is the performance factor.
Performance in general can be measured, for example, by the speed of typical
microprocessors. Figure 2:3 shows the increasing speed and density of present and
future generations of technology nodes. The off-chip frequency is the maximum input
and output signal frequency to board peripheral buses of high performance devices
[2.4]. The off-chip frequency is increasing faster than the on-chip local frequency near
the end of the current edition of the ITRS.

On-Chip (local) frequency Transistors in SRAM

Off-Chip frequency Transistors in Logic
5 4
10 1.6x10
Number of transistors [x 10 ]
6
4
1.2x10
Frequency [ MHz ]

4 3
10 8.0x10

3
4.0x10

10
3 0.0
2001

2004

2007

2010

2013

2016

2019

Year of production

Figure 2:3 The technology trends of on-chip local clock, off-chip frequency, chip density in SRAM and
Logic gats (transistors per cm2). ITRS 2004 Edition

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

In general the frequency is related to the speed of switching of the individual

and simple logic components determined by CMOS transistors which is inversely
proportional to the delay time that takes to propagate signal through the inverter. The
inverter delay time formulated as [2.8]:
τ int = Rsw (Cin + Cout ) (2.1)

Where τint is the inverter delay time, Rsw is the switching resistance, Cin input
capacitance, Cout the output capacitance, and in equation 2.2, Cgate is the gate
capacitance. This inverter delay time can be used as approximation of the CMOS delay
time which is calculated empirically as: [2.9]
VDD
τ = Cgate (2.2)
I dsat

According to the generalised scaling [2.10, 2.11],τ is inversely proportional to the

scaling factor, which allows faster circuit operations. Figure 2:2 also depicts the
increase in the density of transistors in SRAM and Logic circuits. Density is inversely
proportional to the total chip area (1/A). Therefore, density will increase by κ2 as a

result of scaling, where κ ≈ 2 is the scaling constant (see section 2.1.4).

2.1.3 The International Technology Roadmap for Semiconductors

The technology roadmap is an ambitious document widely used as a guiding

reference for advanced semiconductor device research and manufacturing purposes. The
latest edition (2003)† of international technology roadmap for semiconductors (ITRS),
updated in 2004, sets main objectives and targets to 2018. Based on research from the
semiconductor industry and academia, the latest edition of the ITRS outlines the
requirements and identifies the challenges which allow Moore’s law to be maintained
over the next 15 years. In addition to the challenges, it also outlines the possible
solutions to some of the problems that the industry may face and highlights the specific
areas that need urgent research.
Overall, the roadmap has three major contributions. The first is to identify the
needs and requirements to be met by technology solutions currently under development.
The second is to recognize the existence of interim solutions for the medium term
challenges and problems and their limitations at the present time. The third important

†
The latest ITRS edition of 2005 has been published after the completion of this thesis

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

contribution of ITRS is to identify the areas where there are “no known manufacturing
solutions” customarily labelled as the “Red Brick Wall” - to induce the industry to
concentrate on them strategically and focus research efforts in these areas.
The ITRS is a comprehensive document with more than 600 pages, including the
executive summary. It covers fifteen categories related to semiconductor industry and to
basic research and development areas. One of the important sections expanded
significantly in the latest edition ITRS is on the emerging research devices. It was
organized with the aim of finding and building successful new device structures that can
replace conventional MOSFETs. Although some of the listed structures are more of
research type, the device structures such as fully depleted silicon on insulator (FD SOI)
and the multiple gates architectures including the double gate MOSFETs and FinFETs
are the promising candidates to replace mainstream device structures.

Year of Production 2003 2004 2005 2006 2007 2008 2009

Technology Node hp90 hp65
DRAM ½ Pitch (nm) 100 90 80 70 65 57 50
MPU/ASIC M1 ½ Pitch (nm) 120 107 95 85 75 67 60
MPU/ASIC Poli Si ½ Pitch (nm) 100 90 80 70 65 57 50
MPU Printed Lg (nm) 65 53 45 40 35 32 28
MPU Physical Lg (nm) 45 37 32 28 25 22 20
Equivalent tox (nm) 1.3 1.2 1.1 1 0.9 0.8 0.8
Vdd (HP) 1.2 1.2 1.1 1.1 1.1 1 1
Off current , Ioff [µA/µm] 0.03 0.05 0.05 0.05 0.07 0.07 0.07
Drive current, Ion [µA/µm] 980 1110 1090 1170 1510 1530 1590
HP NMOS intrinsic delay τ [ps] 1.2 0.95 0.86 0.75 0.64 0.54 0.48
Relative intrinsic speed, 1/τ 1 1.26 1.39 1.6 1.86 2.2 2.49
Logic gate delay [ps] 30.24 23.94 21.72 18.92 16.23 13.72 12.13
DRAM cell size [µm2] 0.082 0.065 0.048 0.036 0.028 0.019 0.015
S/D extension xj [nm] 24.8 20.4 17.6 15.4 13.8 8.8 8.0

Table 2:1 The near term years (2003-2009) of selected overall roadmap technology characteristics that
are required to continue the present scaling trends of conventional MOSFETs. Half pitch 90 and 65nm
technology nodes are marked as hp90 and hp65 respectively. (ITRS 2003 edition)

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

However, not all of these categories and data are relevant to this research.
Therefore, in this sub-section we only concentrate on the high performance devices,
which are in the heart of this work. The summarised data of device dimensions and
electrical parameters for high performance devices depicted in tables 2:1 (near-term
years) and 2:2 (long-term years) have been adopted as a guide for the scaling of the 35
nm MOSFET described in chapter 4.
The carefully calibrated 35 nm gate length MOSFETs manufactured by Toshiba
[2.12]) were used as a basis for further scaling to gate lengths of 25, 18, 13, and 9 nm
transistors. The overall calibration and scaling methodology and results are presented in
chapter 3 and 4 respectively. The dimensions of the 35 nm MOSFET physical gate
length used for this work are not characteristics of particular node on the ITRS
roadmap. It’s performance, Ion = 676µA/µm, Ioff = 100nA at Vdd = 850mV and design
parameters, tox= 1.2 nm xj = 20 nm are close to the 37 nm high performance device
required for the 90 nm node and 80 nm technology generations.

Year of Production 2010 2012 2013 2015 2016 2018

Technology Node hp45 hp32 hp22
DRAM ½ Pitch (nm) 45 35 32 25 22 18
MPU/ASIC M1 ½ Pitch (nm) 54 42 38 30 27 21
MPU/ASIC Poli Si ½ Pitch (nm) 45 35 32 25 22 18
MPU Printed Lg (nm) 25 20 18 14 13 10
MPU Physical Lg (nm) 18 14 13 10 9 7
Equivalent tox (nm) 0.7 0.7 0.6 0.6 0.5 0.5
Vdd (HP) (V) 1 0.9 0.9 0.8 0.8 0.5
Off current , Ioff [µA/µm] 0.1 0.1 0.3 0.3 0.5 0.5
Drive Current, Ion [µA/µm] 1900 1790 2050 2110 2400 2190
HP NMOS intrinsic delay τ [ps] 0.39 0.3 0.26 0.18 0.15 0.11
Relative intrinsic speed, 1/τ 3.06 4.05 4.64 6.8 8.08 10.77
Logic gate delay [ps] 9.88 7.47 6.55 4.45 3.74 2.81
DRAM cell size [µm2] 0.1222 0.0077 0.0061 0.0038 0.0025 0.0016
S/D extension depth xj [nm] ‡ 7.2 11.2 10.4 8.0 7.2 5.1
Table 2:2 The long - term years (2010-2018)

‡
The extension depth (xj) is calculated with the assumption of introducing new device structures beyond
year 2007, like fully depleted SOI and multi gate device structures. (ITRS 2003 edition)

14
The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

Although the electronics industry prefers to continue as long as possible with the
scaling of conventional MOSFETs, there is “Red Brick Wall” to this process unless
there is a major technological breakthrough. High channel doping, which degrades the
device performance, and ultra thin gate oxides, which introduce unacceptable gate
leakage, are likely to prompt a replacement to conventional MOSFETs somewhere
beyond the 65nm technology node. Among the replacement candidates are, for example,
ultra-thin body SOI and multiple gate devices complimented by the introduction of
strained silicon in the channel region to enhance the carrier mobility, and high
permittivity materials in the gate stack in order to suppress gate leakage. Some of the
critical scaling limitation factors will be examined more closely in the next sections of
this chapter.

2.1.4 The scaling factors and technology trends

The scaling factor of κ ≈ 2 , related to a 70% size reduction of the major

technology nodes every two years, has been adapted for the linear scaling of device
dimensions in this work. The other scaling constant, α for the electric field and
potential used in the generalised scaling scenario [2:10] is not specified on the road
map. However, it can be calculated from the supply voltages (Vdd), which are specified
in the roadmap for corresponding feature sizes and the linear scaling factor κ as:

α V'
V'= V ⇒α =κ (2.3)
κ V

V ' is the new supply voltage given in the technology roadmap and V is the supply
voltage of the previous generation. It should be noted that in some papers [2.13], the
linear scaling factor has been decomposed to separate dimensional scaling parameters in
the so called “selective scaling case”, which introduces different values for vertical,
horizontal, and lateral dimensions multipliers. However, in this work, the generalized
scaling rule has been adopted as a principal guiding rule for device scaling. A review of
the different scaling approaches is presented in the next section.
Unlike the previous editions of ITRS, no prediction of the technology
acceleration has been made in its latest edition (ITRS’03). Also, as illustrated in figure
2.4, in the last ITRS edition, the technology generations are predicted to shift from the
present two-year cycle to a three-year cycle trend around 2007. The technology node

15
The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

continued to be defined as 70% dimension reduction per node or approximately 50%

reduction per two nodes. The “technology-node-cycle” is the period of time in which a
new technology node is introduced.
In addition to the scaling of the gate length, the oxide thickness is another
critical parameter, which has been aggressively scaled down in order to achieve a
sufficient drive current and to control short channel effect. The later can be achieved by
maintaining the electrostatic control of the channel potential by the gate.
Figure 2:4 shows the technology half pitch (hp) and gate length trends adopted
in the ITRS’03 edition. Beyond year 2007 the two year cycle delays by another year and
is expected to be three years until the end the present roadmap projection time-line and
probably beyond. The physical gate length is conventionally adapted as minimum
feature size regarding the individual devices.

DRAM ½ Pitch MPU/ASIC ½ Pitch

MPU Physical Lg MPU Printed Lg
1000
Dimension [nm]

100

10

2 year cycle 3 year cycle

1
1992

1996

2000

2004

2008

2012

2016

2020

Year of production
Figure 2:4 Technology half-pitch and gate length trends.

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

2.2 The scaling rules for conventional MOSFETs

In the preceding sections the technology roadmap and the Moore’s law have
been discussed in order to examine their role in pursuing transistor scaling, and above
all in highlighting scaling’s unprecedented contributions to the enormous advance of
semiconductor technology. Without the extraordinary miniaturization of transistors, it
would be impossible to produce higher volumes of faster devices operating at lower
power. Nobody in the semiconductor industry disputes this state of affairs. This section
further introduces the theory and practice of the scaling process. It begins by reviewing
some of the classic papers on the constant field and generalised device scaling rules,
followed by detailed analysis of advantages and shortcomings of both rules.

2.2.1 Constant field scaling

Dennard at al. presented their pioneering research work on the scaling of

MOSFET devices at the International Electron Device Meeting (IEDM) 1972 [2.14] and
published a comprehensive paper on the scaling of MOS transistors in 1974 [2.15], from
which the “constant field scaling” theory has emerged. The basic principle which they
employ is that in order to increase the performance of a MOSFET we must reduce
linearly the size of the transistor, together with the supply voltage, and increase the
doping concentration in a way which keeps the electric field in the device constant -
hence the name “constant field scaling” (figure 2.5).

Lg Vdd LG
tOX κ Vdd
κ κ
tOX

Lch
κ

Na
Lch κ Na

Figure 2: 5 Illustration of MOSFET miniaturisation. The sketch on the right hand is the scaled device
according to the constant field rule. (Reference [2.15])

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

The scaling process is performed by a linear transformation of three design

parameters (voltage, doping concentration, and physical dimensions) of a particular
generation of transistor by the same scaling factor, κ. The scaled down device will have

a reduced voltage ( Vdd / κ ), vertical ( tOX κ and Xj

κ ) and horizontal ( L κ ) dimensions, and

an increased doping concentration ( κ N a ) as depicted in figure 2.5. Despite the change

in those parameters, the intensity of the electric field ( v / L = v '/ L ' ) remains virtually
unchanged since both the dimension and the supply voltage scale by the same ratio.
Table 2.3 summarises the changes in device dimensions and circuit parameters
as a result of both the constant field and the generalised scaling rules. Only the most
important design and operational parameters are included in the table. The other
quantities which are not given in table 2.3 can be deduced using the listed design
parameters.

Scaled Parameters Constant field Scaling Generalised scaling

tO X , L , W , X j , W d 1 1
κ κ
3
N a , N d ( ions / cm ) κ ακ

Power supply: ( Vdd ) 1 α

κ κ

Electric field in device: ( E ) 1 α

Capacitance: ( C ) 1 1
κ κ

Inversion charge density (Q) 1 α

Circuit delay time: τ CV

I
1
κ
1
κ

Power dissipation: ( P ) 1 α2
κ 2
κ2
Power density (~ P A ) 1 α2

Circuit density κ2 κ2

Chip Area (A) 1 1

κ2 κ2

Current, Drift: (I) 1 1

κ κ

Table 2:3 Summary of the constant field scaling and the generalised scaling rules

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

The other issue addressed in [2.15] was the application of ion implantation in the
fabrication process of the scaled device. This is an important process step which allows
us to more accurately place the dopants in the shallower source drain junctions and
channel of the scaled device. In addition to its advantages, the shortcomings of the
scaling process have also been addressed in [2.15] For example, carrier mobility
degradation as a result of high doping in the channel and the short channel effect
(decreasing of VT) are some of the main drawbacks. The adverse effect of doping
concentration on carrier mobility can be observed from the empirical formula given by
equations (2.4 & 2.5) [2.16].

7.4 × 108 Tr−2.23

µe = 88Tn−0.57 + (2.4)
N  −0.146
1+  d 17 2.4  0.88Tn
 1.26 × 10 T n 

1.36 × 108 Tr−2.23

µ p = 54.3T −0.57
p + (2.5)
N  −0.146
1+  a 17 2.4  0.88Tp
 2.35 × 10 T p 

Where, Tn and Tp are the electron and hole temperatures of interest respectively
and Tr is the room temperature. µn and µ p are the electron and hole mobility

respectively. N a and N d are acceptor and donor concentration. Since carrier mobility is
inversely proportional to the channel doping as shown in the equations, increasing
channel doping reduces the mobility and the device performance. Regardless of
implementation of different channel engineering techniques, the highly doped channel
imposes carrier transport problems in aggressively scaled MOSFETs.

2.2.2 Generalised scaling rule

As device dimensions enter into the sub-micron dimensions, two-dimensional

effects (short channel effect-SC and drain induced barrier lowering-DIBL) become
increasingly important. The gradual field approximation becomes invalid and the field
changes significantly even if the constant field scaling scenario is applied. The field also
increases due to a much slower reduction in the supply voltage in real circuits compared
to the requirements of constant field scaling. This challenge to constant field scaling has

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

been addressed by Brews et al. [2:11], and Baccarani et al. [2:10], who have introduced
a more generalised scaling theory.
Brews et al. mainly concentrated on the minimum channel length for which the
subthreshold characteristics of the long channel device can be maintained in the scaled
devices. For this purpose they suggested an empirical formula given by:

1
Lmin = A  x j tox (Ws + Wd ) 2  3 (2:6)

Where Lmin is the minimum channel length, Ws and Wd are the depletion widths in the
source and drain regions respectively, xj is the junction depth, A and tox are
proportionality constant and oxide thickness respectively.
The main advantage of this approach over the constant field scaling, according
to [2.11], is that the parameters do not all have to be scaled by one factor. But there is a
drawback associated with the way in which the minimum channel length is determined.
It was suggested that the channel length could be reduced until a 10% increase in drain
current is obtained.
However, the tolerance to the short channel effects may not only depend on a
predetermined drain current value, but also depend on circuit applications [2.17]. In
addition to this, the scaling of a MOSFET includes to at least five major design
parameters ( Lg , tox , Vdd , N a , x j ) [2.8] [2.18], not just the three defined in equation

(2.3). The typical electrical behaviour of device under the influence of short channel
effect (SCE) and drain induced barrier lowering (DIBL) are highly dependant on all five
parameters as shown in equation (2.7 and 2.8)§ [2.19] [2.16].

ε si  x j  tox Wdm
2

SCE = 0.64 1 +  Vbi (2.7)

ε ox  L2el  Lel Lel

ε  xj  tox Wdm
2

DIBL = 0.80 si  1 + 2  Vds (2.8)

ε ox  Lel  Lel Lel

§
For further reference on the derivations of equations 2.7 and 2 .8, please look in [2.18]

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2

Vbi and Vds are the built in potential and the in put drain Voltage. The effective channel
length is defined as Lel = Lg − ∆L , where Lg is the physical gate length and ∆L is the

sub-diffusion length. It is also clear that from the empirical formulas of CMOS design
rules, which require x j L ≈ 0.33 , tox
L ≈ 1
30
Wd
L ≈ 0.33 , VT
Vdd ≈ 0.20 , that all the five

parameters influence the electrostatic integrity of the scaled devices, which determines
both SCE and DIBL.
On the other hand, by identifying a significant difference in the two dimensional
pattern of the electric field in the active region of the original and the scaled device,
Baccarani et al. have suggested that the supply voltage and the doping concentration
should be scaled with different scaling factor. To facilitate this a new scaling concept an
additional scaling constant, α, has been suggested. The effect of α can be demonstrated
by examining the Poisson equation within the depletion region, which is explained in
[2:8] and given by the equation:

∂ 2 (αψ / κ ) ∂ 2 (αψ / κ ) qN a'

+ = (2.8)
∂ ( x / κ )2 ∂( y / κ )2 ε si

Where N a' = ακ N a , is the channel doping concentration in the scaled device.

Equation (2.8) is based on the assumption that the potential will be scaled by α / κ and
the electric field by just α (where α ≥1). It is, however, important to note that in [2.17]
the scaled potential is given as ψ ' = ψ / κ which is different than the one shown in
equation (2.3). Moreover scaling the potential by the same factor as the dimensions
leads to the constant field scaling theory. The main reason for adopting in this work the
generalised scaling with α determined by equation (2.3) is the fact that the supply
voltage can not be scaled as fast as the device dimensions due to the non-scaling
property of the threshold voltage and the subthreshold slope [2.10].
The main problem with the generalized scaling rule, particularly in deep sub-100
nm scaled devices is an increase on power density ( P / A ⇒ α2). The scaling of total
area scales as 1/κ2 while the power dissipation per circuit scales as α 2 / κ 2 , i.e., the size
of the area scales down faster than the power dissipation. This difficulty is considered to
be one of the major scaling limitation factors [2.20]. The scaling limits are discussed in
detail in later sections of this chapter.

21