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FSM

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36 views11 pages

FSM

Uploaded by

quangthanhlop10a9
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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FSM

INTRODUCTION

• An FSM (finite state machine) is used to model a system that transits among a finite number of internal states.
The transitions depend on the current state and external input. Unlike a regular sequential circuit, the state
transitions of an FSM do not exhibit a simple, repetitive pattern. Its next-state logic is usually constructed
from scratch and is sometimes known as "random" logic. This is different from the next-state logic of a
regular sequential circuit, which is composed mostly of "structured components, such as incrementors and
shifters.
• In practice, the main application of an FSM is to act as the controller of a large digital system, which
examines the external commands and status and activates proper control signals to control operation of a data
path, which is usually composed of regular sequential components.
B l o c k diagram of a synchronous FSM.

• It consists of a state register, next-state logic, and output logic.


• An FSM is known as a Moore machine if the output is only a function of state, and is known as a
Mealy machine if the output is a function of state and external input.
• Both types of output may exist in a complex FSM, and we simply refer to it as containing a Moore
output and a Mealy output. The Moore and Mealy outputs are similar but not identical.
How to improve the Performance of the FSMs
• 1. Do not use single ‘always’ block to code the FSMs as it does not yield into the efficient results.
• 2. To achieve the efficient synthesis for the FPGA/ASIC, use the multiple ‘always’ block. In practice, we can
think of using a. First always block for the next state logic b. Second always block for the state register c.
Third always block for the output logic.
• 3. Use the blocking assignments inside the next state and output logic block as they are combinational in
nature.
• 4. Use non-blocking assignments inside the state register block as this block is triggered on the active clock
edge may be positive or negative.
• 5. Use the desired encoding method a. Binary encoding needs n flip-flops for the 2n states b. Gray encoding
needs n flip-flops for the 2n states c. One-hot encoding needs 2n flip-flops for the 2n states
• 6. To avoid the latch inference, use the default condition or cover all the case conditions in the case
construct.
• 7. Depending on the number of transitions in the state machine use the if-else construct.
• 8. If area is not a bottleneck in the design for the clean timing uses one-hot encoding FSMs
• 9. For glitch-free output, use the registered output concept to register all the outputs for the clean timing
FSM representation

• An FSM is usually specified by an abstract state diagram or ASMchart both capturing the FSM's input,
output, states, and transitions in a graphical representation.
• The two representations provide the same information. The FSM representation is more compact and better
for simple applications. The ASM chart representation is somewhat like a flowchart and is more descriptive
for applications with complex transition conditions and actions.
State diagram

• A state diagram is composed of nodes, which represent


states and are drawn as circles, and annotated transitional
arcs. A single node and its transition arcs are shown in
Figure. A logic expression expressed in terms of input
signals is associated with each transition arc and
represents a specific condition. The arc is taken when the
corresponding expression is evaluated true.
• The Moore output values are placed inside the circle since
they depend only on the current state.
• The Mealy output values are associated with the
conditions of transition arcs since they depend on the
current state and external input. To reduce clutter in the
diagram, only asserted output values are listed.
Algorithmic state machine chart (ASM chart)

• Consisting of one state box and an optional network of


decision boxes and conditional output boxes.
• A state box represents a state in an FSM, and the asserted
Moore output values are listed inside the box. Note that it has
only one exit path. A decision box tests the input condition
and determines which exit path to take. It has two exit paths,
labeled T and F, which correspond to the true and false
values of the condition. A conditional output box lists asserted
Mealy output values and is usually placed after a decision
box. It indicates that the listed output signal can be activated
only when the corresponding condition in the
decision box is met.
Moore machine
Example

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