Advanced Computer Architecture

CS-522

MS – Computer Science

Credit Hours : 3-0

Dr. Shahid Latif (Associate Professor)

Department of Computer Science & IT

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Sarhad University of Science and Information Technology, Peshawar
Course Details
Course title/code: Adv. Computer Architecture/CS-522

Lecture: 03

Topic: System Buses/Interconnections

Program: MS – Computer Science (Sem: 1st, 2nd, 3rd & 4th)

Department of Computer Science & IT

Sarhad University of Science and Information Technology, Peshawar 2
Lecture Outlines
• Computer Components • Interconnection Structure
• Program concept • Memory connection
• What is a program? • I/O connection
• Computer Components: Top- • CPU connection
level view • Types of Transfer
• Computer Basic Function • Bus Interconnection
• What is bus?
• Instruction cycle • System bus
• Fetch and Execute cycle • Single bus problems
• Example of Program Execution
• Instruction cycle state diagram
• Elements of Bus Design
• Interrupts • Bust Types
• Interrupt cycle • Method of arbitration
• Multiple interrupts • Timing
• Sequential (1st Approach) • Bus width
• Nested (2nd Approach) • Data Transfer Type
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Computer Components

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Program Concept
• Hardwired programs
– Programs in the form of hardware by small set of components to
store data and perform A/L operations on data
– are inflexible (hard/rigid)
Program Concept cont.…
• As alternative
– General purpose hardware (for A/L functions) can do different tasks
– Depending on correct control signals applied to hardware
• Instead of re-wiring for (each new program)
– Supply a new set of control signals
What is a program?
• A sequence of steps
• At each step, some arithmetic or logical operation is performed

– For each operation, a different set of control signals is needed

– i.e. unique code for each control signals
– e.g. ADD → addition, MOVE → data movement, Jump etc.

• A hardware segment (Instruction interpreter) accepts the code

and issues the control signals

• This method of programming, a sequence of codes or

instructions is called software
Components
• The Control Unit (CU) and the Arithmetic and Logic Unit
(ALU) constitute/compose the Central Processing Unit (CPU)
– i.e. CU+ALU=CPU (von Neumann Machine/Chapter-2)

• Data and instructions need to get

– into the system and (Input module)
– results need to get out (Output module)
• Together referred as I/O components

• Temporary storage of code and results is needed

– Main memory
Computer Components: Top Level View
Computer Basic Function
• Basic function performed by a computer is execution of a
program
– Consists of a set of instructions stored in memory
• Instruction processing consists of two step:
– Fetch (read instructions from memory one at a time)
– Execute (perform that instruction)
• Instruction cycle: The processing required for a single
instruction
Fetch Cycle
• Instruction cycle begins with fetch cycle
– Program Counter (PC) holds address of next instruction to be fetched

– Processor fetches instruction from memory location pointed to by PC

– Increment PC (to fetch the next instruction in sequence)

• Unless told otherwise

Execute Cycle
– Instruction loaded into Instruction Register (IR)

– Processor interprets instruction and performs required actions

Execute Cycle
• Actions perform by processor during execution cycle

– Processor-memory
• Data may be transfer between Processor and main memory
– Processor -I/O
• Data may be transfer between Processor and I/O module (unit)
– Data processing
• Perform arithmetic or logical operation on data
– Control
• Alteration of sequence of operations e.g. jump
– Combination of above actions
 Example of Program Execution
(Add 3(940) & 2(941) and replace result at 941
Instruction Cycle State Diagram
(For example: ADD AX, BX)
Exercise
• Consider a CPU with
– An instruction set consisting of 16 instructions
– The instruction memory can store 64 instructions
– Data memory has a capacity of 256 words
– Each instruction is 32 bits long
– Each memory word is also 32 bits long
• The CPU fetches and executes instructions in the following
steps:
– Fetch instruction,
– Decode instruction,
– Fetch data operands,
– Execute instruction
– Write the result back
Exercise
• Given the scenario above, answer the following questions:

1. How many bits are needed for the address of the instruction
memory?
2. How many bits are needed for the address of the data memory?
3. If the program counter (PC) is 8 bits wide, what is the
maximum number of instructions that the CPU can address?
4. If the CPU needs 3 clock cycles to fetch an instruction, 2 clock
cycles to decode it, 1 clock cycle to fetch operands, and 4 clock
cycles to execute it, calculate the total time required to execute
a single instruction.
5. If a program has 100 instructions and there are no pipeline
hazards or stalls, how many clock cycles are needed to execute
the entire program?
Exercise - Solution
• Address bits for instruction memory:
– As instruction memory can store 64 instructions
– To address 64 instructions, the CPU needs 6 bits (i.e. 26 = 64)

• Address bits for data memory:

– As data memory has a capacity of 256 words
– To address 256 words, the CPU needs 8 bits (i.e. 28 = 256) bits

• Maximum number of instructions addressable:

– If PC is 8 bits wide, the maximum number of instructions that the CPU
can address is 28 = 256 instructions
Exercise - Solution
• Total time to execute a single instruction:
– Fetch: 3 clock cycles
– Decode: 2 clock cycles
– Operand fetch: 1 clock cycle
– Execute: 4 clock cycles
• Total time to execute a single instruction = 3 + 2 + 1 + 4 = 10 clock
cycles

• Total clock cycles to execute the 100-instruction program:

– Assuming no pipeline and each instruction takes 10 clock cycles to
execute
• Total clock cycles = 100 instructions × 10 clock cycles/instruction =
1000 clock cycles
Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt
normal sequence of processing
• Most common classes of interrupts:
– Program = occurs as a result of an instruction execution
• e.g. overflow, division by zero, illegal machine instruction
– Timer
• Interrupt generated by internal processor timer
• Used in pre-emptive multi-tasking/OS
– I/O
• Generated from I/O controller
• to signal normal completion of an operation or
• to signal a variety of error conditions
– Hardware failure
• e.g. power failure, memory parity error
Program Flow Control
(with and without interrupts)
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
– Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
– Suspend execution of current program
– Save context (background information)
– Set PC to start address of interrupt handler routine
– Process interrupt
– Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing Short I/O Wait
Program Timing Long I/O Wait
Instruction Cycle -State Diagram
(Instruction cycle with Interrupts)
Multiple Interrupts(communication line & printing)
• Disable interrupts (1st approach)
– Processor will ignore further interrupts while processing one interrupt
– Interrupts remain pending and are checked after first interrupt has been
processed
– Interrupts handled in sequence as they occur

• Define priorities (2nd approach)

– Low priority interrupts can be interrupted by higher priority interrupts
– When higher priority interrupt has been processed, processor returns to
previous interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
Interconnection Structure

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Connecting (Interconnection structures)
• As we know, computer is a network of basic modules
– all the units (modules) must be connected
– The collection of paths connecting the various modules is called the
interconnection structures

• Different type of connection for different type of unit

– Memory
– Input/output
– CPU or Processor
Computer Modules
(types of exchanges)
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
– Read
– Write
– Timing
Input/Output Connection(1)
Similar to memory from computer’s point of view
• Output → Receive data from computer, send data to peripheral

• Input → Receive data from peripheral, send data to computer

• Control → Receive control signals from computer, send control

signals to peripherals
– e.g. spin disk
Input/Output Connection(2)
• Interrupt → Send interrupt signals

• Address → Receive addresses from computer

– I/O modules may control more than one external device
– Thus, interfaces to an external device is referred as a port with a unique
address (e.g., 0, 1, . . . , M–1)
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
Types of Transfer
• The interconnection structure must support the following
types of transfers:
– Memory to processor: processor reads instructions/data from memory

– Processor to memory: processor writes instructions/data to memory

– I/O to processor: processor reads data from I/O devices

– Processor to I/O: processor sends data to I/O devices

– I/O to/from memory: I/O module exchanges data directly with

memory, without going through the processor
• Using direct memory access (DMA)
Bus Interconnection
What is a Bus?
• A communication pathway connecting two or more devices
– It is a shared transmission medium
– Usually broadcast
• Signal transmitted by one device is available to all other devices attached
with bus
– Only one device can transmit at a time
• Otherwise signals will overlap and become garbled (distorted)
– Often grouped
• A number of channels/paths/lines in one bus
• e.g. 32 bit data bus is 32 separate single bit channels
System Bus
• Computer systems contain a number of different buses
– providing pathways between components
– A bus that connects major computer components (processor, memory,
I/O) is called a system bus
– Typically, a system bus consists of 50 to 100s of separate lines
– Each line is assigned a particular meaning or function
– the lines can be classified into three functional groups
• Data lines
• Address lines
• control lines
• there may be power distribution lines that supply power to the
attached modules
Bus Interconnection Scheme
Data Bus
• Carries data among system modules
– Assume, there is no difference between “data” and “instruction” at this level

– Width of data bus (i.e. number of lines)

– It determines how many bits can be transferred at a time
– Bus width is a key factor to determine the overall system performance,
• e.g.
• If 8-bits data bus and 16-bits instructions
• Then processor will access the memory twice during each instruction cycle
Address bus
• Identify the source or destination of data on data bus
– e.g. CPU needs to read an instruction (data) from a given location in
memory
– Bus width determines maximum memory capacity of system
– e.g.
– 8080 has 16 bit address bus giving 64k address space
– 8086 has 20 bit address bus giving 1M address space

Remember, address bus is also used to address I/O ports

Control Bus
• As data and address bus are shared by all components so
– Control bus is used to control the access and use of these buses

• Control signals transmit commands and timing (validity of

data/address) information among modules

– Memory read/write signals (MEMR, MEMW)

– I/O read/write signals (IOR, IOW)
– Interrupt request/acknowledge (INTR, INTA)
– Bus request/grant (BR/GT)
– Clock signals (CLK) and Reset
– Etc.
Physical understanding of Bus Architecture

Modern systems tends to have

all major components on single board or even on
single chip (like processor)
Single Bus Problems
• Lots of devices on one bus leads to:
– Greater the bus length, hence, greater Propagation delays
• Long data paths mean that co-ordination of bus (i.e. control of bus from to
another device) can adversely affect performance
– Bus may become a bottle neck
• as aggregate data (collect) transfer demand approaches bus capacity
• Solution may be use of wider busses
• But due to rapidly growing data rate generated by attached devices
• Use of single bus destined to lose

• Most systems use multiple buses to overcome these problems

Traditional bus architecture

Network = LAN, WAN etc.

SCSI = type of bus used to support disk
drives and other peripherals
(Small Computer System Interface)
Serial = serial port = printer & scanner etc.
High Performance Bus
(mezzanine architecture)

P1934 = Fire wire

(Interface controller
To peripheral buses)
Elements of Bus Design
Elements of Bus Design
• Bust Types
– Dedicated
– multiplexed
• Method of arbitration
– Centralized
– Distributed
• Timing
– Synchronous
– Asynchronous
• Bus width
• Data Transfer Type
Bus Types
• Dedicated
– Permanently assigned to one function/physical subset of computer
components
– Separate data & address lines
– High throughput, but increased size and cost of the system

• Multiplexed (time multiplexing)

– Shared lines,
– Address valid or data valid control line
– Advantage: Fewer lines (that saves cost and space)
– Disadvantages
• More complex control
• reduced performance (as events sharing same lines can not take place in parallel)
Bus Arbitration (settlement)
• If more than one module need control of bus
– e.g. CPU and DMA controller
– As only one module may control bus at one time
– So some methods of Arbitration is needed

• Arbitration methods can be classified in:

– Centralised
– Distributed
Centralised or Distributed Arbitration
• Centralised
– Single hardware device controlling bus access
• Bus Controller/Arbiter
• Responsible for allocating time on bus
– May be part of CPU or separate module

• Distributed
– No central controller
– Modules have Access Control logic
– Each module may claim the shared bus
Timing
• The way of Co-ordination of events on a bus
– Types: Synchronous timing & asynchronous timing

• Synchronous Timing
– Occurrence of events determined by clock signals
– Bus includes clock line at which clock transmits signal (regular sequence
of 1’s and 0’s)
– single 1,0 transmission = clock cycle or bus cycle = time slot
– All devices can read clock line
– Usually a single cycle for an event

• Asynchronous Timing
– occurrence of one event on a bus follows and depends on the occurrence of
a previous event
Synchronous Timing Diagram
Asynchronous Timing – Read Diagram
Asynchronous Timing – Write Diagram
Adv/disadvantages
• Synchronous timing
– Simpler to implement and test
– Less flexible b/c devices are tied to a fixed clock rate

• Asynchronous timing
– Mixture of slow and faster devices can share a bus
Please, read and understand the remaining two
requirements/elements of bus design

Bus width
Data Transfer Type
Quiz-01
A short quiz is scheduled for the class of the upcoming week

The quiz comprises:

2-3 Questions
Duration: 20-30 mints
Worth: 10 Marks
Wrapping Lectures- 1-3
 Thank you

Dr. Shahid Latif (Associate Professor)

Department of Computer Science & IT

Sarhad University of Science and Information Technology, Peshawar

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