Xilinx Platform Studio tutorial

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[email protected]
March 17, 2011

This tutorial intends to show you how to create a simple and very basic sys-
tem. Starting with Xilinx Platform Studio (XPS) version 6.1 this has been
significantly simplified due to the Base System Builder wizard (the current XPS
version is 12.2).

note To save disk space you can remove temporary files from the project by
Project→Clean All Generated Files.

note A tutorial movie showing you how to use the BSB wizard is available at
http://fileadmin.cs.lth.se/cs/Education/EDA385/HT10/videos/create1PsystemISE12.avi

1 Creating a system architecture from scratch

This tutorial will guide you through the creation of a new design using Xilinx
Platform Studio (XPS). XPS is a GUI that helps you to specify your system,
i.e.
• which processors, memory blocks and other soft IPs (peripherals) to use

• how the different IPs are interconnected

• the memory map, i.e. for addresses for memory mapped IO/peripherals
XPS also interfaces the tools used throughout the whole design flow. In this
tutorial you will create a system consisting of three components, a MicroBlaze
processor, a UART (serial port), and a memory block. The system functionality
is just to write a message to the UART.

1.1 Start Xilinx Platform Studio(XPS)

You can find the program in Windows start menu. start→ all programs→
Xilinx ISE Design Suite 12.2→ EDK → Xilinx Platform Studio

1.2 Create a new design

When you start XPS there will be a dialog from which you can start the Base
System Builder wizard. The dialog can also be launched from File→New
Project. . .

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 • In the first wizard dialog, specify the project location and name1 . XPS will
create a lot of files in the project directory, so create a new empty directory.
You will also need some configuration files for the Digilent FPGA-board.
The files can be downloaded from the course web page (under assignments
klick on Support files for the Digilent board ). Unpack the zip file. In the
XPS dialog check the Set Project Peripheral Repositories box and write in
the path to the directory called lib from the unpacked zip-file. Click OK.
• In the new dialog select “I would like to create a new design”, Click Next.

• In the new dialog set the target board as follows:

Board Vendor Digilent
Board Name Nexys 2-1200 Board
Board Revision C
Click Next.
• Choose the single processor system, then click Next.
• Keep the 50MHz system clock. During the labs it is recommended to in-
crease the size of the local memory to at least 16 KB. Note that MicroBlaze
is the only available processor option. To continue click Next.
• At this step you may choose which board components (LEDs, buttons,
switches etc.) you want to create interfaces for. Keep whichever LEDs
and buttons, add an xps timer if you wish and then click next.
• Do not check the caches in this step, just click next.

• Now you must select the location of your software and the mapping of
STDIN/OUT. Keep the RS232 (UART) for your STDIN and STDOUT
(for the C I/O functions, i.e. printf() and scanf()). Make sure all the
applications have their data and instructions mapped into local on-chip
memories (accessed through ilmb ctrl and dlmb ctrl respectively).

• Now you are done, click next in the remaining dialogs, and Finish. After
this you will want to “Start using Platform Studio”.
You have created your initial system. All you need to do now is compile and
run logic synthesis, as will be explained later. Now is a good time to ex-
plore XPS a bit. Lets start by looking into the hardware architecture gen-
erated for you. It can be visualized by selecting Project→ Generate and
View Block Diagram. A block diagram will appear in the frame to the
rightDo not worry if you do not get all the abbreviations. Here is a partial list:
LMB Local Memory Bus CPU ↔ memory bus (point to point bus)
PLB Processor Local Bus CPU ↔ peripheral bus (shared bus)
GPIO General Purpose IO glue logic for the buttons/leds on the board
RS232 serial port used for text input/output of your application
An extended view which also contains more information about the components
is created by selecting Project→Generate and View Design Report.
1 The path cannot contain spaces. We recommend you use the local C:/Temp/yourdir for

all your projects.

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 There are three main frames in the XPS window. Let’s start with the left
frame. It contains three tabs Project, Applications, and IP Catalog. In the
Project tab you find general system files as well as log files, in the Application
tab you find the software parts of your system, and finally in the IP Catalog you
find a tree containing all the IP components you can use to build your system.
Select the Application tab. There are two projects, one for memory test and
one for peripheral test. The projects which are not active (downloaded) have
a red cross in their icon. Right click on a project and select Mark to Initialize
BRAMs to activate it. By right clicking you can also compile (build) individual
software projects. There can only be one main function for every processor, so
do not activate several projects that contain a main function.
The frame to the right in the XPS window is used for viewing and editing
documents. This is where you opened the block diagram earlier. Select the
System Assembly tab (the tabs are in the bottom of the frame). This view
contains a list/tree of your system components and their connections. There
are three busses. The two blue are LMBs connecting the processor and the
memory controller, one is used for instruction fetch (ilmb) and the other is
used for data read/write (dlmb). The red lines are not buses, but illustrate the
connection between the memory controller and the memory block(s). Finally the
gold line is a PLB connecting the processor and the peripherals. All peripherals
are memory mapped, thus they can be addressed through read/write to memory
addresses (see the Addresses tab). To connect/disconnect a component to/from
a bus click on the circles. Double click on a component to get a dialog in which
you can change its parameters.

2 Building your system

XPS keeps track of all dependencies in your system and will automatically
rebuild the parts which are affected if you change a parameter or edit a file. Note
that this next step may take a long time (10 minutes) depending on whether
or not the hardware part of the system is already synthesized or not. You may
select Device Configuration→Update Bitstream and the tool will build
the whole system (both synthesize the hardware and compile the software, see
Figure 1.) and prepare the configuration file for the FPGA. To download and
run this onto the FPGA you must use another application, specific for the
Digilent boards. All these step are explained below.
First, let’s have a look at the software part. In a system, the user pro-
grams access the hardware resources via libraries. XPS automatically con-
figures and generates the library code for your system. To do this, select (
Software→Generate Libraries and BSPs). This step also generates header
files containing symbolic names for memory mapped peripherals. Run this step
and look at your software projects (the Applications tab in the left frame).
Click on the + left of processor:microblaze 0 in your active project. There
you will find a header file (xparameters.h) with symbolic names of all mem-
ory mapped peripherals. Use the symbolic names in your C code, so you can
change the memory layout later without changing the C code. Header files are
also generated (if necessary) under Headers (the same level in the tree as proces-
sor:microblaze 0 ). Here you will find functions specific to your peripherals, for
example functions to read/write from/to GPIO. Note, the standard C function

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 Hardware
Software
Flow
Flow

Generate Generate
Bitstream Libraries

Build User
Application

Device
Configuration

Update
Bitstream

Download Configuration

Figure 1: System Design Flow

printf requires huge libraries, which will not fit in the small on-chip memory.
Instead use print, or xil printf functions to output text. xil printf is sim-
ilar to printf, but much smaller and lacks some of the formatting, i.e. floating
point support. If you want to discover more about the software settings, have
a look at Software→Software Platform Settings. . . . Now compile your
programs by selecting Software→Build All User Applications.
Let’s move on to the hardware. Hardware synthesis is done in several steps
(create the logic circuit (netlist), create the FPGA configuration (bitmap)), but
you do not need to worry about this just yet. Simply select Hardware→
Generate Bitstream and everything will be generated automatically for you.
This might take a long time, in the range of 10 minutes or even more, depending
on whether your hardware was already synthesized or not. Fortunately the
hardware is independent of the software, so whenever you change your C files,
this step will not rerun. During the hardware synthesis, the tools use a User
Constraint File (UCF), which can be found in the left frame in the Project tab.
This file binds external ports in your design to physical pins on the FPGA. It
is important that the names in the design are the same as in this file, so do
not rename the external ports. Also if you add or remove external pins this file
must be edited, i.e. removing a GPIO peripheral.
The last step before dowloading the configuration to the FPGA is to merge
software binaries and the bit stream from the hardware synthesis, run Device
Configuration→ Update Bitstream. This places the executable in the on-
chip memory, making the configuration file ready to be downloaded on the
FPGA.

2.1 Run the final implementation on the FPGA

When you run your system it is nice to see some output, i.e. the result of
print(). The text is forwarded to the serial port (STDOUT being set to
the RS232 device) and to monitor this we can use the windows hypertermi-

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nal start→ all programs→ accessories→ communications→ hyperter-
minal. Give the new connection a new name and chose com1 in the Connect
using frame. Use port settings according to the uart parameters:
Bits per second 9600
Data bits 8
Parity None
Stop bits 1
Flow control None
This must be the same as the configuration of the RS232 peripheral. Feel free
to change the speed of the UART, but beware, if you change the peripheral
parameters you must run hardware synthesis again.
Now you are about to run the system and you need a FPGA board, connect
it (both the USB and the RS232 cables) and switch the power on. The Digilent
boards can be configured with the system you just synthesized using a specific
program, found in start→ all programs→ Xilinx ISE Design Suite 12.2→
Adept (Digilent)→ Adept. At this point you should have a new window
called Digilent Adept. You should be able to see two devices - one being the
FPGA, xc3s1200e, and one being the ROM device for the boot configuration
xcf04s. (If this does not happen, check your USB connection again). We will
only configure the FPGA directly, so click Browse button for the FPGA and
select the download.bit configuration file from your project directory home,
under implementation/. Finally, click the Program button to download the
configuration to the FPGA.
The system should start to run directly. Depending on the application you
selected for BRAM Initialization, you may see some LEDs blinking and text
messages in the hyperterminal (this assumes you are running the peripheral test
application). Press the button labelled BTN0 on the FPGA board to restart
the program (will give a new printout).
XPS keeps track of most dependencies among the source files, so if you
change anything, selecting a download to the FPGA will rebuild all parts that
are affected. You can force XPS to rerun a step by choosing Software→Clean
Software and Hardware→ Clean Hardware. This removes all generated
files, thus it also saves disk space.

3 That was easy, what’s next?

You should have by now created and run your first system. Use the remaining
time in the first lab to explore the XPS program. The following labs will contain
much more work and you will not be able to finish unless you have prepared
ahead, i.e. created the system. In the next lab you will need a system consisting
of a MicroBlaze, a RS232 (xps uartlite) and a timer (xps timer). If you have
time you can start to create this system. Read the documentation of the timer.
To find the documentation, right click on it in the IP Catalog tab in the left
XPS frame.

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4 Power and energy consumption
Once you have your system hardware and software, you can estimate its power
and energy consumption. In embedded systems (and not only) power and energy
are very important since they determine the cooling, power supply and battery
lifetime. To get a rough estimate of your system’s power you can use the XPower
Analyzer tool that comes with Xilinx ISE, found in start→ all programs→
Xilinx ISE Design Suite 12.2→ ISE Design Tools→ Tools→ XPower
Analyzer. Once XPower starts, choose File→ Open Design to specify the
design you want to examine. In the dialog that appears, the design file is
necessary, and it is the system.ncd file located in the your project directory, in
implementation subdirectory. This file is the result of hardware synthesis, so it
will only be present if you went through the synthesis step already. You should
at least specify the Physical Constraints File, system.pcf, present in the same
directory2 . Choose OK to start the analysis, and pay attention to the output
comments. Also inspect the tables produced in the main window, since these
gather the power figures for your design.
Once you have the total power for the design, you may multiply this with
the time it takes to execute any of your applications (you will need to use a
timer core and instrument the program to record the number of clock cycles
used - this is detailed later) in order to obtain the energy consumption for that
program.
A tutorial movie showing you how to use the XPower Analyzer is accessible at
http://fileadmin.cs.lth.se/cs/Education/EDA385/HT10/videos/startingXPowerISE12.avi.

5 Dual-processor systems
Let’s continue by creating a dual processor system, that will be needed in lab
3. You may either extend the uni-processor system you are currently using,
or extend a dual-processor system created with the wizard you used before.
The first solution focuses on using FIFOs to communicate between processors,
while the second uses shared memory/mutexes or mailboxes to the same end.
These mechanisms do not exclude each other and can be used at the same time,
granted your system contains the hardware support. Finally by the end of this
section you should be able to have three different ways of sending data between
two processors:
1. FIFOs (Fast Simplex Link)
2. mutex/shared memory (xps mutex and Micron RAM)

3. mailbox (on PLB)

5.1 Starting from a single processor system

Start by creating a system containing only one MicroBlaze and a RS232 (xps uartlite)
using the BSB wizard (or continue working with the system you just created).
To add a second processor you need to manually duplicate all components and
parameters in the processor/memory subsystem. Look at the block diagram to
2 To make the analysis more accurate, more of the optional files may be specified.

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see how the memory and CPU are connected (CPU↔ LMB↔ LMB controller↔
memory block). Notice that MicroBlaze uses a Harvard architecture, where data
and instructions have separate pathways. On the other hand, the memory blocks
are dual ported, meaning that you can connect both the instruction and data
bus to the same memory block. To add IP components to your design, select
the IP from the IP Catalog tab in the left XPS frame, and double-click on it.
The newly added IP should appear in the System Assembly tab, where you can
also rename the instance. Now add the following:

• one Processor→microblaze,
• one Memory Block→bram block,
• two Memory Controllers→lmb bram if ctrl,
• two Buses→lmb v10,

• two Fast Simplex Link Buses→fsl v20).

Connect the components you’ve just added. The processor should also be
connected to the common PLB bus. This is done in the System Assembly tab.
Make sure that the Bus Interface tab is selected. All busses are shown to the left
(vertical lines). Simply click on a circle/box to connect a component instance
to a bus. You can only connect ports on an instance, so click on the + to see
the component ports first.
Fast Simplex Link (FSL) is a uni-directional point to point connection which
will be used to communicate directly between the processors. To use them,
you must add FSL ports to the processors. To do this, double click on the
processor, select the Bus Interface tab and change Number of FSL Links to one
(meaning one duplex interface, with a master port and a slave port). Connect
the processors to the FSL busses. A FSL is directed, so one processor should
write (master) and the other should read (slave) on the same FSL. To have
communication in both directions you need two FSLs. Your system should be
looking something like in Figure 2.
You also need to connect the clock and reset signals. Change the filter
from Bus Interface to Ports. First connect the reset signal of the newly added
processor to the mb reset signal. Connect all four buses you added to the clock
and reset nets (clk 50 000MHz and sys bus reset: click on No Connection and
select the appropriate signal). Note that names may differ in your tool version,
so the best hint is to examine how the rest of the buses are connected to signals
(e.g. ilmb). Your ports should be connected now as depicted in Figure 3.
Let’s move on to the memory layout of the newly added processor. Change
the filter from Ports to Addresses. The two new LMBs have unknown address
space. Set the memory size to 16K for both, which will result in Base Address
set to 0x00000000 and High Address set to 0x00003FFF. Using more than 16K
might make your system too large to fit on the FPGA.
Now, that the hardware system is set up properly, let’s continue with the
software. You must direct STDIN or STDOUT of the new processor to the
common serial port. Select Software→Software Platform Settings. Select
the new processor, under OS and Libraries assign STDIN and STDOUT to
RS232 PORT.

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 Figure 2: Dual MicroBlaze system view

Finally you also need a program to run on the second processor. In the left
frame, select the Applications tab. You should have two projects. Lets run one
on each processor. To select the target processor for a project open its tree
structure (click on the + to the left), right click on Processor:. . . and select the
target processor. Make sure both projects areMark to Initialize BRAMs (if not
right click on Project:. . . ).
Thats all you need to do. Run hardware synthesis, software compilation,
and configure (download to) the FPGA.

5.2 FSL communication

Once you have got both CPUs running (messages from both show up on the
terminal), it is time to do something useful. Let’s make them talk to each other,
through the FSL. Macros for reading and writing from/to the FSL are already
available in a header file that should be included in your sources mb interface.h,
file that can be found in under your_project\microblaze_0\include. The
commonly used macros are putfsl(data, port) and getfsl(data, port).
Both are blocking, data is the data to read/write. For the read/get operation it
must be a variable, which then will be updated to contain the value read, port
is the FSL port number, starting from 0. Example program (assuming there is
a FSL in both directions):

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Figure 3: Ports Connection

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 MicroBlaze 0: MicroBlaze 1:
#include <mb_interface.h>
#include <mb_interface.h>
#include <xutil.h>
#include <xutil.h>
int main(void){
int main(void){
int i;
int i = 0;
while(1){
while(i<10){
getfsl(i, 0);
putfsl(i, 0);
i++;
getfsl(i, 0);
xil_printf("ping %d\n\r", i);
xil_printf("pong %d\n\r", i);
putfsl(i, 0);
}
}
}
}

5.3 Using the Wizard to create a dual processor system

When you created your single processor system using the wizard in XPS, at
one point you were asked to choose between single processor or dual processor
systems. At the same step you may choose dual-processor system to create an
architecture that contains two processors, a few peripherals, including a mailbox,
a mutex and a Micron RAM cores. Once the wizard has completed, your system
will also contain test applications for each processor. The TestApp Peripheral
applications contain examples of using both the mailbox and the mutex. Have
a good look at these, if you intend to use mailboxes, or mutex/memory instead
of FSLs in lab 3.

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