A microcontroller is a small and low-cost microcomputer, which is designed to perform the

specific tasks of embedded systems like displaying microwave’s information, receiving remote
signals, etc.
The general microcontroller consists of the processor, the memory (RAM, ROM, EPROM),
Serial ports, peripherals (timers, counters), etc.

Difference between Microprocessor and Microcontroller

The following table highlights the differences between a microprocessor and a microcontroller
−

Microcontroller Microprocessor

Microcontrollers are used to execute a single Microprocessors are used for big
task within an application. applications.

Its designing and hardware cost is low. Its designing and hardware cost is high.

Easy to replace. Not so easy to replace.

It is built with CMOS technology, which Its power consumption is high because it
requires less power to operate. has to control the entire system.

It consists of CPU, RAM, ROM, I/O ports. It doesn’t consist of RAM, ROM, I/O ports. It
uses its pins to interface to peripheral
devices.

Types of Microcontrollers
Microcontrollers are divided into various categories based on memory, architecture, bits and
instruction sets. Following is the list of their types −
Bit
Based on bit configuration, the microcontroller is further divided into three categories.
 8-bit microcontroller − This type of microcontroller is used to execute arithmetic and
logical operations like addition, subtraction, multiplication division, etc. For example, Intel
8031 and 8051 are 8 bits microcontroller.
 16-bit microcontroller − This type of microcontroller is used to perform arithmetic and
logical operations where higher accuracy and performance is required. For example,
Intel 8096 is a 16-bit microcontroller.
 32-bit microcontroller − This type of microcontroller is generally used in automatically
controlled appliances like automatic operational machines, medical appliances, etc.
Memory
Based on the memory configuration, the microcontroller is further divided into two categories.
  External memory microcontroller − This type of microcontroller is designed in such a
way that they do not have a program memory on the chip. Hence, it is named as
external memory microcontroller. For example: Intel 8031 microcontroller.
 Embedded memory microcontroller − This type of microcontroller
ontroller is designed in such
a way that the microcontroller has all programs and data memory, counters and timers,
interrupts, I/O ports are embedded on the chip. For example: Intel 8051 microcontroller.
Instruction Set
Based on the instruction set config
configuration,
uration, the microcontroller is further divided into two
categories.
 CISC − CISC stands for complex instruction set computer. It allows the user to insert a
single instruction as an alternative to many simple instructions.
 RISC − RISC stands for Reduced In Instruction
struction Set Computers. It reduces the operational
time by shortening the clock cycle per instruction.

Applications of Microcontrollers
Microcontrollers are widely used in various different devices such as −
 Light sensing and controlling devices like LED.
 Temperature sensing and controlling devices like microwave oven, chimneys.
 Fire detection and safety devices like Fire alarm.
 Measuring devices like Volt Meter.

 8051 microcontroller is designed by Intel in 1981. It is an 8 8-bit

bit microcontroller. It is built
with 40 pins DIP (dual inline package), 4kb of ROM storage and 128 bytes of RAM
storage, 2 16-bit bit timers. It consists of are four parallel 8 8-bit
bit ports, which are
programmable as well as addressable as per the requirement. An on-chip on crystal
oscillator is integrated in the microcontroller having crystal frequency of 12 MHz.
 Let us now discuss the architecture of 8051 Microcontroller.
 In the following diagram, the ssystem
ystem bus connects all the support devices to the CPU.
The system bus consists of an 8 8-bit data bus, a 16-bit
bit address bus and bus control
signals. All other devices like program memory, ports, data memory, serial interface,
interrupt control, timers, and tthe
he CPU are all interfaced together through the system bus.


The pin diagram of 8051 microcontroller looks as follows −

 Pins 1 to 8 − These pins are known as Port 1.

This port doesn’t serve any other functions. It
is internally pulled up, bi-directional I/O port.
 Pin 9 − It is a RESET pin, which is used to
reset the microcontroller to its initial values.
 Pins 10 to 17 − These pins are known as Port
3. This port serves some functions like
interrupts, timer input, control signals, serial
communication signals RxD and TxD, etc.
 Pins 18 & 19 − These pins are used for
interfacing an external crystal to get the
system clock.
 Pin 20 − This pin provides the power supply to
the circuit.
 Pins 21 to 28 − These pins are known as Port
2. It serves as I/O port. Higher order address
bus signals are also multiplexed using this
port.
 Pin 29 − This is PSEN pin which stands for
Program Store Enable. It is used to read a
signal from the external program memory.
 Pin 30 − This is EA pin which stands for
External Access input. It is used to enable/disable the external memory interfacing.
 Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to demultiplex
the address-data signal of port.
 Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order
address and data bus signals are multiplexed using this port.
 Pin 40 − This pin is used to provide power supply to the circuit.
8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or
output. Hence, total 32 input/output pins allow the microcontroller to be connected with the
peripheral devices.
 Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as per
the logic state.
o Input/Output (I/O) pin − All the circuits within the microcontroller must be
connected to one of its pins except P0 port because it does not have pull-up
resistors built-in.
o Input pin − Logic 1 is applied to a bit of the P register. The output FE transistor is
turned off and the other pin remains connected to the power supply voltage over a
pull-up resistor of high resistance.
 Port 0 − The P0 (zero) port is characterized by two functions −
o When the external memory is used then the lower address byte (addresses A0A7)
is applied on it, else all bits of this port are configured as input/output.
 o When P0 port is configured as an output then other ports consisting of pins with
built-in pull-up resistor connected by its end to 5V power supply, the pins of this
port have this resistor left out.
Input Configuration
If any pin of this port is configured as an input, then it acts as if it “floats”, i.e. the input has
unlimited input resistance and in-determined potential.
Output Configuration
When the pin is configured as an output, then it acts as an “open drain”. By applying logic 0 to
a port bit, the appropriate pin will be connected to ground (0V), and applying logic 1, the
external output will keep on “floating”.
In order to apply logic 1 (5V) on this output pin, it is necessary to build an external pullup
resistor.
Port 1
P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this port can be
configured as general I/O only. It has a built-in pull-up resistor and is completely compatible
with TTL circuits.
Port 2
P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses
intended for the external memory chip. This port can be used for higher address byte with
addresses A8-A15. When no memory is added then this port can be used as a general
input/output port similar to Port 1.
Port 3
In this port, functions are similar to other ports except that the logic 1 must be applied to
appropriate bit of the P3 register.

Pins Current Limitations

 When pins are configured as an output (i.e. logic 0), then the single port pins can receive
a current of 10mA.
 When these pins are configured as inputs (i.e. logic 1), then built-in pull-up resistors
provide very weak current, but can activate up to 4 TTL inputs of LS series.
 If all 8 bits of a port are active, then the total current must be limited to 15mA (port P0:
26mA).
 If all ports (32 bits) are active, then the total maximum current must be limited to 71mA.
The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for
microprocessors to perform timing and counting functions using three 16-bit registers. Each
counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a counter, a
16-bit count is loaded in its register. On command, it begins to decrement the count until it
reaches 0, then it generates a pulse that can be used to interrupt the CPU.

Difference between 8253 and 8254

The following table differentiates the features of 8253 and 8254 −

8253 8254

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is available

Reads and writes of the same counter cannot Reads and writes of the same counter can
be interleaved. be interleaved.

Features of 8253 / 54
The most prominent features of 8253/54 are as follows −
 It has three independent 16-bit down counters.
 It can handle inputs from DC to 10 MHz.
 These three counters can be programmed for either binary or BCD count.
 It is compatible with almost all microprocessors.
 8254 has a powerful command called READ BACK command, which allows the user to
check the count value, the programmed mode, the current mode, and the current status
of the counter.

8254 Architecture
The architecture of 8254 looks as follows −
8254 Pin Description
Here is the pin diagram of 8254 −

In the above figure, there are three counters, a

data bus buffer, Read/Write control logic, and a
control register. Each counter has two input
signals - CLOCK & GATE, and one output signal
- OUT.
Data Bus Buffer
It is a tri-state, bi-directional, 8-bit buffer, which is
used to interface the 8253/54 to the system data
bus. It has three basic functions −

 Programming the modes of 8253/54.

 Loading the count registers.
 Reading the count values.

Read/Write Logic
It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O
mode, the RD and WR signals are connected to IOR and IOW, respectively. In the
memorymapped I/O mode, these are connected to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is
tied to a decoded address. The control word register and counters are selected according to
the signals on lines A0 & A1.

A1 A0 Result

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection
Control Word Register
This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command word,
which specifies the counter to be used, its mode, and either a read or write operation.
Following table shows the result for various control inputs.

A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2

1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation

Counters
Each counter consists of a single, 16 bit-down counter, which can be operated in either binary
or BCD. Its input and output is configured by the selection of modes stored in the control word
register. The programmer can read the contents of any of the three counters without disturbing
the actual count in process.

8253/54 can be operated in 6 different modes. In this chapter, we will discuss these
operational modes.

Mode 0 ─ Interrupt on Terminal Count

 It is used to generate an interrupt to the microprocessor after a certain interval.
 Initially the output is low after the mode is set. The output remains LOW after the count
value is loaded into the counter.
  The process of decrementing the counter continues till the terminal count is reached, i.e.,
the count become zero and the output goes HIGH and will remain high until it reloads a
new count.
 The GATE signal is high for normal counting. When GATE goes low, counting is
terminated and the current count is latched till the GATE goes high again.

Mode 1 – Programmable One Shot

 It can be used as a mono stable multi-vibrator.
 The gate input is used as a trigger input in this mode.
 The output remains high until the count is loaded and a trigger is applied.

Mode 2 – Rate Generator

 The output is normally high after initialization.
 Whenever the count becomes zero, another low pulse is generated at the output and the
counter will be reloaded.

Mode 3 – Square Wave Generator

 This mode is similar to Mode 2 except the output remains low for half of the timer period
and high for the other half of the period.

Mode 4 − Software Triggered Mode

 In this mode, the output will remain high until the timer has counted to zero, at which
point the output will pulse low and then go high again.
 The count is latched when the GATE signal goes LOW.
 On the terminal count, the output goes low for one clock cycle then goes HIGH. This low
pulse can be used as a strobe.

Mode 5 – Hardware Triggered Mode

 This mode generates a strobe in response to an externally generated signal.
 This mode is similar to mode 4 except that the counting is initiated by a signal at the gate
input, which means it is hardware triggered instead of software triggered.
 After it is initialized, the output goes high.
 When the terminal count is reached, the output goes low for one clock cycle.

The 8259 is known as the Programmable Interrupt Controller (PIC)

microprocessor. In 8085 and 8086 there are five hardware interrupts and two hardware
interrupts respectively. Bu adding 8259, we can increase the interrupt handling capability. This
chip combines the multi-interrupt input source to single interrupt output. This provides 8-
interrupts from IR0 to IR7. Let us see some features of this microprocessor.
 This chip is designed for 8085 and 8086.
  It can be programmed either in edge triggered, or in level triggered mode
 We can mask individual bits of Interrupt Request Register.
 By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines
 Clock cycle is not needed.

The pin level diagram and functional pin

diagram is like below -

The block diagram is like below -

 Block Description

Data Bus Buffer This block is used to communicate between 8259 and 8085/8086
by acting as buffer. It takes the control word from 8085/8086 and
send it to the 8259. It transfers the opcode of the selected
interrupts and address of ISR to the other connected
microprocessor. It can send maximum 8-bit at a time.

R/W Control Logic This block works when the value of pin CS is 0. This block is used
to flow the data depending upon the inputs of RD and WR. These
are active low pins for read and write.

Control Logic It controls the functionality of each block. It has pin called INTR.
This is connected to other microprocessors for taking the interrupt
request. The INT pin is used to give the output. If 8259 is enabled,
and also the interrupt flags of other microprocessors are high then
this causes the value of the output INT pin high, and in this way
this chip can responds requests made by other microprocessors.

Interrupt Request It stores all interrupt level that are requesting for interrupt service.
Register

Interrupt Service It stores interrupt level that are currently being execute.
Register

Interrupt Mask It stores interrupt level that will be masked, by storing the masking
Register bits of interrupt level.

Priority Resolver It checks all three registers, and set the priority of the interrupts.
Interrupt with the highest priority is set in the ISR register. It also
reset the interrupt level which is already been serviced in the IRR.

Cascade Buffer To increase number of interrupt pin, we can cascade more number
of pins, by using cascade buffer. When we are going to increase
the interrupt capability, CSA lines are used to control multiple
interrupts.

8279 programmable keyboard/display controller is designed by Intel that interfaces a keyboard

with the CPU. The keyboard first scans the keyboard and identifies if any key has been
pressed. It then sends their relative response of the pressed key to the CPU and vice-a-versa.
How Many Ways the Keyboard is Interfaced with the CPU?
The Keyboard can be interfaced either in the interrupt or the polled mode. In the Interrupt
mode, the processor is requested service only if any key is pressed, otherwise the CPU will
continue with its main task.
In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether any
key is pressed or not with key pressure.
How Does 8279 Keyboard Work?
The keyboard consists of maximum 64 keys, which are interfaced with the CPU by using the
key-codes. These key-codes
codes are de
de-bounced and stored in an 8-byte
byte FIFORAM, which can be
accessed by the CPU. If more than 8 characters are ente
entered
red in the FIFO, then it means more
than eight keys are pressed at a time. This is when the overrun status is set.
If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt mode else the
CPU checks the status in polling to read the entry. Once the CPU reads a key entry, then FIFO
is updated, and the key entry is pushed out of the FIFO to generate space for new entries.
Architecture and Description

I/O Control and Data Buffer

This unit controls the flow of data through the microprocessor. It is enabled only when D is low.
Its data buffer interfaces the external bus of the system with the internal bus of the
microprocessor. The pins A0, RD, and WR are used for command, status or data read/write
operations.
Control and Timing Register and Timing Control
This unit contains registers to store the keyboard, display modes, and other operations as
programmed by the CPU. The timing and control unit handles the timings for the operation of
the circuit.
Scan Counter
It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter
provides the binary count that is to be externally decoded to provide the scan lines for the
keyboard and display.
In the decoded scan mode, the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of 4 scan on SL 0-SL3.
Return Buffers, Keyboard Debounce, and Control
This unit first scans the key closure row
row-wise,
wise, if found then the keyboard debounce unit
debounces the key entry. In case, the same key is detected, then the code of that key is
directly transferred to the sensor RAM along with SHIFT & CONTROL key status.
FIFO/Sensor RAM and Status Logic
This unit acts as 8-byte first-in-first
first-out (FIFO) RAM where the key code of every pressed key
is entered into the RAM as per their sequence. The status logic generates an interrupt request
after each FIFO read operation till the FIFO gets empty.
In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is loaded
with the status of their corresponding row of sensors into the matrix. When the sensor changes
its state, the IRQ line changes to high and interrupts the CPU.
Display Address Registers and Display RAM
This unit consists of display addres
addresss registers which holds the addresses of the word currently
read/written by the CPU to/from the display RAM.
8279 − Pin Description
The following figure shows the pin diagram of 8279 −

Data Bus Lines, DB0 - DB7

These are 8 bidirectional data bus lines used to transfer the
data to/from the CPU.
CLK
The clock input is used to generate internal timings required
by the microprocessor.
RESET
As the name suggests this pin is used to reset the
microprocessor.
CS Chip Select
When this pin is set to low, it allows read/write operations,
else this pin should be set to high.
A0
This pin indicates the transfer of command/status
information. When it is low, it indicates the transfer of data.
RD, WR
This Read/Write pin enables the data buffer to send/receive data over the data bus.
IRQ
This interrupt output line goes high when there is data in the FIFO sensor RAM. The interrupt
line goes low with each FIFO RAM read operation. However, if the FIFO RAM further contains
any key-code entry to be read by the CPU, this pin again goes high to generate an interrupt to
the CPU.
Vss, Vcc
These are the ground and power supply lines of the microprocessor.
SL0 − SL3
These are the scan lines used to scan the keyboard matrix and display the digits. These lines
can be programmed as encoded or decoded, using the mode control register.
RL0 − RL7
These are the Return Lines which are connected to one terminal of keys, while the other
terminal of the keys is connected to the decoded scan lines. These lines are set to 0 when any
key is pressed.
SHIFT
The Shift input line status is stored along with every key code in FIFO in the scanned keyboard
mode. Till it is pulled low with a key closure, it is pulled up internally to keep it high
CNTL/STB - CONTROL/STROBED I/P Mode
In the keyboard mode, this line is used as a control input and stored in FIFO on a key closure.
The line is a strobe line that enters the data into FIFO RAM, in the strobed input mode. It has
an internal pull up. The line is pulled down with a key closure.
BD
It stands for blank display. It is used to blank the display during digit switching.
OUTA0 – OUTA3 and OUTB0 – OUTB3
These are the output ports for two 16x4 or one 16x8 internal display refresh registers. The data
from these lines is synchronized with the scan lines to scan the display and the keyboard.

Operational Modes of 8279

There are two modes of operation on 8279 − Input Mode and Output Mode.
Input Mode
This mode deals with the input given by the keyboard and this mode is further classified into 3
modes.
 Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using either
encoded or decoded scans. In the encoded scan, an 8×8 keyboard or in the decoded
scan, a 4×8 keyboard can be interfaced. The code of key pressed with SHIFT and
CONTROL status is stored into the FIFO RAM.
  Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the
processor using either encoder or decoder scans. In the encoder scan, 8×8 sensor
matrix or with decoder scan 4×8 sensor matrix can be interfaced.
 Strobed Input − In this mode, when the control line is set to 0, the data on the return
lines is stored in the FIFO byte by byte.
Output Mode
This mode deals with display-related operations. This mode is further classified into two output
modes.
 Display Scan − This mode allows 8/16 character multiplexed displays to be organized
as dual 4-bit/single 8-bit display units.
 Display Entry − This mode allows the data to be entered for display either from the right
side/left side.