WLP HDaudio
WLP HDaudio
B2.8.4.1 NEW – HD Audio controllers comply with the Intel High Definition
Audio Controller specification
If the audio/modem controller is an HD Audio controller, except where noted
otherwise within this document it must:
A UAA device must support 256 entries each for the command output ring
buffer (CORB) and the response input ring buffer (RIRB).
The bus driver does not use the DMA position lower base address
(DPLBASE) and DMA position upper base address (DPUBASE) registers (at
offsets 70h and 74h).
The bus driver does not use the immediate command output, immediate
response input, and immediate command status registers (at offsets 60h, 64h,
and 68h).
The bus driver does not need to use the flush control bit in the global
control register (at offset 08h).
Design and Implementation Notes:
An HD Audio bus controller design can omit these features and still be fully
compatible with the Microsoft HD Audio bus driver. However, a hardware
vendor should consider whether these features might be necessary for
compatibility with other device-specific software. For example, a BIOS routine
might make use of the immediate command, response, and status registers.
B2.8.4.1.3 NEW – UAA version 1.0 HD Audio hardware use version number 1.0
For UAA version 1.0, the HD Audio hardware version must be 1.0. The VMAJ and
VMIN registers must specify a major version number of 01h and a minor version
number of 00h.
The controller must have at least three separate DMA engines for input
streams and at least four separate DMA engines for output streams.
Input:
DMA1: RTC (Headset)
DMA2: Record audio (separate from RTC)
DMA3: Modem
Output:
DMA1: RTC (Headset)
DMA2: Multi-channel Audio Playback (HD Audio codec listens to this stream for
both digital and analog output at the same time)
DMA3: Modem
DMA4: Futures (HDMI)
Design and Implementation Notes:
To keep stream latency small, a DMA engine in an HD Audio controller
implementation must avoid adding a significant hardware-buffering delay to an
audio data stream. Setting an upper limit on the buffering delay requires
restricting the DMA engine's FIFO to a maximum size in bytes that varies
according to the stream format. For each format, the hardware designer should
limit the FIFO to a size that keeps the latency small while providing glitch-free
audio.
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