Eetop - CN TN45CLDR001 2 6

SECURITY B
tsmc Taiwan Semiconductor Manufacturing Co., LTD

TSMC-RESTRICTED SECRET
Ver. Eff_Date ECN No. Author Change Description

2.6 10-31-19 E120201933134 M. H. Yang Please refer to Appendix A.13 Revision
(PDS) History for the update from V2.5 to V2.6.
2.5_R 10-31-18 E120201842189 M. H. Yang Correct attached seal ring gds file names.
(PDS) No any rule and gds content change.
2.5 09-19-18 E120201838097 M. H. Yang Please refer to Appendix A.12 Revision

2.4 07-29-16 E120201631098 M. S. Hsieh Please refer to Appendix A.11 Revision

Approvals : Title
Please refer to EDW workflow to see detail approval TSMC 45/40 NM CMOS LOGIC AND
records MS_RF DESIGN RULE
(CLN45LP/LPG, CLN40LP/LPG/LP+,
CLN40G)
Document No. : T-N45-CL-DR-001
Contents : 600
Attach. :0
Total : 600
The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in 1 of 600
whole or in part without prior written permission of TSMC.
SECURITY B
tsmc Taiwan Semiconductor Manufacturing Co., LTD
TSMC-RESTRICTED SECRET
Ver. Eff_Date ECN No. Author Change Description

2.3 08-03-15 E120201531138 Y. L. Chen Please refer to Appendix A.10 Revision
2.2 12-01-14 E120201436190 Y. L. Chen Please refer to Appendix A.9 Revision

(PDS) History for the update from V2.1 to V2.2
2.1 06-28-13 E120201316032 Y. L. Chen 1.Please refer to Appendix A.8 Revision

2.Change title
2.0 07-31-12 E120201231088 C. M. Kao Please refer to Appendix A.7 Revision

(PDS) History for the update from V1.3_1 to V2.0.
1.3_1 12-15-10 E070201048072 C. M. Kao Please refer to Appendix A.6 Revision

(PDS) History for the update from V1.3 to V1.3_1.
1.3 09-03-10 E070201036011 M. C. Lee Please refer to Appendix A.5 Revision

1.2 09-30-09 E070200935010 Y. M. Chen Please refer to Appendix A.4 Revision

History for the update from V1.1 to V1.2.
1.1 06-30-08 E120200826098 C. H. Lu Please refer to Appendix A.3 Revision



0.1 04-04-07 E120200713104 C. T. Tsai Provide the official N45GS design rule
manual
0.04 01-05-07 E120200704034 C. T. Tsai Original
Title
TSMC 45/40 NM CMOS LOGIC AND

MS_RF DESIGN RULE
(CLN45LP/LPG, CLN40LP/LPG/LP+,
CLN40G)
SECURITY B – TSMC RESTRICTED SECRET
tsmc Confidential – Do Not Copy Version : 2.6
TSMC 45/40 NM CMOS LOGIC AND MS_RF DESIGN RULE

(CLN45LP/LPG, CLN40LP/LPG/LP+, CLN40G)
Table of Contents
1 INTRODUCTION ................................................................................................................................................................. 8
1.1 OVERVIEW .................................................................................................................................................................. 8
1.2 REFERENCE DOCUMENT ............................................................................................................................................. 9
2 TECHNOLOGY OVERVIEW ............................................................................................................................................. 12
2.1 SEMICONDUCTOR PROCESS ...................................................................................................................................... 12
2.1.1 Front-End Features ......................................................................................................................................... 12
2.1.2 Back-End Features.......................................................................................................................................... 14
2.2 DEVICES................................................................................................................................................................... 15
2.3 POWER SUPPLY AND OPERATION TEMPERATURE RANGES.......................................................................................... 16
2.4 CROSS–SECTION ...................................................................................................................................................... 17
2.5 METALLIZATION OPTIONS .......................................................................................................................................... 23
3 GENERAL LAYOUT INFORMATION ............................................................................................................................... 27
3.1 MASK INFORMATION, KEY PROCESS SEQUENCE, AND CAD LAYERS............................................................................ 27
3.2 METAL/VIA CAD LAYER INFORMATION FOR METALLIZATION OPTIONS ......................................................................... 51
3.3 DUMMY PATTERN FILL CAD LAYERS ......................................................................................................................... 53
3.4 SPECIAL RECOGNITION CAD LAYER SUMMARY .......................................................................................................... 54
3.5 DEVICE TRUTH TABLES ............................................................................................................................................. 58
3.5.1 N45/N40 Low Power (LP): 1.1V Core Design ................................................................................................. 59
3.5.2 N40 Low Power Plus (N40LP+): 1.1V Core and 2.5V I/O Design .................................................................. 61
3.5.3 N45LPG/N40LPG: 1.1V/0.9V Core Design ..................................................................................................... 62
3.5.4 N40G (N45GS) General Purpose Superb: 0.9V Core Design ........................................................................ 64
3.5.5 MOM ................................................................................................................................................................ 65
3.5.6 Inductor ........................................................................................................................................................... 67
3.6 MASK REQUIREMENT FOR DEVICE OPTIONS (HIGH/STD/LOW VT/ULTRA LOW VT PLUS).............................................. 69
3.7 DESIGN GEOMETRY RESTRICTIONS ........................................................................................................................... 70
3.7.1 Design Grid Rules ........................................................................................................................................... 70
3.7.2 OPC Recommendations and Guidelines ........................................................................................................ 71
3.8 DESIGN HIERARCHY GUIDELINES ............................................................................................................................... 73
3.9 CHIP IMPLEMENTATION AND TAPE OUT CHECKLIST ..................................................................................................... 74
4 LAYOUT RULES AND RECOMMENDATIONS ............................................................................................................... 75
4.1 LAYOUT RULE CONVENTIONS .................................................................................................................................... 75
4.2 DERIVED GEOMETRIES USED IN PHYSICAL DESIGN RULES.......................................................................................... 76
4.2.1 Derived Geometries ........................................................................................................................................ 76
4.2.2 Special Definition............................................................................................................................................. 77
4.3 DEFINITION OF LAYOUT GEOMETRICAL TERMINOLOGY ................................................................................................ 78
4.4 MINIMUM PITCHES .................................................................................................................................................... 86
4.5 LAYOUT RULES AND GUIDELINES ............................................................................................................................... 87
4.5.1 Gate Oxide and Diffusion (OD) Layout Rules (Mask ID: 120) ........................................................................ 87
4.5.2 Deep N-Well (DNW) Layout Rules (Mask ID: 119) [Optional] ........................................................................ 91
4.5.3 N-Well (NW) Layout Rules .............................................................................................................................. 94
4.5.4 N-Well Resistor Within OD (NWROD) Layout Rules ...................................................................................... 95
4.5.5 N-Well Resistor Under STI (NWRSTI) Layout Rules ...................................................................................... 97
4.5.6 Native Device (NT_N) Layout Rules ............................................................................................................... 98
4.5.7 Thick Oxide (OD2) Layout Rules (Mask ID: 152) .......................................................................................... 100
4.5.8 Dual Core Oxide (DCO) Layout Rules (Mask ID: 153) ................................................................................. 102
4.5.9 1.2V Core Oxide (OD_12) Layout Rules (Mask ID: 12A).............................................................................. 104
4.5.10 OD25_33 Layout Rules ................................................................................................................................. 106
4.5.11 OD25_18 Layout Rules ................................................................................................................................. 107
4.5.12 OD18_15 Layout Rules ................................................................................................................................. 108
4.5.13 Poly (PO) Layout Rules (Mask ID: 130) ........................................................................................................ 109
4.5.14 High Vt NMOS (VTH_N) Layout Rules (Mask ID: 11H) ................................................................................ 116
4.5.15 High Vt PMOS (VTH_P) Layout Rules (Mask ID: 11G) ................................................................................ 117
4.5.16 Low Vt NMOS (VTL_N) Layout Rules (Mask ID: 118) .................................................................................. 118
4.5.17 Low Vt PMOS (VTL_P) Layout Rules (Mask ID: 117) .................................................................................. 119
4.5.18 Ultra Low Vt Plus Devices Layout Rules ....................................................................................................... 120
4.5.19 P+ Source/Drain Ion Implantation (PP) Layout Rules (Mask ID: 197) .......................................................... 124
4.5.20 N+ Source/Drain Ion Implantation (NP) Rules (Mask ID: 198) ..................................................................... 126
4.5.21 Layout Rules for LDD Mask Logical Operations ........................................................................................... 128
4.5.22 Resist Protection Oxide (RPO) Layout Rules (Mask ID: 155) ...................................................................... 130
4.5.23 OD and Poly Resistor Layout Rules.............................................................................................................. 131
4.5.24 HVMOS_25 Layout Rules ............................................................................................................................. 133
4.5.25 HVMOS_18 Layout Rules ............................................................................................................................. 139
4.5.26 HVMOS Guard-Ring Rules and Guidelines for HVMOS_25 and HVMOS_18 ............................................. 145
4.5.27 MOS Varactor Layout Rules (VAR)............................................................................................................... 146
4.5.28 Contact (CO) Layout Rules (Mask ID: 156) .................................................................................................. 149
4.5.29 Metal-1 (M1) Layout Rules (Mask ID: 360) ................................................................................................... 152
4.5.30 VIAx Layout Rules (Mask ID: 378, 379, 373, 374, 375, 376, 377) ................................................................ 159
4.5.31 Mx Layout Rules (Mask ID: 380, 381, 384, 385, 386, 387, 388) .................................................................. 165
4.5.32 LOWMEDN Layout Rules ............................................................................................................................. 172
4.5.33 VIAy Layout Rules (Mask ID: 379, 373, 374, 375, 376, 377, 372, 37A) ....................................................... 174
4.5.34 My Layout Rules (Mask ID: Second Inter-layer Metal (385, 386, 387, 388) and Top Metal (381, 384, 385,
386, 387, 388, 389, 38A)) ............................................................................................................................................ 179
4.5.35 Top VIAz Layout Rules (Mask ID: 379, 373, 374, 375, 376, 377, 372, 37A) ................................................ 182
4.5.36 Top Mz Layout Rules (Mask ID: 381, 384, 385, 386, 387, 388, 389, 38A) ................................................... 186
4.5.37 Top VIAr Layout Rules (Mask ID: 375, 376, 377, 372, 37A) ......................................................................... 188
4.5.38 Top Mr Layout Rules (Mask ID: 386, 387, 388, 389, 38A) ........................................................................... 191
4.5.39 RV Layout Rules (Mask ID: 306)................................................................................................................... 193
4.5.40 Al Redistributional Layer (AP RDL) Layout Rules (Mask ID: 309) ................................................................ 194
4.5.41 Via Layout Recommendations ...................................................................................................................... 196
4.5.42 MOM Layout Rules........................................................................................................................................ 197
4.5.43 Top VIAu Layout Rules (Mask ID: 373, 374, 375, 376, 377, 372, 37A) ........................................................ 203
4.5.44 Mu (Ultra Thick Metal) Layout Rules ............................................................................................................. 204
4.5.45 Inductor Layout Rules ................................................................................................................................... 206
4.5.46 Introduction of Inductor and Transmission Line ............................................................................................ 215
4.5.47 SRAM Rules .................................................................................................................................................. 219
4.5.48 NPreDOSRM (50;21) Layout Rules .............................................................................................................. 225
4.5.49 SRAM Periphery (Word Line Driver) Rules ................................................................................................... 227
4.5.50 SRAM CO2 (100;0) Layout Rule for Embedded DRAM (eDRAM) Process ................................................. 228
4.5.51 ROM Rules .................................................................................................................................................... 229
4.5.52 Antenna Effect Prevention (A) Layout Rules ................................................................................................ 230
4.5.53 Product Labels and Logo Rules .................................................................................................................... 235
4.5.54 Seal Ring Overview ....................................................................................................................................... 236
4.5.55 Resistor Warning Rules ................................................................................................................................ 276
4.5.56 DRM and DRC Completeness ...................................................................................................................... 277
5 LAYOUT GUIDELINES FOR THE DEVICE GEOMETRY EFFECT ............................................................................... 278
5.1 LAYOUT RULES FOR THE WPE (W ELL PROXIMITY EFFECT)....................................................................................... 278
5.2 LAYOUT GUIDELINES FOR LOD (LENGTH OF THE OD REGION) EFFECT ...................................................................... 282
5.2.1 What is LOD? ................................................................................................................................................ 282
5.2.2 How to have a precise LOD Simulation ........................................................................................................ 282
5.3 LAYOUT GUIDELINES FOR OSE (OD SPACE EFFECT) ............................................................................................... 283
5.3.1 What is OSE? ................................................................................................................................................ 283
5.3.2 Id change on device due to OSE .................................................................................................................. 283
5.3.3 How to reduce the differences between pre-simulation and post-simulation ............................................... 284
5.4 LAYOUT GUIDELINES FOR PSE (POLY SPACE EFFECT) ............................................................................................. 287
5.4.1 What is PSE? ................................................................................................................................................ 287
5.4.2 Id change on device due to PSE ................................................................................................................... 287
5.4.3 How to reduce the differences between pre-simulation and post-simulation on N40G circuit? ................... 287
5.5 LAYOUT GUIDELINES FOR D-CESL EFFECT .............................................................................................................. 288
5.5.1 What is d-CESL effect? ................................................................................................................................. 288
5.5.2 Id change on the N40G device due to d-CESL ............................................................................................. 288
5.5.3 How to reduce the differences between pre-simulation and post-simulation on N40G circuit? ................... 289
6 N40LP/LPG DESIGN INFORMATION ............................................................................................................................ 291
6.1 NON-SHRINKABLE LAYOUT RULES ........................................................................................................................... 291
6.1.1 Purpose: ........................................................................................................................................................ 291
6.1.2 Non-shrinkable Rules .................................................................................................................................... 291
6.1.3 Stress Migration and Wide Metal Spacing Rules Adjustment (Rule Relaxing) ............................................. 292
6.1.4 Pad Rule for Wire Bond ................................................................................................................................ 294
6.1.5 Flip Chip Bump Rules ................................................................................................................................... 294
6.2 DESIGN FLOW FOR TAPE-OUT ................................................................................................................................ 295
6.2.1 How to design for CLN40LP/LPG shrink technology .................................................................................... 295
6.2.2 How to prepare a new design of CLN40LP/LPG .......................................................................................... 295
6.2.3 CLN45LP/LPG Design Migration to CLN40LP/LPG Technology .................................................................. 296
6.2.4 Layout check and post simulation ................................................................................................................. 297
7 LAYOUT RULES AND RECOMMENDATIONS FOR ANALOG CIRCUITS .................................................................. 301
7.1 USER GUIDES ......................................................................................................................................................... 301
7.2 LAYOUT RULES, RECOMMENDATIONS AND GUIDELINES FOR THE ANALOG DESIGNS ................................................... 302
7.2.1 General Guidelines........................................................................................................................................ 302
7.2.2 MOS Recommendations ............................................................................................................................... 303
7.2.3 Bipolar Transistor (BJT) Rules and Recommendations ................................................................................ 304
7.2.4 Resistor Rules ............................................................................................................................................... 305
7.2.5 Capacitor Guidelines ..................................................................................................................................... 306
7.3 LAYOUT RULES AND GUIDELINES FOR DEVICE PLACEMENT ....................................................................................... 307
7.3.1 General Rules and Guidelines ...................................................................................................................... 307
7.3.2 Matching Rules and Guidelines .................................................................................................................... 308
7.3.3 Electrical Performance Rules and Guidelines ............................................................................................... 315
7.3.4 Noise ............................................................................................................................................................. 320
7.4 BURN-IN GUIDELINES FOR ANALOG CIRCUITS ........................................................................................................... 323
8 DUMMY PATTERN RULE AND FILLING GUIDELINE .................................................................................................. 325
8.1 DUMMY OD (DOD/SR_DOD) RULES AND GUIDELINES ............................................................................................ 325
8.1.1 DOD Layout Rules ........................................................................................................................................ 326
8.1.2 SR_DOD Layout Rules ................................................................................................................................. 328
8.2 DUMMY POLY (DPO/SR_DPO) RULES AND GUIDELINES ......................................................................................... 330
8.2.1 DPO Layout Rules......................................................................................................................................... 331
8.2.2 SR_DPO Layout Rules ................................................................................................................................. 332
8.3 DUMMY TCD RULE AND FILLING GUIDELINE ............................................................................................................. 334
8.3.1 Dummy TCD Rules ....................................................................................................................................... 334
8.3.2 Dummy TCD layout Summary ...................................................................................................................... 338
8.4 DUMMY TCD DESIGN INFORMATION ........................................................................................................................ 339
8.4.1 Overview ....................................................................................................................................................... 339
8.4.2 Design Consideration of Dummy TCD Insertion ........................................................................................... 339
8.4.3 Dummy TCD Macro Placement .................................................................................................................... 340
8.4.4 P&R Dummy TCD Rule Check ..................................................................................................................... 341
8.4.5 Dummy TCD Macros Insertion Flow ............................................................................................................. 341
8.4.6 TCD Library Kits ............................................................................................................................................ 342
8.5 IN CHIP OVERLAY (ICOVL) RULE AND FILLING GUIDELINE........................................................................................ 343
8.5.1 In Chip Overlay (ICOVL) Rules ..................................................................................................................... 343
8.5.2 ICOVL layout Summary ................................................................................................................................ 349
8.5.3 N40 In-Chip OVL Marker Design Insertion Methodology .............................................................................. 350
8.6 DUMMY METAL (DM) RULES ................................................................................................................................... 353
8.7 DUMMY VIA (DVIAX) RULES ................................................................................................................................... 357
8.8 DUMMY PATTERN FILL USAGE SUMMARY ................................................................................................................. 359
8.8.1 Dummy Pattern Filling Requirements ........................................................................................................... 359
8.8.2 Recommended Flow for Dummy Pattern Filling ........................................................................................... 360
8.8.3 Blockage Layer (ODBLK/POBLK/DMxEXCL/ DVIAxEXCL) Requirements and Recommendations ........... 361
8.8.4 Dummy Pattern Filling Guidelines ................................................................................................................. 362
8.8.5 Mask Revision Guidelines ............................................................................................................................. 363
8.8.6 Dummy Pattern Re-fill Evaluation Flow Chart ............................................................................................... 364
9 DESIGN FOR MANUFACTURING (DFM) ...................................................................................................................... 368

9.1 LAYOUT GUIDELINES FOR YIELD ENHANCEMENT....................................................................................................... 368
9.1.1 Layout Tips for Minimizing Critical Areas ...................................................................................................... 368
9.1.2 Guidelines for Optimal Electrical Model and Silicon Correlation ................................................................... 371
9.1.3 Electrical Wiring............................................................................................................................................. 378
9.1.4 Guidelines for Mask Making Efficiency ......................................................................................................... 378
9.2 DFM RECOMMENDATIONS AND GUIDELINES SUMMARY............................................................................................. 379
9.2.1 Action-Required Rules .................................................................................................................................. 379
9.2.2 Recommendations ........................................................................................................................................ 380
9.2.3 Guidelines ..................................................................................................................................................... 385
9.2.4 Grouping Table of Recommendations .......................................................................................................... 386
9.3 GDA DIE SIZE OPTIMIZATION KIT ............................................................................................................................ 389
9.3.1 What is MFU?................................................................................................................................................ 390
9.3.2 Design Guidelines for Higher MFU ............................................................................................................... 390
9.3.3 Recommended GDA criteria MFU > 80% ..................................................................................................... 390
9.3.4 MFU Reference Table for N45 ...................................................................................................................... 391
9.3.5 MFU Reference Table for N40 ...................................................................................................................... 392
10 LAYOUT GUIDELINES FOR LATCH-UP AND I/O ESD .............................................................................................. 393
10.1 LAYOUT RULES AND GUIDELINES FOR LATCH-UP PREVENTION .................................................................................. 394
10.1.1 Latch-up Introduction .................................................................................................................................... 394
10.1.2 Layout Rules and Guidelines for Latch-up Prevention.................................................................................. 397
10.1.3 Test Specification and Requirements ........................................................................................................... 416
10.2 I/O ESD PROTECTION CIRCUIT DESIGN, LAYOUT RULES AND GUIDELINES ................................................................ 417
10.2.1 ESD introduction ........................................................................................................................................... 417
10.2.2 TSMC IO ESD layout style introduction ........................................................................................................ 420
10.2.3 ESD Implant (ESDIMP) Layout Rules (MASK ID: 111) ................................................................................ 422
10.2.4 SR_ESD device Layout Rules (N40G only) .................................................................................................. 423
10.2.5 ESD Dummy Layers Summary ..................................................................................................................... 424
10.2.6 ESD circuits Definition ................................................................................................................................... 425
10.2.7 Requirements for ESD Implant Masks .......................................................................................................... 426
10.2.8 DRC methodology for ESD guidelines .......................................................................................................... 426
10.2.9 ESD Guidelines ............................................................................................................................................. 431
10.3 ESD BACK-END RELIABILITY GUIDELINES ................................................................................................................ 456
10.3.1 Test Methodology .......................................................................................................................................... 456
10.3.2 Failure Mechanism ........................................................................................................................................ 457
10.3.3 Maximum ESD Current Density for Resistor ................................................................................................. 457
10.3.4 Maximum ESD Current Density for Via and Metal ........................................................................................ 458
10.3.5 Minimum ESD Current for ESD Device......................................................................................................... 459
10.4 TIPS FOR THE ESD/LATCHUP DESIGN ...................................................................................................................... 460
10.4.1 Tips for General Latchup Design .................................................................................................................. 460
10.4.2 Tips for General ESD Design ........................................................................................................................ 460
10.4.3 Tips for Power-Ground ESD Protection ........................................................................................................ 462
10.4.4 Tips for MOS gate directly connected to power/ground/IO PAD .................................................................. 463
10.5 ESD TESTING METHODOLOGY ................................................................................................................................. 466
10.5.1 Stress condition and Measurement condition ............................................................................................... 466
10.5.2 Failure criteria................................................................................................................................................ 466
11 CLN45LP/LPG RELIABILITY RULES .......................................................................................................................... 467
11.1 TERMINOLOGY ........................................................................................................................................................ 467
11.2 FRONT-END PROCESS RELIABILITY RULES AND MODELS .......................................................................................... 467
11.2.1 I/O Over Drive Voltage .................................................................................................................................. 467
11.2.2 Gate Oxide Integrity ...................................................................................................................................... 467
11.2.3 Hot Carrier Injection Effect ............................................................................................................................ 470
11.2.4 Negative Bias Temperature Instability (NBTI) ............................................................................................... 473
11.2.5 N45 Poly Current Density .............................................................................................................................. 475
11.2.6 N45 Poly EM Joule heating ........................................................................................................................... 475
11.2.7 N45 OD Current Density ............................................................................................................................... 476
11.3 BACK-END PROCESS RELIABILITY RULES................................................................................................................. 477
11.3.1 Stress Migration (SM) ................................................................................................................................... 477
11.3.2 Low-k Dielectric Integrity ............................................................................................................................... 477
11.3.3 Cu Metal Current Density (EM) Specifications .............................................................................................. 478
11.3.4 AP RDL Current Density (EM) Specifications ............................................................................................... 484
11.3.5 Cu Metal AC Operation ................................................................................................................................. 485
11.3.6 AP RDL AC Operation .................................................................................................................................. 494
12 CLN40LP/LPG/45GS(=40G) RELIABILITY RULES .................................................................................................... 495
12.1 TERMINOLOGY ........................................................................................................................................................ 495
12.2 FRONT-END PROCESS RELIABILITY RULES AND MODELS .......................................................................................... 495
12.2.1 I/O Over Drive Voltage .................................................................................................................................. 495
12.2.2 Gate Oxide Integrity ...................................................................................................................................... 495
12.2.3 Hot Carrier Injection Effect ............................................................................................................................ 499
12.2.4 Negative Bias Temperature Instability (NBTI) ............................................................................................... 502
12.2.5 N40 Poly Current Density .............................................................................................................................. 504
12.2.6 N40 Poly EM Joule heating ........................................................................................................................... 504
12.2.7 N40 OD Current Density ............................................................................................................................... 505
12.3 BACK-END PROCESS RELIABILITY RULES................................................................................................................. 506
12.3.1 Stress Migration (SM) ................................................................................................................................... 506
12.3.2 Low-k Dielectric Integrity ............................................................................................................................... 506
12.3.3 Cu Metal Current Density (EM) Specifications .............................................................................................. 508
12.3.4 AP RDL Current Density (EM) Specifications ............................................................................................... 514
12.3.5 Cu Metal AC Operation ................................................................................................................................. 515
12.3.6 AP RDL AC Operation .................................................................................................................................. 526
13 APPENDIX A REVISION HISTORY .............................................................................................................................. 527
A.1 FROM VERSION 0.1 TO 0.2........................................................................................................................................... 527
A.2 FROM VERSION 0.2 TO 1.0........................................................................................................................................... 537
A.3 FROM VERSION 1.0 TO 1.1........................................................................................................................................... 539
A.4 FROM VERSION 1.1 TO 1.2........................................................................................................................................... 544
A.5 FROM VERSION 1.2 TO 1.3........................................................................................................................................... 563
A.6 FROM VERSION 1.3 TO 1.3_1....................................................................................................................................... 565
A.7 FROM VERSION 1.3_1 TO 2.0....................................................................................................................................... 567
A.8 FROM VERSION 2.0 TO 2.1........................................................................................................................................... 592
A.9 FROM VERSION 2.1 TO 2.2........................................................................................................................................... 595
A.10 FROM VERSION 2.2 TO 2.3......................................................................................................................................... 597
A.11 FROM VERSION 2.3 TO 2.4......................................................................................................................................... 599
A.12 FROM VERSION 2.4 TO 2.5......................................................................................................................................... 599
A.13 FROM VERSION 2.5 TO 2.6......................................................................................................................................... 600
1 Introduction
This chapter has been divided into the following topics:
1.1 Overview
1.2 Reference document
1.1 Overview
This document provides all the rules and reference information for the design and layout of integration circuits
using the TSMC 45 nm CMOS LOGIC 1P10M (single poly, 10 metal layers), salicide, Cu technology. These
rules and information about other specifications apply to TSMC semiconductor process: CLN45LP, CLN40LP,
CLN40LP+, CLN45LPG, N40LPG, N40G (= N45GS), and N45/N40 MSRF.
 CLN45LP is a low-power product for applications with an 1.1V core design and with an 1.8V or a 2.5V
capable I/O’s.
 CLN40LP is a low-power product which is 90% linear shrinkage from CLN45LP layout dimension for
applications with an 1.1V core design, and with an 1.8V or a 2.5V capable I/O’s.
 CLN40LP+ (40nm low power plus) is a low-power product for applications with an 1.1V core design and
with a 2.5V capable I/O’s by adding ultra low Vt plus devices into TSMC 40nm CMOS logic low power
(CLN40LP) process.
 CLN45LPG is a low-power and low standby power product for applications with both 1.1V (LP) and 0.9V
(G) core designs and with an 1.8V capable I/O’s.
 CLN40LPG is a low-power and low standby power product which is 90% linear shrinkage from CLN45
layout dimension for applications with both 1.1V (LP) and 0.9V (G) core designs and with a 3.3V capable
I/O’s. If you want to shrink CLN45LPG to CLN40LPG, you must redesign 3.3V I/O since 1.8V I/O cannot
be shrunk in LPG process.
 N40G (= N45GS) is a general-purpose product which is 90% linear shrinkage from 45nm layout
dimension for applications with a 0.9V core design and with 1.8V, 2.5V capable I/O’s.
 N45/N40 MSRF process can adopt the regular logic processes (CLN45LP/ CLN40LP/ CLN45LPG/
CLN40LPG/ CLN40G (=CLN45GS)), or adopt an ultra thick metal (Mu: 34KÅ or 35KÅ ) as the most top
metal layer (Mu layer only can be used as the most top metal layer).
In this document, figures and tables are usually numbered with 3 digits. The first two digits indicate section
number and the last one is sequence number. For example, Table 1.2.1 is the first table in the section 1.2 of
Chapter 1.
Warning: All tape-outs MUST be DRC clean.
1.2 Reference Document

Table 1.2.1 Reference Documents
Content Reference Document
 T-N45-CL-LE-001
GDS layer usage
TSMC 45/40 NM GENERAL PURPOSE GDS LAYER USAGE DESCRIPTION FILE
 T-N45-CL-DR-001-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
DRC deck TSMC 45 NM CMOS LOGIC AND 40NM CMOS LOGIC DRC COMMAND FILE (CLN45LP/LPG, CLN40LP/LPG,
CLN40G)
Wire bond and EU Flip Chip  T-N45-CL-DR-003
DRM TSMC 45NM/40NM WIRE BOND, EUTECTIC FLIP CHIP AND INTERCONNECTION DESIGN RULE
Wire bond and EU Flip Chip  T-N45-CL-DR-003-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
DRC deck TSMC 45NM/40NM WIRE BOND, EUTECTIC FLIP CHIP AND INTERCONNECTION DRC COMMAND FILE
 T-N40-CM-DR-004
DENMOS DRM
TSMC 40 NM RF HIGH VOLTAGE NMOS (DEMOS) DESIGN RULE
 T-N45-CL-DR-017
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH BUILD UP SUBSTRATE (FCBGA, FLIP CHIP BALL
GRID ARRAY) AND INTERCONNECTION DESIGN RULE
LF Flip Chip DRM
 T-N45-CL-DR-022
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH LAMINATE SUBSTRATE (FCCSP, FLIP CHIP CHIP
SCALE PACKAGE) AND INTERCONNECTION DESIGN RULE
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH BUILD UP SUBSTRATE (FCBGA, FLIP CHIP BALL
GRID ARRAY) AND INTERCONNECTION DRC COMMAND FILE
LF Flip Chip DRC
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH LAMINATE SUBSTRATE (FCCSP, FLIP CHIP CHIP
SCALE PACKAGE) AND INTERCONNECTION DRC COMMAND FILE
 T-N45-CL-DR-001-X2 (X is the code of EDA tool. Please refer to TSMC-Online for the details)
Dummy pattern generation TSMC 45NM CMOS LOGIC DUMMY OD/PO GENERATION UTILITY
utility  T-N45-CL-DR-001-X3 (X is the code of EDA tool. Please refer to TSMC-Online for the details)
TSMC 45NM CMOS LOGIC DUMMY METAL GENERATION UTILITY
 T-N40-CL-RP-020
TSMC 40 NM CMOS LOGIC GENERAL PURPOSE DFM ROLLOUT PACKAGE REPORT
DFM guideline
 T-N40-CL-RP-016
TSMC N45/N40 LAYOUT GUIDELINES FOR LAYOUT ENVIRONMENT AND CO PLACEMENT
DFM utility
TSMC 45NM DFM REDUNDANT VIA UTILITY
 T-N45-CL-SP-001
TSMC 45NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE Cu_ELK 1.1V/1.8V SPICE MODELS
(CLN45LP)
 T-N45-CL-SP-012
TSMC 45 NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE CU_ELK 1.1V/2.5V SPICE MODELS
(CLN45LP)
 T-N45-CL-SP-051
TSMC 45 NM CMOS LOGIC LOW POWER HIGH VOLTAGE 1P10M+AL_RDL SALICIDE CU_ELK 2.5V SPICE
MODELS 45LP
 T-N40-CL-SP-040
TSMC 40 NM CMOS LOGIC GENERAL PURPOSE SALICIDE 1P10M_7X2Z+UT-ALRDL CU_ELK HD BEOL SPICE
MODEL 40G
 T-N45-CE-SP-001
TSMC 45 NM CMOS EMBEDDED DRAM GENERAL PURPOSE SUPERB 1P8M_5X2R_UT-ALRDL SALICIDE
CU_LOWK 0.9V&1.4V SPICE MODELS 40G (CLN45GS EDRAM)
 T-N40-CL-SP-038
SPICE
MODELS 40LP
 T-N40-CL-SP-034
TSMC 40 NM CMOS LOGIC LOW POWER HIGH VOLTAGE 1P10M+ AL_RDL SALICIDE CU_ELK 2.5V SPICE
MODEL 40LP
 T-N40-CL-SP-041
TSMC 40 NM CMOS LOGIC LOW POWER SALICIDE 1P10M_7X2Z+UT-ALRDL CU_ELK HD BEOL SPICE
MODEL 40LP
 T-N40-CL-SP-031-P1
TSMC 40 NM CMOS LOGIC LP-BASED TRIPLE GATE OXIDE WITH DUAL CORE 1P10M+AL_RDL SALICIDE
ELK CU 0.9/1.1/3.3V SPICE MODEL 40LPG (PRE-RELEASE)
 T-N40-CE-SP-001
TSMC 40 NM CMOS EMBEDDED DRAM LOW POWER 1P8MT2 (2XTM : M7-M8) SALICIDE CU_LOWK
1.1V&1.5V SPICE MODELS (CLN40LP EDRAM)
 T-N40-CL-SP-051
TSMC 40 NM CMOS LOGIC LOW POWER PLUS 1P10M SALICIDE CU_ELK 1.1/2.5V SPICE MODEL 40LE
 T-N40-CL-SP-038
MODELS 40LP
 T-N40-CL-SP-034
TSMC 40 NM CMOS LOGIC LOW POWER HIGH VOLTAGE 1P10M+ AL_RDL SALICIDE CU_ELK 2.5V SPICE
MODEL 40LP
 T-N40-CL-SP-032
TSMC 40NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE CU_ELK 1.1V/1.8V SPICE MODELS 40LP
 T-N40-CL-SP-004
TSMC 40NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE CU_ELK 1.1V/2.5V SPICE MODELS 40LP
 T-N45-CL-SP-012
TSMC 45NM CMOS LOGIC LOW POWER 1P10M+AL_RDL SALICIDE Cu_ELK 1.1V/2.5V SPICE MODELS
(CLN45LP)
 T-N45-CL-SP-010
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M+AL_RDL SALICIDE CU_ELK 0.9V/1.2V/1.8V
SPICE MODELS 40G
 T-N45-CL-SP-011
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M+AL_RDL SALICIDE CU_ELK 0.9/1.2V/2.5V
SPICE MODEL 40G
 T-N45-CL-SP-053
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M+AL RDL SALICIDE CU_ELK 0.9/1.8V
SPICE MODELS 40G
 T-N45-CM-SP-004
TSMC 45 NM CMOS MIXED SIGNAL RF LOW POWER 1P9M+AL_RDL SALICIDE CU_ELK 1.1&1.8V SPICE
MODEL 45LP
 T-N40-CM-SP-004
TSMC 40 NM CMOS MIXED SIGNAL RF GENERAL PURPOSE 1P10M+AL_RDL SALICIDE CU_ELK 0.9/1.8V
SPICE MODEL 40G (45GS, TGO)
 T-N40-CM-SP-007
SPICE MODEL 40G (45GS, DGO)
 T-N40-CM-SP-003
SPICE MODEL 40G (45GS)
 T-N40-CM-SP-002
MODEL 40LP
 T-N40-CM-SP-001
MODEL 40LP
 T-N45-CM-SP-003
MODEL 45LP
 T-N45-CL-LS-001
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE 1P10M SALICIDE DEVICE FORMATION EXAMPLES AND LVS
PROPERTIES
 T-N45-CL-LS-002
Device formation examples
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU_ELK 0.9&2.5V DEVICE
and LVS properties
FORMATION EXAMPLES AND LVS PROPERTIES
 T-N40-CL-LS-001
TSMC 40 NM CMOS LOW POWER DEVICE FORMATION EXAMPLES AND LVS PROPERTIES
(CLN40LP/CLN40LPG/CRN40LP)
 T-N45-CL-LS-001-X1 (X is the code of EDA tool. Please refer to TSMC-Online for the details.)
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE DEVICE FORMATION EXAMPLES AND LVS PROPERTIES
LVS COMMAND FILE
LVS
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU_ELK 0.9&2.5V DEVICE
FORMATION EXAMPLES AND LVS PROPERTIES
TSMC 40 NM CMOS LOW POWER LVS COMMAND FILE (CLN40LP/CLN40LPG/CRN40LP)
 T-N45-CL-SP-010-K1
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M+AL_RDL SALICIDE CU_ELK 0.9V/1.8V PDK
CLN45GS=CLN40G (INCLUDES: CLN45GS 0.9V/2.5V)
 T-N45-CM-SP-003-K1
TSMC 45 NM CMOS MIXED SIGNAL RF LOW POWER 1P9M+AL_RDL SALICIDE CU_ELK 1.1&2.5V PDK
(CRN45LP) (INCLUDES: CRN45LP 1.1V/2.5V; CRN45LP 1.1V/1.8V)
PDK
 T-N40-CM-SP-001-K1
TSMC 40 NM CMOS MIXED SIGNAL RF LOW POWER 1P9M+AL_RDL SALICIDE CU_ELK 1.1&2.5V PDK
(INCLUDES: CRN40LP 1.1V/1.8V)
 T-N40-CL-SP-051-K1
TSMC 40 NM CMOS MIXED SIGNAL RF LOW POWER PLUS 1P10M+AL_RDL SALICIDE CU_ELK 1.1&2.5V PDK
(1.1V/1.8V)
 T-N45-CL-CL-010
TSMC 45 NM CMOS LOGIC LOW POWER 1P10M SALICIDE CU_LOWK 1.1/1.8V 6T/8T SRAM CELL LAYOUT &
MODEL
 T-N45-CL-CL-014
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU_ELK 0.9V 6T/8T SRAM CELL
LAYOUT & MODEL (45GS (=40G), G SRAM)
 T-N45-CL-CL-015
SRAM
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU_ELK 0.9V (0.8V) 6T/8T SRAM
CELL LAYOUT & MODEL (45GS (=40G), GL SRAM)
 T-N40-CL-CL-001
TSMC 40 NM CMOS LOGIC LOW POWER 1P10M SALICIDE CU_ELK 6T/8T SRAM CELL LAYOUT & SPICE
MODEL (6T SINGLE PORT SRAM AND 8T DUAL PORT SRAM)
 T-000-CL-RP-002
TSMC EMBEDDED SRAM REDUNDANCY IMPLEMENTATION RULE AND ECC GUIDELINE
 T-N45-CL-QR-001
TSMC 45 NM CMOS LOGIC LOW POWER 1P7M SALICIDE CU_LOWK 1.1/1.8V QUALIFICATION REPORT-
FAB12
 T-N45-CL-QR-005
FAB12
 T-N45-CL-QR-006
TSMC 45 NM CMOS LOGIC LOW POWER 1P9M SALICIDE CU_ELK 1.1/1.8V CUP WIRE BOND PBGA
PACKAGE QUALIFICATION REPORT – 12 INCH FAB
 T-N45-CL-QR-010
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU ELK 0.9V/2.5V
QUALIFICATION REPORT-FAB12 (45GS (=40G))
 T-N45-CL-QR-011
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE SUPERB 1P10M SALICIDE CU ELK 0.9/1.8V QUALIFICATION
REPORT-FAB12 (45GS (=40G))
 T-N40-CL-QR-004
Qualification report TSMC 40 NM CMOS LOGIC LOW POWER 1P10M SALICIDE CU_ELK 1.1/2.5V QUALIFICATION REPORT-FAB12
(40LP)
 T-N40-CL-QR-005
TSMC 45 NM / 40 NM CMOS LOGIC 1P9M CU_ELK CUP WIRE BOND PBGA PACKAGE QUALIFICATION
REPORT-12 INCH FAB
 T-N40-CL-QR-027
TSMC 40 NM CMOS LOGIC LOW POWER HVMOS 1P10M SALICIDE CU_LOW K 1.1&2.5V AND HVMOS
(D5G2.5) PROCESS QUALIFICATION REPORT- FAB12
 T-N40-CL-QR-031
TSMC 40 NM CMOS LOGIC LOW POWER HVMOS 1P10M SALICIDE CU_LOW K 1.1&1.8V AND HVMOS
(D5G1.8) PROCESS QUALIFICATION REPORT- FAB12
 T-N40-CL-QR-043
TSMC 40 NM CMOS LOGIC LOW POWER HVMOS 1P10M SALICIDE CU_LOW K 1.1&2.5V and HVMOS
(D5G2.5) PROCESS QUALIFICATION REPORT-FAB14
 T-N40-CL-QR-049
FAB14 (HVMOS, D5G2.5)- FAB14
 E-MSS-02-02-024
Test Line Layout
TSMC TEST LINE LAYOUT USER GUIDELINE
 Q-QSM-05-03-221
Automotive
TSMC AUTOMOTIVE SERVICE FOR WAFER MANUFACTURING
2 Technology Overview
This chapter provides information about the following:
2.1 Semiconductor process (including front-end and back-end features)
2.2 Devices
2.3 Power supply and operation temperature ranges
2.4 Cross-section
2.5 Metallization options
2.1 Semiconductor Process

The process consists of the front-end features and the back-end features.
2.1.1 Front-End Features

 Shallow trench isolation (STI)
Used for active isolation to reduce active pitch (OD pitch)
 Retrograde twin well CMOS technology on <110> P- substrate (epitaxy wafer) (subtrate resistivity
of 8-12 Ω-cm) for N40G, and on <100> P- substrate (epitaxy wafer) (subtrate resistivity of 8-12 Ω-
cm) for N45LP/N40LP.
 Retrograde twin well CMOS technology
For a low well sheet resistance and enhancement of latch-up behavior (compared to conventionally
diffused wells). Also provides for a good control of short parasitic field transistors.
 Triple well, Deep N-Well (optional)
For isolating P-Well from the substrate
 Dual gate oxide process
Dual gate oxide LP (1.1V/2.5V or 1.1V/1.8V), GS (0.9V/2.5V,or 0.9V/1.8V)
 Triple gate oxide process

Dual core gate oxide and IO gate oxide N45LPG (0.9V/1.1V/1.8V(I/O)) and N40LPG(0.9V/1.1V/3.3V(I/O))
 N+/P+ poly gate
Allows symmetrical design of NMOS and PMOS devices
 Multiple Vt devices for low leakage or high performance requirements
These devices may be mixed on the same die.
 Native devices with dual gate oxide
 SRAM cells offering (The cells described here are before shrinkage)
Technology N45LP/N45LPG-LP N40LP/N40LP+/N40LPG-LP
HD = 0.299um^2 HD = 0.299um^2
(Vcc_nom = 1.1V) (Vcc_nom = 1.1V)
HC = 0.374um^2 HC (HP) = 0.374um^2
(Vcc_nom = 1.1V) (Vcc_nom = 1.0V - 1.1V)
HDDP (HP) = 0.589um^2*
Cell Size --
(Vcc_nom = 1.1V)
DP = 0.589um^2 DP = 0.589um^2
HCDP = 0.741um^2 HCDP (HP) = 0.741um^2
*HDDP(HP) 0.589um^2 will replace DP 0.589um^2 and share the same implant mask 11N/11P with HC(HP) and
HCDP(HP). Original DP will be kept supporting but not official offering any more. Please refer to SRAM cell doc T-
N40-CL-CL-001 for HDDP(HP) GDS and more information.
Technology N40G(=N45GS)
Process Option G GL
HD = 0.299um^2 HD = 0.299um^2 (=G)*
(Vcc_nom = 0.9V - 1.0V) (Vcc_nom = 0.9V - 1.0V)
HC = 0.374um^2 HC = 0.374um^2
Cell Size
DP = 0.589um^2 DP = 0.589um^2 (=G)**
HCDP = 0.741um^2 HCDP = 0.741um^2
**D299 and D589 in N40GL process belong to N40G.
 Self-aligned Ni-silicided drain, source, and gate

Silicide is necessary to short N+ and P+ gates; furthermore, it drastically reduces gate and S/D serial
resistance. Self-aligned silicide on source/drain structures allows butting straps with only one minimally
sized contact.
 Unsilicided poly and OD resistors
Silicide protection (requires one additional mask, RPO) is used to prevent silicide formation over the active
and poly area.
 Varactor
MOS varactor provides 0.9V/1.1V/1.2V/1.8V/2.5V NMOS-in-NW capacitor structure and 0.9V/1.8V/2.5V
PMOS-in-PW capacitor structure.
2.1.2 Back-End Features

 Tungsten contact connecting poly or OD to first metal level
 Three to ten Cu metal levels, plus last metal level in Al pad.
 Two kinds of inter-layer metal:
 Mx: First Inter-layer Metal, W/S=0.07μm/0.07μm.
 My: Second Inter-layer Metal, W/S=0.14μm/0.14μm.
 Four kinds of top-layer metal:
 Mz (TM): top metal pitch is 0.8μm (W/S=0.4μm/0.4μm).
 My (2XTM): top metal pitch is two times of Mx pitch (W/S=0.14μm/0.14μm).
 Mr: top metal pitch is 1.0μm (W/S=0.5μm/0.5μm)
 Mu: top metal pitch is 3.0μm (W/S=2μm/1μm)
 AlCu pad layer can be used as a redistribution layer (AP RDL) option.
 One or two thick last (top) Cu metal layers at a relaxed pitch for power, clock, busses, and major
interconnect signal distribution
 Tight pitch levels for routing on thin Cu for the other metal levels below the thick level
 Chemical mechanical polishing (CMP) for enhanced planarization (STI, contact, metals, vias,
passivation)
 Dual damascene copper interconnection, for metal-2 to the last (top) metal
 ELK inter-metal dielectric for thin metal
 Metal oxide metal (MOM) capacitor
 Use metal lines to design metal capacitor. The device does not require any additional mask.
 High-Q copper inductor for RF process:
 Have Mz, Mu process for inductor metal.
 Wire bond or flip chip terminals
 T-N45-CL-DR-003: TSMC WIRE BOND, EUTECTUC FLIP CHIP, AND INTERCONNECTION DESIGN
RULE
 For Lead-Free Flip Chip, please refer to section 1.2, Reference Document.
 Electrical fuse
The IP of electrical fuse is provided. Please contact your account manager to get the related information.
2.2 Devices
The technology provides multiple Vt devices, and optional thin and thick gate oxide native devices.
Table 2.2.1 Available Vt in each technology

Technology
Core
N45LP/N40LP N40LP+ N45LPG N40LPG N40G (0.9V)

High Vt   N/A 
(N40 LPG-LP only)
STD Vt     

Low Vt    
(N40 LPG-G only)
Ultra Low Vt Plus N/A  N/A N/A N/A

Native   N/A 
(N40 LPG-LP only)
Varactor*     
MOM     
Inductor     
* Please refer to section 4.5.26, MOS Varactor Layout Rules (VAR), in details.
2.3 Power Supply and Operation Temperature

Ranges
Table 2.3.1 Power Supplies
Technology
N45LP/N40LP N40LP+ N45LPG/N40LPG N40G
Normal *Max Normal *Max Normal *Max Normal *Max
power power power power power power power power
supply supply supply supply supply supply supply supply
Core (thin 1.1V(LP), 1.26(LP), 0.9V, 1.1V,
1.1V 1.26V 1.1V 1.26V
oxide) 0.9V(G) 1.05V(G) 1.2V(OD_12) 1.32V(OD_12)
1.8V 1.98V
1.8V 1.98V N/A N/A 1.8V 1.98V
(N45LPG) (N45LPG)
I/O (thick 2.5V 2.75V 2.5V 2.75V N/A N/A 2.5V 2.75V
oxide) 3.3V 3.63V
N/A N/A N/A N/A N/A N/A
(N40LPG) (N40LPG)
5V** 5.5V** 5V** 5.5V** N/A N/A N/A N/A
2.5V
overdrive 3.3V 3.63V 3.3V 3.63V N/A N/A 3.3V 3.63V
to 3.3V
2.5V
underdrive 1.8V 1.98V 1.8V 1.98V N/A N/A 1.8V 1.98V
to 1.8V
1.8V
1.5V 1.65V
underdrive NA NA N/A N/A 1.5V 1.65V
(N40LP) (N40LP)
to 1.5V
** Only drain side can be applied to 5V. The other terminals can only be applied to 2.5V (HVMOS_25 for
N45LP/N40LP/N40LP+) or 1.8V (HVMOS_18 for only N40LP).
The operation temperature range is -40C to 125C (junction temperature).
* Maximum power supply voltage means variation upper limit of product operation voltage.
o p e r a ti o n M a x i m u m p o w e r s u p p ly v o lta g e
v o lta g e
N o m ina l p o w e r
s u p p ly v o lta g e
o p e r a ti o n ti m e
2.4 Cross–section
Cross section (1P10M as inter Mx, top Mz(TM))
P a s s iv a tio n - 2
A P P a s s iv a tio n - 1
M 1 0 (C u ) M 10
U S G
M 1 0 W /S = 0 .4 /0 .4
V 9 W /S = 0 .3 6 /0 .3 4 V 9
M 9 (C u ) M 9
U S G
M 9 W /S = 0 .4 /0 .4
V 8 W /S = 0 .3 6 /0 .3 4 V 8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
E LK
~
~
M 3 W /S = 0 .0 7 /0 .0 7 M 3
M 3 (C u )
E LK
V 2
V 2 W /S = 0 .0 7 /0 .0 7
M 2 W /S = 0 .0 7 /0 .0 7 M 2 (C u )
M 2
E LK
V 1 W /S = 0 .0 7 /0 .0 7 V 1
M 1 W /S = 0 .0 7 /0 .0 7 M 1 (C u ) E LK
M 1
P O W /S = 0 .0 4 /0 .1 0 (o n S T I) C O W /S = 0 .0 6 /0 .0 8
0 .0 4 /0 .1 4 (o n O D ) W - P lu g
P o ly P o ly
O D W /S = 0 .0 6 /0 .0 8
S a lic id e S TI
Figure 2.4.1 Cross-section for 1P10M_7x2z
Cross section (1P10M as inter Mx, top My(2XTM))
AP P a s s iv a tio n - 1
M 1 0 (C u ) M 10
USG
M 1 0 W /S = 0 .1 4 /0 .1 4
V 9 W /S = 0 .1 4 /0 .1 4 V9
M 9 (C u ) M 9
USG
M 9 W /S = 0 .1 4 /0 .1 4
V 8 W /S = 0 .1 4 /0 .1 4 V8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
ELK
~
~
M 3 W /S = 0 .0 7 /0 .0 7 M 3
M 3 (C u )
ELK
V2
V 2 W /S = 0 .0 7 /0 .0 7
M 2 W /S = 0 .0 7 /0 .0 7 M 2 (C u )
M 2
ELK
V 1 W /S = 0 .0 7 /0 .0 7 V1
M 1 W /S = 0 .0 7 /0 .0 7 M 1 (C u ) ELK
M 1
P O W /S = 0 .0 4 /0 .1 0 (o n S T I) C O W /S = 0 .0 6 /0 .0 8
0 .0 4 /0 .1 4 (o n O D ) W - P lu g
P o ly P o ly
O D W /S = 0 .0 6 /0 .0 8
S a lic id e STI
Figure 2.4.2 Cross-section for 1P10M_7x2y
Cross section (1P10M as inter Mx/My, top Mz(TM))
AP P a s s iv a tio n - 1
M 1 0 (C u ) M 10
M 1 0 W /S = 0 .4 /0 .4 USG
V9
V 9 W /S = 0 .3 6 /0 .3 4
M 9 (C u ) M9
M 9 W /S = 0 .4 /0 .4
V8
V 8 W /S = 0 .3 6 /0 .3 4 USG
M 8 (C u ) M8
M 8 W /S = 0 .1 4 /0 .1 4 LK
V7
V 7 W /S = 0 .1 4 /0 .1 4
M 7 (C u ) M7
M 7 W /S = 0 .1 4 /0 .1 4 V6 LK
V 6 W /S = 0 .1 4 /0 .1 4
M 6 W /S = 0 .0 7 /0 .0 7 M6
M6 ELK
~
~
------------------------------------- -------------------------------------
M 2 W /S = 0 .0 7 /0 .0 7 M 2 (C u ) M2
ELK
V 1 W /S = 0 .0 7 /0 .0 7 V1
M 1 W /S = 0 .0 7 /0 .0 7 M 1 (C u ) ELK
M1
P O W /S = 0 .0 4 /0 .1 0 (o n S T I) C O W /S = 0 .0 6 /0 .0 8
0 .0 4 /0 .1 4 (o n O D ) W - P lu g
P o ly P o ly
O D W /S = 0 .0 6 /0 .0 8
S a lic id e STI
Figure 2.4.3 Cross-section for 1P10M_5x2y2z
Cross section (1P10M as inter Mx, top Mr)
A P P a s s iv a tio n - 1
M 1 0 (C u ) M 10
U S G
M 1 0 W /S = 0 .5 /0 .5
V 9 W /S = 0 .4 6 /0 .4 4 V 9
M 9 (C u ) M 9
U S G
M 9 W /S = 0 .5 /0 .5
V 8 W /S = 0 .4 6 /0 .4 4 V 8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
E LK
~
~
M 3 W /S = 0 .0 7 /0 .0 7 M 3
M 3 (C u )
E LK
V 2
V 2 W /S = 0 .0 7 /0 .0 7
M 2 W /S = 0 .0 7 /0 .0 7 M 2 (C u )
M 2
E LK
V 1 W /S = 0 .0 7 /0 .0 7 V 1
M 1 W /S = 0 .0 7 /0 .0 7 M 1 (C u ) M 1 E LK
P O W /S = 0 .0 4 /0 .1 0 (o n S T I) C O W /S = 0 .0 6 /0 .0 8
0 .0 4 /0 .1 4 (o n O D ) W - P lu g
P o ly P o ly
O D W /S = 0 .0 6 /0 .0 8
S a lic id e S TI
Figure 2.4.4 Cross-section for 1P10M_7x2r
Cross section (1P10M as inter Mx, top Mz/Mu (TM))
-
A P P a s s iv a tio n
1
M 1 0 (C u ) M 10
U S G
M 1 0 W /S = 2 .0 /1 .0
V 9 W /S = 0 .3 6 /0 .3 4 V 9
M 9 (C u ) M 9
U S G
M 9 W /S = 0 .4 /0 .4
V 8 W /S = 0 .3 6 /0 .3 4 V 8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
E LK
~
~
M 3 W /S = 0 .0 7 /0 .0 7 M 3
M 3
(C u )
E LK
V 2
V 2 W /S = 0 .0 7 /0 .0 7
M 2
M 2 W /S = 0 .0 7 /0 .0 7
(C u ) M 2
E LK
V 1 W /S = 0 .0 7 /0 .0 7 V 1
M 1 W /S = 0 .0 7 /0 .0 7 M 1
M 1 E LK
(C u ) C O W /S =
P O W /S = 0 .0 4 /0 .1 0 (o n S T I) W -
0 .0 4 /0 .1 4 (o n O D ) 0 .0 6 /0 .0 8
P lu g
P o ly P o ly
O D W /S =
0 .0 6 /0 .0 8
S a lic id e S TI
Figure 2.4.5 Cross-section for 1P10M_7x1z1u
Cross section (1P10M as inter Mx, top My(2XTM)/Mu(TM))
-
AP P a s s iv a tio n
1
M 1 0 (C u ) M 10
USG
M 1 0 W /S = 2 .0 /1 .0
V 9 W /S = 0 .3 6 /0 .3 4 V9
M 9 (C u ) M 9
USG
M 9 W /S = 0 .1 4 /0 .1 4
V 8 W /S = 0 .1 4 /0 .1 4 V8
M 8 W /S = 0 .0 7 /0 .0 7
M 8
ELK
~
~
M 3 W /S = 0 .0 7 /0 .0 7 M 3
M 3
(C u )
ELK
V2
V 2 W /S = 0 .0 7 /0 .0 7
M 2
M 2 W /S = 0 .0 7 /0 .0 7
(C u ) M 2
ELK
V 1 W /S = 0 .0 7 /0 .0 7 V1
M 1 W /S = 0 .0 7 /0 .0 7 M 1
M 1 ELK
(C u ) C O W /S =
P O W /S = 0 .0 4 /0 .1 0 (o n S T I) W -
0 .0 4 /0 .1 4 (o n O D ) 0 .0 6 /0 .0 8
P lu g
P o ly P o ly
O D W /S =
0 .0 6 /0 .0 8
S a lic id e STI
Figure 2.4.6 Cross-section for 1P10M_7x1y1u
2.5 Metallization Options

1. The general 45 nm logic process is offered with a single poly and ten metal layers (1P10M). In addition to
1P10M, please refer to the following tables for the other metallization options.
2. CAD layer datatype of Mu metal is “60” (that of dummy Mu layer is “61”), and CAD layer datatype of its
associated VIA (VIAu, the VIA under Mu) is “40” (the same as that of VIAz due to the same via size).
3. Follow VIAz rule for VIAu design.
4. For eddy current reduction to achieve better inductor RF performance, a special metal (and OD/PO) dummy
block layer called "INDDMY" (CAD layer:144) is offered to allow very low metal density within an inductor.
When "INDDMY" layer is used to construct inductors, one must follow the additional process-related design
rules listed in INDDMY inductor section.
5. For the INDDMY layer identified low metal density inductor region, the inter-via (both Vx and Vy) and top via
Vy (2XTM) are all not allowed. Please refer to the section 4.5.45 for the rules in details.
Table 2.5.1 N40G/N45LP/N40LP/N45LPG/N40LPG Naming for Different Metal

W/S (μm)
Metal type Code N40G/ Mask layers

N45LP/
N40LP/
N45LPG
N40LPG
M1 M1 0.07/0.07 0.07/0.07 M1 (360) only
First Inter-layer
Mx 0.07/0.07 0.07/0.07 M2~M8 (380, 381, 384, 385, 386, 387, 388), max : seven layers
Metal
Second Inter-layer
My 0.14/0.14 0.14/0.14 M5~M8 (385, 386, 387, 388), max : two layers
Metal
*Top Metal (2XTM) My 0.14/0.14 0.14/0.14 M3~M10 (381, 384, 385, 386, 387, 388, 389, 38A), max : two layers
Top Metal (TM) Mz 0.4/0.4 0.4/0.4 M3~M10 (381, 384, 385, 386, 387, 388, 389, 38A), max : two layers
*Top Metal (TM) Mr 0.5/0.5 0.5/0.5 M6~M10 (386, 387, 388, 389, 38A), max: two layers
M4~M10 (384, 385, 386, 387, 388, 389, 38A), max: one layer only
Ultra Thick Metal Mu 2.0/1.0 2.0/1.0
(the most top metal)
*: not for N45LP/N45LPG
Table 2.5.2 N40G/N45LP/N40LP/N45LPG/N40LPG Naming for Different Via Types

W/S(μm)
Via type Code N40G/ Mask layers

N45LP/
N40LP/
N45LPG
N40LPG
First Inter-layer
Vx 0.07/0.07 0.07/0.07 VIA1~VIA7 (378, 379, 373, 374, 375, 376, 377), max : seven layers
Via
Second Inter-
Vy 0.14/0.14 0.14/0.14 VIA4~VIA7 (374, 375, 376, 377), max : two layers
layer Via
*Top Via (2XTM) Vy 0.14/0.14 0.14/0.14 VIA2~VIA9 (379, 373, 374, 375, 376, 377, 372, 37A), max : two layers
Top Via (TM) Vz 0.36/0.34 0.36/0.34 VIA2~VIA9 (379, 373, 374, 375, 376, 377, 372, 37A), max : two layers
*Top Via Vr 0.46/0.44 0.46/0.44 VIA5~VIA9 (375, 376, 377, 372, 37A), max: two layers
Via under Ultra Vu VIA3~VIA9 (373, 374, 375, 376, 377, 372, 37A),
0.36/0.34 0.36/0.34
Thick Metal (Datatype:40) max : one layer only
*: not for N45LP/N45LPG
Table 2.5.3 Metallization Options for Mz (My/Vy are used as second inter-layer Metal/Via, where the
dielectric film material for inter-layer My/Vy is “LK”.)
Metal/ Total Number of Metal Layers
Via 3 4 5 6 7 8 9 10
M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1
VIA1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1
M2 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1
VIA2 Vz1 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2
M3 Mz1 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2
VIA3 Vz1 Vx3 Vz1 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3
M4 Mz1 Mx3 Mz1 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3
VIA4 Vz1 Vz2 Vx4 Vz1 Vy1 Vx4 Vx4 Vy1 Vx4 Vy1 Vx4 Vx4 Vx4 Vx4 Vx4 Vy1 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4
M5 Mz1 Mz2 Mx4 Mz1 My1 Mx4 Mx4 My1 Mx4 My1 Mx4 Mx4 Mx4 Mx4 Mx4 My1 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4
VIA5 Vz1 Vz2 Vz1 Vx5 Vy1 Vy2 Vz1 Vz1 Vx5 Vx5 Vy1 Vx5 Vy1 Vy2 Vx5 Vx5 Vx5 Vx5 Vx5 Vy1 Vx5 Vx5 Vx5
M6 Mz1 Mz2 Mz1 Mx5 My1 My2 Mz1 Mz1 Mx5 Mx5 My1 Mx5 My1 My2 Mx5 Mx5 Mx5 Mx5 Mx5 My1 Mx5 Mx5 Mx5
VIA6 Vz1 Vz1 Vz1 Vz2 Vz2 Vx6 Vy1 Vy2 Vz1 Vz1 Vz1 Vx6 Vx6 Vy1 Vx6 Vy1 Vy2 Vx6 Vx6 Vy1
M7 Mz1 Mz1 Mz1 Mz2 Mz2 Mx6 My1 My2 Mz1 Mz1 Mz1 Mx6 Mx6 My1 Mx6 My1 My2 Mx6 Mx6 My1
VIA7 Vz1 Vz1 Vz1 Vz2 Vz2 Vz2 Vx7 Vy1 Vy2 Vz1 Vz1 Vz1 Vx7 Vy1 Vy2
M8 Mz1 Mz1 Mz1 Mz2 Mz2 Mz2 Mx7 My1 My2 Mz1 Mz1 Mz1 Mx7 My1 My2
VIA8 Vz1 Vz1 Vz1 Vz2 Vz2 Vz2 Vz1 Vz1 Vz1
M9 Mz1 Mz1 Mz1 Mz2 Mz2 Mz2 Mz1 Mz1 Mz1
VIA9 Vz2 Vz2 Vz2
M10 Mz2 Mz2 Mz2
Table 2.5.4 Metallization Options for My (My/Vy are used as 2X top Metal/Via, where the dielectric film
material for top My/Vy is “USG”.)
Metal / Total Number of Metal Layers
Via 3 4 5 6 7 8 9 10
M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1
VIA1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1
M2 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1
VIA2 VyTV1 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2
M3 MyTM1 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2
VIA3 VyTV1 Vx3 VyTV1 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3
M4 MyTM1 Mx3 MyTM1 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3
VIA4 VyTV1 VyTV2 Vx4 VyTV1 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4
M5 MyTM1 MyTM2 Mx4 MyTM1 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4
VIA5 VyTV1 VyTV2 Vx5 VyTV1 Vx5 Vx5 Vx5 Vx5
M6 MyTM1 MyTM2 Mx5 MyTM1 Mx5 Mx5 Mx5 Mx5
VIA6 VyTV1 VyTV2 Vx6 VyTV1 Vx6 Vx6
M7 MyTM1 MyTM2 Mx6 MyTM1 Mx6 Mx6
VIA7 VyTV1 VyTV2 VyTV1 Vx7
M8 MyTM1 MyTM2 MyTM1 Mx7
VIA8 VyTV2 VyTV1
M9 MyTM2 MyTM1
VIA9 VyTV2
M10 MyTM2
Table 2.5.5 Metallization Options for Mr

Metal Total Number of Metal Layers
/Via 7 8 9 10
M1 M1 M1 M1 M1 M1 M1 M1
VIA1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1
M2 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1
VIA5 Vx5 Vr1 Vx5 Vx5 Vx5 Vx5 Vx5
M6 Mx5 Mr1 Mx5 Mx5 Mx5 Mx5 Mx5
VIA6 Vr1 Vr2 Vx6 Vr1 Vx6 Vx6 Vx6
M7 Mr1 Mr2 Mx6 Mr1 Mx6 Mx6 Mx6
VIA7 Vr1 Vr2 Vx7 Vr1 Vx7
M8 Mr1 Mr2 Mx7 Mr1 Mx7
VIA8 Vr1 Vr2 Vr1
M9 Mr1 Mr2 Mr1
VIA9 Vr2
M10 Mr2
Table 2.5.6 Metallization Options for Mu (Mu with second inter-layer metal/via (My/Vy) are used,
where the dielectric film material for inter-layer My/Vy is “LK”.)
Via 4 5 6 7 8 9 10
M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1
VIA1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1
M2 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1
VIA2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2
M3 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2
VIA3 Vu1 Vx3 Vz1 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3 Vx3
M4 Mu1 Mx3 Mz1 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3 Mx3
VIA4 Vu1 Vu1 Vx4 Vz1 Vy1 Vx4 Vx4 Vx4 Vy1 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4 Vx4
M5 Mu1 Mu1 Mx4 Mz1 My1 Mx4 Mx4 Mx4 My1 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4 Mx4
VIA5 Vu1 Vu1 Vu1 Vx5 Vy1 Vz1 Vz1 Vx5 Vx5 Vx5 Vy1 Vx5 Vx5 Vx5 Vx5 Vx5 Vx5
M6 Mu1 Mu1 Mu1 Mx5 My1 Mz1 Mz1 Mx5 Mx5 Mx5 My1 Mx5 Mx5 Mx5 Mx5 Mx5 Mx5
VIA6 Vu1 Vu1 Vu1 Vu1 Vx6 Vy1 Vz1 Vz1 Vx6 Vx6 Vx6 Vy1 Vx6 Vx6
M7 Mu1 Mu1 Mu1 Mu1 Mx6 My1 Mz1 Mz1 Mx6 Mx6 Mx6 My1 Mx6 Mx6
VIA7 Vu1 Vu1 Vu1 Vu1 Vx7 Vy1 Vz1 Vz1 Vx7 Vy1
M8 Mu1 Mu1 Mu1 Mu1 Mx7 My1 Mz1 Mz1 Mx7 My1
VIA8 Vu1 Vu1 Vu1 Vu1 Vz1 Vz1
M9 Mu1 Mu1 Mu1 Mu1 Mz1 Mz1
VIA9 Vu1 Vu1
M10 Mu1 Mu1
Table 2.5.7 Metallization Options (Mu with top metal/via (My/Vy, 2XTM) are used, where the dielectric
film material for top My/Vy is “USG”.)
Via 5 6 7 8 9 10
M1 M1 M1 M1 M1 M1 M1
VIA1 Vx1 Vx1 Vx1 Vx1 Vx1 Vx1
M2 Mx1 Mx1 Mx1 Mx1 Mx1 Mx1
VIA2 Vx2 Vx2 Vx2 Vx2 Vx2 Vx2
M3 Mx2 Mx2 Mx2 Mx2 Mx2 Mx2
VIA3 VyTV1 Vx3 Vx3 Vx3 Vx3 Vx3
M4 MyTM1 Mx3 Mx3 Mx3 Mx3 Mx3
VIA4 Vu1 VyTV1 Vx4 Vx4 Vx4 Vx4
M5 Mu1 MyTM1 Mx4 Mx4 Mx4 Mx4
VIA5 Vu1 VyTV1 Vx5 Vx5 Vx5
M6 Mu1 MyTM1 Mx5 Mx5 Mx5
VIA6 Vu1 VyTV1 Vx6 Vx6
M7 Mu1 MyTM1 Mx6 Mx6
VIA7 Vu1 VyTV1 Vx7
M8 Mu1 MyTM1 Mx7
VIA8 Vu1 VyTV1
M9 Mu1 MyTM1
VIA9 Vu1
M10 Mu1
Table 2.5.8 Reference documents about top metal scheme requirement for wire bond and flip chip
(EU and LF bumps) applications
Assmebly Type Document No. Document Title
TSMC 45NM/40NM WIRE BOND, EUTECTIC FLIP CHIP AND
Wire bond (WB) T-N45-CL-DR-003
INTERCONNECTION DESIGN RULE
Eutectic (EU) Bump Flip TSMC 45NM/40NM WIRE BOND, EUTECTIC FLIP CHIP AND
T-N45-CL-DR-003
Chip INTERCONNECTION DESIGN RULE
Lead Free (LF) Bump Flip TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH BUILD
Chip with build up (FCBGA) T-N45-CL-DR-017 UP SUBSTRATE (FCBGA, FLIP CHIP BALL GRID ARRAY) AND
substrate INTERCONNECTION DESIGN RULE
Lead Free (LF) Bump Flip TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH
Chip with laminate T-N45-CL-DR-022 LAMINATE SUBSTRATE (FCCSP, FLIP CHIP CHIP SCALE
(FCCSP) substrate PACKAGE) AND INTERCONNECTION DESIGN RULE
3 General Layout Information

This chapter provides the following general layout information:
3.1 Mask information, key process sequence, and CAD layers
3.2 Metal/via CAD layer information for metallization options
3.3 Dummy pattern fill CAD Layers
3.4 Special recognition CAD layer summary
3.5 Device truth tables
3.6 Mask requirements for device options (High/Std/Low Vt)
3.7 Design geometry restrictions
3.8 Design hierarchy guidelines
3.9 Chip Implementation and Tape Out Checklist
3.1 Mask Information, Key Process Sequence,

and CAD Layers
All tables list masks and corresponding masking steps.
1. TSMC uses NW and OD2 (OD_18, OD_25) to generate NW1V, NW2V, PW1V, and PW2V masks by
logical operations. Designers can draw NW only.
2. TSMC uses NP, PP, and other layers to generate N1V, N2V, P1V, and P2V masks by logical operations.
Designers do not need to draw these masks.
3. An Al pad is a reverse tone of CB with bias. However, in a flip-chip product, Al pad is a drawn layer.
The Mask Name column lists names that are reserved for standard mask steps. These names should not
be used for another purpose in tape out files without prior authorization from TSMC.
The CAD Layer column lists CAD layer numbers. To obtain all related CAD layer usage information,
please refer to TSMC Document, T-N45-CL-LE-001
4. In the tables of section 3.1, “ * “ means an optional mask. “ # “ means a non-design level mask which is no
need to draw (or design) this layer. This non-design level mask is generated by logical operation from other
drawn layers.
Warning:
1. Please contact TSMC for actually re-tapeout mask set if FEOL OD/Poly/CO GDS are
changed except all-FEOL-layer-change RTO.
2. 12E and 12F are composed of NW, OD, PO, NP, PP, CO, OD2, SRM, RH, VAR,
BJTDMY, and POFUSE. Whenever 12E and 12F tape out, up-to-date CAD layers
mentioned above must be enclosed in one database to generate correct pattern. If ≥
one of the above CAD layers is revised, both 12E and 12F must be re-taped out.
3. Must include VIA layer with metal layer while tape out, since metal OPC requires to
refer to VIA layer.
Warning:
A CAD layer number must be less than, or equal to, 255. If the number is greater than 255, the
mask making will fail.
Table 3.1.1 Mask Name and ID, Key Process Sequence, and CAD Layer for CLN45LP/CLN40LP
Key Process
Sequence Digitized Area Reference Layer in Logical Operation
Mask Name Mask ID CAD Layer Description
* = Optional (Dark or Clear) and OPC
Mask
OD, DOD, SR_DOD, DUMMYOD1~12,
DUMMYOD16, DPSRM, SRM_10TTP,
Device, ACTIVE, STRAP and
1 OD 120 D Derived SRM_8TTP, SRM_HC, SRM_HD,
interconnection regions
SRM_LV, SRM_HCDP, SRM, NW,
NDIFF, PDIFF, PRSRM
2* DNW 119 C 1 - Deep N-Well.
3# PW1V 191 D Derived NW, NT_N, OD2, SRM;0, HVD_P Core device P-Well.
OD2, NW, NT_N, HVD_N, NDIFF,
4# PW2V 193 C Derived 1.8V or 2.5V (only for N40LP) P-Well.
PDIFF, OD, PO
OD2, NW, NT_N, SRM;0, HVD_N,
5# NW1V 192 C Derived Core and I/O device N-Well.
HVD_P, NDIFF, PDIFF, OD, PO
16 1.8V: OD_18 1.8V or 2.5V (only for N40LP) thick
6 OD2 152 D
18 2.5V: OD_25 oxide for DGO process.
7# NPO 196 C Derived NP, SRM;21, SRM;0, POFUSE Pre-doped N+ poly.
PO, OD, OD2, NP, PP, SRM;0, SRM;1,
SRM;2, SRM_HC, PRSRM,
8 PO 130 D Derived Poly-Si.
DUMMYPO5, DPO, SR_DPO. NDIFF,
PDIFF, POFUSE
NP, NW, OD2, RH, VAR, POFUSE,
1.8V or 2.5V (only for N40LP) NLDD
9# N2V 116 C Derived BJTDMY, HVD_N, HVD_P, NDIFF,
implantation.
PDIFF, NT_N, OD, PO, PP.
PP, NW, OD2, RH, VAR, NT_N,
1.8V or 2.5V (only for N40LP) PLDD
10# P2V 115 C Derived POFUSE, BJTDMY, HVD_N, HVD_P,
implantation.
NDIFF, PDIFF, OD, PO, NP.
11* VTH_N 11H C Derived VTH_N, SRM;0 High Vt NMOS implantation.
OD2, NW, VTL_N, SRM;0, BJTDMY,
Low Vt NMOS implantation for LP
12* VTL_N 118 D Derived VTH_N, NT_N, SRM;1, RH, VAR,
only.
POFUSE, SRM;2, ULVT_N, PP
NP, NW, OD2, RH, VAR, SRM;0,
13# N1V 114 C Derived POFUSE, SRM;1, VTH_N, BJTDMY, Core device NLDD implantation.
SRM;2, ULVT_N, PP
Ultra-low Vt plus NMOS implantation
14* ULVT_N 11E C Derived ULVT_N, SRM;0
(only for N40LP)
SRM;0, NW, SRM;1, SRM_8TTP, SRAM HP cell NMOS Vt IMP2 only for
15* VTC_N2 11N C Derived
SRM_LV, PRSRM, PP N40LP.
16* VTC_N 112 C Derived PP, SRM;1, ULVT_N , VTH_N SRAM cell NMOS Vt.
17* VTH_P 11G C Derived VTH_P, SRM;0 High Vt PMOS implantation.
Low Vt PMOS implantation for LP
OD2, NW, VTL_P, SRM;0, SRM;2, RH,
only.
18* VTL_P 117 C Derived VAR, POFUSE, VTH_P, BJTDMY,
N40LP: Mask 117 is a must if
HVD_P, PO, NP, SRM;1, ULVT_P ,
HVPMOS_18 is used.
OD2, NW, VTL_P, SRM;0, SRM;2, RH, N45LP: 11C is a must if
19* VTL_P2 11C C Derived VAR, POFUSE, VTH_P, BJTDMY, PP, (a) No PMOS LVT (117) and
NP (b) NCI SRAM cell is used
PP, NW, OD2, RH, VAR, SRM;0,
20# P1V 113 C Derived SRM;2, BJTDMY, VTH_P, NP, SRM;1, Core device PLDD implantation.
ULVT_P, POFUSE
Ultra-low Vt plus PMOS implantation
21* ULVT_P 11F C Derived ULVT_P, SRM;0
(only for N40LP)
NW, SRM;0, SRM;2, NP, VTH_P, SRAM HP cell PMOS Vt IMP2 only for
22* VTC_P2 11P C Derived
ULVT_P N40LP.
23* VTC_P 199 C Derived NP, SRM;2, ULVT_P , VTH_P SRAM cell PMOS Vt.
PP, SRM;0, DOD, DPO, HVD_P,
24 PP 197 C Derived P+ implantation.
NDIFF, PDIFF, OD, PO
NP, SRM;0, POFUSE, DOD, DPO,
DUMMYOD9, HVD_N, NDIFF, PDIFF,
25 NP 198 C Derived N+ implantation.
OD, PO, PP, PRSRM, SRM_8TTP,
SRM_HC, SRM_HD, SRM_LV
ESD3, ESDIMP, NW, NP, NDIFF,
26* ESD 111 C 189;0 ESD implantation.
PDIFF, OD, PO, RPO
It can be skipped for N40LP 2.5V I/O
27* RPO2 124 C Derived OD2, BJTDMY, POFUSE, RH
w/o RPO2 mask
PO, RPO, HVD_N, HVD_P, OD, CO,
28 RPO 155 D Derived Silicide protection.
NDIFF, PDIFF
Key Process
Sequence Digitized Area Reference Layer in Logical Operation
Mask Name Mask ID CAD Layer Description
* = Optional (Dark or Clear) and OPC
Mask
CO;0, CO;11, OD, SRM;0,
SRAMDMY;4, SRAMDMY;1, PRSRM,
SRM_UHD, DUMMYOD1,
DUMMYOD3, DUMMYOD10,
29 CO 156 C Derived DUMMYOD11, DUMMYOD12, Contact window from M1 to OD or PO.
SRM_HD, NW, SRM_HCDP, PO,
SRM_HC, PP, DUMMYPO1, SDPRM,
DPSRM, SRM_10TTP, SRM_8TTP,
SRM_LV
30 M1 360 C 31 M1, DM1, DM1_O, VIA1 1st metal for interconnection.
31 VIA1 378 C 51 DVIA1 Via1 hole between M2 and M1.
32 M2 380 C 32 M2, DM2, DM2_O, VIA1, VIA2 2nd metal for interconnection.
34 M3 381 C 33 M3, DM3, DM3_O, VIA2, VIA3 3rd metal for interconnection.
36 M4 384 C 34 M4, DM4, DM4_O, VIA3, VIA4 4th metal for interconnection.
45 VIA8 372 C 58 - Via8 hole between M9 and M8.
46 M9 389 C 39 M9, DM9, VIA8, VIA9 9th metal for interconnection.
47 VIA9 37A C 59 - Via9 hole between M10 and M9.
48 M10 38A C 40 M10, DM10, VIA9 10th metal for interconnection
FBEOL option1 (Wire bond without AP RDL)
49 CB 107 C 76 - Passivation-1 open for bond pad.
50 AP 307 D Derived CB, CB2_WB Al pad.
86;20
51 CB2 308 C - Passivation-2 open for bond pad.
(CB2_WB)
Derived CB2_WB
52* PM 009 D Polyimide opening
5;0 -
FBEOL option2 (Flip chip without AP RDL)

48 CB 107 C 169 - Passivation-1 open for bump pad.
49 AP 307 D 74 - Al pad.
86;0
50 CB2 308 C - Passivation-2 open for bump pad.
(CB2_FC)
51 PM 009 D 5;0 - Polyimide opening
52 UBM 020 D 170;0 - Under bump metallurgy for flip chip.
FBEOL option3 (Wire bond with AP RDL)

48 CB-VD 306 C Derived CB, RV Passivation-1 open for bond pad, AP RDL via.
49 AP-MD 309 D 74 - Al pad, AP RDL.
86;20
50 CB2 308 C - Passivation-2 open.
(CB2_WB)
Derived CB2_WB
5;0 -
FBEOL option4 (Flip chip with AP RDL)

48 CB-VD 306 C Derived CBD, RV Passivation-1 open for bump pad, AP RDL via.
86;0
(CB2_FC)
Table 3.1.2 Mask Name and ID, Key Process Sequence, and CAD Layer for CLN40LP+ (1.1V Core and
2.5V I/O Design)
Key Process
Digitized Area
Sequence Mask CAD Reference Layer in Logical Operation and
Mask ID (Dark or Description
* = Optional Name Layer OPC
Clear)
Mask
1 OD 120 D Derived SRM_HCDP, SRM;0, NW, SRM_8TTP,
SRM_HC, SRM_HD, SRM_LV, NDIFF, PDIFF,
PRSRM
3# PW1V 191 D Derived NW, NT_N, OD2, SRM;0, HVD_P Core device P-Well.
OD2, NW, NT_N, OD, PO, HVD_N, NDIFF,
4# PW2V 193 C Derived 2.5V P-Well.
PDIFF
OD2, NW, NT_N, SRM;0, HVD_N, HVD_P, OD,
5# NW1V 192 C Derived Core and I/O device N-Well.
PO, NDIFF, PDIFF
2.5V thick oxide for DGO
6 OD2 152 D Derived OD_25, DCO_LPP
process.
N40LP+ dual core oxide for ultra
7 DCO_LPP 153 C 90;1 -
low Vt plus devices’ speed boost
PO, OD, OD2, NP, PP, SRM;0, SRM;1, SRM;2,
SRM_HC, PRSRM, DUMMYPO5, DPO,
SR_DPO, DCO_LPP, NDIFF, PDIFF, POFUSE,
ULVT_N, ULVT_P
NP, NW, OD2, RH, VAR, POFUSE, BJTDMY,
10# N2V 116 C Derived HVD_N, HVD_P, OD, PO, NDIFF, PDIFF, NT_N, 2.5V NLDD implantation.
PP
PP, NW, OD2, RH, VAR, NT_N, POFUSE,
11# P2V 115 C Derived BJTDMY, HVD_N, HVD_P, OD, PO, NDIFF, 2.5V PLDD implantation.
PDIFF, NP
12* VTH_N 11H C Derived VTH_N, SRM;0 High Vt NMOS implantation.
OD2, NW, VTL_N, SRM;0, BJTDMY, VTH_N,
13 VTL_N 118 D Derived NT_N, SRM;1, SRM;2, RH, VAR, POFUSE, Low Vt NMOS implantation.
DCO_LPP, PP, ULVT_N
NP, NW, OD2, RH, VAR, SRM;0, POFUSE,
14# N1V 114 C Derived SRM;1, VTH_N, BJTDMY, DCO_LPP, PP, Core device NLDD implantation.
SRM;2, ULVT_N
Ultra-low Vt plus NMOS
15 ULVT_N 11E C Derived ULVT_N, SRM;0, DCO_LPP
implantation for N40LP+ only
SRM;0, NW, SRM;1, SRM_8TTP, SRM_LV, SRAM HP cell NMOS Vt IMP2
16* VTC_N2 11N C Derived
PRSRM, DCO_LPP, PP only for N40LP+.
17* VTC_N 112 C Derived SRM;1, DCO_LPP, PP, ULVT_N, VTH_N SRAM cell NMOS Vt.
OD2, NW, VTL_P, SRM;0, SRM;2, RH, VAR,
19* VTL_P 117 C Derived POFUSE, VTH_P, BJTDMY, DCO_LPP, NP, Low Vt PMOS implantation.
SRM;1, ULVT_P
PP, NW, OD2, RH, VAR, SRM;0, SRM;2,
20# P1V 113 C Derived BJTDMY, VTH_P, NP, DCO_LPP, POFUSE, Core device PLDD implantation.
SRM;1, ULVT_P
Ultra-low Vt plus PMOS
21 ULVT_P 11F C Derived ULVT_P, SRM;0, DCO_LPP
implantation for N40LP+ only
NW, SRM;0, SRM;2, NP, VTH_P, DCO_LPP, SRAM HP cell PMOS Vt IMP2
22* VTC_P2 11P C Derived
ULVT_P only for N40LP+.
23* VTC_P 199 C Derived SRM;2, DCO_LPP, NP, ULVT_P, VTH_P SRAM cell PMOS Vt.
24 PP 197 C Derived PP, SRM;0, HVD_P, PO P+ implantation.
NP, SRM;0, POFUSE, DUMMYOD9, HVD_N,
PO, PP, PRSRM, SRM_HC, SRM_HD
26* ESD 111 C 189;0 - ESD implantation.
27* RPO2 124 C Derived OD2, BJTDMY, POFUSE, RH It is must for 2.5V [N40LP+]
28 RPO 155 D Dirived HVD_N, HVD_P, PO, RPO Silicide protection.
Key Process
Digitized Area
Sequence Mask CAD Reference Layer in Logical Operation and
Mask ID (Dark or Description
* = Optional Name Layer OPC
Clear)
Mask
CO;0, CO;11, OD, SRM;0, SRAMDMY;4,
SRAMDMY;1, PRSRM, SRM_UHD,
DUMMYOD1~4, DUMMYOD10, DUMMYOD11,
Contact window from M1 to OD
29 CO 156 C Derived DUMMYOD12, SRM_HD, NW, SRM_HCDP, PO,
or PO.
SRM_HC, PP, DUMMYPO1, DUMMYPO5,
SDPRM, DPSRM, NP, NDIFF, PDIFF,
SRM_10TTP, SRM_8TTP, SRM_LV
86;20
(CB2_WB)
Derived CB2_WB
5;0 -

50 AP 307 D 74 - Al pad.
86;0
(CB2_FC)

86;20
(CB2_WB)
Derived CB2_WB
5;0 -

86;0
(CB2_FC)
Table 3.1.3 Mask Name and ID, Key Process Sequence, and CAD Layer for CLN45LPG/N40LPG
Key Process
Sequence Mask Digitized Area Reference Layer in Logical Operation
Mask ID CAD Layer Description
* = Optional Name (Dark or Clear) and OPC
Mask
1 OD 120 D Derived SRM_8TTP, SRM_HC, SRM_HD,
SRM_LV, SRM_HCDP, SRM;0, NW,
NDIFF, PDIFF, PRSRM
3# PW1V 191 D Derived NW, NT_N, OD2, SRM;0,DCO Core device P-Well.
4# PW2V 193 C Derived OD2, NW, NT_N, DCO 1.8V or 3.3V P-Well.
5# NW1V 192 C Derived OD2, NW, NT_N, SRM;0,DCO Core device/1.8V N-Well.
6# NW2V 194 C Derived OD2, NW, NT_N, DCO 3.3V N-Well.(N40LPG only)
1.8V or 3.3V thick oxide for DGO
7 OD2 152 D Derived OD2, DCO
process.
8 DCO 153 C 90 GP oxide
PO, OD, OD2, NP, PP, SRM;0, SRM;1,
SRM;2, SRM_HC, PRSRM,
DUMMYPO5, DPO, DCO, SR_DPO,
NDIFF, PDIFF, POFUSE.
11# N2V 116 C Derived BJTDMY, NDIFF, PDIFF, NT_N, OD, 1.8V or 3.3V NLDD implantation.
PO, PP.
12# P2V 115 C Derived POFUSE, BJTDMY, NDIFF, PDIFF, OD, 1.8V or 3.3V PLDD implantation.
PO, NP.
1.45LPG: Low Vt NMOS
OD2, NW, VTL_N, SRM;0, BJTDMY,
implantation for both LP and GP.
13* VTL_N 118 D Derived VTH_N, NT_N, SRM;1, RH, VAR,DCO,
2.40LPG: Delta dose implantation for
POFUSE, NP
LPHVt NMOS and G LVt NMOS.
14# N1V_G 106 C Derived POFUSE, SRM;1, SRM;2, VTH_N, GP Core device NLDD implantation.
BJTDMY,DCO
SRM;0, NW, SRM;1, SRM_8TTP, SRAM HP cell NMOS Vt IMP2 only
15 VTC_N2 11N C Derived
SRM_LV, PRSRM , DCO, PP for N40LPG-LP.
SRAM HP cell PMOS Vt IMP2 only
16 VTC_P2 11P C Derived NW, SRM;0, SRM;2, NP, VTH_P, DCO
for N40LPG-LP
GP SRAM cell NMOS Vt
VTC_N_
17*# 104 C Derived SRM;1, DCO, PP, VTH_N It is a must if GP SRAM cell is used.
GP
(N40LPG only)
18# N1V 114 C Derived POFUSE, SRM;1, SRM;2, VTH_N, LP Core device NLDD implantation.
BJTDMY, DCO, PP
19# VTC_N 112 C Derived SRM;1, DCO, VTH_N, PP LP SRAM cell NMOS Vt.
1.45LPG: Low Vt PMOS
OD2, NW, VTL_P, SRM;0, SRM;1,
implantation for both LP and GP.
20* VTL_P 117 C Derived SRM;2, RH, VAR, POFUSE, VTH_P,
2.40LPG: Delta dose implantation for
BJTDMY, DCO, NP
LPHVt PMOS and G LVt PMOS.
21# P1V_G 105 C Derived POFUSE, SRM;1, SRM;2, VTH_N, GP Core device PLDD implantation.
BJTDMY, DCO, PP
GP SRAM cell PMOS Vt
VTC_P_
22*# 103 C Derived SRM;2, DCO, VTH_P, NP It is a must if GP SRAM cell is used.
GP
(N40LPG only)
(1) N45LPG: 11C is a must if
OD2, NW, VTL_P, SRM;0, SRM;2, RH, (a) No PMOS LVT (117) and
23* VTL_P2 11C C Derived
VAR, POFUSE, VTH_P, BJTDMY (b) NCI SRAM cell is used
(c) Only for LP of LPG
24# P1V 113 C Derived SRM;1, SRM;2, BJTDMY, VTH_P, DCO, LP Core device PLDD implantation.
POFUSE
25# VTC_P 199 C Derived SRM;2, DCO, VTH_P, NP LP SRAM cell PMOS Vt.
26 PP 197 C Derived PP, SRM;0 P+ implantation.
NP, SRM;0, POFUSE, DUMMYOD9,
PP, PRSRM, SRM_HC, SRM_HD
28 ESD 111 C 189;0 - ESD implantation.
Key Process
Sequence Mask Digitized Area Reference Layer in Logical Operation
Mask ID CAD Layer Description
* = Optional Name (Dark or Clear) and OPC
Mask
OD2, BJTDMY, POFUSE, RH, DCO,
29* RPO2 124 C Derived It is a must for 3.3V(N40LPG only)
SRM;0
30 RPO 155 D Derived PO Silicide protection.
CO;0, CO;11, OD, SRM;0,
SRAMDMY;4, SRAMDMY;1, PRSRM,
SRM_UHD, DUMMYOD1~4,
DUMMYOD10~12, DUMMYPO1, Contact window from M1 to OD or
31 CO 156 C Derived
DUMMYPO5, SRM_HD, NW, PO.
SRM_HCDP, DPSRM, NDIFF, PDIFF,
NP, PO, PP, SRM_10TTP, SRM_8TTP,
SRM_LV, SRM_HC
86;20
(CB2_WB)
Derived CB2_WB
5;0 -
52 AP 307 D 74 - Al pad.
86;0
(CB2_FC)
86;20
(CB2_WB)
Derived CB2_WB
5;0 -
86;0
(CB2_FC)
Table 3.1.4 Mask Name and ID, Key Process Sequence, and CAD Layer for CLN40G
Key Process
Digitized
Sequence Mask Mask CAD Reference Layer in Logical
Area (Dark Description
* = Optional Name ID Layer Operation and OPC
or Clear)
Mask
OD, DOD, SR_DOD,
DUMMYOD1~12, DUMMYOD16,
DPSRM, SRM_10TTP,
1 OD 120 D Derived SRM_HCDP, SRM;0, NW, OD2,
PO, PP, CO, NDIFF, PDIFF,
PRSRM, SRM_8TTP, SRM_HC,
SRM_HD, SRM_LV,
3# PW1V 191 D Derived NW, NT_N, OD2, SRM;0 Core device P-Well.
4# PW2V 193 C Derived OD2, NW, NT_N 1.8V or 2.5V P-Well.
High Vt NMOS implantation.
5* VTH_N 11H C Derived VTH_N, SRM;0, SRM;1 N40G: 11H is a must if SRAM is
used.
6# NW1V 192 C Derived OD2, NW, NT_N, SRM;0 Core device N-Well.
7# NW2V 194 C Derived NW, OD2, NT_N 1.8V or 2.5V N-Well.
9* OD_12 12A C 14;1 - 1.2V device oxide
16 1.8V or 2.5V thick oxide for DGO
10 OD2 152 D OD2, OD_12
18 process.
PO, OD, OD2, OD_12, NP, PP,
SRM;0, DPO, SR_DPO, NDIFF,
12 PO 130 D Derived PDIFF, POFUSE, DPSRM, Poly-Si.
SRM_HCDP, PRSRM,
DUMMYPO5, SRAMDMY;1
13# N2V 116 C Derived 1.8V or 2.5V NLDD implantation.
NT_N, BJTDMY,
14# P2V 115 C Derived 1.8V or 2.5V PLDD implantation.
POFUSE, BJTDMY
PP, NP, NW, OD2, RH, VAR, AP,
DOD, SRM;0, SR_ESD, OD, PO,
15 ODRZ 123 C Derived
DPO, SR_DPO, BJTDMY, NDIFF,
PDIFF,
OD2, NW, VTL_N, SRM;0, NT_N,
16* VTL_N 118 D Derived SRM;1, RH, VAR, POFUSE, Low Vt NMOS implantation
SRM;2, , BJTDMY
17# N1V 114 C Derived POFUSE, SRM;1, SRM;2 , VTH_N, Core device NLDD implantation.
BJTDMY
18* VTC_N 112 C 50;1 - SRAM cell NMOS Vt.
OD2, NW, VTL_P, SRM;0, SRM;1,
19* VTL_P 117 C Derived SRM;2, RH, VAR, POFUSE, NT_N, Low Vt PMOS implantation
PP, BJTDMY
20# P1V 113 C Derived SRM;2, BJTDMY, VTH_P, SRM;1, Core device PLDD implantation.
NT_N, POFUSE
21* VTC_P 199 C 50;2 - SRAM cell PMOS Vt.
11C is a must if N40GL 0.8V and N40G
22* VTL_P2 11C C Derived SRM;2, SRM_HC, SRM_HCDP
0.9V SRAM cell are both used
23 NSSD 13A C Derived PO, DPO, SR_DPO
24* ESD 111 C 189;0 - ESD implantation.
25 PP 197 C Derived PP, SRM;0 P+ implantation.
26 NP 198 C Derived NP, SRM;0, POFUSE N+ implantation.
NW, OD2, PP, SRN;0, BJTDMY,
27 SSMT 124 C Derived RH, VAR, POFUSE, SRM;0,
SRM;1, SRM;2
28 RPO 155 D Derived PO Silicide protection.
NW, OD, OD2 (OD_18, OD_25,
OD_33), PO, NP, PP, CO, SRM;0,
29 NILD 12E C Derived
RH, VAR, POFUSE, BJTDMY,
NDIFF, PDIFF, DOD
NW, OD, OD2 (OD_18, OD_25,
OD_33), PO, NP, PP, CO, SRM;0,
30 PILD 12F C Derived
RH, VAR, POFUSE, BJTDMY,
NDIFF, PDIFF, DOD
Key Process
Digitized
Sequence Mask Mask CAD Reference Layer in Logical
Area (Dark Description
* = Optional Name ID Layer Operation and OPC
or Clear)
Mask
CO;0, CO;11, OD, SRM;0,
SRAMDMY;1, SRAMDMY;5, NP,
NW, PO, PP, DUMMYOD1~4,
DUMMYOD11, DUMMYOD12,
31 CO 156 C Derived NDIFF, PDIFF, DPSRM, SRM_HC, Contact window from M1 to OD or PO.
PRSRM, DUMMYPO1,
DUMMYPO5, SRM_10TTP,
SRM_8TTP, SRM_LV, SRM_HD,
SRM_HCDP

86;20
(CB2_WB)
Derived CB2_WB
5;0 -

52 AP 307 D 74 - Al pad.
86;0
(CB2_FC)

Passivation-1 open for bond pad, AP
51 CB-VD 306 C Derived CB, RV
RDL via.
86;20
(CB2_WB)
Derived CB2_WB
5;0 -

Passivation-1 open for bump pad, AP
51 CB-VD 306 C Derived CBD, RV
RDL via.
86;0
(CB2_FC)
Table 3.1.5 N45LP/N40LP/N40LP+/N45LPG/N40LPG Mask Name/ID/Grade/Type, OPC, and PSM

Information
Mask Name Mask ID Mask Grade Mask Type OPC PSM Group
OD 120 L ASF A C
DNW 119 E DSF B B
PW1V 191 H DSF B B
VTC_N 112 H DSF A B
VTC_P 199 H DSF A B
PW2V 193 H DSF B B
VTH_N 11H H DSF A B
NW1V 192 H DSF B B
NW2V 194 H DSF B B
VTH_P 11G H DSF A B
OD2 152 H DSF B B
DCO/DCO_LPP 153 H DSF B B
NPO 196 H DSF A B
PO 130 M ASF A C
VTC_N2 11N H DSF A B
VTC_P2 11P H DSF A B
N2V 116 H DSF A B
P2V 115 H DSF A B
VTL_N 118 H DSF A B
ULVT_N 11E H DSF A B
N1V_G 106 H DSF A B
VTC_N_GP 104 H DSF A B
VTC_P_GP 103 H DSF A B
N1V 114 H DSF A B
VTL_P 117 H DSF A B
ULVT_P 11F H DSF A B
VTL_P2 11C H DSF A B
P1V_G 105 H DSF A B
P1V 113 H DSF A B
NP 198 H DSF A B
PP 197 H DSF A B
ESD 111 H DSF B B
RPO2 124 H DSF A B
RPO 155 F DSF B B
CO 156 L ASF A C
M1 360 L ASF A C
VIA1 378 K ASF A C
M2 380 K ASF A C
K ASF A C VIAx
I (N45) DSF (N45)
VIA2 379 A C VIAy
J (N40) ASF (N40)
F DSF B B VIAz
K ASF A C Mx
M3 381 I DSF A B My
F DSF B B Mz
K ASF A C VIAx
I (N45) DSF (N45)
VIA3 373 A C VIAy
J (N40) ASF (N40)
F DSF B B VIAz
K ASF A C Mx
I DSF A B My
M4 384
F DSF B B Mz
F DSF B B Mu
K ASF A C VIAx
I (N45) DSF (N45)
VIA4 374 A C VIAy
J (N40) ASF (N40)
F DSF B B VIAz
K ASF A C Mx
I DSF A B My
M5 385
F DSF B B Mz
F DSF B B Mu
K ASF A C VIAx
I (N45) DSF (N45)
VIA5 375 A C VIAy
J (N40) ASF (N40)
F DSF B B VIAz
K ASF A C Mx
I DSF A B My
M6 386
F DSF B B Mz
F DSF B B Mu
K ASF A C VIAx
I (N45) DSF (N45)
A C VIAy
J (N40) ASF (N40)
VIA6 376
F DSF B B VIAz
F DSF B B VIAu
F DSF B B VIAr
K ASF A C Mx
I DSF A B My
M7 387 F DSF B B Mz
F DSF B B Mr
F DSF B B Mu
K ASF A C VIAx
I (N45) DSF (N45)
A C VIAy
VIA7 377 J (N40) ASF (N40)
F DSF B B VIAz
F DSF B B VIAr
K ASF A C Mx
I DSF A B My
M8 388 F DSF B B Mz
F DSF B B Mr
F DSF B B Mu
I (N45) DSF (N45)
A C VIAy
J (N40) ASF (N40)
VIA8 372
F DSF B B VIAz
F DSF B B VIAr
I DSF A B My
F DSF B B Mz
M9 389 F DSF B B Mr
F DSF B B Mr
F DSF B B Mu
I (N45) DSF (N45)
A C VIAy
J (N40) ASF (N40)
VIA9 37A
F DSF B B VIAz
F DSF B B VIAr
I DSF A B My
F DSF B B Mz
M10 38A
F DSF B B Mr
F DSF B B Mu
CB 107 A DSF B B
CB-VD 306 D DSF B B
AP 307 A DSF B B
AP-MD 309 D DSF B B
CB2 308 A DSF B B
Table 3.1.6 N40G Mask Name/ID/Grade/Type, OPC, and PSM Information

OD 120 L ASF A C
DNW 119 E DSF B B
PW1V 191 H DSF B B
VTC_N 112 H DSF A B
VTC_P 199 H DSF A B
PW2V 193 H DSF B B
VTH_N 11H H DSF A B
NW1V 192 H DSF B B
NW2V 194 H DSF B B
VTH_P 11G H DSF A B
OD2 152 H DSF B B
OD_12 12A H DSF B B
NILD 12E H DSF A B
PILD 12F H DSF A B
ODRZ 123 H DSF A B
NSSD 13A H DSF A B
SSMT 124 H DSF A B
NPO 196 H DSF A B
PO 130 M ASF A C
N2V 116 H DSF A B
P2V 115 H DSF A B
VTL_N 118 H DSF A B
N1V 114 H DSF A B
VTL_P 117 H DSF A B
VTL_P2 11C H DSF A B
P1V 113 H DSF A B
NP 198 H DSF A B
PP 197 H DSF A B
ESD 111 H DSF B B
RPO 155 F DSF B B
CO 156 L ASF A C
M1 360 L ASF A C
VIA1 378 K ASF A C
M2 380 K ASF A C
K ASF A C VIAx
VIA2 379 J ASF A C VIAy
F DSF B B VIAz
K ASF A C Mx
M3 381 I DSF A B My
F DSF B B Mz
K ASF A C VIAx
F DSF B B VIAz
K ASF A C Mx
M4 384 I DSF A B My
F DSF B B Mz
K ASF A C VIAx
F DSF B B VIAz
K ASF A C Mx
M5 385 I DSF A B My
F DSF B B Mz
K ASF A C VIAx
F DSF B B VIAz
K ASF A C Mx
M6 386 I DSF A B My
F DSF B B Mz
K ASF A C VIAx
J ASF A C VIAy
VIA6 376 F DSF B B VIAz
F DSF B B VIAu
F DSF B B VIAr
K ASF A C Mx
I DSF A B My
M7 387
F DSF B B Mz
F DSF B B Mr
K ASF A C VIAx
J ASF A C VIAy
VIA7 377
F DSF B B VIAz
F DSF B B VIAr
K ASF A C Mx
I DSF A B My
M8 388
F DSF B B Mz
F DSF B B Mr
J ASF B C VIAy
VIA8 372 F DSF B B VIAz
F DSF B B VIAr
I DSF A B My
M9 389 F DSF B B Mz
F DSF B B Mr
J ASF B C VIAy
VIA9 37A F DSF B B VIAz
F DSF B B VIAr
I DSF A B My
M10 38A F DSF B B Mz
F DSF B B Mr
CB 107 A DSF B B
CB-VD 306 D DSF B B
AP 307 A DSF B B
AP-MD 309 D DSF B B
CB2 308 A DSF B B
Category Abbreviation Description

DSF DUV scanner
Mask type:
ASF 193nm scanner
B Non-OPC (Binary)
OPC:
A OPC
B Non-PSM (Binary)
PSM:
C PSM
Table 3.1.7 N40G 1.8V Mask to CAD layer mapping table

CAD DNW NW OD DOD NT_N VTL_N VTL_P OD_12 OD_18 PO DPO SR_DPO PP NP
Mask 1;0 3;0 6;0 6;1 11;0 12;0 13;0 14;1 16;0 17;0 17;1 17;7 25;0 26;0
120 OD V V V V V V
119 DNW V
191 PW1V V V V
193 PW2V V V V
192 NW1V V V V
194 NW2V V V V
152 OD2 V V
12A OD_12 V
196 NPO V
130 PO V V V V V V V
116 N2V V V V V
115 P2V V V V V
11H VTH_N
118 VTL_N V V V
114 N1V V V V
112 VTC_N
11G VTH_P
117 VTL_P V V V V V
113 P1V V V V V
199 VTC_P
13A NSSD V V V
197 PP V
198 NPO V
111 ESD
124 SSMT V V
123 ODRZ V V V V V V V V
12E NILD V V V V V V
12F PILD V V V V V V
155 RPO V
156 CO V V V V
CAD RPO CO CO;11 SRM;0 SRM;1 SRM;2 SRM;21 VTH_N VTH_P DPSRM PRSRM SRM_HC SRM_HD
Mask 29;0 30;0 30;11 50;0 50;1 50;2 50;21 67;0 68;0 80;0 80;11 80;13 80;14
120 OD V V V V V V
119 DNW
191 PW1V V
193 PW2V
192 NW1V V
194 NW2V
152 OD2
12A OD_12
196 NPO V V
130 PO V V V
116 N2V
115 P2V
11H VTH_N V V
118 VTL_N V V
114 N1V V
112 VTC_N V
11G VTH_P V V
117 VTL_P V
113 P1V V
199 VTC_P V
13A NSSD
197 PP V
198 NPO V
111 ESD
124 SSMT V
123 ODRZ V
12E NILD V V
12F PILD V V
155 RPO V
156 CO V V V V V V V
CAD SRM_LV SRM_HCDP SRM_8TTP SRM_10TTP DUMMYOD DUMMYPO BJTDMY RH SR_ESD VAR POFUSE SRAMDMY ESDIMP
Mask 80;15 80;16 80;17 80;18 82 83 110;0 117;0 121;0 143;0 156;0 186 189;0
120 OD V V V V V
119 DNW
191 PW1V
193 PW2V
192 NW1V
194 NW2V
152 OD2
12A OD_12
196 NPO V
130 PO V V V V
116 N2V V V V V
115 P2V V V V V
11H VTH_N
118 VTL_N V V V V
114 N1V V V V V
112 VTC_N
11G VTH_P
117 VTL_P V V V V
113 P1V V V V V
199 VTC_P
13A NSSD
197 PP
198 NPO V
111 ESD V
124 SSMT V V V V
123 ODRZ V V V V
12E NILD V V V V
12F PILD V V V V
155 RPO
Table 3.1.8 N40G 2.5V Mask to CAD layer mapping table

CAD DNW NW OD DOD NT_N VTL_N VTL_P OD_12 OD_25 PO DPO SR_DPO PP NP
Mask 1;0 3;0 6;0 6;1 11;0 12;0 13;0 14;1 18;0 17;0 17;1 17;7 25;0 26;0
120 OD V V V V V V
119 DNW V
191 PW1V V V V
193 PW2V V V V
192 NW1V V V V
194 NW2V V V V
152 OD2 V V
12A OD_12 V
196 NPO V
116 N2V V V V V
115 P2V V V V V
11H VTH_N
118 VTL_N V V V
114 N1V V V V
112 VTC_N
11G VTH_P
117 VTL_P V V V V V
113 P1V V V V V
199 VTC_P
13A NSSD V V V
197 PP V
198 NPO V
111 ESD
124 SSMT V V V
123 ODRZ V V V V V V V V
12E NILD V V V V V V V
12F PILD V V V V V V V
155 RPO V
156 CO V V V V
CAD RPO CO CO;11 SRM;0 SRM;1 SRM;2 SRM;21 VTH_N VTH_P DPSRM PRSRM SRM_HC SRM_HD
Mask 29;0 30;0 30;11 50;0 50;1 50;2 50;21 67;0 68;0 80;0 80;11 80;13 80;14
120 OD V V V V V V
119 DNW
191 PW1V V
193 PW2V
192 NW1V V
194 NW2V
152 OD2
12A OD_12
196 NPO V V
130 PO V V V
116 N2V
115 P2V
11H VTH_N V V
118 VTL_N V V
114 N1V V
112 VTC_N V
11G VTH_P V V
117 VTL_P V
113 P1V V
199 VTC_P V
13A NSSD
197 PP V
198 NPO V
111 ESD
124 SSMT V
123 ODRZ V
12E NILD V V
12F PILD V V
155 RPO V
CAD SRM_LV SRM_HCDP SRM_8TTP SRM_10TTP DUMMYOD DUMMYPO BJTDMY RH SR_ESD VAR POFUSE SRAMDMY ESDIMP
Mask 80;15 80;16 80;17 80;18 82 83 110;0 117;0 121;0 143;0 156;0 186 189;0
120 OD V V V V V
119 DNW
191 PW1V
193 PW2V
192 NW1V
194 NW2V
152 OD2
12A OD_12
196 NPO V
130 PO V V V V
116 N2V V V V V
115 P2V V V V V
11H VTH_N
118 VTL_N V V V V
114 N1V V V V V
112 VTC_N
11G VTH_P
117 VTL_P V V V V
113 P1V V V V V
199 VTC_P
13A NSSD
197 PP
198 NPO V
111 ESD V
124 SSMT V V V V
123 ODRZ V V V V
12E NILD V V V V
12F PILD V V V V
155 RPO
Table 3.1.9 N40LP 1.8V Mask to CAD layer mapping table

CAD DNW NW OD DOD NT_N VTL_N VTL_P OD_18 PO DPO SR_DPO PP NP RPO CO CO;11 SRM;0
Mask 1;0 3;0 6;0 6;1 11;0 12;0 13;0 16;0 17;0 17;1 17;7 25;0 26;0 29;0 30;0 30;11 50;0
120 OD V V V V
119 DNW V
191 PW1V V V V V
193 PW2V V V V
192 NW1V V V V
152 OD2 V
196 NPO V V
130 PO V V V V V V V V
116 N2V V V V V V V
115 P2V V V V V V V V
11H VTH_N V
118 VTL_N V V V V V
114 N1V V V V V V
11N VTC_N2 V V V
112 VTC_N V
11G VTH_P V
117 VTL_P V V V V V
113 P1V V V V V
11P VTC_P2 V V V
199 VTC_P V
197 PP V V
198 NP V V
111 ESD
155 RPO V V V V
CAD SRM;1 SRM;2 SRM;21 VTH_N VTH_P DPSRM PRSRM SRM_HC SRM_HD SRM_LV SRM_HCDP SRM_8TTP SRM_10TTP DUMMYOD DUMMYOD1 DUMMYOD2 DUMMYOD3
Mask 50;1 50;2 50;21 67;0 68;0 80;0 80;11 80;13 80;14 80;15 80;16 80;17 80;18 82 82;1 82;2 82;3
120 OD V V V V V V V V V V V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO V
130 PO V V V
116 N2V
115 P2V
11H VTH_N V
118 VTL_N V V V V V V
114 N1V V V V V V V
11N VTC_N2 V V V V
112 VTC_N V V
11G VTH_P V
117 VTL_P V V V
113 P1V V V V
11P VTC_P2 V V
199 VTC_P V V
197 PP
198 NP
111 ESD
155 RPO
156 CO V V V V V V V V V V
CAD DUMMYOD4 DUMMYOD5 DUMMYOD6 DUMMYOD7 DUMMYOD8 DUMMYOD11 DUMMYOD12 DUMMYOD16 DUMMYPO1 DUMMYPO5 BJTDMY RH VAR POFUSE SRAMDMY;1 SRAMDMY;4 ESDIMP
Mask 82;4 82;5 82;6 82;7 82;8 82;11 82;12 82;16 83;1 83;5 110;0 117;0 143;0 156;0 186;1 186;4 189;0
120 OD V V V V V V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO V
130 PO V V
116 N2V V V V V
115 P2V V V V V
11H VTH_N
118 VTL_N V V V V
114 N1V V V V V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P V V V V
113 P1V V V V V
11P VTC_P2
199 VTC_P
197 PP
198 NP V
111 ESD V
155 RPO
156 CO V V V V V
CAD HVD_N HVD_P
Mask 91;1 91;2
120 OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO
130 PO
116 N2V V
115 P2V
11H VTH_N
118 VTL_N
114 N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P V
113 P1V
11P VTC_P2
199 VTC_P
197 PP
198 NP
111 ESD
155 RPO V V
156 CO

Mask 1;0 3;0 6;0 6;1 11;0 12;0 13;0 16;0 17;0 17;1 17;7 25;0 26;0 29;0 30;0 30;11 50;0
120 OD V V V V
119 DNW V
191 PW1V V V V V
193 PW2V V V V
192 NW1V V V V
152 OD2 V
196 NPO V V
116 N2V V V V V V
11H VTH_N V
118 VTL_N V V V V V
114 N1V V V V V V
11N VTC_N2 V V V
112 VTC_N V
11G VTH_P V
117 VTL_P V V V V V
113 P1V V V V V
11P VTC_P2 V V V
199 VTC_P V
197 PP V V
198 NP V V
111 ESD
155 RPO V V V V
Mask 50;1 50;2 50;21 67;0 68;0 80;0 80;11 80;13 80;14 80;15 80;16 80;17 80;18 82 82;1 82;2 82;3
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO V
130 PO V V V
116 N2V
115 P2V
11H VTH_N V
114 N1V V V V V V V
11N VTC_N2 V V V V
112 VTC_N V V
11G VTH_P V
117 VTL_P V V V
113 P1V V V V
11P VTC_P2 V V
199 VTC_P V V
197 PP
198 NP
111 ESD
155 RPO
Mask 82;4 82;5 82;6 82;7 82;8 82;11 82;12 82;16 83;1 83;5 110;0 117;0 143;0 156;0 186;1 186;4 189;0
120 OD V V V V V V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO V
130 PO V V
116 N2V V V V V
115 P2V V V V V
11H VTH_N
118 VTL_N V V V V
114 N1V V V V V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P V V V V
113 P1V V V V V
11P VTC_P2
199 VTC_P
197 PP
198 NP V
111 ESD V
155 RPO
156 CO V V V V V

Mask 1;0 3;0 6;0 6;1 11;0 12;0 13;0 18;0 17;0 17;1 17;7 25;0 26;0 29;0 30;0 30;11 50;0
120 OD V V V V
119 DNW V
191 PW1V V V V V
193 PW2V V V V
192 NW1V V V V
152 OD2 V
196 NPO V V
116 N2V V V V V V V V
11H VTH_N V
118 VTL_N V V V V V
114 N1V V V V V V
11N VTC_N2 V V V
112 VTC_N V
11G VTH_P V
117 VTL_P V V V V V
113 P1V V V V V
11P VTC_P2 V V V
199 VTC_P V
197 PP V V
198 NP V V
111 ESD
124 SSMT V
155 RPO V V V V
Mask 50;1 50;2 50;21 67;0 68;0 80;0 80;11 80;13 80;14 80;15 80;16 80;17 80;18 82 82;1 82;2 82;3
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO V
130 PO V V V
116 N2V
115 P2V
11H VTH_N V
114 N1V V V V V V V
11N VTC_N2 V V V V
112 VTC_N V V
11G VTH_P V
117 VTL_P V V V
113 P1V V V V
11P VTC_P2 V V
199 VTC_P V V
197 PP
198 NP
111 ESD
124 RPO2
155 RPO
Mask 82;4 82;5 82;6 82;7 82;8 82;11 82;12 82;16 83;1 83;5 110;0 117;0 143;0 156;0 186;1 186;4 189;0
120 OD V V V V V V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO V
130 PO V V
116 N2V V V V V
115 P2V V V V V
11H VTH_N
118 VTL_N V V V V
114 N1V V V V V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P V V V V
113 P1V V V V V
11P VTC_P2
199 VTC_P
197 PP
198 NP V
111 ESD V
124 RPO2 V V V
155 RPO
156 CO V V V V V
CAD HVD_N HVD_P
Mask 91;1 91;2
120 OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO
130 PO
116 N2V V V
115 P2V
11H VTH_N
118 VTL_N
114 N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P
113 P1V
11P VTC_P2
199 VTC_P
197 PP
198 NP
111 ESD
124 RPO2
155 RPO V V
156 CO

Mask 1;0 3;0 6;0 6;1 11;0 12;0 13;0 18;0 17;0 17;1 17;7 25;0 26;0 29;0 30;0 30;11 50;0
120 OD V V V V
119 DNW V
191 PW1V V V V V
193 PW2V V V V
192 NW1V V V V
152 OD2 V
196 NPO V V
116 N2V V V V V V V
11H VTH_N V
118 VTL_N V V V V V
114 N1V V V V V V
11N VTC_N2 V V V
112 VTC_N V
11G VTH_P V
117 VTL_P V V V V V
113 P1V V V V V
11P VTC_P2 V V V
199 VTC_P V
197 PP V V
198 NP V V
111 ESD
124 RPO2 V
155 RPO V V V V
Mask 50;1 50;2 50;21 67;0 68;0 80;0 80;11 80;13 80;14 80;15 80;16 80;17 80;18 82 82;1 82;2 82;3
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO V
130 PO V V V
116 N2V
115 P2V
11H VTH_N V
114 N1V V V V V V V
11N VTC_N2 V V V V
112 VTC_N V V
11G VTH_P V
117 VTL_P V V V
113 P1V V V V
11P VTC_P2 V V
199 VTC_P V V
197 PP
198 NP
111 ESD
124 RPO2
155 RPO
Mask 82;4 82;5 82;6 82;7 82;8 82;11 82;12 82;16 83;1 83;5 110;0 117;0 143;0 156;0 186;1 186;4 189;0
120 OD V V V V V V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO V
130 PO V V
116 N2V V V V V
115 P2V V V V V
11H VTH_N
118 VTL_N V V V V
114 N1V V V V V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P V V V V
113 P1V V V V V
11P VTC_P2
199 VTC_P
197 PP
198 NP V
111 ESD V
124 RPO2 V V V
155 RPO
156 CO V V V V V
CAD HVD_N HVD_P
Mask 91;1 91;2
120 OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
196 NPO
130 PO
116 N2V
115 P2V
11H VTH_N
118 VTL_N
114 N1V
11N VTC_N2
112 VTC_N
11G VTH_P
117 VTL_P
113 P1V
11P VTC_P2
199 VTC_P
197 PP
198 NP
111 ESD
124 RPO2
155 RPO V V
156 CO
Table 3.1.13 N40LP Plus (N40LP+) 2.5V Mask to CAD layer mapping table
CAD DNW NW OD DOD NT_N VTL_N VTL_P OD_25 PO DPO SR_DPO PP NP RPO CO CO;11 SRM;0 SRM;1
Mask 1;0 3;0 6;0 6;1 11;0 12;0 13;0 18;0 17;0 17;1 17;7 25;0 26;0 29;0 30;0 30;11 50;0 50;1
120 OD V V V V
119 DNW V
191 PW1V V V V V
193 PW2V V V V
192 NW1V V V V
152 OD2 V
153 DCO_LPP
196 NPO V V
130 PO V V V V V V V V V
11H VTH_N V
11E ULVT_N V
114 N1V V V V V V V
11N VTC_N2 V V V V
112 VTC_N V V
11G VTH_P V
117 VTL_P V V V V V V
11F ULVT_P V
113 P1V V V V V V
11P VTC_P2 V V V
199 VTC_P V
197 PP V V
198 NP V V
111 ESD
124 RPO2 V
155 RPO V V
CAD SRM;2 SRM;21 VTH_N VTH_P DPSRM PRSRM SRM_HC SRM_HD SRM_LV SRM_HCDP SRM_8TTP SRM_10TTP DUMMYOD DUMMYOD1 DUMMYOD2 DUMMYOD3 DUMMYOD4 DUMMYOD5
Mask 50;2 50;21 67;0 68;0 80;0 80;11 80;13 80;14 80;15 80;16 80;17 80;18 82 82;1 82;2 82;3 82;4 82;5
120 OD V V V V V V V V V V V V V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
153 DCO_LPP
196 NPO V
130 PO V V
116 N2V
115 P2V
11H VTH_N V
118 VTL_N V V V V V
11E ULVT_N
114 N1V V V V V V
11N VTC_N2 V V V
112 VTC_N V
11G VTH_P V
117 VTL_P V V
11F ULVT_P
113 P1V V V
11P VTC_P2 V V
199 VTC_P V V
197 PP
198 NP
111 ESD
124 RPO2
155 RPO
CAD DUMMYOD6 DUMMYOD7 DUMMYOD8 DUMMYOD11 DUMMYOD12 DUMMYOD16 DUMMYPO1 DUMMYPO5 DCO_LPP BJTDMY RH VAR ULVT_N ULVT_P POFUSE SRAMDMY;1 SRAMDMY;4 ESDIMP
Mask 82;6 82;7 82;8 82;11 82;12 82;16 83;1 83;5 90;1 110;0 117;0 143;0 151;1 152;1 156;0 186;1 186;4 189;0
120 OD V V V V
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2 V
153 DCO_LPP V
196 NPO V
130 PO V V V
116 N2V V V V V
115 P2V V V V V
11H VTH_N
11E ULVT_N V
114 N1V V V V V V
11N VTC_N2 V
112 VTC_N V
11G VTH_P
117 VTL_P V V V V V
11F ULVT_P V V
113 P1V V V V V V
11P VTC_P2 V
199 VTC_P V
197 PP
198 NP V
111 ESD V
124 RPO2 V V V
155 RPO
156 CO V V V V V
Table 3.1.14 N45LPG 1.8V Mask to CAD layer mapping table

CAD DNW NW OD DOD NT_N VTL_N VTL_P OD_12 OD_18 PO DPO SR_DPO PP NP RPO CO CO;11
Mask 1;0 3;0 6;0 6;1 11;0 12;0 13;0 14;1 16;0 17;0 17;1 17;7 25;0 26;0 29;0 30;0 30;11
120 OD V V V
119 DNW V
191 PW1V V V V
193 PW2V V V V
192 NW1V V V
152 OD2 V
153 DCO
196 NPO V
116 N2V V V V V V V
115 P2V V V V V V V
118 VTL_N V V V V V
106 N1V_G V V V V
VTC_N_
104 V
GP
114 N1V V V V V V
112 VTC_N V
117 VTL_P V V V V
105 P1V_G V V V V
VTC_P_
103 V
GP
113 P1V V V V V
11C VTL_P2 V V
199 VTC_P V
197 PP V V V V V
198 NP V V V V V
111 ESD
155 RPO V
156 CO V V V V V V
SRM_HCD SRM_10TT
CAD SRM;0 SRM;1 SRM;2 SRM_RP SRM;21 VTH_N VTH_P DPSRM PRSRM SRM_UHD SRM_HC SRM_HD SRM_LV SRM_8TTP DUMMYOD
P P
Mask
50;0 50;1 50;2 50;5 50;21 67;0 68;0 80;0 80;11 80;12 80;13 80;14 80;15 80;16 80;17 80;18 82
120 OD V V V V V V V V V
119 DNW
191 PW1V V
193 PW2V
192 NW1V V
152 OD2
153 DCO
196 NPO V V
130 PO V V V V V V
116 N2V
115 P2V
118 VTL_N V V
106 N1V_G V V
VTC_N_
104 V
GP
114 N1V V V
112 VTC_N V
117 VTL_P V
105 P1V_G V V
VTC_P_
103 V
GP
113 P1V V V V
11C VTL_P2 V V V
199 VTC_P V
197 PP V
198 NP V
111 ESD
155 RPO
156 CO V V V V V V
DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYPO DUMMYPO
CAD DUMMYPO DCO BJTDMY RH
1 2 3 4 5 6 7 8 11 12 16 1 5
Mask
82;1 82;2 82;3 82;4 82;5 82;6 82;7 82;8 82;11 82;12 82;16 83 83;1 83;5 90;0 110;0 117;0
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2 V
153 DCO V
196 NPO
130 PO V V
116 N2V V V
115 P2V V V
118 VTL_N V V
106 N1V_G V V V
VTC_N_
104 V
GP
114 N1V V V V
112 VTC_N V
117 VTL_P V V
105 P1V_G V V V
VTC_P_
103 V
GP
113 P1V V V V
11C VTL_P2 V
199 VTC_P V
197 PP
198 NP
111 ESD
155 RPO
156 CO V V V V V
SRAMDMY SRAMDMY
CAD SR_ESD VAR POFUSE SRAMDMY ESDIMP
;1 ;4
Mask
121;0 143;0 156;0 186 186;1 186;4 189;0
120 OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
152 OD2
153 DCO
196 NPO V
130 PO
116 N2V V V
115 P2V V V
118 VTL_N V V
106 N1V_G V V
VTC_N_
104
GP
114 N1V V V
112 VTC_N
117 VTL_P V V
105 P1V_G V
VTC_P_
103
GP
113 P1V V
11C VTL_P2
199 VTC_P
197 PP
198 NP V
111 ESD
155 RPO
156 CO V V
Table 3.1.15 N40LPG 3.3V Mask to CAD layer mapping table

CAD DNW NW OD DOD NT_N VTL_N VTL_P OD_12 OD_33 PO DPO SR_DPO PP NP RPO CO CO;11
Mask 1;0 3;0 6;0 6;1 11;0 12;0 13;0 14;1 15;0 17;0 17;1 17;7 25;0 26;0 29;0 30;0 30;11
120 OD V V V
119 DNW V
191 PW1V V V V
193 PW2V V V V
192 NW1V V V V
194 NW2V V V V
152 OD2 V
153 DCO
196 NPO V
118 VTL_N V V V V
106 N1V_G V V V
VTC_N_
104 V
GP
114 N1V V V V V
11N VTC_N2 V V
112 VTC_N V
117 VTL_P V V V V
105 P1V_G V V V
VTC_P_
103 V
GP
113 P1V V V V
11P VTC_P2 V V
199 VTC_P V
197 PP V
198 NP V
111 ESD
124 RPO2 V
155 RPO V V
156 CO V V V V V V
SRM_HCD SRM_10TT
CAD SRM;0 SRM;1 SRM;2 SRM_RP SRM;21 VTH_N VTH_P DPSRM PRSRM SRM_UHD SRM_HC SRM_HD SRM_LV SRM_8TTP DUMMYOD
P P
Mask
50;0 50;1 50;2 50;5 50;21 67;0 68;0 80;0 80;11 80;12 80;13 80;14 80;15 80;16 80;17 80;18 82
119 DNW
191 PW1V V
193 PW2V
192 NW1V V
194 NW2V
152 OD2
153 DCO
196 NPO V V
130 PO V V V V
116 N2V
115 P2V
118 VTL_N V
106 N1V_G V V V
VTC_N_
104 V V
GP
11N VTC_N2 V V V V V
112 VTC_N V V
117 VTL_P V V V V
105 P1V_G V V V
VTC_P_
103 V V
GP
113 P1V V V V V
11P VTC_P2 V V V
199 VTC_P V V
197 PP V
198 NP V
111 ESD
124 RPO2
155 RPO
156 CO V V V V V V V V V
DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYOD DUMMYPO DUMMYPO
CAD DUMMYPO DCO BJTDMY RH
1 2 3 4 5 6 7 8 11 12 16 1 5
Mask
82;1 82;2 82;3 82;4 82;5 82;6 82;7 82;8 82;11 82;12 82;16 83 83;1 83;5 90;0 110;0 117;0
119 DNW
191 PW1V
193 PW2V
192 NW1V
194 NW2V
152 OD2 V
153 DCO V
196 NPO
130 PO V V
116 N2V V V
115 P2V V V
118 VTL_N V
106 N1V_G V V V
VTC_N_
104 V
GP
114 N1V V V V
11N VTC_N2
112 VTC_N V
117 VTL_P V V V
105 P1V_G V V V
VTC_P_
103 V
GP
113 P1V V V V
11P VTC_P2 V
199 VTC_P V
197 PP
198 NP
111 ESD
124 RPO2 V V
155 RPO
156 CO V V V V V
SRAMDMY SRAMDMY
CAD SR_ESD VAR POFUSE SRAMDMY ESDIMP
;1 ;4
Mask
121;0 143;0 156;0 186 186;1 186;4 189;0
120 OD
119 DNW
191 PW1V
193 PW2V
192 NW1V
194 NW2V
152 OD2
153 DCO
196 NPO V
130 PO V
116 N2V V V
115 P2V V V
118 VTL_N
106 N1V_G V V
VTC_N_
104
GP
114 N1V V V
11N VTC_N2
112 VTC_N
117 VTL_P V V
105 P1V_G V V
VTC_P_
103
GP
113 P1V V V
11P VTC_P2
199 VTC_P
197 PP
198 NP V
111 ESD V
124 RPO2 V
155 RPO
156 CO V V
3.2 Metal/Via CAD Layer Information for

Metallization Options
 Due to the complexity of metallization schemes, Table 3.2.1 is the summary of TSMC metal/via CAD
layer number, name, and datatype.
The labels “x”, “y’, “z”, “r”, “u” denote different metal schemes and minimum pitches. “x” using datatype “0”
is first inter-layer metal (Mx) with minimum pitch 0.14μm. “y” using datatype “20” is second inter-layer
metal (My) or 2x top layer metal (My) with minimum pitch 0.28μm. “z” using datatype “40” is top layer metal
(Mz) with minimum pitch 0.8μm. “r” using datatype “80” is top layer metal (Mr) with minimum pitch 1.0 m.
The via datatype is the same as the metal right upon the via.
 For any metal combination, a marker (1+A+B+C) M_AxByCz or (1+A+D)M_AxDr can be used to
represent the metal combination of Mx, My, Mz and Mr.
The marker is interpreted as one layer of M1, A layers of Mx, B layers of My, C layers of Mz and D layers
of Mr. The total metal layer number is 1+A+B+C or 1+A+D. For example, a 7 metal layer process with one
M1 layer, three Mx layers, one My layer and two Mz layers, can be denoted as 7M_3x1y2z.
Table 3.2.1 Metal/Via CAD Layer Number, Name, and Datatype

CAD Datatype
Layer Name
Layer # x y z r u
M1 31 0 - - - -
VIA1 51 0 - - - -
M2 32 0 - - - -
VIA2 52 0 20 40 - -
M3 33 0 20 40 - -
VIA3 53 0 20 40 - 40
M4 34 0 20 40 - 60
VIA4 54 0 20 40 - 40
M5 35 0 20 40 - 60
VIA5 55 0 20 40 - 40
M6 36 0 20 40 - 60
VIA6 56 0 20 40 80 40
M7 37 0 20 40 80 60
VIA7 57 0 20 40 80 40
M8 38 0 20 40 80 60
VIA8 58 - 20 40 80 40
M9 39 - 20 40 80 60
VIA9 59 - 20 40 80 40
M10 40 - 20 40 80 60
The following is the CAD layer/datatype example of a 7 metal layer process with one M1 layer, three Mx layers,
one My layers and two Mz layers, which can be denoted as 7M_3x1y2z. The CAD layer designators are
specified according to the format of GDS layer #; datatype.
CAD layer datatype of Mu metal is “60” (that of dummy Mu layer is “61”), and CAD layer datatype of its
Follow VIAz rule for VIAu design.
Table 3.2.2 CAD Layer/Datatype Example for 7M_3x1y2z

Process CAD
Sequence Layer #/Datatype
Metal-1 31; 0
Via-1 51; 0
Metal-2 32; 0
Via-2 52; 0
Metal-3 33; 0
Via-3 53; 0
Metal-4 34; 0
Via-4 54; 20
Metal-5 35; 20
Via-5 55; 40
Metal-6 36; 40
Via-6 56; 40
Metal-7 37; 40
3.3 Dummy Pattern Fill CAD Layers

The layers in Table 3.3.1 are for planarization (dummy fill) geometry, referring to Table 3.2.1.
Table 3.3.1 Dummy Pattern CAD Layer Number, Name, and Datatype
CAD Dummy Datatype
Layer Name
Layer # X y z r u
DOD 6 1 - - - -
DPO 17 1,7 - - - -
DM1 31 1,7 - - - -
DM2 32 1,7 - - - -
DM3 33 1,7 21 41 - -
DM4 34 1,7 21 41 - 61
DM5 35 1,7 21 41 - 61
DM6 36 1,7 21 41 - 61
DM7 37 1,7 21 41 81 61
DM8 38 1,7 21 41 81 61
DM9 39 - 21 41 81 61
DM10 40 - 21 41 81 61
DVIA1 51 1 - - - -
DVIA2 52 1 - - - -
DVIA3 53 1 - - - -
DVIA4 54 1 - - - -
DVIA5 55 1 - - - -
DVIA6 56 1 - - - -
DVIA7 57 1 - - - -
Table notes:
Metal datatypes 1 (DMx) and 41 (DMz) are the dummy metals without receiving OPC. Datatypes 7 (DMx_O), which will
be generated from TSMC metal dummy utility, will receive OPC same as main metal pattern. Please refer to the
Dummy Metal Rules chapter.
3.4 Special Recognition CAD Layer Summary

Table 3.4.1 lists special layers used in CLN45 design rules and in DRC/LVS command files. These layers are
used for CAD device recognition, and DRC waivers. Some CAD layer designators include a GDS datatype
according to the GDS layer;datatype format.
The column "Tape out required layer" indicates that this layer must be noted on the mask tapeout form to
provide information for mask making.
Table 3.4.1 Special Layer Summary

Tape out
TSMC Default
Special Layer Name Description Associated With DRC required
CAD Layer
layer
General
NW resistor dummy layer for DRC and LVS.
NWROD and NWRSTI
NWDMY 114 The NW region covered by both NWDMY and RPO layers is 
rules
the "NW within OD resistor.” The NW region covered by only
NWDMY is the "NW under STI resistor."
DRC needs NCap_NTN to waive the NMOS capacitors with
same potential.
Ncap_NTN 11;20 NT_N rules 
DRC also flags NCap_NTN and OD outside of the NCap_NTN
in the same NT_N.
DRC dummy layer for 2.5V thick oxide (second gate oxide)
OD25_33 18;3 OD25_33 rules 
overdrive to 3.3V
DRC dummy layer for 2.5V thick oxide (second gate oxide)
OD25_18 18;4 OD25_18 rules 
underdrive to 1.8V
OD18_15 16;4 DRC dummy layer for 1.8V thick oxide underdrive to 1.5V OD18_15 rules 
OD and PO resistor
RH 117;0 For OD, PO resistors  
rules
Dummy layer to exclude unsilicided OD/PO resistor with square
RHDMY1 117;4 RES.R.1 
number (length/width) less than one for non-precision usage
MOS/Junc. Varactor
VAR 143 This layer is for MOS and Junc. type varactors.  
rules
BJTDMY 110;0 Cover BJT device Analog layout rule  
RFDMY 161;0 For RF device DRC/LVS. VAR rules 
LVS dummy layer for SRAM process to exclude OD area and
RODMY 49;0 DRC dummy layer for PO.R.7 exclusion, TSMC internally used Poly layout rule 
layer. Please review with TSMC whenever used.
OD and Poly Resistor
RPDMY 115 Poly/OD resistors dummy layer for LVS and DRC 
Layout Rules
SR_DOD 6;7 SR_DOD (6;7) only can be used for dummy patterns. SR_DOD layout rule  
SR_DPO 17;7 SR_DPO (17;7) only can be used for dummy patterns. Poly layout rule  
HVD_N 91;1 Define N-HVMOS drain side where sustains high voltage HVNMOS rules  
HVD_P 91;2 Define P-HVMOS drain side where sustains high voltage HVPMOS rules  
LOGO 158 LOGO and product labels layer for DRC Logo rules 
M1_LV 31;200~31;214 For the nets of voltage 0~1.4V Metal1 rules 
M1_MV 31;215~31;217 For the nets of voltage 1.5~1.7V Metal1 rules 
M1_HV 31;218 For the nets of voltage 1.8V Metal1 rules 
M1_5V 31;221 For the nets of voltage 5V Metal1 rules 
Mn_LV 3n;200~3n;214 For the nets of voltage 0~1.4V Metalx rules 
Mn_MV 3n;215~3n;217 For the nets of voltage 1.5~1.7V Metalx rules 
Mn_HV 3n;218 For the nets of voltage 1.8V Metalx rules 
Mn_5V 3n;221 For the nets of voltage 5V Metalx rules 
IP 63;63 IP tagging layer
LOWMEDN 255;15 For low metal density region LOWMEDN rules 
Tape out
TSMC Default
CAD Layer
layer
N40LP+
DCO_LPP, ULVT_N,
DCO_LPP 90;1 Dual core OX for ultra low Vt plus devices’ speed boost.  
and ULVT_P rules
DCODMY_SC 90;2 DRC dummy layer for TSMC N40LP+ standard cell recognition DCO_LPP rules 
DCO_LPP and
ULVT_N 151;1 Ultra low Vt N+ implant for N40LP+ Logic  
ULVT_N rules
DCO_LPP and
ULVT_P 152;1 Ultra low Vt P+ implant for N40LP+ Logic  
ULVT_P rules
RF
INDDMY 144;0 Dummy layer for inductor. Inductor rules 
INDDMY_MD 144;42 Dummy layer for medium metal density inductor INDDMY_MD rules 
INDDMY_HD 144;43 Dummy layer for high metal density (logic) inductor INDDMY_HD rules 
TLDMY 116;30 Dummy layer for transmission line Inductor rules 
MOM
MOMDMY_1 155;1 Dummy layer for M1 MOM region MOM rules 
MOMDMY_AP 155;20 Dummy layer for AP MOM region MOM rules 
OD.W.1® , OD.L.2,
NT_N.R.3,
MOMDMY 155;21 Dummy layer for RTMOM SR_DPO.R.4, 
SR_DPO.R.6,
RES.W.1, RES.R.5,
Dummy
ODBLK 150;20 Dummy OD exclusion marker layer DOD rules 
POBLK 150;21 Dummy PO exclusion marker layer DPO rules 
DMxEXCL 150;x Dummy Mx exclusion marker layer and redundant VIA DMx rules 
DVIAxEXCL 150;5x Dummy VIAx exclusion marker layer DVIAx rules 
TCDDMY 165;1 Dummy TCD layer DTCD Rules  
TCDDMY_H 165;4 Dummy layer for Horizonal dummy TCD pattern DTCD Rules  
TCDDMY_V 165;5 Dummy layer for Vertical dummy TCD pattern DTCD Rules  
ICOVL 165;3 Dummy layer for ICOVL monitor pattern ICOVL rules  
OD.L.2, PO.DN.3,
RFIP_DMY 161;1 RFIP Dummy layer for tsmc PDK cell 
RES.R.4, RES.R.5
SRAM
Covers the SRAM cell array. The edge of the SRM layer should
SRM;0 50;0 be aligned to the boundary of the SRAM cell array, which may SRAM rules  
include storage, strapping, and dummy edge cells.
SRM;1 50;1 Define SRAM NMOS cell imp SRAM rules  
SRM;2 50;2 Define SRAM PMOS cell imp SRAM rules  
NPreDOSRM 50;21 SRAM drawing layer for N+ Predoping area SRAM rules  
SRAM DRC Violation waiver layer and OPC. Detail waived rule
list, please refer to the section of SRAM Rules. Before using
SRAMDMY;0 186;0 SRAMDMY, please make sure that TSMC has revised the SRAM rules  
SRAM library to avoid real violations that are automatically
waived by the SRAMDMY marker layer.
SRAMDMY;1 186;1 To identify PG transistor for LVS and PG transistor sizing SRAM rules  
SRAM periphery DRC layer can only be used in the word-line
driver of TSMC SRAM for LP process. This layer is only to
waive CO.S.3 and G.1. And the SRAM and word-line driver
SRAMDMY;4 186;4 must be reviewed by TSMC’s R&D and PE even if customer SRAM rules  
uses TSMC cell.
SRAMDMY;4 (186;4) overlap of SRAMDMY;0 (186;0) is not
allowed.
SRAM periphery DRC layer can only be used in the word-line
driver of TSMC SRAM for N40G process. This layer is only to
waive CO.S.3 and G.1. And the SRAM and word-line driver
SRAMDMY;5 186;5 must be reviewed by TSMC’s R&D and PE even if customer SRAM rules  
uses TSMC cell.
SRAMDMY;5 (186;5) overlap of SRAMDMY;0 (186;0) is not
allowed.
Tape out
TSMC Default
CAD Layer
layer
DPSRM 80;0 To identify TSMC standard offer DP SRAM for transistor sizing SRAM rules  
SRAM_HS 50;7 Identify HS cell SRAM rules  
SRAM bit-cell process logic operation; only in bit-cell not
PRSRM 80;11 SRAM rules  
including strap and edge and dummy cell
SRM_UHD 80;12 To identify UHD SRAM (cover bit-cell, strapping and edge cell) SRAM rules  
SRM_HC 80;13 To identify HC SRAM (cover bit-cell, strapping and edge cell) SRAM rules  
SRM_HD 80;14 To identify HD SRAM (cover bit-cell, strapping and edge cell) SRAM rules  
SRM_LV 80;15 To identify LV SRAM (cover bit-cell, strapping and edge cell) SRAM rules  
To identify HCDP SRAM (cover bit-cell, strapping and edge
SRM_HCDP 80;16 SRAM rules  
cell)
To identify 8T TP SRAM (cover bit-cell, strapping and edge
SRM_8TTP 80;17 SRAM rules  
cell)
To identify 10T TP SRAM (cover bit-cell, strapping and edge
SRM_10TTP 80;18 SRAM rules  
cell)
DUMMYOD1 82;1
~ ~ For SRAM data preparation SRAM rules  
DUMMYOD16 82;16
DUMMYPO1 83;1
~ ~ For SRAM data preparation SRAM rules  
DUMMYPO7 83;7
CO;11 (30;11) is a must for CO mask tape-out in SRAM.
The CO_11 is square CO in bit cell except butted CO.
1. If CO;11 exists, it must cover CO;0
CO;11 30;11 2. CO;11 must be 0.06μm x 0.06μm SRAM rules  
3. CO;11 must be exactly the same as CO;0.
4. CO;11 must be fully covered by SRM (50;0) and
SRAMDMY;0 (186;0)
IP 63;63 IP tagging layer IP tagging layer  
eDRAM
CO2 100;0 Stacked contact for eDRAM process CO2 rule  
PO.R.7, PO.R.9,
RAM1TDMY 160;0 Recognize 1TRAM region SRAM.R.15, 
SRAM.R.21
ROM

ROM 50;6 This layer is required for ROM rule checks in ROM devices. ROM rule 
(for N40G )
Latch-Up
LUPWDMY is a drawn layer to waive latch up rules for verified
LUPWDMY 255;1 Latch-Up rule 
circuit.
VDDDMY 255;4 Dummy Layer for Power(Vdd) PAD Latch-Up rule 
VSSDMY 255;5 Dummy Layer for Power(Vss) PAD Latch-Up rule 
RES200 255;9 Recognize resistor over 200ohm Latch-Up rule 
LUPWDMY_2 255;18 Area Array IO LUP rules check Latch-Up rule 
M1(pin) 131;0 Metal1 pin for text layer Latch-Up rule 
ESD
It is required to cover all ESD MOS OD regions that are
SDI 122 ESD guidelines 
connected to the pads.
ESD guidelines
ESDIMP 189;0 This drawn layer is required for ESD implant. and  
ESDIMP rule
SR (special rule) exclusion marker layer for N40G ESD device
SR_ESD 121;0 SR_ESD rules  
only
HIA_DUMMY 168;0 Dummy layer for high current diode HIA_DIO guideline 
Fuse
POFUSE 156;0 Poly fuse implant layer, cover all poly fuse regions. PO rule  
Tape out
TSMC Default
CAD Layer
layer
DFM
DFM redundant VIA
DFMEXCL 153;20 Blockage layer for all DFM redundant VIA utility 
utility
DFM redundant VIA
COEXCL 153;0 Blockage layer for CO redundant VIA utility 
utility
153;x, DFM redundant VIA
VIAxEXCL Blockage layer for redundant VIA utility 
x=1-9, utility
RRuleRequire 182;1 DRC dummy layer for DFM Action-Required recommendation DFM Action-Required 
RRuleRecommend 182;2 DRC dummy layer for DFM Recommended recommendation DFM Recommended 
Rules and
DRC dummy layer for DFM Recommended Dimension for
RRuleAnalog 182;3 Recommendations for 
Analog Designs
Analog Designs
dummy layer for excluding DFM action-required
excludeRRuleRequire 182;11 DFM Action-Required 
recommnedation check
excludeRRuleRecom dummy layer for excluding DFM recommendaed
182;12 DFM Recommended 
mended recommendation check
Rules and
dummy layer for excluding Rules and Recommendations check
excludeRRuleAnalog 182;13 Recommendations for 
for Analog Designs
Analog Designs
SENDMY 255;8 DRC recognition layer for sensitive circuit DFM Recommended 
Package and interconnect
DMxEXCL 150;x Dummy Mx exclusion within oxide slot of MT region DMx rules 
WBDMY 157;0 Design rule waiver within CUP pad region CUP rules 
SEALRING 162;0 Sealring region Sealring rules 
SEALRING_DB 162;1 Scribe line dummy bar region Sealring rules 
SEALRING_ALL 162;2 Sealring region, SLDB, CSR, and assembly isolation Sealring rules 
It is required for sealring structure and DFM VIA enhancer. It’s
LMARK 109;0 Metal rules 
also a DRC recognition layer of L-mark for DRC purpose.
CSRDMY 166;0 Chip corner stress relief pattern dummy layer Sealring rules 
CSRBIB1DMY 166;1 Sealring region Sealring rules 
CSRBIB2DMY 166;2 Sealring region Sealring rules 
CDUDMY 165;0 DRC dummy layer to recognize CDU pattern Sealring rules 
3.5 Device Truth Tables

This section contains the device truth tables for:
 CLN45/CLN40 CMOS Logic Low Power (LP) technology
 CLN40 CMOS Logic Low Power Plus (LP+) technology
 CLN45/CLN40 CMOS Logic LP-based Triple Gate Oxide (LPG) technology
 CLN45 CMOS Logic General Purpose Superb (N40G) technology
 CLN45/CLN40 MOM
 CMN45/CMN40 Inductor
The following provides a legend for the following device truth table.
Table 3.5.1.1 Device Truth Table for N45LP/N40LP
Table 3.5.1.2 Device Truth Table for N40LP 5V HVMOS_18
Table 3.5.2 Device Truth Table for N40LP Plus (N40LP+): 1.1V Core and 2.5V I/O DesignTable 3.5.3 Device
Truth Table for N45LPG
Table 3.5.4 Device Truth Table for N40LPG
Table 3.5.5 Device Truth Table for N40G (=N45GS)
Table 3.5.6 Device Truth Table for MOM
Table 3.5.7 Device Truth Table for Inductor
0 Does not cover the structures
1 Covers or matches the structures
* Don’t care
3.5.1 N45/N40 Low Power (LP): 1.1V Core Design

Table 3.5.1.1 Device Truth Table for N45LP/N40LP
Design Levels Special Layer
RHDMY1
BJTDMY
DIODMY
NWDMY
Device SPICE Name
RPDMY
OD_18
HVD_N
HVD_P
VTH_N
VTH_P
OD_25
VTL_N
VTL_P
POLY
NT_N
DNW
RPO
VAR
NW
OD
RH
N+
P+
NMOS (1.1V) nch * 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
PMOS (1.1V) pch * 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
High Vt NMOS (1.1V) nch_hvt * 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
High Vt PMOS (1.1V) pch_hvt * 1 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Low Vt NMOS (1.1V) nch_lvt * 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Low Vt PMOS (1.1V) pch_lvt * 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0
I/O NMOS (1.8V) nch_18 * 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
I/O PMOS (1.8V) pch_18 * 1 1 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
I/O NMOS (2.5V) nch_25 * 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
I/O PMOS (2.5V) pch_25 * 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Native NMOS (1.1V) nch_na 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Native I/O NMOS
nch_na18 0 1 0 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
(1.8V)
Native I/O NMOS
nch_na25 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
(2.5V)
HV NMOS (5V) nch_hv25_snw 0 1 0 0 1 0 1 0 0 0 0 1 0 0#a 0 0 0 0 0 0 0 1 0
HV PMOS (5V) pch_hv25_spw 1 1 1 0 1 0 1 0 0 0 0 0 1 0#a 0 0 0 0 0 0 0 0 1
N+/PW Junction Diode ndio * 1 0 0 * * 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
P+/NW Junction Diode pdio * 1 1 0 * * 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
N+/PW Junction Diode
ndio_hvt * 1 0 0 * * 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
w/ High Vt
N-Well Psub Diode nwdio 0 1 1 0 * * 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
P-Well Contact * 1 0 0 * * 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
N-Well Contact * 1 1 0 * * 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Silicided N+ PO
rnpoly * 0 * 0 * * 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0
Resistor
Silicided P+ PO
rppoly * 0 * 0 * * 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0
Resistor
Silicided N+ OD
rnod * 1 0 0 * * 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0
Resistor
Silicided P+ OD
rpod * 1 1 0 * * 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0
Resistor
Unsilicided N+ PO
rnpolywo * 0 * 0 * * 1 0 0 0 0 1 0 1 1 * 0 0 0 0 1 0 0
Resistor
Unsilicided P+ PO
rppolywo * 0 * 0 * * 1 0 0 0 0 0 1 1 1 * 0 0 0 0 1 0 0
Resistor
Unsilicided N+ OD
rnodwo * 1 0 0 * * 0 0 0 0 0 1 0 1 1 * 0 0 0 0 1 0 0
Resistor
Unsilicided P+ OD
rpodwo * 1 1 0 * * 0 0 0 0 0 0 1 1 1 * 0 0 0 0 1 0 0
Resistor
NW Resistor (under
rnwsti 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
STI)
NW Resistor (under
rnwod 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0
OD)
2
Vertical PNP pnp2 (2x2μm )
(P+/NW/Psub) pnp5 (5x5μm 2) 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0
(constant emitter size) pnp10 (10x10μm 2)
Vertical NPN npn2 (2x2μm 2)
(N+/PW/DNW) npn5 (5x5μm 2) 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0
(constant emitter size) npn10 (10x10μm 2)
1.1V Varactor nmoscap * 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
1.8V Varactor nmoscap_18 * 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
2.5V Varactor nmoscap_25 * 1 1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
#a: Both HVNMOS_25 and HVPMOS_25 require RPO layer, but customers don't have to draw RPO (29;0) CAD layer for HVNMOS_25
or HVPMOS_25. TSMC will use logic operation to generate the RPO pattern for HVNMOS_25 and HVPMOS_25 during mask
masking, so customers must tape out RPO (155) mask when using HVNMOS_25 or HVPMOS_25.
Table 3.5.1.2 Device Truth Table for N40LP 5V HVMOS_18

BJTDMY
DIODMY
NWDMY
Device SPICE Name
RPDMY
HVD_N
HVD_P
VTH_N
VTH_P
OD_25
OD_18
VTL_N
VTL_P
POLY
NT_N
DNW
RPO
VAR
NW
OD
RH
N+
P+
HV NMOS (5V) nch_hv18_snw 0 1 0 0 0 1 1 0 0 0 0 1 0 0#a 0 0 0 0 0 0 1 0
HV PMOS (5V) pch_hv18_spw 1 1 1 0 0 1 1 0 0 0 0#b 0 1 0#a 0 0 0 0 0 0 0 1
#b: HVPMOS_18 requires VTL_P layer, but customers don't have to draw VTL_P (13;0) CAD layer for HVPMOS_18. TSMC will use
logic operation to generate the VTL_P pattern for HVPMOS_18 during mask masking, so customers must tape out VTL_P (117)
mask when using HVPMOS_18.
3.5.2 N40 Low Power Plus (N40LP+): 1.1V Core and

2.5V I/O Design
Table 3.5.2 Device Truth Table for N40LP Plus (N40LP+): 1.1V Core and 2.5V I/O Design
DCO_LPP
BJTDMY
DIODMY
NWDMY
ULVT_N
ULVT_P
Device SPICE Name
RPDMY
HVD_N
HVD_P
VTH_N
VTH_P
OD_25
VTL_N
VTL_P
POLY
NT_N
DNW
RPO
VAR
NW
OD
RH
N+
P+
NMOS (1.1V) nch * 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
PMOS (1.1V) pch * 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
High Vt NMOS (1.1V) nch_hvt * 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
High Vt PMOS (1.1V) pch_hvt * 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Low Vt NMOS (1.1V) nch_lvt * 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Low Vt PMOS (1.1V) pch_lvt * 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0
Ultra Low Vt Plus
nch_lppulvt * 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0
NMOS (1.1V)
Ultra Low Vt Plus
pch_lppulvt * 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
PMOS (1.1V)
I/O NMOS (2.5V) nch_25 * 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
I/O PMOS (2.5V) pch_25 * 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Native NMOS (1.1V) nch_na 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Native I/O NMOS
nch_na25 0 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
(2.5V)
HV NMOS (5V) nch_hv25_snw 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0#a 0 0 0 0 0 0 1 0
HV PMOS (5V) pch_hv25_spw 1 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0#a 0 0 0 0 0 0 0 1
N+/PW Junction Diode ndio * 1 * 0 0 * 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
P+/NW Junction Diode pdio * 1 * 1 0 * 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0
Ultra Low Vt Plus
ndio_lppulvt * 1 1 0 0 * 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0
N+/PW Junction Diode
Ultra Low Vt Plus
pdio_lppulvt * 1 1 1 0 * 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0
P+/NW Junction Diode
N-Well Psub Diode nwdio 0 1 0 1 0 * 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
P-Well Contact * 1 0 0 0 * 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
N-Well Contact * 1 0 1 0 * 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Silicided N+ PO
rnpoly * 0 0 * 0 * 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0
Resistor
Silicided P+ PO
rppoly * 0 0 * 0 * 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0
Resistor
Silicided N+ OD
rnod * 1 0 0 0 * 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0
Resistor
Silicided P+ OD
rpod * 1 0 1 0 * 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0
Resistor
Unsilicided N+ PO
rnpolywo * 0 0 * 0 * 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0
Resistor
Unsilicided P+ PO
rppolywo * 0 0 * 0 * 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0
Resistor
Unsilicided N+ OD
rnodwo * 1 0 0 0 * 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0
Resistor
Unsilicided P+ OD
rpodwo * 1 0 1 0 * 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0
Resistor
NW Resistor (under
rnwsti 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0
STI)
NW Resistor (under
rnwod 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0
OD)
pnp2 (2x2μm2)
Vertical PNP
pnp5 (5x5μm2)
(P+/NW/Psub) 0 1 * 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0
pnp10
(constant emitter size)
(10x10μm2)
npn2 (2x2μm2)
Vertical NPN
npn5 (5x5μm2)
(N+/PW/DNW) 1 1 * 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0
npn10
(10x10μm2)
1.1V Varactor nmoscap * 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
2.5V Varactor nmoscap_25 * 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
3.5.3 N45LPG/N40LPG: 1.1V/0.9V Core Design

Table 3.5.3.1 Device Truth Table for N45LPG
BJTDMY
DIODMY
NWDMY
RPDMY
Device SPICE Name
OD_18
VTL_N
VTL_P
POLY
NT_N
DNW
DCO
RPO
VAR
NW
OD
RH
N+
P+
NMOS (1.1V) nch * 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0
PMOS (1.1V) pch * 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0
Low Vt NMOS (1.1V) nch_lvt * 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0
Low Vt PMOS (1.1V) pch_lvt * 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0
NMOS (0.9V) nch_lpg * 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0
PMOS (0.9V) pch_lpg * 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0
Low Vt NMOS (0.9V) nch_lpglvt * 1 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0
Low Vt PMOS (0.9V) pch_lpglvt * 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0
I/O NMOS (1.8V) nch_18 * 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0
I/O PMOS (1.8V) pch_18 * 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0
N+/PW Junction Diode (1.1V) ndio * 1 0 0 * 0 0 0 0 1 0 0 0 0 0 0 1 0
P+/NW Junction Diode (1.1V) pdio * 1 1 0 * 0 0 0 0 0 1 0 0 0 0 0 1 0
N+/PW Junction Diode (0.9V) ndio_lpg * 1 0 0 * 1 0 0 0 1 0 0 0 0 0 0 1 0
P+/NW Junction Diode (0.9V) pdio_lpg * 1 1 0 * 1 0 0 0 0 1 0 0 0 0 0 1 0
N-Well Psub Diode nwdio 0 1 1 0 * 0 0 0 0 1 0 0 0 0 0 0 1 0
P-Well Contact * 1 0 0 * 0 0 0 0 0 1 0 0 0 0 0 0 0
N-Well Contact * 1 1 0 * 0 0 0 0 1 0 0 0 0 0 0 0 0
Silicided N+ PO Resistor rnpoly * 0 * 0 * 0 1 0 0 1 0 0 1 0 0 0 0 1
Silicided P+ PO Resistor rppoly * 0 * 0 * 0 1 0 0 0 1 0 1 0 0 0 0 1
Silicided N+ OD Resistor rnod * 1 0 0 * 0 0 0 0 1 0 0 1 0 0 0 0 1
Silicided P+ OD Resistor rpod * 1 1 0 * 0 0 0 0 0 1 0 1 0 0 0 0 1
Unsilicided N+ PO Resistor rnpolywo * 0 * 0 * 0 1 0 0 1 0 1 1 0 0 0 0 1
Unsilicided P+ PO Resistor rppolywo * 0 * 0 * 0 1 0 0 0 1 1 1 0 0 0 0 1
Unsilicided N+ OD Resistor rnodwo * 1 0 0 * 0 0 0 0 1 0 1 1 0 0 0 0 1
Unsilicided P+ OD Resistor rpodwo * 1 1 0 * 0 0 0 0 0 1 1 1 0 0 0 0 1
NW Resistor (under STI) rnwsti 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0
NW Resistor (under OD) rnwod 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0
pnp2 (2x2μm2)
Vertical PNP (P+/NW/Psub)
pnp5 (5x5μm2) 0 1 1 0 0 * 0 0 0 1 1 1 0 0 0 1 0 0
pnp10 (10x10μm2)
npn2 (2x2μm2)
Vertical NPN (N+/PW/DNW)
npn5 (5x5μm2) 1 1 1 0 0 * 0 0 0 1 1 1 0 0 0 1 0 0
npn10 (10x10μm2)
0.9V Varactor nmoscap_lpg 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0
1.1V Varactor nmoscap 0 1 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0
1.8V Varactor nmoscap_18 0 1 1 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0
Table 3.5.3.2 Device Truth Table for N40LPG

Special Layer
Design Levels
BJTDMY
Device SPICE Name
DIODMY
NWDMY
RPDMY
VTH_N
VTH_P
OD_33
VTL_N
VTL_P
POLY
NT_N
DNW
DCO
RPO
VAR
NW
OD
RH
N+
P+
NMOS (1.1V) nch * 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
PMOS (1.1V) pch * 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0
High Vt NMOS (1.1V) nch_hvt * 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0
High Vt PMOS (1.1V) pch_hvt * 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0
NMOS (0.9V) nch_lpg * 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0
PMOS (0.9V) pch_lpg * 1 1 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0
Low Vt NMOS (0.9V) nch_lpglvt * 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0
Low Vt PMOS (0.9V) pch_lpglvt * 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0
I/O NMOS (3.3V) nch_33 * 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
I/O PMOS (3.3V) pch_33 * 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0
Native NMOS (1.1V) nch_na 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
Native I/O NMOS (3.3V) nch_na33 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
N+/PW Junction Diode (1.1V) ndio * 1 0 0 * 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0
P+/NW Junction Diode (1.1V) pdio * 1 1 0 * 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0
N+/PW Junction Diode (0.9V) ndio_lpg * 1 0 0 * 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0
P+/NW Junction Diode (0.9V) pdio_lpg * 1 1 0 * 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0
N-Well Psub Diode nwdio 0 1 1 0 * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
P-Well Contact * 1 0 0 * 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
N-Well Contact * 1 1 0 * 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Silicided N+ PO Resistor rnpoly * 0 * 0 * 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1
Silicided P+ PO Resistor rppoly * 0 * 0 * 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1
Silicided N+ OD Resistor rnod * 1 0 0 * 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1
Silicided P+ OD Resistor rpod * 1 1 0 * 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1
Unsilicided N+ PO Resistor rnpolywo * 0 * 0 * 0 1 0 0 0 0 1 0 1 1 0 0 0 0 1
Unsilicided P+ PO Resistor rppolywo * 0 * 0 * 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1
Unsilicided N+ OD Resistor rnodwo * 1 0 0 * 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1
Unsilicided P+ OD Resistor rpodwo * 1 1 0 * 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1
NW Resistor (under STI) rnwsti 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0
NW Resistor (under OD) rnwod 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0
pnp2 (2x2μm2)
Vertical PNP (P+/NW/Psub)
pnp5 (5x5μm2) 0 1 1 0 0 * 0 0 0 0 0 1 1 1 0 0 0 1 0 0
pnp10 (10x10μm2)
npn2 (2x2μm2)
Vertical NPN (N+/PW/DNW)
npn5 (5x5μm2) 1 1 1 0 0 * 0 0 0 0 0 1 1 1 0 0 0 1 0 0
npn10 (10x10μm2)
0.9V Varactor nmoscap 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0
1.1V Varactor nmoscap 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0
3.3V Varactor nmoscap_33 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0
3.5.4 N40G (N45GS) General Purpose Superb: 0.9V

Core Design
Table 3.5.4 Device Truth Table for N40G (N45GS)
BJTDMY
Device SPICE Name
DIODMY
SR_ESD
NWDMY
RPDMY
VTH_N
VTH_P
OD_25
OD_18
OD_12
VTL_N
VTL_P
POLY
NT_N
DNW
RPO
VAR
NW
SDI
OD
RH
N+
P+
NMOS (0.9V) nch * 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
NMOS (1.2V) nch_12 * 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
PMOS (0.9V) pch * 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
PMOS (1.2V) pch_12 * 1 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
High Vt NMOS (0.9V) nch_hvt * 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
High Vt PMOS (0.9V) pch_hvt * 1 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0
Low Vt NMOS (0.9V) nch_lvt * 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0
Low Vt PMOS (0.9V) pch_lvt * 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
ESD NMOS (0.9V) nch_hia 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1
I/O NMOS (1.8V) nch_18 * 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
I/O PMOS (1.8V) pch_18 * 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
I/O NMOS (2.5V) nch_25 * 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
I/O PMOS (2.5V) pch_25 * 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Native NMOS (0.9V) nch_na 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Native NMOS (1.2V) nch_na12 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Native I/O NMOS (1.8V) nch_na18 0 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Native I/O NMOS (2.5V) nch_na25 0 1 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
N+/PW Junction Diode NDIO * 1 0 0 * * * 0 0 0 0 0 1 0 0 * 0 0 0 1 0 0 0
P+/NW Junction Diode PDIO * 1 1 0 * * * 0 0 0 0 0 0 1 0 * 0 0 0 1 0 0 0
N-Well Psub Diode nwdio 0 1 1 0 * * * 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
P-Well Contact * 1 0 0 * * * 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
N-Well Contact * 1 1 0 * * * 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Silicided N+ PO Resistor rnpoly * 0 * 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0
Silicided P+ PO Resistor rppoly * 0 * 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0
Silicided N+ OD Resistor rnod * 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0
Silicided P+ OD Resistor rpod * 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0
Unsilicided N+ PO
rnpolywo * 0 * 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0
Resistor
Unsilicided P+ PO
rppolywo * 0 * 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0
Resistor
Unsilicided N+ OD
rnodwo * 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0
Resistor
Unsilicided P+ OD
rpodwo * 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0
Resistor
NW Resistor (under STI) rnwsti 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0
NW Resistor (under OD) rnwod 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0
Vertical PNP pnp2 (2x2 μm2)
(P+/NW/Psub) pnp5 (5x5 μm2) 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0
(constant emitter size) pnp10 (10x10 μm2)
Vertical NPN npn2 (2x2 μm2)
(N+/PW/DNW) npn5 (5x5 μm2) 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0
(constant emitter size) npn10 (10x10 μm2)
0.9V NMOS Varactor nmoscap * 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
0.9V PMOS Varactor pmoscap * 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0
1.2V NMOS Varactor nmoscap_12 * 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
1.8V NMOS Varactor nmoscap_18 * 1 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
1.8V PMOS Varactor for
pmoscap_18 * 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
PMOS
2.5V NMOS Varactor
(including 2.5V overdrive nmoscap_25 * 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0
3.3V)
2.5V PMOS Varactor
(including 2.5V overdrive pmoscap_25 * 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0
3.3V)
3.5.5 MOM
Table 3.5.5 Device Truth Table for MOM
Design Levels
SR_DPO
OD_18
OD_25
OD_33
POLY
NT_N
Node Device DNW
VIA5
VIA1
VIA2
VIA3
VIA4
VIA6
VIA7
VIA8
VIA9
DOD
RPO
M10
NW
PW
CO
OD
RV
AP
M1
M2
M3
M4
M5
M6
M7
M8
M9
N+
P+
N45/N40 crtmom 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_wo, NW 0 1 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_wo, PW 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_wo, NTN 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_rf 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_wo_rf, NW 0 1 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_wo_rf, PW 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_wo_rf, NTN 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_mx 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_wo_mx, NW 0 1 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_wo_mx, PW 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_wo_mx, NTN 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N45/N40 crtmom_2t * * * * * * * * * * * * * * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * * * * * *
N40 cfmom 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_wo, NW 0 1 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_wo, PW 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_wo, NTN 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_rf 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_wo_rf, NW 0 1 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_wo_rf, PW 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_wo_rf, NTN 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_mx 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_wo_mx, NW 0 1 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_wo_mx, PW 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_wo_mx, NTN 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
N40 cfmom_2t * * * * * * * * * * * * * * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * * * * * *
Special Layers
DM10EXCL(150;10)
MOMDMY(155;100)
MOMDMY_1(155;1)
MOMDMY_2(155;2)
MOMDMY_3(155;3)
MOMDMY_4(155;4)
MOMDMY_5(155;5)
MOMDMY_6(155;6)
MOMDMY_7(155;7)
MOMDMY_8(155;8)
MOMDMY(155;21)
MOMDMY(155;22)
MOMDMY(155;23)
MOMDMY(155;24)
MOMDMY(155;25)
MOMDMY(155;27)
MOMDMY(155;31)
MOMDMY(155;32)
MOMDMY(155;33)
DM1EXCL(150;1)
DM2EXCL(150;2)
DM3EXCL(150;3)
DM4EXCL(150;4)
DM5EXCL(150;5)
DM6EXCL(150;6)
DM7EXCL(150;7)
DM8EXCL(150;8)
DM9EXCL(150;9)
MOMDMY(155;0)
ODBLK(150;20)
POBLK(150;21)
RFDMY(161;0)
Node Device
N45/N40 crtmom 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_wo, NW 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_wo, PW 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_wo, NTN 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_rf 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_wo_rf, NW 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_wo_rf, PW 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_wo_rf, NTN 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_mx 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_wo_mx, NW 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_wo_mx, PW 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_wo_mx, NTN 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 crtmom_2t 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_wo, NW 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_wo, PW 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_wo, NTN 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_rf 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_wo_rf, NW 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_wo_rf, PW 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_wo_rf, NTN 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_mx 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_wo_mx, NW 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_wo_mx, PW 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_wo_mx, NTN 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
N40 cfmom_2t 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Note:
1. MOMDMY(155;0) dummy layer RTMOM device
2. MOMDMY(155;100) dummy layer FMOM device
3. MOMDMY(155;21) dummy layer to waive violations in MOM region
4. MOMDMY(155;22) denotes MX MOM recogition.
5. MOMDMY(155;23) to recognize pin plus 1, minus 1 for MX MOM.
6. MOMDMY(155;24) to recognize pin plus 2, minus 2 for MX MOM.
7. MOMDMY(155;25) to recognize for cross-coupled mom pin.
8. MOMDMY(155;27) to recognize for 2T BB MOM
9. MOMDMY(155;31) dummy layer for MOM devices wi NW shield
10. MOMDMY(155;32) dummy layer for MOM devices wi PW shield
11. MOMDMY(155;33) dummy layer for MOM devices wi NTN shield
12. RFDMY(161;0) dummy layer for RF devices.
13. DOD is an option pattern layer to meet the requirement of the OD density under MOM.
3.5.6 Inductor
Table 3.5.6 Device Truth Table for inductor
Design Levels
POLY
NT_N
DNW
VIA1
VIA2
VIA3
VIA4
VIA5
VIA6
VIA7
VIA8
VIA9
Node Device
RPO
M10
NW
CO
OD
RV
AP
M1
M2
M3
M4
M5
M6
M7
M8
M9
N+
P+
N45/N40 spiral_std_mz_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * 1 1
N45/N40 spiral_sym_mz_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * 1 1
N45/N40 spiral_sym_ct_mz_a_x 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 * * 1 1
N45/N40 spiral_std_mza_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * 1 1
N45/N40 spiral_sym_mza_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * 1 1
N45/N40 spiral_sym_ct_mza_a_x 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 * * 1 1
N45/N40 spiral_sym_mz_ax 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 * * 1 1
N45/N40 spiral_sym_ct_mz_ax_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 * * 1 1
N45/N40 spiral_std_m2za_za 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1
N45/N40 spiral_sym_m2za_z 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1
N45/N40 spiral_sym_ct_m2za_z_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1
N45/N40 spiral_std_mu_x 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 * * 0 0
N45/N40 spiral_sym_mu_x 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 * * 0 0
N45/N40 spiral_sym_ct_mu_x_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 * * 1 1
N45/N40 spiral_std_mu_z 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0
N45/N40 spiral_sym_mu_z 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0
N45/N40 spiral_sym_ct_mu_z_x 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0
N40 spiral_sym_ct_mu_z_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1
N40 spiral_std_mu_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * 1 1
N40 spiral_sym_mu_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * 1 1
N40 spiral_sym_ct_mu_a_a 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * 1 1
N40 spiral_sym_ct_mu_a_x 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 * * 0 0
Special Layer
INDDMY(DMYDIS, 144;31)
RFIP_DMY (161;1)
INDDMY(144;30)
INDDMY(144;32)
INDDMY(144;33)
INDDMY(144;34)
INDDMY(144;35)
INDDMY(144;36)
INDDMY(144;37)
INDDMY(144;38)
INDDMY(144;39)
INDDMY(144;0)
Node Device
N45/N40 spiral_std_mz_a 1 1 1 1 1 1 1 1 1 1 0 0
N45/N40 spiral_sym_mz_a 1 1 1 1 1 1 1 1 1 1 0 1
N45/N40 spiral_sym_ct_mz_a_x 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 spiral_std_mza_a 1 1 1 1 1 1 1 1 1 1 0 0
N45/N40 spiral_sym_mza_a 1 1 1 1 1 1 1 1 1 1 0 1
N45/N40 spiral_sym_ct_mza_a_x 1 1 1 1 1 1 1 1 1 1 1 1
N45/N40 spiral_sym_mz_ax 1 1 1 1 1 1 1 1 1 1 0 1
N45/N40 spiral_sym_ct_mz_ax_a 1 1 1 1 1 1 1 1 1 1 0 1
N45/N40 spiral_std_m2za_za 1 1 1 1 1 1 1 1 1 1 0 0
N45/N40 spiral_sym_m2za_z 1 1 1 1 1 1 1 1 1 1 0 1
N45/N40 spiral_sym_ct_m2za_z_a 1 1 1 1 1 1 1 1 1 1 0 1
N45/N40 spiral_std_mu_x 1 1 1 1 1 1 1 1 1 1 0 0
N45/N40 spiral_sym_mu_x 1 1 1 1 1 1 1 1 1 1 0 1
N45/N40 spiral_sym_ct_mu_x_a 1 1 1 1 1 1 1 1 1 1 0 1
N45/N40 spiral_std_mu_z 1 1 1 1 1 1 1 1 1 1 0 0
N45/N40 spiral_sym_mu_z 1 1 1 1 1 1 1 1 1 1 0 1
N45/N40 spiral_sym_ct_mu_z_x 1 1 1 1 1 1 1 1 1 1 1 1
N40 spiral_sym_ct_mu_z_a 1 1 1 1 1 1 1 1 1 1 0 1
N40 spiral_std_mu_a 1 1 1 1 1 1 1 1 1 1 0 0
N40 spiral_sym_mu_a 1 1 1 1 1 1 1 1 1 1 0 1
N40 spiral_sym_ct_mu_a_a 1 1 1 1 1 1 1 1 1 1 0 1
N40 spiral_sym_ct_mu_a_x 1 1 1 1 1 1 1 1 1 1 1 1
Note:
1. The inductor with most metal layers scheme (1P10M for two top metal layers scheme and 1P9M for one top metal layer
scheme) is illustrated in the truth table
2. RFIP_DMY (161;1, drawing1) identifies the tsmc msrf specific (tsmc msrf process design kit) device structure.
3. INDDMY(144;0, drawing) identifies the Metal/OD/PO dummy blocked low pattern density inductor.
4. INDDMY(144;30, rad) identifies the inductor inner radius.
5. INDDMY(144;31, dummy1) identifies the distance from spiral outer edge to [guard-ring outer edge + 2.5um]
6. INDDMY(144;32, dummy2) identifies the inductor turn numbers.
7. INDDMY(144;33, dummy3) identifies the inductor coil width at Port2.
8. INDDMY(144;34, dummy4) identifies the inductor center-tap port region.
9. INDDMY(144;35, dummy5) identifies the inductor coil width.
10. INDDMY(144;36, dummy6) identifies the inductor coil spacing.
11. INDDMY(144;37, dummy7) identifies the inductor type by text label.
12. INDDMY(144;38, dummy8) identifies the stacked Mx layer number(s) of inductor center-tap .
13. INDDMY(144;39) identifies the ratio of inductor center-tap width over coil width
3.6 Mask Requirement for Device options

(High/STD/Low VT/Ultra Low VT Plus)
Table 3.6.1 Mask Requirement for N45LP/N40LP
Mask Requirements
Device Well LDD
3 masks 4 masks
STD Vt + I/O (DGO)
PW1V/2V, NW1V N1V/2V, P1V/2V
3 masks 6 masks
STD Vt + Low Vt + I/O
PW1V/2V, NW1V N1V/2V, P1V/2V, VTL_N/P
3 masks 6 masks
STD Vt + High Vt + I/O
PW1V/2V, NW1V N1V/2V, P1V/2V, VTH_N/P
3 masks 8 masks
STD Vt + Low Vt + High Vt + I/O
PW1V/2V, NW1V N1V/2V, P1V/2V, VTL_N/P, VTH_N/P
Table 3.6.2 Mask Requirement for N40LP Plus (N40LP+): 1.1V Core and 2.5V I/O Design
Mask Requirements
Device Well LDD
8 masks
STD Vt + Low Vt + Ultra Low Vt Plus‡ 3 masks
N1V/2V, P1V/2V, VTL_N/P,
+ I/O PW1V/2V, NW1V
ULVT_N/P
8 masks
STD Vt + High Vt + Ultra Low Vt Plus‡ 3 masks
N1V/2V, P1V/2V, VTH_N/P,
+ I/O PW1V/2V, NW1V
ULVT_N/P
10 masks
STD Vt + Low Vt + High Vt + Ultra 3 masks
N1V/2V, P1V/2V, VTL_N/P,
Low Vt Plus‡ + I/O PW1V/2V, NW1V
VTH_N/P, ULVT_N/P
‡: DCO_LPP mask (Mask code: 153) is also required for Ultra Low Vt Plus devices at N40LP+.
Table 3.6.3 Mask Requirement for N45LPG/N40LPG

Mask Requirements
Device Well LDD
4 masks 6 masks
STD Vt + I/O (DGO)
PW1V/2V, NW1V/2V N1V/N1V_G/N2V, P1V/P1V_G/P2V
8 masks
4 masks
STD Vt + Low Vt + I/O N1V/N1V_G/N2V, P1V/P1V_G/P2V,
PW1V/2V, NW1V/2V
VTL_N/P
Table 3.6.4 Mask Requirement for N40G (N45GS)

Mask Requirements
Device Well LDD
4 masks 4 masks
STD Vt + I/O (DGO)
PW1V/2V, NW1V/2V N1V/2V, P1V/2V
4 masks 6 masks
STD Vt + Low Vt + I/O
PW1V/2V, NW1V/2V N1V/2V, P1V/2V, VTL_N/P
6 masks 4 masks
STD Vt + High Vt + I/O
PW1V/2V, NW1V/2V,VTH_N/P N1V/2V, P1V/2V
6 masks 6 masks
STD Vt + Low Vt + High Vt + I/O
PW1V/2V, NW1V/2V, VTH_N/P N1V/2V, P1V/2V, VTL_N/P
3.7 Design Geometry Restrictions

3.7.1 Design Grid Rules
Table 3.7.1
Rule No. Description Label Op. Rule
The design grid must be an integer multiple of 0.005μm except PO and CO layers inside the layer 186;5 for
GS/GL and 186;4 for LP/LPG
0.005μm deviation is allowed for 45-degree polygon dimensions.
G.1 For circuits of 110% size-up part (40LP) can allow 1nm design grid. This is uncheckable. Please refer to the 0.005
chapter “N40LP Design Information”.
(Except UBM, CBD[in UBM], CB2_FC[in UBM], PM[in UBM], AP[in UBM], CB2_WB/CB2_FC[in Cu_PPI of
WLCSP process], PM1/Cu_PPI[in WLCSP process], PM2[in UBM for WLCSP process] region)
Shapes with acute angles between line segments are not allowed. (Except UBM, CBD[in UBM], CB2_FC[in UBM],
G.2 PM[in UBM], AP[in UBM], CB2_WB/CB2_FC[in Cu_PPI of WLCSP process], PM1/Cu_PPI[in WLCSP process],
PM2[in UBM for WLCSP process] region)
Only shapes that are orthogonal or on a 45-degree angle are allowed.
G.3 (Except UBM, CBD[in UBM], CB2_FC[in UBM], PM[in UBM], AP[in UBM], CB2_WB/CB2_FC[in Cu_PPI of
WLCSP process], PM1/Cu_PPI[in WLCSP process], PM2[in UBM for WLCSP process] region)
For the OPC layers, any edge of length < 1.0 x minimum width cannot have another adjacent edge of length < 1.0
x minimum width. (Figure 3.7.1)
G.4
The OPC layers: OD (including SR_DOD), PO (including SR_DPO), VTL_N, VTL_P, VTH_N, VTH_P, ULVT_N,
ULVT_P, DCO_LPP, NP, PP, CO, M1, VIAx, Mx, VIAy, My
For OD, PO, VTL_N, VTL_P, VTH_N, VTH_P, ULVT_N, ULVT_P, DCO_LPP, NP, PP, M1, Mx, My, all vertices
G.6gU and intersections of 45-degree polygon must be on an integer multiple of 0.005 μm except PO inside the layer
186;5 for GS/GL and 186;4 for LP/LPG.
< 1 .0 X m in w id th < 1 .0 X m in w id th
> 1 .0 X m in w id th
< 1 .0 X m in w id th or
< 1 .0 X m in w id th
< 1 .0 X m in w id th > 1 .0 X m in w id th
or
< 1 .0 X m in w id th > 1 .0 X m in w id th
or
Figure 3.7.1 Illustration for G.4.
Figure 3.7.2 Illustration for G.6gU.
3.7.2 OPC Recommendations and Guidelines

The following OPC recommendations are very important tips to reduce OPC and mask-making cycle time (or
physical verification) and ensure the best silicon performance:
 Make certain that the design is DRC clean (free of all DRC violations).
 Do not use circles, oval shapes, or logos of arbitrary geometry (Figure 3.7.3). Use rectangular or 45-
degree polygons to write words, logos, and other marks that are not part of the circuit.
 Verify that all line-ends are rectangular.
 Limit cell names to 127 or fewer characters.
 Use a well-organized, hierarchical layout structure.
Avoid redundant or excessive overlaps of polygons from two, or more than two, different cells or
cell placements. For example, avoid forming a straight line from numerous cell placements, with each
one contributing a little piece. Refer to the “Design Hierarchy Guidelines” section in this chapter.
 Worse performance in the simulation of contour for the layout with small jog/zigzag (Figure 3.7.4).
Avoid small jogs (Figure 3.7.4).
OPC.R.2gU It is recommended to use greater than, or equal to, half of the
minimum width of each layer for each segment of a jog.
Figure 3.7.3 Logo Geometry Example
O rig in a l la y o u t
 0.16
S im u la tio n
o f c o n to u r
Figure 3.7.4 Simulation contour for the layout with and without small jog/zigzag. The simulation is Mx
line and not well treated due to small jog/zigzag, and cause smaller VIAx overlap.
3.8 Design Hierarchy Guidelines

The style of the cell hierarchy in a design can significantly affect the following:
 OPC and mask-making cycle time
 Run time and memory usage of physical verification.
The following items are the recommended practices:

 Re-use design blocks as much as possible.
Do not create two different cells for the same device.
 Whenever possible, avoid using L, U, or ring shapes.
For inevitable ring structures such as seal rings and power rings, use cells for holding each ring segment
instead of drawing the whole ring at once. The same method applies to the L and U shapes.
 Put everything as low in the cell hierarchy as possible. Here are some examples:
 Put all shapes required for defining a device or circuit into the same cell. An inverter cell, for example,
should include NW, OD, PO, NP, and PP, as well as CO and M1 (for pins).
 Avoid drawing a large shape to cover a whole circuit.
 Place texts at the lowermost cell where devices can be formed.
 For layout patches/revisions/ECOs, avoid changing device properties or metal connections at upper
cells in the design hierarchy.
 Draw within the cell the shapes required in TSMC’s logic operations.
Please consider all independent layers used in each rule logic operations and derived layer logic
operations. For example, LDN.EX.2 applies to NP and OD2; therefore, NP should reside in the same
cell as OD2.
 Make certain each cell is DRC clean in a bottom-up construction of the cell hierarchy.
For example, when placing a contact in a cell, place M1 in that cell as well, with the required amount of M1.
 Keep dummy fill geometry in a separate hierarchy from the main patterns and reduce the count of
flattened dummy fill geometry as much as possible.
3.9 Chip Implementation and Tape Out Checklist

The following checklist is required to be completed prior to the tape out:
 IP are correctly utilized in the design
 Pay attentions to the special orientation/direction (eg. SRAM), guard ring or space keep-out
requirements of placement.
 Pay attentions to routing constrains in resistance matching, power net spacing, layers available for over
block routing, layers allowed dummy fill, and power connection/width.
 To avoid using non-silicon proven library and IP, please pay attentions to the available library/IP
validation status from TSMC Online (Design Portal  Library/IP).
 It is highly recommended that do not modify or remove the IP tags (CAD 63;63) in the design.
 The design passes signal/power/IR/ESD integrity analysis
 Simulations of all CKTs in setup time, hold time, and noise analysis under design operating corners or
sign-off corners.
 Analyses in leakage with considering statistical factor, total power consumption, power network
robustness, static/dynamic IR, IO SSO meet design specifics over all operating corners.
 Ensure all contacts/vias and metal lines meet EM lifetime requirement.
 ESD/latch-up layout and design requirements have been met.
 The design passes DRC
 Use the most update DRC command file version corresponding to the design rule document.
 Need to choose the DRC options carefully and correctly.
 Need to cover all the DRC, including latch-up, ESD, anntena, assembly check.
 It is recommended running full chip DRC if there is any layout change in cell level.
 Any DRC violation needs to be reviewed by TSMC, to make sure no production concern.
 The design passes LVS/ERC checks
 Use the most update LVS/ERC command file version corresponding to the SPICE document.
 DFM services and requirements are recommended
 Utilize TSMC DFM redundant VIA utility to insert redundant vias and enlarge via enclosure.
 Utilize TSMC dummy OD/PO/metal generation utilities to insert dummy patterns to meet pattern density
requirements.
 RC extraction by DFM-LPE to have accurate SPICE simulations in IP design.
 The section 3.8 Design Hierarchy Guidelines have been considered.
 Tape out information
 Make sure to have every “tape out required CAD layer” filled correctly in the TSMC i-tapeout system.
Additionally, to correctly fill DRC-only CAD layers of the design is welcome.
 It is highly recommended that the GDSII file taped out to TSMC contains IP tags information (CAD
63;63).
4 Layout Rules and Recommendations

4.1 Layout Rule Conventions
4.2 Derived Geometries Used in Physical Design Rules
4.3 Definition of Layout Geometrical Terminology
4.4 Minimum Pitches
4.5 Layout Rules and Guidelines
4.1 Layout Rule Conventions

Layout rules follow these conventions:
 Unless otherwise specified, all rules are of minimum dimension.
 The basic unit of measure is μm; the basic unit of area is μm2.
o Process, product, and reliability yields are expected to be improved when designs are relaxed from
minimum dimensions. Minimum dimensions showed only to be used to shrink the chip size or to improve
the circuit performance.
o Design rules requiring exact dimensions (“=” in the rule tables) are not to be relaxed.
 Guideline is grouped by a separate table.
 DFM recommendations and guidelines are designated by a registered symbol ® or “g” after the rule
number.
 A registered symbol “U“ is marked after the rule number as the rule is not checked by DRC.
 Rules denoted by “#” depend on the capability of each individual probing/ assembly house. These rules are
checked by DRC, and may be waived by customers with agreement from their subcontractors.
 Rules denoted by “t” applied for tsmc bumping only. These rules are checked by DRC, and may be waived
by customers with agreement from a third-party bumping house.
 Bracket usage in the rules should be noted carefully:
 Parentheses ( ) are used for explanation.
 Square brackets [ ] are used for certain conditions.
 Curved brackets { } are used to indicate that an operation is performed.
4.2 Derived Geometries Used in Physical Design

Rules
4.2.1 Derived Geometries
Term Definition
ACTIVE N+ ACTIVE OR P+ ACTIVE
ALLOD OD OR DOD OR SR_DOD
Butted_STRAP STRAP TOUCH ACTIVE
FIELD NOT OD
FIELD PO PO NOT OD
GATE PO AND OD
N+ ACTIVE (NP AND OD) NOT NW
N+OD NP AND OD
NW STRAP (NP AND OD) AND NW
1. NW NOT OD2 (Note 1)
NW1V
2. NW OUTSIDE OD2 (Notes 1~2)
1. NW AND OD2 (Note 1)
NW2V
2. NW NOT OUTSIDE OD2 (Notes 1~2)
NWROD (NW INTERACT NWDMY) INTERACT RPO
NWRSTI (NW INTERACT NWDMY) NOT INTERACT RPO
OD2 OD_18, OD_25, OD_33
P+ ACTIVE (PP AND OD) AND NW
P+OD PP AND OD
PW STRAP (PP AND OD) NOT NW
RW STRAP ((PP AND OD) NOT NW) INSIDE DNW
STRAP NW STRAP OR PW STRAP
RW (Chip NOT NW) INSIDE DNW
PW Chip NOT NW
BTC (CO NOT CO;11) AND SRM;0
Table note:
1. For DRC recognition purpose, NW covered by OD2 is necessary for NW applied by voltage greater than core voltage.
It is very important to manually take care of NW to NW space ≥ 1um if NW cannot be covered by OD2 and at least
one NW is applied by voltage greater than core voltage.
2. If the switch, NW_SUGGESTED, turns ON (default), DRC will not only run NW.S.3 and NW.S.4 but also additionally
check “SUGGESTED.NW.S.3_NW.S.4” by recognizing NW1V by {NW OUTSIDE OD2} and NW2V by {NW NOT
OUTSIDE OD2}. If it turns OFF, DRC only checks NW.S.3 and NW.S.4.
NW NOT OD2 N W O U T S ID E O D 2
NW OD2
NW
OD2 NW NW
NW NW
NW
NW AND OD2 N W N O T O U T S ID E O D 2
4.2.2 Special Definition

Term Definition
NW N-WELL
PW P-WELL
MOS Transistor structure consisting of a source, a drain, and a gate.
NMOS N type MOS
PMOS P type MOS
DOD Dummy OD
SR_DOD Dummy OD (smaller dimension)
DPO Dummy PO
SR_DPO Dummy PO (smaller dimension)
BTC Butted Contact
DMx Dummy Metal
DMx_O OPC dummy metal. The rules of DMx_O are the same as real metal, Mx.
“Prime Chip” doesn’t include seal ring and assembly isolation.
If seal-ring is added by TSMC, the “Prime Chip” means: GDS EXTENT
Prime Chip
If seal-ring is added by you, the “Prime Chip” means:
EXTENT of {INNER EDGE OF SEALRING_ALL (162;2)}
The 6um inner region of SEALRING_ALL (162;2) which surrounds {Prime Chip NOT triangle
Assembly isolation
empty areas}
ENDCAP The PO extension of a transistor gate in the width direction onto the field.
CB Passivation opening for wire bond design
CBD Passivation opening for flip chip design
RV Redistribution VIA for connecting AP-MD with Mtop
CB2_FC Passivation 2 opening for flip chip
CB2_WB Passivation 2 opening for wire bond
AP Al pad metal layer after CB or CBD in Cu process
AP RDL Al pad redistribution layer
PM Polyimide opening
UBM Under bump metallurgy
Wire bond pad design for Circuit Under Pad.CUP has 2 solid metal layer at Mtop/Mtop-1 and
CUP
coverd by WBDMY
4.3 Definition of Layout Geometrical Terminology

Width: Distance of interior-facing edge for single layer. (W)
Space: Distance of exterior-facing edge for one or two layer (S)
S
S S
S
Overlap: Distance of interior-facing edge for two layers (O)
Enclosure: Distance of inside edge to outside edge (Fully inside) (EN)
Extension: Distance of inside edge to outside edge (EX)
Prime Chip:
GDS w/I seal ring : GDS w/o seal ring:
Prime chip: Prime chip:

EXTENT of {INNER EDGE of Gds extent edge
SEALRING_ALL (162;2)}
Triangle
empty area
Seal ring (162;2)

Interact with:
A INTERACT B:
A A A IN T E R A C T B A A
A A A
A A
A
A NOT INTERACT B:
A A A N O T IN T E R A C T B A
A A
A
A
A
INSIDE:
A INSIDE B:
A A A IN S ID E B A
A A A
A
A
A NOT INSIDE B:
A A A N O T IN S ID E B A
A A A
A A
A A
A OUTSIDE B:
A A A O U T S ID E B
A A A
A A
A A
A NOT OUTSIDE B:
A A A
A A N O T O U T S ID E B A
A A
A
A
AREA (A):
ENCLOSED Area (A):
3-Neighboring:
Projection:
Individual projection (L1, L2)
Union projection (L1 + L2)
W1
W2
L2
L1
If W1 > certain w idth and W2 > certain

w idth, L = L1+ L2
If W1 > certain w idth and W2 < certain
w idth, L = L1
Parallel run length:
Length and width

Length: the longer edge
L
L
W
W
Width: the shorter edge

Size up a Size down b
a b original
a a b b
original
a b
Butted
A ABUT B:
A A A ABUT B A
A A
A A
A
A AND B:
A A A A
A AND B A
A A
A
A
A OR B:
B B
A A A OR B A A
A A A A
A A
A A
Guard ring
R in g - t y p e O D a n d M 1 w it h C O
a s m a n y a s p o s s ib le
S e a l r in g P r o te c tio n r in g G u a r d r in g
C h ip /IP le v e l C h ip I P ( w it h o u t I n d u c t o r ) I P ( w it h I n d u c t o r ) IP
CO bar Y N N
V IA b a r Y Y ( c o n t in u o u s ) Y ( c o n t in u o u s o r b r e a c h ) N
C O h o le Y O p t io n Y
V IA h o le N N Y
S tr u c tu r e O D /C O / O D /C O /M 1 /
(O D /C O /M e ta l/V ia ) a ll M e t a ls / a ll V I A s M 1 / a ll V I A x / a ll M x V I A 1 a b o v e is o p t io n a l.
P le a s e r e fe r to s e c ti o n 4 .5 .5 4 P le a s e r e fe r to s e c ti o n 4 .5 .3 5 L O W M E D N la y o u t r u le s . P le a s e r e fe r to s e c ti o n s fo r
s e a l rin g o ve rvie w . a n a lo g c i r c u i t/ D F M / L a tc h - u p .
One track
O n e tr a c k = M x w id th + M x s p a c e
VTH_N VTH_N
O n e tra c k O n e tra c k O n e tra c k

VTH_N
VTH_N
A llo w e d A llo w e d
N o t a llo w e d
CUT
A CUT B:
A A A CUT B A
A A
A
A
B CUT A:
B
B
A B A B
B CUT A
B CUT A
A
A NOT CUT B:
A A A NOT CUT B A
A A
A A
A A
A
A
Channel width
PO
OD
Channel length
PO
OD
Vertex/Corner: Polygon whose edge form an angle
Vertex
Hole width
Enclosed space
4.4 Minimum Pitches

Definition of Layout Geometrical Terminology
CLN45
Layer
(Unit: μm)
OD interconnect pitch 0.14 (W/S=0.06/0.08)
OD interconnect width 0.06
OD transistor pitch 0.20 (W/S=0.12/0.08)
PO interconnect pitch (on STI) 0.14 (W/S=0.04/0.10)
PO interconnect width 0.04
PO transistor pitch (on OD) 0.18 (W/S=0.04/0.14)
PO transistor pitch (on OD with CO) 0.18
Minimum length of a transistor 0.04
Minimum width of a transistor 0.12
N+/P+ spacing 0.16
M1 pitch 0.14 (W/S=0.07/0.07)
Mx pitch 0.14 (W/S=0.07/0.07)
My pitch 0.28 (W/S=0.14/0.14)
Mz Pitch 0.80 (W/S=0.40/0.40)
Mr pitch 1.0 (W/S=0.5/0.5)
Mu pitch 3.0 (W/S=2.0/1.0)
CO Pitch 0.14 (W/S=0.06/0.08)
CO Pitch in different net 0.17 (W/S=0.06/0.11)
CO  3 neighboring Pitch 0.16 (W/S=0.06/0.10)
VIAx Pitch 0.14 (W/S=0.07/0.07)
VIAx Pitch in different net 0.165 (W/S=0.07/0.095)
VIAx  3 neighboring Pitch 0.16 (W/S=0.07/0.09)
VIAy Pitch 0.28 (W/S=0.14/0.14)
VIAy  3 neighboring Pitch 0.30 (W/S=0.14/0.16)
VIAz Pitch 0.70 (W/S=0.36/0.34)
VIAz  3 neighboring Pitch 0.90 (W/S=0.36/0.54)
VIAr pitch 0.90 (W/S=0.46/0.44)
VIAr  3 neighboring pitch 1.12 (W/S=0.46/0.66)
4.5 Layout Rules and Guidelines

4.5.1 Gate Oxide and Diffusion (OD) Layout Rules
(Mask ID: 120)
OD.W.1 Width A  0.06
OD.W.1® Recommended minimum interconnect OD width (except MOMDMY (155;21) region and TCDDMY) A  0.08
OD.W.2 Channel width of core device B  0.12
Maximum channel width of core NMOS device for GS and LPG G device
OD.W.2.1GS B  10
(This check doesn’t include the regions covered by layers NT_N, SR_ESD, LOGO, TCDDMY and VAR)
Maximum channel width of core PMOS device for GS
OD.W.2.2GS B  1.5
(This check doesn’t include the regions covered by layers NT_N, LOGO, TCDDMY and VAR)
OD.W.3 Channel width of MOS [for I/O device] C  0.32
Width of 45-degree bent OD. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid
OD.W.4 D  0.17
(refer to the rule, G.6, in section 3.7))
OD.S.1 Space E  0.08
OD.S.1® Recommended minimum OD space to reduce the short possibility caused by particle E  0.10
OD.S.2 Space (inside OD2) F  0.15
OD.S.3 Space to OD [width > 0.12 μm] if the parallel run length  0.14 µm (P) G  0.10
OD.S.3.1 Space to OD [width > 0.12 μm] if the parallel run length  0.14 µm (P1) in PO gate direction G1  0.11
OD.S.4 Space to 45-degree bent OD H  0.17
OD.S.5 Space between two segments of a U-shape or an O-shape OD (notch only) I  0.15
OD.A.1 Area (This check doesn't include the patterns filling 0.06 μm x 0.26 μm rectangular tiles) K  0.035
OD.A.2 Area [with all of edge lengths < 0.21 μm] K’  0.055
OD.A.3 Enclosed area L  0.04
OD.A.4 Enclosed area [with all of inner edge lengths < 0.21 μm] L’  0.077
Maximum ACTIVE area sum of core PMOS device in the same checking area of OD. (Not including the
gate area) (For GS)
DRC methodology:
OD.A.5.GS Maximum area sum of ((Core P+ ACTIVE INTERACT PO) NOT (PO OR SR_DPO)) in the same  300
checking area of OD.
The checking area is defined by sizing 0.22um in S/D direction, and 0.08um in endcap direction from
gate.
Maximum length of {ACTIVE (source) [width < 0.12 μm] interacts with butted_STRAP} if no CO in M
OD.L.1 M  0.4
region.
Maximum OD length [OD width < 0.12 µm] between two contacts as well as between one contact and
OD.L.2 N  60
the OD line-end. (except {RFDMY AND RFIP_DMY} and {MOMDMY(155;21) SIZING 1.2um})
1. OD.DN.2/OD.DN.2.1/OD.DN.2.2 and OD.DN.3/OD.DN.3.1/OD.DN.3.2 are checked over any window
150 μm x 150 μm, stepping 75 μm .
2. (outside OD2) means the overlapped width between the checking window and OD2 layer is smaller
than 37.5 μm.
3. For OD.DN.2/OD.DN.2.1/OD.DN.2.2/OD.DN.3/OD.DN.3.1/OD.DN.3.2, the following regions can be
excluded:
OD.DN.0
- NWDMY/LOGO/INDDMY/INDDMY_MD
- Chip corner stress relief and seal-ring
4. OD.DN.2/OD.DN.2.1/OD.DN.2.2 are applied when the width of (checking window NOT the item 3) is
 37.5 μm.
5. OD.DN.3/OD.DN.3.1/OD.DN.3.2 must be followed for every defined ODBLK region. This rule is only
applied when the width of ((checking window AND ODBLK) NOT item 3) is  37.5 μm.
OD.DN.1 Minimum {OD OR DOD OR SR_DOD} density across full chip  25%
OD.DN.1.1 Maximum {OD OR DOD OR SR_DOD} density across full chip  75%
OD.DN.2 Minimum {OD OR DOD OR SR_DOD} local density (window 150μm x 150 μm, stepping 75 μm)  20%
Maximum {OD OR DOD OR SR_DOD} local density [OUTSIDE OD2] (window 150 μm x 150 μm,
OD.DN.2.1  80%
stepping 75 μm)
OD.DN.2.2 Maximum {OD OR DOD OR SR_DOD} local density (window 150 μm x 150 μm, stepping 75 μm)  90%
Minimum {OD OR DOD OR SR_DOD} local density inside ODBLK (window 150 μm x 150 μm,
OD.DN.3  20%
stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density inside ODBLK [OUTSIDE OD2] (window 150 μm x
OD.DN.3.1  80%
150 μm, stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density inside ODBLK (window 150 μm x 150 μm, stepping
OD.DN.3.2  90%
75 μm)
It is not recommended the gate interact with the region of {(OD local density < 10%) SIZING 20um}.
The definition of the gate is as follows:
OD.DN.4® {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}  10%
The definition of the region OD local density is as follows:
{OD OR DOD OR SR_DOD} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(OD local density > 70%) SIZING 20um}.
OD.DN.5® {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}  70%
It is not recommended the gate interact with the region of {(OD local density < 20%) SIZING 100um}.
OD.DN.6® {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}  20%
It is not recommended the gate interact with the region of {(OD local density > 70%) SIZING 100um}.
OD.DN.7® {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}  70%
It is not recommended the unsalicided poly resistor interact with the region of {(OD local density < 20%)
SIZING 100um}.
The definition of the unsalicided poly resistor is as follows:
OD.DN.8®  20%
{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY*)}
It is not recommended the unsalicided poly resistor interact with the region of {(OD local density > 60%)
SIZING 100um}.
OD.DN.9®  60%
OD.R.1 OD must be fully covered by {NP OR PP} except for {(DOD OR SR_DOD) OR NWDMY}
DOD is a must. DOD CAD layer (TSMC default, 6;1) must be different from OD’s. Please refer to
DOD.R.1*
section 8.1.
It is important to use TSMC DOD/DPO utility to insert the SR_DOD and SR_DPO properly surrounding
your IP and circuit, and then do post-simulation carefully before chip implementation.
DOD.R.4® DRC will flag the empty rectangle area larger than 1.8x1.8um2 inside  1.8x1.8um2
{(GATE SIZE 2.8) NOT (((OD OR DOD) OR SR_DOD) SIZE 0.12) NOT ((PO SIZE 0.05) OR ((DPO OR
SR_DPO) SIZE 0.03)) NOT ((NW SIZE 0.08) NOT (NW SIZE -0.08))} (Except TCDDMY and
SEALRING_ALL (162;2))
It is strongly suggested to limit the max interconnect length (M) to be as short as possible to avoid high
OD.L.2gU
Rs variation.
* CAD layer SENDMY (255;8) is used to check OD.DN.4® ~ OD.DN.9® for sensitive circuits. If your IP is sensitive to
the Isat variation due to low/high OD density, you can cover the SENDMY to perform this check.
Table Notes:
 In order to meet the extremely tight requirement in terms of process control for STI etch, polish, OSE as
well as channel length definition (inter-level dielectric (ILD) planarization), you must fill the DOD globally
and uniformly even if the originally drawn OD already satisfies the required OD density rule
(OD.DN.1~OD.DN.3.2). Inder to cover the OSE (refer to the section of Layout Guidelines for OSE (OD
Space Effect)), it is important to follow the layout guideline (refer to the section of How to reduce the
differences between pre-simulation and post-simulation) and use TSMC DOD/DPO utility to reduce the
gap between SPICE and silicon. It is recommended to manually add DOD uniformly inside regions
covered by the ODBLK layer, to gain better process window and electrical performance.
OD
O D .W .1 O D .S .3 / O D .S .3 .1
E
W < = 0 .1 2
A
OD
O D .W .3 G1
P1
OD OD2
C
P W > 0 .1 2
PO
F
W > 0 .1 2 G
OD
O D .S .5
OD I
O D .W .4 / O D .S .4 / O D .L .3
B
E A I
PO
E
O
H OD
E
OD
O D .L .1
O D .A .1 / O D .A .3 BUTTED
OD
OD
M
OD PO
OD BUTTED
< 0 .1 2 OD < 0 .1 2
PO
> 0 .1 2 OD
K /K ’ L /L ' OD M
L /L ' OD N o n e e d to
BUTTED
fo llo w
< 0 .1 2 BUTTED
M O D .L .1
OD < 0 .1 2
< 0 .1 2
> 0 .1 2 PO
OD
> 0 .1 2 P O
OD
W < 0 .1 2 u m O D .L .2
N <= 60 um N  60 um
DOD.R.4® and SR_DOD.R.4gU Analog Device or IP

DOD/DPO
surrounded with
Analog Device or IP SR_DOD/SR_DPO dummy devices
Not recommend (Si to simulation gap:) Recommend Recommend

(>10%) (>10%) (>10%) (<5%) (<5%)
1. Without dummy devices & DOD/DPO IP surrounded IP surrounded
2. Only surrounded by dummy devices, but no DOD/DPO with DOD/DPO with dummy devices
protect by updated utility first, then insert
3. Only surrounded by DOD/DPO, but no SR_DOD/SR_DPO
DOD/DPO
DOD.R.4® U
D O D . R . 2 ® and
& S RSR_DOD.R.4g
U
_ D O D .R .4
0 .1
0 .8 8
0 .0 4 /0 .1
0 .0 4 /0 .1
S R _ D O D (6 ;7 )
S R _ D P O (1 7 ;7 )
0 .2
0 .2
P O LY (1 7 ;0 )
0 .1
O D (6 ;0 )
0 .1 2
0 .0 5
0 .1
0 .8 8 0 .5
0 .0 4 /0 .1
4um
4.5.2 Deep N-Well (DNW) Layout Rules (Mask ID: 119)

[Optional]
DNW.W.1 Width A  3
DNW.S.1 Space B  3.5
Space to NW with different potential
DNW.S.2 C  2.5
DRC only checks when NW does not exist in same DNW.
DNW.S.3 Space to {N+ ACTIVE outside DNW} D  1.65
DNW.S.4 RW space to {RW OR PW} with different potential E  0.8
DNW.S.5 {RW OR PW} space to {RW INTERACT OD2} with different potential F  1.0
DNW.EN.1® Recommended enclosure by NW for better noise isolation G  1.0
DNW.EN.3 Enclosure of N+ ACTIVE K  0.48
DNW.O.1 Overlap of NW H  0.4
DNW.R.3U Keep {NW INTERACT DNW} and PW in reverse bias
DNW.R.4U {NW INTERACT DNW} must be at the same potential
DNW.R.5 N+ ACTIVE cut DNW is not allowed
Recommended not using floating RW unless necessary to avoid unstable
DNW.R.6gU
device performance.
Maximum cumulative area ratio of DNW to {(NMOS/P-VAR core gates)
DNW.R.7 OUTSIDE DNW} [connects to {P+ ACTIVE INSIDE {NW INTERACT DNW}}] ≤ 5.0E+05
This rule is checked by the ANTENNA DRC command file.
Maximum cumulative area ratio of DNW [area ≥ 1E+06 µm2] to {(NMOS/P-
VAR core gates) OUTSIDE DNW} [connects to {P+ ACTIVE INSIDE {NW
INTERACT DNW}}, and does not connect to STRAP]
DNW.R.7.1 ≤ 5.0E+05
This rule is checked by the cumulative connections (from M1 to AP
respectively) and the DRC command files in ANTENNA_DRC directory.
DNW.R.7.2 Maximum cumulative area ratio of DNW [area 1E+06 um2] to ≦ 500000
{core_NMOS/P-VAR INSIDE DNW [area ≤1E03um2]}
If ≧ 4 um2 {N+ OD AND PW} added in discharging path with lower metal
layers (M1 or M2) which outside DNW, it is allowed maximum cumulative area
ratio of DNW [area 1E+06 um2] to {core_NMOS/P-VAR INSIDE DNW [area
≤1E03um2]} up to 4.1E+06.
Definition of core_NMOS/P-VAR:
1. NMOS and P-VAR gates do not inside OD2, and
2.Connect to {P+ ACTIVE INSIDE (NW INTERACT DNW) [area ≥1E+06
um2]}, and
3.Do not connect to STRAP
This rule is checked by the cumulative connections (from M1 to AP

respectively) and the DRC command files in ANTENNA_DRC directory.
D
DNNW
W
NW
G NW
H DNW H
RW RW PW
X X'
E
K
(F )
+
N A C T IV E
E (F )
DNW
+
N A C T IV E
D
C
B
+
R W (P W in s id e D N W ) N A C T IV E NW
NW
DNW
DNW A
C r o s s S e c t io n ( X - X ') f o r N W , R W , a n d D N W
X X'
NW RW NW RW NW PW
DW N
For better noise isolation, it is recommended to follow the DNW.EN.1® rule
G NW
H DNW
RW RW RW
X X'
E
(F )
D
C
B
+
R W (P -w e ll in D N W ) N OD NW
NW
DNW
DNW A
C r o s s S e c t io n ( X - X ') f o r N W , R W , a n d D N W
X X'
NW RW NW RW NW RW NW
DW N
4.5.3 N-Well (NW) Layout Rules

NW.W.1 Width, except SRAMDMY A  0.34
NW.S.1 Space C  0.34
NW.S.2 Space of two NW1V with different potentials (*) D  0.8
NW.S.3 NW1V space to NW2V with different potentials (*) E  1
NW.S.4 Space of two NW2V with different potentials (*) F  1
NW.S.5 Space to PW STRAP G  0.08
NW.S.6 Space to N+ ACTIVE (except NW resistor) H  0.08
NW.S.6.1 Space to N+ ACTIVE [at least one edge at each corner] (except NW resistor) H1  0.16
NW.S.7 Space to {N+ ACTIVE INTERACT OD2} I  0.22
NW.EN.1 Enclosure of NW STRAP (except NW resistor) K  0.08
NW.EN.2 Enclosure of P+ ACTIVE L  0.08
NW.EN.2.1 Enclosure of P+ ACTIVE [at least one edge at each corner] L1  0.16
NW.EN.3 Enclosure of {P+ ACTIVE INTERACT OD2} M  0.22
NW.A.1 Area O  0.64
NW.A.2 Enclosed area P  0.64
Recommend not using unintentional floating well to avoid unstable device performance. DRC flags
NW.R.1g
{NW OUTSIDE {N+OD INTERACT CO}}.
NW.R.2U OD2 must overlap NW [applied by voltage greater than core voltage]
Table notes:*: DRC implementation is on different nets.

1. For DRC recognition purpose, NW overlapped by OD2 is necessary for NW applied by voltage greater than core
voltage. It is very important to manually take care of NW to NW space ≥ 1um if NW cannot be operlapped by OD2
and at least one NW is applied by voltage greater than core voltage.
2. If the switch, NW_SUGGESTED, turns ON (default), DRC will not only run NW.S.3 and NW.S.4 but also additionally
check “SUGGESTED.NW.S.3_NW.S.4” by recognizing NW1V by {NW OUTSIDE OD2} and NW2V by {NW NOT
OUTSIDE OD2}. If it turns OFF, DRC only checks NW.S.3 and NW.S.4.
NW
N W
C A A
D /E /F P
O P
N W
N W N W
N W
N W
P W N W
L 1 (o r L ) H 1 (o r H )
+ +
P O D N O D
a t le a s t o n e e d g e a t e a c h c o r n e r
L (o r L 1 ) H (o r H 1 )
K G
+ +
N O D P O D
O D 2
+ M I +
P O D N O D
N W P W
4.5.4 N-Well Resistor Within OD (NWROD) Layout

Rules
NWROD.W.1 Width A  1.8
NWROD.S.1 Space to NWROD or to NW B  1.0
NWROD.S.2 Space to RPO C  0.3
Recommended RPO space to CO in NW resistor within OD for SPICE
NWROD.S.3® G = 0.3
simulation accuracy
NWROD.EN.1 Enclosure by OD D  1.0
NWROD.EN.2 Enclosure of CO E  0.3
RPO overlap of NP. Use exact value (0.4 μm) on sides touching
NWROD.O.1 F = 0.4
NWDMY.
{OD AND NWDMY} overlap of {NP, PP, VTH_N, VTH_P, VTL_N, or
NWROD.O.2
VTL_P} (all implant layers except NW) is not allowed.
Recommended to use rectangle shape resistor for the SPICE simulation
NWROD.R.3g
accuracy. DRC can flag {NWDMY AND NW} is not a rectangle.
NWROD.R.4 Only one NW inside NWROD is allowed in one OD.
NWROD.R.5 Only two NPs in NWROD are allowed in one OD.
NWROD.R.6 Only two RPO holes(Sailcide) in NWROD are allowed in the same OD
For U-shape or S-shape NWROD, both OD and NW must be U-shape or
S-shape and the OD edge must be parallel to the NW edge. DRC can
NWROD.R.7
only flag the pattern without OD space when two edges of NW [NW
space or notch ≤ 5 um] have a parallel run length > 0 um.
NWROD.R.8g Recommend: NWDMY intersecting NWROD forms two or more NWs.
Table Notes:
 The mean value and deviation of an N-Well resistor depends on the layout and dimension.
 Dummy layer NWDMY is needed for DRC and LVS.
NWROD
RPO
OD
D
N W R O D .W .1
E F F E
B
NW R P O .E X .1
NW
0 .2 2
A
G G C
NW
R P O H o le R P O H o le
NP NP
N W e ll R e s is to r
NW DMY
N W R O D .R .4
N W R O D .R .5 N W R O D .R .7
OD
NP NP NP
NW
NW NW
OD
NW DMY
NW
OD
NW DMY
NW DMY
N W R O D .R .7 N W R O D .R .7
N W R O D .R .6
OD OD
NW NW
RPO
NW
NW
OD
NW DMY
NW DMY NW DMY
T h e la y o u t is u n c h e c k a b le
4.5.5 N-Well Resistor Under STI (NWRSTI) Layout

Rules
NWRSTI.W.1 Width A  1.8
NWRSTI.S.1 Space to NWRSTI or to NW B  1.0
NWRSTI.EN.1 NP enclosure of OD C  0.4
NWRSTI.EN.2 OD enclosure of CO D  0.3
Recommended OD enclosure of CO in NW resistor under STI for SPICE
NWRSTI.EN.2® D = 0.3
simulation accuracy
NWRSTI.EN.3 Enclosure of CO E  0.3
NWRSTI.EX.1 OD extension on NWRSTI F  0.3
{NP INTERACT NWDMY} overlap of {PP, VTH_P, or VTL_P} (all p-type
NWRSTI.O.1
implant layers) is not allowed
Recommended to use rectangle shape resistor for the SPICE simulation
NWRSTI.R.3g accuracy.
DRC can flag {NWDMY AND NW} is not a rectangle.
NWRSTI.R.4g Recommend: NWDMY intersecting NWRSTI forms two or more NWs.
NWRSTI
N W R S T I.W .1
N W N W
N W e ll R e s is to r
O D O D
E C E
D F
NW
NP NP
NW DM Y
4.5.6 Native Device (NT_N) Layout Rules

NT_N, Native NMOS Blocked Implant Definition
This layer is used to block NW and PW implant. If you use native NMOS devices in a circuit design, please use this drawn
layer with NW to generate PW. Native NMOS is only allowed being designed in the standard device region. It cannot be
applied to pure high/low Vt designs.
NT_N.W.1 Width A  0.34
NT_N.W.2 Channel length of 0.9V/1.1V/1.2V native device for N45LP/N45LPG/N40G B  0.30
NT_N.W.2.1 Channel length of 1.1V native device only for N40LP/N40LPG B  0.20
Channel length of 2.5V/3.3V native device (for 2.5V overdrive to 3.3V,
NT_N.W.3 C  1.20
please refer to section OD25_33 Layout Rules)
Channel length of 1.8V native device (for 2.5V underdrive to 1.8V, please
NT_N.W.4 D  0.8
refer to section OD25_18 Layout Rules)
NT_N.W.5 Channel width E  0.5
NT_N.S.1 Space F  0.34
NT_N.S.2 Space to [Active outside NT_N] G  0.38
NT_N.S.3 Space to NW H  1
NT_N.EN.1 Enclosure range of N+OD. I = 0.26
NT_N.EX.1 PO extension on {OD inside NT_N} (PO endcap) J  0.35
NT_N.A.1 Area K  0.64
NT_N.A.2 Enclosed area L  0.64
NT_N.R.1 Overlap of {NW OR DNW} is not allowed
P+ ACTIVE region is not allowed in NT_N but PW STRAP is allowed.
NT_N.R.2
DRC only can check P+ Gate is not allowed in NT_N.
Only one OD region is allowed in NT_N
 Except NMOS capacitor with the same potential, pickup and
MOMDMY (155;21) region.
 You have to draw a NCap_NTN layer to cover the NMOS
NT_N.R.3
capacitors. The NCap_NTN enclosure of OD have to be  0um. All
the source and drain must be connected together.
 DRC also flags NCap_NTN and OD, which is outside of the
NCap_NTN in the same NT_N.
NT_N
L
K L
N o m in a l
A C, D
OD
D e v ic e O D
F G
PO LY
OD I
E
H
PW NW
N T _ N .R .3
NT_N NT_N
Ncap_NTN Ncap_NTN
Ncap_NTN
OD OD
OD OD
P r o h ib it e d A llo w e d
4.5.7 Thick Oxide (OD2) Layout Rules (Mask ID: 152)

 Define thick oxide area of 1.8V or 2.5V or 3.3V I/O transistors.
 The OD_33 layer (CAD layer: 15) is used for 3.3V gate oxide area only for N40LPG.
 The OD_25 layer (CAD layer: 18) is used for 2.5V gate oxide area.
 The OD_18 layer (CAD layer: 16) is used for 1.8V gate oxide area.
 OD2 refers to any thick oxide device, for example, OD2 = OD_18, OD_25, or OD_33.
OD2.W.1 Width A  0.34
OD2.W.2 Width of {OD2 OR {NW OR NT_N}} O  0.34
Width of {OD2 NOT {NW OR NT_N}}, except {{OD2 NOT {NW OR NT_N}}
OD2.W.3 W  0.34
[width < 0.34um] NOT INTERACT OD} and LOGO regions
OD2.S.1 Space B  0.34
Space to {ACTIVE OR GATE}
OD2.S.2 C  0.2
({ACTIVE OR GATE} cut OD2 is not allowed)
OD2.S.3 Space to 0.9V/1.2V GATE in S/D direction. G  0.25
OD2.S.4 Space to NW. Space = 0 μm is allowed. E  0.34
OD2.S.5 Space of {NW NOT OD2} P  0.34
OD2.S.6 Space of {NW AND OD2} Q  0.34
OD2.S.7 Space of {OD2 NOT {NW OR NT_N}} R  0.34
Space of {OD2 OR {NW OR NT_N}}, except {{OD2 OR {NW OR NT_N}} [space
OD2.S.8 S  0.34
< 0.34um] NOT INTERACT OD} and LOGO regions
OD2.EN.1 Enclosure of 1.8V/2.5V/3.3V Gate in S/D direction. D  0.25
OD2.EX.1 NW extension on OD2. Extension = 0 μm is allowed. H  0.34
OD2.EX.2 Extension on NW. Extension = 0 μm is allowed. I  0.34
OD2.EX.3 Extension on {ACTIVE OR GATE} J  0.2
OD2.O.1 Overlap of NW. Overlap = 0 μm is allowed. K  0.34
OD2.R.1 OD_18, OD_25, and OD_33 cannot be used on the same die.
Only OD_25 (CAD layer: 18) is allowed for N40LP+.
Neither OD_33 (CAD layer: 15) nor OD_18 (CAD layer: 16) is allowed for
OD2.R.2.LPP
N40LP+.
DRC will flag {(CHIP INTERACT DCO_LPP) INTERACT (OD_18 OR OD_33 )}
OD2
O D 2
O D 2
J
O D 2
O D 2
K I K H
A B C
O D N W
N W
J A C T IV E
O D 2
O D 2 E O D 2 O
N W N W
X
PO
PO
O D 2 O D 2
O D R
P Q
N o t a llo w e d ( O D 2 .S .2 ) N W N W
O D 2
D G
O D
L M
PO
PO
B u tte d S tra p O D 2
O D 2
O D 2
A llo w e d ( O D 2 .S .2 )
W
{O D 2 O R {N W S {O D 2 O R {N W
{N W O R N T_N } O R N T _ N }} O R N T _ N }}
4.5.8 Dual Core Oxide (DCO) Layout Rules (Mask ID:

153)
DCO (CAD layer: 90;0) is a layer to cover G core device in N45/40LPG process.
DCO.W.1 Width A  0.34
DCO.W.2 Width of {DCO OR NW}, except SRAMDMY O  0.34
DCO.S.1 Space B  0.34
DCO.S.2 Space to ACTIVE C  0.05
DCO.S.3 Space to LP (core 1.1V) Gate in S/D direction. D  0.16
DCO.S.4 Space to LP (core 1.1V) Gate in end-cap direction. D1  0.09
DCO.S.5 Space to NW. Space = 0 is allowed. E  0.34
DCO.S.6 Space to OD2. Space = 0 is allowed. F  0.34
DCO.S.8 Space of {DCO NOT NW} P  0.34
DCO.S.9 Space of {DCO AND NW} Q  0.34
DCO.S.10 Space of {NW NOT DCO} R  0.34
DCO.EN.1 Enclosure of G (core 0.9V) Gate in S/D direction. G  0.16
DCO.EN.2 Enclosure of G (core 0.9V) Gate in end-cap direction. G1  0.09
DCO.EX.1 NW extension on DCO. Extension = 0 is allowed. H  0.34
DCO.EX.2 Extension on NW. Extension = 0 is allowed. I  0.34
DCO.EX.3 Extension on ACTIVE [Cut is not allowed if without Gate] J  0.05
DCO.A.1 Area M  0.7
DCO.A.2 Enclosed area N  0.7
DCO.O.1 Overlap of NW. Overlap = 0 is allowed. K  0.34
DCO.R.2 Overlap of OD2 is not allowed
DCO.R.3 DCO cut RH is not allowed
DCO
DCO M
J
DCO
B C DCO DCO
K
A I
N
OD OD
NW
DCO
DCO DCO
D C O .R 2
G1 OD2
D
DCO K H
PO
PO
G1
G
NW
D1
F
OD2
RH
DCO DCO
DCO
NW
D C O .R 3
DCO DCO
D G
R
PO
PO
O
NW DCO
OD
NW
DCO
Q
NW
4.5.9 1.2V Core Oxide (OD_12) Layout Rules (Mask ID:

12A)
OD_12 (CAD layer: 14;1) is a layer to cover 1.2V core device in N40G process.
OD_12.W.1 Width A  0.34
OD_12.W.3 Channel length  0.07
OD_12.S.1 Space B  0.34
OD_12.S.2 Space to {ACTIVE OR GATE} C  0.05
OD_12.S.3 Space to core 0.9V Gate in S/D direction. D  0.16
OD_12.S.4 Space to core 0.9V Gate in end-cap direction. D1  0.09
OD_12.S.6 Space to OD2. Space = 0 μm is allowed. F  0.18
OD_12.EN.1 Enclosure of core 1.2V Gate in S/D direction. G  0.16
OD_12.EN.2 Enclosure of core 1.2V Gate in end-cap direction. G1  0.09
OD_12.EX.3 Extension on ACTIVE [Cut is not allowed if without Gate] J  0.05
OD_12.A.1 Area M  0.64
OD_12.A.2 Enclosed area N  0.64
Overlap of VTH_N, VTH_P, VTL_N, VTL_P, RPO, RH, NWDMY, BJTDMY,
OD_12.R.2
OD2 is not allowed
OD_12 cut {ACTIVE OR GATE} is not allowed
OD_12.R.3 (Except OD shared by core and OD_12 is at same potential, DRC can not
exclude this exception.)
OD_12.R.4 Point-touch, one/two track (0.14μm) space and overlap is allow
OD_12
O D _12 M
J
O D _12
B C O D _12
A
N
OD OD
O D _12
O D _12
O D _ 1 2 .R .2
G1 OD2
D
O D _12
PO
PO
G1
G
D1
F
OD2
O D _ 1 2 .R .2
RH
O D _12 O D _12
O D _ 1 2 .R .3
O D _12
X
PO
PO
OD
N o t a llo w e d
4.5.10 OD25_33 Layout Rules

OD25_33 (CAD layer: 18;3) is used for 2.5V overdrive to 3.3V for N45/N40LP and N40G. This is not a mask
layer.
Channel length of 2.5V NMOS overdrive to 3.3V (NMOS Gate AND
OD25_33) for N45LP/N40LP.
OD25_33.W.1.LP A  0.5
It is not shrinkable as the channel length is ≤ 0.545 for N40LP. You have to
draw ≥ 0.55.
OD25_33.W.1.GS A  0.55
OD25_33) for N40G.
Channel length of 2.5V PMOS overdrive to 3.3V (PMOS Gate AND
OD25_33) for N45LP/N40LP.
OD25_33.W.2.LP B  0.4
It is not shrinkable as the channel length is ≤ 0.435 for N40LP. You have to
draw ≥ 0.44.
OD25_33.W.2.GS B  0.44
OD25_33) for N40G.
Channel length of 2.5V native NMOS overdrive to 3.3V. ((Gate AND NT_N)
OD25_33.W.3  1.2
AND OD25_33)
(Gate AND OD25_33) can’t overlap OD_18 or OD_33 or OD25_18. (Gate
OD25_33.R.1 AND OD25_33) must be covered by OD_25. GATE cut OD25_33 is not
allowed.
OD25_33
O D_25 O D 25_33
N M O S G a te P M O S G a te
PO PO
O D O D
A B
O D 2 5 _ 3 3 .R .1
O D 25_33 O D 25_33
PO PO PO
O D O D O D
G a te G a te G a te
O D 25_33
O D _18 or O D _33 or O D 25_18 O D_25

OD25_18 (CAD layer: 18;4) is only used for 2.5V underdrive to 1.8V for N45/N40LP and N40G. This is not a
mask layer.
OD25_18.W.1 Channel length of 2.5V MOS underdrive to 1.8V (Gate AND OD25_18) A  0.25
OD25_18.W.1.GS Channel length of 2.5V PMOS underdrive to 1.8V (Gate AND OD25_18) A  0.27
Channel length of 2.5V native NMOS underdrive to 1.8V ((Gate AND
OD25_18.W.2  1.2
NT_N) AND OD25_18)
(Gate AND OD25_18) can’t overlap OD_18 or OD_33 or OD25_33. (Gate
OD25_18.R.1 AND OD25_18) must be covered by OD_25. GATE cut OD25_18 is not
allowed.
OD25_18
O D_25 O D 25_18
PO PO
OD OD
A A
O D 2 5 _ 1 8 .R .1
O D 25_18 O D 25_18
PO PO PO
OD OD OD
O D 25_18
O D _18 or O D _33 or O D 25_33 O D_25

OD18_15 (CAD layer: 16;4) is only used for 1.8V underdrive to 1.5V in N40G (=45GS) and N40LP process.
This is not a mask layer.
Channel length of 1.8V MOS underdrive to 1.5V (Gate AND OD18_15) for
OD18_15.W.1.GS A  0.105
GS
Channel length of 1.8V MOS underdrive to 1.5V (Gate AND OD18_15) for
OD18_15.W.1.LP A  0.125
N40LP
(Gate AND OD18_15) can’t overlap OD_25 or OD_33 or OD25_18, or
OD18_15.R.1 OD25_33. (Gate AND OD18_15) must be covered by OD_18. OD18_15
can’t cut GATE.
OD18_15.R.2 1.8V and 1.5V cannot share the same NW.
OD18_15
O D_18 O D 18_15
PO PO
OD OD
A A
O D 1 8 _ 1 5 .R .1
O D 18_15 O D 18_15
PO PO PO
OD OD OD
O D 18_15
O D _25 or O D _33or O D 25_18 or D 25_33 O D_18
4.5.13 Poly (PO) Layout Rules (Mask ID: 130)

CAD layer SENDMY (255;8) is used to check PO.DN.4® ~ PO.DN.9® for sensitive circuits. If your IP is sensitive to the
Isat variation due to low/high PO density, you can cover the SENDMY to perform this check.
PO.W.1 Width A  0.04
PO.W.1® U Recommended minimum interconnect PO width A  0.06
Channel length of 2.5V MOS (for 2.5V overdrive to 3.3V, please refer to section OD25_33 Layout
PO.W.2 B  0.27
Rules)
PO.W.3.LP Channel length of 3.3V MOS only for N40LP and N40LPG. C  0.42
Channel length of 1.8 V MOS (For 2.5V underdrive to 1.8V, please refer to section OD25_18 Layout
PO.W.4 D  0.15
Rules. For 1.8V underdrive to 1.5V, please refer to section OD18_15 Layout Rules.)
Channel length of core device for GS 0.04 / 0.045 / 0.05
PO.W.6.GS (This check doesn’t include CDUDMY region and the regions covered by layers of NT_N, SDI, and A = / 0.06 / 0.07 /
VAR.) 0.08~10
Width of 45-degree FIELD PO (except PO fuse element, POFUSE, 156;0). (Please make sure the
PO.W.7 E  0.17
vertex of 45-degree pattern is on 5nm grid (refer to the rule, G.6U, in section 3.7))
PO.W.8 Maximum Channel length of NMOS [for LPG G device] A ≤ 10
PO.S.1 Space F  0.10
PO.S.1® Recommended minimum interconnect PO space to reduce the short possibility caused by particle F  0.12
The poly gate space range to neighboring {PO OR SR_DPO} [for channel length < 0.06μm]. This
allows a violation with a length ratio < 30% on one side and one segment.
0.12 ~ 0.22 or
PO.S.2.LP The length ratio = violation length / device width. G =
0.32
The 0.12 ~ 0.125 are not shrinkable. This rule is for poly gate CDU control
(Except SRAMDMY;0 (186;0) region)
PO.S.2.LP® Recommended GATE space in the same OD to avoid Isat degradation for LP/LPG G  0.14
The poly gate space range to neighboring {PO OR SR_DPO} [for channel length < 0.08 μm], and
allow a violation with a length ratio < 30% on one side and one segment.
The length ratio = violation length / device width.
PO.S.2.GS G = 0.14 / 0.16 / 0.2
This rule is for poly gate CDU control.
(This check doesn’t include the regions covered by layer SRAMDMY;5)
PO.S.2.1LP Gate space [either one channel length  0.06μm] for LP/LPG G1  0.14
PO.S.2.1GS Gate space [either one channel length  0.08 μm] for GS G1  0.14
Maximum gate [channel length  0.08 μm] space to neighboring {PO OR SR_DPO} in core device
PO.S.2.1.1GS regions for GS G1  0.32
(This check doesn’t include the regions covered by layer SR_ESD and LOGO.)
PO.S.3 {GATE inside OD2} space in the same OD H  0.22
FIELD PO space to OD
PO.S.4 I  0.03
(except CSRDMY (166;0) region)
PO.S.4.1 Gate space [L-shape OD and L-shape PO enclosed area < 0.0121 μm2 ] I1  0.11
Recommended gate space [L-shape OD and L-shape PO enclosed area < 0.0196 μm2] for PO/OD
PO.S.4.1® I1’  0.14
rounding effect
Recommended space to L-shape OD when PO and OD are in the same MOS (avoid corner
PO.S.5.LP® J  0.1
rounding effect) for LP/LPG
Recommended space to L-shape OD when PO and OD are in the same MOS (avoid corner
PO.S.5.GS® J  0.06
rounding effect) for GS
L-shape PO space to OD when PO and OD are in the same MOS [L-shape PO length (R1)  0.06
PO.S.6 I2  0.04
μm]
Recommended L-shape PO space to OD when PO and OD are in the same MOS (avoid corner
PO.S.6.LP® K  0.1
rounding effect) for LP/LPG
Recommended L-shape PO space to OD when PO and OD are in the same MOS (avoid corner
PO.S.6.GS® K  0.07
rounding effect) for GS
L-shape PO space to OD when PO and OD are in the same MOS [L-shape PO length > 0.06 μm
PO.S.6.1 I2’  0.05
(R1) and L-shape PO length  0.1 μm (R1)]
Space if at least one {PO OR SR_DPO} width > 0.12 μm, and the {PO OR SR_DPO} parallel run
PO.S.7 L  0.16
length > 0.14 μm (individual projection).
PO.S.9 Space [in same RPO] N  0.18
Space at {PO OR SR_DPO} line-end (W < 0.07 μm (Q1)) in a dense-line-end configuration: If {PO
OR SR_DPO} has parallel run length with opposite {PO OR SR_DPO} (measured with T1 = 0.035
PO.S.10 μm extension) along two adjacent edges of {PO OR SR_DPO} [any one edge < Q1 distance from S1/S2  0.11
the corner of the two edges], then one of the spaces (S1 or S2) needs to be at least this value
(This check doesn't include small jog with edge length < 0.04 μm (R))
Large PO to gate [channel length  0.08 μm] space. The large PO is defined as PO area  630 μm2
PO.S.15 and interacts with regions of density > 70% in window 30 μm x 30 μm, stepping 15 μm. DPO will be  1.0
excluded from density check.
PO.S.16 Space to 45-degree bent {PO OR SR_DPO} M  0.17
Recommended Gate edge [channel length = 0.04um, channel width ≤ 0.2um] space to {(PO OR
PO.S.17® SR_DPO) OR DPO } [width ≥ 0.12um] [projection in S/D direction], and Gate edge parallel run length S0  0.16
(individual projection) in the same gate ≥ 0.1um, for poly gate CDU control
Recommend to add 2nd poly away from 1st poly [for channel length < 0.08μm] (DRC only check 1st
PO.S.18.GS® U = 0.14~0.2
poly space to gate ≤ 0.2um and width < 0.08um)
PO.EX.1 Extension on OD (end-cap) O  0.09
PO.EX.1® Recommended extension on OD (end-cap) to avoid line-end shortening. O  0.11
PO.EX.2 OD extension on PO P  0.09
Recommended OD extension on PO (full and symmetrical contact placement are recommended at
PO.EX.2® both source and drain side) to avoid Isat degradation, especially for channel width > 1.5 μm. P  0.13
When you use poly space = 0.16 μm (PO.S.2), please use = 0.13 μm for this recommendation.
Maximum OD extension on the edge gate [channel length  0.08 μm] in core device regions. (For the
PO.EX.2.1GS edge gate, it is OK to follow either PO.S.2.1.1GS or PO.EX.2.1GS) P1  0.32
This check doesn’t include the regions covered by layer SR_ESD.
Extension on OD (end-cap) when the PO to L-shape OD (in the same MOS) space < 0.1 μm.
PO.EX.3 Q  0.11
(This check doesn’t include ACTIVE jog  0.02 μm.)
Maximum PO length between two contacts, as well as the length from any point inside PO gate to
PO.L.1 the nearest CO when the PO width is < 0.08 μm. (This check doesn’t include ESD protection R  18
devices.)
PO.A.1 Area (This check doesn’t include the pattern filling 0.04 μm x 0.3 μm rectangular tile) S  0.022
PO.A.2 Area [with all of edge length < 0.21 μm] S  0.055
PO.A.3 Enclosed area T  0.04
PO.A.4 Enclosed area [with all of inner edge length < 0.21 μm] T  0.077
PO.DN.1 Minimum {(PO OR DPO) OR SR_DPO} density across full chip  14%
PO.DN.1.1 Maximum {(PO OR DPO) OR SR_DPO} density across full chip  40%
{OD OR DOD OR SR_DOD OR PO OR DPO OR SR_DPO} local density
1. PO.DN.2 is checked by window 20 μm x 20 μm, stepping 10 μm.
2. For PO.DN.2 rules, the following regions can be excluded:
(1) ODBLK/POBLK/NWDMY/LOGO/INDDMY/INDDMY_MD as default
PO.DN.2  0.1%
(2) Chip corner stress relief area if seal-ring and stress relief pattern added by TSMC.
3. Even in areas covered by {ODBLK OR POBLK}, this pattern density that follows the PO.DN.2
rules is recommended.
4. The rule is applied when the width of (checking window NOT item 2) is  5 μm.
PO.DN.3 PO density within POBLK. (except {RFDMY AND RFIP_DMY}, MOMDMY(155;21), and TCDDMY)  14%
It is not recommended the gate interact with the region of {(PO local density < 5%) SIZING 20um}.
The definition of gate is as follows:
1. Channel length ≤ 0.05um
PO.DN.4®  5%
2. {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND RODMY)}
The definition of the region PO local density is as follows:
{(PO OR DPO) OR SR_DPO} local density (window 20umx20um, stepping 10um)
It is not recommended the gate interact with the region of {(PO local density > 35%) SIZING 20um}.
PO.DN.5®  35%
It is not recommended the gate interact with the region of {(PO local density < 15%) SIZING 100um}.
PO.DN.6®  15%
It is not recommended the gate interact with the region of {(PO local density > 35%) SIZING 100um}.
PO.DN.7®  35%
It is not recommended the unsalicided poly resistor interact with the region of {(PO local density <
15%) SIZING 100um}.
The definition of unsalicided poly resistor is as follows:
PO.DN.8®  15%
It is not recommended the unsalicided poly resistor interact with the region of {(PO local density >
40%) SIZING 100um}.
PO.DN.9®  40%
GATE must be a rectangle orthogonal to grid. (Both bent GATE and gate with jog are not allowed).
PO.R.1
(Except CSRDMY region)
PO.R.2U PO line-end must be rectangular. Other shapes are not allowed.
PO.R.4 PO intersecting OD must form two or more diffusions. (Except CSRDMY region)
H-gate that fulfills the following conditions at the same time is not allowed. [inner space < 0.43 μm
PO.R.6 (U), channel length < 0.10 μm (V), interconnect PO width < 0.25 μm (W), and interconnect PO length
> 0.065 μm(X)]
Poly gates of all SRAM cells (50;0 OR 186;0) must be uni-directional in a chip.
PO.R.7 (This check doesn’t include the regions covered by layer 49 (RODMY) and RAM1TDMY (160;0))
Chips on MPW or shuttles may be rotated due to this rule
Floating gate is prohibited if the effective source/drain are not connected together.
Floating gate in the DRC is as follows:

(1) Gate without Poly CO.
(2) Gate with Poly CO but not connected to MOS OD, STRAP or PAD.
PO.R.8 (3) It is not a floating gate if the Gate is connected to OD by butted CO in SRAM bit cell.
The effective source/drain in DRC is as follows:

(1)Source/drain is connected to different {MOSOD NOT PO}, STRAP, Gate, or PAD.
This rule is only checked on the whole chip, not on the IP level.
Poly gates of Pass gate (PG) of all eDRAM cells (RAM1TDMY, 160;0) must be uni-directional in a
PO.R.9
chip.
DPO is a must. DPO CAD layer (TSMC default, 17;1) must be a different layer from the PO CAD
DPO.R.1
layer. Please refer to section 8.2.
Recommend to limit the max interconnect PO length (R) as short as possible to avoid high Rs
PO.L.1gU
variation.
* CAD layer SENDMY (255;8) is used to check PO.DN.4® ~ PO.DN.9® for sensitive circuits. If your IP is sensitive to
the Isat variation due to low/high PO density, you can cover the SENDMY to perform this check.
Table note:
 In order to meet the tight requirement in terms of the complex photo, poly critical dimension (CCD) control
etching process, as well as the PSE layout effect (refer to the section of Layout Guidelines for PSE (Poly
Space Effect), it is important to adopt TSMC DOD//DPO utility to reduce the CD variation, and also
reduce the gap between SPICE model and silicon data.
 Please use POs with the same or similar channel length neighboring with a critical device. For example,
prevent any PO with a larger channel length, eg.  70nm, from neighboring with a critical device’s gate
with the channel length as 40nm.
40nm 40nm >= 70nm
PO OD
PO
F A /B /C /D
I I
G ,G 1 , P O .S .5 R / P O .S .6 R
H
PO
Q J
O
I2 '
N + /P
+
OD
I
P
O
K
P O .S .7
F F
0 .1 4
L > 0 .1 2
T h e fie ld P O to O D s p a c e
C O o n th e P O a x is
I2 '
(0 .0 6 < R 1 = < 0 .1 ) R1 R1
I (R 1 > 0 .1 )
N + /P + N + /P +
> = 0 .1 2 OD OD
R1
I2 (R 1 < = 0 .0 6 )
P O .S .9
P o ly e n d c a p < 0 .1
(0 .0 2 < R 2 = < 0 .0 8 )
RPO
O O
R2 N
O O
P O .S .1 0
P O . S . 4PO.S.4.1 ®
PO.S.4.1/
S1 S1 S1
PO
S1 S1
I1 /I1 ' <

OD
S2 S2 S2 Q1 S2
R e g io n 1 o r 2 c a n n o t h a v e o th e r p o ly
T1 T1
p a tte r n s a t th e s a m e tim e . O n e o f th e m
w ith o th e r p o ly p a tte r n s is a llo w e d .
S1
F T1
F R e g io n 1 R e g io n 2
<Q 1
W <Q 1
T1 T1
S2 T1
S1
<Q 1
S2
W <Q 1
P O .R .6
PO.W.6.GS
P O .W .6 / P O .S .1 6 / P O .L .2
F A
W
V
U
U
E
M X
M PO
F
PO
P O .R .2 P O .R .4
P O .A .1 / P O .A .3
PO OD OD
PO
PO
T
S
PO PO
P O .L .1
W < 0 .0 8 u m
R <= 18um R <= 18um
W < 0 .0 8 u m O D O D O D
R <= 18 um R <= 18 um R <= 18 um R <= 18 um R > 18 um
P O .R .8 N o n - f lo a t in g G a t e
F lo a t in g G a t e F lo a t in g G a t e F lo a t in g G a t e F lo a t in g G a t e F lo a t in g G a t e
PO PO PO
OD OD
OD OD PO
M e ta l M e ta l
M e ta l M e ta l
A llo w e d A llo w e d A llo w e d A llo w e d A llo w e d A llo w e d
F lo a t in g G a t e F lo a t in g G a t e F lo a t in g G a t e
PO PO PO
OD OD OD
B u tte d _
S T R A P.
M e ta l M e ta l M e ta l M e ta l
M e ta l M e ta l
P r o h ib it e d
P r o h ib it e d P r o h ib it e d
S o u r c e / d r a in is c o n n e c t e d t o d iff e r e n t { M O S O D N O T P O } , S T R A P, G a t e , o r P A D .
P O .S .2
L1
C ase A: P a s s d u e to o n e s e g m e n t w ith (L 1 /L ) < 3 0 % .

C ase B: T r u e v io la tio n d u e to tw o s e g m e n t s (O n ly o n e s e g m e n t is a llo w e d ).
C ase C: T r u e v io la tio n d u e to th r e e s e g m e n ts (O n ly o n e s e g m e n t is a llo w e d ).
C ase D: O n e s e g m e n t (L 1 = L 2 + L 3 ). If (L 1 /L ) = 3 0 % , tr u e v io la tio n ; if (L 1 /L ) < 3 0 % , p a s s .
O K , if L 1 /L ( o r L 2 / L a , L 3 / L b ) < 3 0 %
L1
L3 L3
L3
L4
Lb
La
L
L2 L2 L2
0 .1 4 /0 .1 6 /0 .2
L1
P O .S .1 7 ® v io la te pass
P a r a lle l
r u n le n g th
< 0 .1 u m
W 1 > = 0 .1 2 u m
W 0 ( w id th o f p o ly g a te ) < = 0 . 1 2 0 ~ 0 .2 u m . P a r a lle l r u n le n g th
L 0 = 0 .0 4 u m .
> = 0 .1 u m
If S 0 = < 0 .1 6 u m , v io la te .
P O .S .1 8 .G S ®
nd st st nd
2 P o ly 1 P o ly G a te 1 P o ly 2 P o ly
L g < 0 .0 8 u m
U < = 0 .2 < = 0 .2 U
4.5.14 High Vt NMOS (VTH_N) Layout Rules (Mask ID:

11H)
It is not allowed in 1.8V, 2.5V, and 3.3V devices.
VTH_N.W.1 Width A  0.18
VTH_N.S.1 Space B  0.18
VTH_N.S.2 Space to gate in PO endcap direction C  0.08
VTH_N.S.2.1 Space to gate in S/D direction D  0.14
VTH_N.S.3 Space to unsilicided PO/OD resistor E  0.18
VTH_N.EN.1 Enclosure of gate in S/D direction F  0.14
VTH_N.EN.2 Enclosure of gate in PO endcap direction G  0.08
VTH_N.A.1 Area H  0.19
VTH_N.A.2 Enclosed area I  0.19
VTH_N.R.1 Overlap of P+ ACTIVE, VAR, VTL_N, NT_N, or OD2 is not allowed.
VTH_N.R.2 Point touch of corners is allowed.
VTH_N.R.3 One-track overlap / space are allowed. = 0.14
VTH_N.L.1 45-degree edge length  0.5
VTH_N
A
O D P O
N +
I
O D
B
P O P O
C
P W
I
G
P O
O D
D F F D
P O o r O D r e s is to r
p o in t to u c h O n e - tr a c k o v e r la p
V TH _N V TH _N
is a llo w e d is a llo w e d
0 .1 4 u m 0 .1 4 u m
V TH _N X O n e -tra c k s p a c e
V TH _N
is a llo w e d
N o t a llo w e d if s p a c e < 0 .1 8 u m
4.5.15 High Vt PMOS (VTH_P) Layout Rules (Mask ID:

11G)
VTH_P.W.1 Width A  0.18
VTH_P.S.1 Space B  0.18
VTH_P.S.2 Space to gate in PO endcap direction C  0.08
VTH_P.S.2.1 Space to gate in S/D direction D  0.14
VTH_P.S.3 Space to unsilicided PO/OD resistor E  0.18
VTH_P.EN.1 Enclosure of gate in S/D direction F  0.14
VTH_P.EN.2 Enclosure of gate in PO endcap direction G  0.08
VTH_P.A.1 Area H  0.19
VTH_P.A.2 Enclosed area I  0.19
VTH_P.R.1 Overlap of N+ ACTIVE, VAR, VTL_P, NT_N, or OD2 is not allowed.
VTH_P.R.2 Point touch of corners is allowed.
VTH_P.R.3 One-track overlap / space are allowed. = 0.14
VTH_P.L.1 45-degree edge length  0.5
VTH_P
A
O D P O
P +
I
O D
B
P O P O
C
N W
P O I
G
O D
D F F D
P O or O D r e s is to r
V TH _P V TH _P
0 .1 4 u m 0 .1 4 u m
V TH _P X O n e -tra c k s p a c e
V TH _P
is a llo w e d
4.5.16 Low Vt NMOS (VTL_N) Layout Rules (Mask ID:

118)
VTL_N.W.1 Width A  0.18
VTL_N.S.1 Space B  0.18
VTL_N.S.2 Space to gate in PO endcap direction C  0.08
VTL_N.S.2.1 Space to gate in S/D direction D  0.14
VTL_N.S.3 Space to unsilicided PO/OD resistor E  0.18
VTL_N.EN.1 Enclosure of gate in S/D direction F  0.14
VTL_N.EN.2 Enclosure of gate in PO endcap direction G  0.08
VTL_N.A.1 Area H  0.19
VTL_N.A.2 Enclosed area I  0.19
VTL_N.R.1 Overlap of P+ ACTIVE, VAR, VTH_N, NT_N, or OD2 is not allowed.
VTL_N.R.2 Point touch of corners is allowed.
VTL_N.R.3 One-track overlap / space are allowed. = 0.14
VTL_N.L.1 45-degree edge length  0.5
VTL_N
A
O D P O
N +
I
O D
B
P O P O
C
P W
P O I
G
O D
D F F D
V TL_N V TL_N
0 .1 4 u m 0 .1 4 u m
V TL_N X V TL_N O n e -tra c k s p a c e
is a llo w e d
4.5.17 Low Vt PMOS (VTL_P) Layout Rules (Mask ID:

117)
VTL_P.W.1 Width A  0.18
VTL_P.S.1 Space B  0.18
VTL_P.S.2 Space to gate in PO endcap direction C  0.08
VTL_P.S.2.1 Space to gate in S/D direction D  0.14
VTL_P.S.3 Space to unsilicided PO/OD resistor E  0.18
VTL_P.EN.1 Enclosure of gate in S/D direction F  0.14
VTL_P.EN.2 Enclosure of gate in PO endcap direction G  0.08
VTL_P.A.1 Area H  0.19
VTL_P.A.2 Enclosed area I  0.19
VTL_P.R.1 Overlap of N+ ACTIVE, VAR, VTH_P, NT_N, or OD2 is not allowed.
VTL_P.R.2 Point touch of corners is allowed.
VTL_P.R.3 One-track overlap / space are allowed. = 0.14
VTL_P.L.1 45-degree edge length  0.5
VTL_P
A
O D P O
P +
I
O D
B
P O P O
C
N W
P O I
G
O D
D F F D
V TL_P V TL_P
0 .1 4 u m 0 .1 4 u m
V TL_P X O n e -tra c k s p a c e
V TL_P
is a llo w e d
4.5.18 Ultra Low Vt Plus Devices Layout Rules

Ultra low Vt plus devices layout rules, including DCO_LPP, ULVT_N, and ULVT_P layers, are only available for
N40LP+, and not allowed for other technologies.
4.5.18.1 DCO_LPPLUS (DCO_LPP) Layout Rules (Mask ID:

153)
 DCO_LPP (CAD layer: 90;1) is used for ultra low Vt plus devices’ speed boost.
 DCO_LPP is only used for core devices (1.1V). It is not allowed in I/O devices (2.5V).
DCO_LPP.W.1 Width A  0.34
DCO_LPP.S.1 Space B  0.34
DCO_LPP.S.2 Space to ACTIVE C  0.04
Space to {Gate NOT INTERACT (OD2 OR DCO_LPP)} in S/D
DCO_LPP.S.3 D  0.16
direction.
Space to {Gate NOT INTERACT (OD2 OR DCO_LPP)} in end-cap
DCO_LPP.S.4 D1  0.09
direction.
DCO_LPP.S.6 Space to OD2. Space = 0 is allowed. F  0.34
DCO_LPP.EN.1 Enclosure of 1.1V Gate in S/D direction. G  0.16
DCO_LPP.EN.2 Enclosure of 1.1V Gate in end-cap direction. G1  0.09
Extension on ACTIVE [Cut is not allowed if without Gate]
DCO_LPP.EX.3 Cut ACTIVE of TSMC N40LP+ standard cell (90;2, DCODMY_SC) is J  0.04
allowed.
DCO_LPP.A.1 Area, except DCO_LPP.A.1.1 M  0.7
Area [width ≥ 0.42um] for only TSMC N40LP+ standard cell (90;2,
DCO_LPP.A.1.1 M  0.5292
DCODMY_SC)
DCO_LPP.A.2 Enclosed area, except DCO_LPP.A.2.1 N  0.7
Enclosed area [hole width (N1) ≥ 0.42um] for TSMC N40LP+
DCO_LPP.A.2.1 N  0.5292
standard cell (90;2, DCODMY_SC)
Overlap of VAR, VTL_N, VTL_P, VTH_N, VTH_P, NT_N, TCDDMY,
DCO_LPP.R.1
SRM, ROM, or OD2 is not allowed.
DCO_LPP.R.2 {DCO_LPP CUT RH} is not allowed
DCO_LPP.R.3 {Gate AND DCO_LPP} must be covered by {ULVT_N OR ULVT_P}
Point touch of corners is allowed for only TSMC N40LP+ standard cell
DCO_LPP.R.4
(90;2, DCODMY_SC)
One-track overlap / space are allowed for only TSMC N40LP+ 0.14, 0.19,
DCO_LPP.R.5 =
standard cell (90;2, DCODMY_SC) 0.28
If DCODMY_SC exists, DCODMY_SC must be identical to
DCO_LPP.R.6 DCO_LPP. DCODMY_SC can not exist without DCO_LPP.
DCO_LPP can exist without DCODMY_SC.
DCO_LPP
D C O _LPP M
J
D C O _LPP
B C D C O _LPP
A
OD OD
N
N1
DCO _LPP
D C O _ L P P .R .1
G1 OD2
D DCO _LPP
DCO _LPP
G1
PO
PO
D1
F
D C O _ L P P .R .2 OD2
RH
D C O _LPP
DCO _LPP
DCO _LPP
D G
PO
PO
OD
DCO_LPP (90;1) DCO_LPP (90;1)

point touch One-track overlap
is allowed is allowed DCODMY_SC (90;2)
DCODMY_SC (90;2)
DCO_LPP (90;1) 0.14, 0.19, or 0.28um 0.14, 0.19, or 0.28um

X DCO_LPP (90;1)
DCODMY_SC (90;2) One-track space
DCODMY_SC (90;2) is allowed
Not allowed if space < 0.34um
4.5.18.2 Ultra Low Vt Plus NMOS (ULVT_N) Layout Rules

(Mask ID: 11E)
 ULVT_N (CAD layer: 151;1), 1.1V ultra low Vt plus NMOS Implant Definition
 ULVT_N is only used for core devices (1.1V). It is not allowed in I/O devices (2.5V).
ULVT_N.W.1 Width A  0.18
ULVT_N.S.1 Space B  0.18
ULVT_N.S.2 Space to gate in PO endcap direction C  0.08
ULVT_N.S.2.1 Space to gate in S/D direction D  0.14
ULVT_N.S.3 Space to unsilicided PO/OD resistor E  0.18
ULVT_N.EN.1 Enclosure of gate in S/D direction F  0.14
ULVT_N.EN.2 Enclosure of gate in PO endcap direction G  0.08
ULVT_N.A.1 Area H  0.19
ULVT_N.A.2 Enclosed area I  0.19
Overlap of P+ACTIVE, VAR, VTL_N, VTH_N, NT_N, TCDDMY, {OD AND NWDMY}, SRM, ROM,
ULVT_N.R.1
BJTDMY, RH, POFUSE, or OD2 is not allowed.
ULVT_N.R.2 Point touch of corners is allowed.
ULVT_N.R.3 One-track overlap / space are allowed. = 0.14
ULVT_N.R.4 {Gate AND ULVT_N} must be covered by DCO_LPP.
ULVT_N.L.1 45-degree edge length  0.5
ULVT_N
A
O D P O
N +
I
O D
B
P O P O
C
P W
P O I
G
O D
D F F D
p o in t to u c h O n e -tra c k o v e r la p
U L V T _ N U L V T _ N
0 .1 4 u m 0 .1 4 u m
U L V T _ N X U L V T _ N O n e -tra c k s p a c e
is a llo w e d
4.5.18.3 Ultra Low Vt Plus PMOS (ULVT_P) Layout Rules

(Mask ID: 11F)
 ULVT_P (CAD layer: 152;1), 1.1V ultra low Vt plus PMOS Implant Definition
 ULVT_P is only used for core devices (1.1V). It is not allowed in I/O devices (2.5V).
ULVT_P.W.1 Width A  0.18
ULVT_P.S.1 Space B  0.18
ULVT_P.S.2 Space to gate in PO endcap direction C  0.08
ULVT_P.S.2.1 Space to gate in S/D direction D  0.14
ULVT_P.S.3 Space to unsilicided PO/OD resistor E  0.18
ULVT_P.EN.1 Enclosure of gate in S/D direction F  0.14
ULVT_P.EN.2 Enclosure of gate in PO endcap direction G  0.08
ULVT_P.A.1 Area H  0.19
ULVT_P.A.2 Enclosed area I  0.19
Overlap of N+ACTIVE, VAR, VTL_P, VTH_P, NT_N, TCDDMY, {OD AND NWDMY}, {NP
ULVT_P.R.1
INTERACT NWDMY}, SRM, ROM, BJTDMY, RH, POFUSE, or OD2 is not allowed.
ULVT_P.R.2 Point touch of corners is allowed.
ULVT_P.R.3 One-track overlap / space are allowed. = 0.14
ULVT_P.R.4 {Gate AND ULVT_P} must be covered by DCO_LPP.
ULVT_P.L.1 45-degree edge length  0.5
ULVT_P
H
A
O D P O
P +
I
O D
B
P O P O
C
N W
P O I
G
O D
D F F D
p o in t to u c h O n e -tra c k o v e r la p
U L V T _ P U L V T _ P
0 .1 4 u m 0 .1 4 u m
U L V T _ P X O n e -tra c k s p a c e
U L V T _ P
is a llo w e d
4.5.19 P+ Source/Drain Ion Implantation (PP) Layout

Rules (Mask ID: 197)
PP.W.1 Width A  0.18
PP.S.1 Space B  0.18
PP.S.2 Space to N+ ACTIVE (non-butted) C  0.08
PP.S.3 Space to {N+ ACTIVE OR NW STRAP} (butted) D = 0.00
PP.S.4 Space to NW STRAP (non-butted) E  0.02
PP.S.5 {PP edge on OD} space to NMOS GATE F  0.23
Butted PW STRAP space to PO in the same OD [the butted N+ ACTIVE
PP.S.6 G  0.23
extending 0 < J1 < 0.13 μm]
PP.S.7 Space to N-type unsilicided OD/PO resistor H  0.14
PP.EN.1 {NP OR PP} enclosure of PO (except DPO) I  0.11
PP.EX.1 Extension on P+ ACTIVE J  0.08
PP.EX.2 Extension on PW STRAP (except SEALRING_ALL (162;2)) K  0.02
PP.EX.3 Extension on P-type unsilicided OD/PO resistor L  0.14
PP.EX.4 {PP edge on OD} extension on PMOS GATE M  0.23
PP.O.1 Overlap of OD N  0.10
PP.A.1 Area O  0.11
PP.A.2 Enclosed area P  0.11
PP.A.3 Area of butted PW STRAP Q  0.021
PP.R.1 PP must fully cover {PMOS GATE SIZING 0.08 μm} R  0.08
PP.R.2 Overlap of NP is not allowed.
PP.R.3 OD must be fully covered by {NP OR PP} (except DOD and SR_DOD).
PP.R.4 PO must be fully covered by {NP OR PP} (except DPO and SR_DPO).
PP.L.1 45-degree edge length  0.5
PP
PP
PO
R P P
O
J PP
N PP PP
+
A P
+
P
OD
OD
PP
B +
P OD
K
PW
+
P
OD
E I I I
D I I
M
+
N + PO PO PO
N
OD
OD
NW
PW
N ty p e
K
P lo y
Q r e s is to r
+
P
OD
G J1
PO PP
L H
C
D F
K P +
+
N
OD K
OD
P ty p e P lo y
r e s is to r
4.5.20 N+ Source/Drain Ion Implantation (NP) Rules

(Mask ID: 198)
NP.W.1 Width A  0.18
NP.S.1 Space B  0.18
NP.S.2 Space to P+ ACTIVE (non-butted) C  0.08
NP.S.3 Space to {P+ ACTIVE OR PW STRAP} (butted) D = 0.00
NP.S.4 Space to PW STRAP (non-butted) E  0.02
NP.S.5 {NP edge on OD} space to PMOS GATE F  0.23
Butted NW STRAP space to PO in the same OD [the butted P+ ACTIVE
NP.S.6 G  0.23
extending 0 < J1 < 0.13 μm]
NP.S.7 Space to P-type unsilicided OD/PO resistor H  0.14
NP.EN.1 {NP OR PP} enclosure of PO (except DPO) I  0.11
NP.EX.1 Extension on N+ ACTIVE (except NWROD) J  0.08
NP.EX.2 Extension on NW STRAP (except NWROD) K  0.02
NP.EX.3 Extension on N-type unsilicided OD/PO resistor L  0.14
NP.EX.4 {NP edge on OD} extension on NMOS GATE M  0.23
NP.O.1 Overlap of OD N  0.10
NP.A.1 Area O  0.11
NP.A.2 Enclosed area P  0.11
NP.A.3 Area of butted NW STRAP Q  0.021
NP.R.1 NP must fully cover {NMOS GATE SIZING 0.08 μm} R  0.08
NP.R.2 Overlap of PP is not allowed.
NP.R.3 OD must be fully covered by {NP OR PP} (except DOD and SR_DOD).
NP.R.4 PO must be fully covered by {NP OR PP} (except DPO and SR_DPO).
NP.L.1 45-degree edge length  0.5
NP
NP
PO
R
P
O P
J NP
N
NP NP
A N +
OD
N +
OD NP
B +
N OD
K
NW
+
N OD
E I I I
D I I
M
+
P +
OD P PO PO PO
OD
PW
NW
P ty p e P lo y
K r e s is to r
Q
+
N OD
G J1
PO NP
L H
C
D
F
K
+
+ N OD
P OD K
N ty p e P lo y
r e s is to r
4.5.21 Layout Rules for LDD Mask Logical Operations

N1V/N2V/P1V/P2V and VTC_N/VTC_P/VTL_N/VTL_P
As a default, TSMC generates some masking layers from drawn layers by logic operations. These include
N1V/N2V/P1V/P2V and VTC_N/VTC_P/VTL_N/VTL_P masks. The following rules (Fig. 1 - Fig. 6) are defined
to avoid small patterns during mask making.
Warning:
If the rules are not followed, the mask making cycle

time will be seriously impacted.
The following are special requirements.

The minimum extension/clearance between two
d  0.18 μm
corners of two layers
If either dimension X or Y < 0.18 μm (including 0, 2
X/Y (the extension/space between two edges
edges aligned), the other dimension must be  0.18
of two layers in an X/Y)
μm.

LDN.EX.1 NP extension on NW Fig. 1  0.18
LDN.EX.2 NP extension on OD2 Fig. 2  0.18
LDN.EX.3 NP extension on {RH OR BJTDMY} Fig. 1  0.18
LDN.EX.4 NP extension on VAR Fig. 1  0.18
LDN.O.1 NP overlap of OD2 Fig. 3  0.18
LDP.EX.1 PP extension on OD2 Fig. 2  0.18
LDP.EX.2 PP extension on {RH OR BJTDMY} Fig. 1  0.18
LDP.EX.3 PP extension on VAR Fig. 1  0.18
LDP.O.1 PP overlap of NW Fig. 3  0.18
LDP.O.2 PP overlap of OD2 Fig. 3  0.18
VT.S.1 VTL_N space to {OD2 OR NW} Fig. 5  0.18
VT.EX.2 NW extension on {OD2 OR VTL_P} Fig. 6  0.18
LDD Mask
(F ig . 1 ) N P /P P (F ig . 2 ) NP/ PP
Y Y
d d
X X
N W /R H /V A R OD2
(F ig . 3 ) NP/ PP
Y
d
N W /O D 2
(F ig . 5 ) VTL_N (F ig . 6 ) NW
Y Y
d d
X X
(O D 2 O R N W ) (O D 2 O R V T L _ P )
4.5.22 Resist Protection Oxide (RPO) Layout Rules

(Mask ID: 155)
RPO.W.1 Width A  0.40
RPO.S.1 Space B  0.40
RPO.S.2 Space to OD C  0.22
RPO.S.3 Space to CO (overlap of CO is not allowed.) D  0.22
RPO.S.4 Space to GATE (overlap of GATE is not allowed except ESD circuit.) E  0.38
RPO.S.5 Space to PO F  0.30
Extension on unsilicided OD/PO
RPO.EX.1 G  0.22
(This check doesn’t include the regions covered by the layer SDI)
Extension on unsilicided OD/PO [RPO width > 10 μm]
RPO.EX.1.1 G1  0.30
Extension on unsilicided OD/PO [RPO width  0.43 μm]
RPO.EX.1.2 G1  0.30
RPO.EX.2 OD extension on RPO H  0.22
RPO.A.1 Area I  1.00
RPO.A.2 Enclosed area J  1.00
RPO.R.1 Butted NP/PP on unsilicided OD/PO is not allowed.
RPO
H D
RPO
OD
G, C
G1 RPO
E
B
PO A
OD
RPO
R P O .R .1 G, F
G1
PO or O D
PO
D
RPO
N+ P+ N + /P +
J
I J
RPO
RPO
RPO
4.5.23 OD and Poly Resistor Layout Rules

RH layer is required for OD and poly resistors. RH layer is a dummy layer that blocks NLDD or PLDD implants
in the logic operations that generate N1V, N2V, P1V, and P2V.
Unsilicided OD resistor: {{RH AND {RPO AND OD}} AND RPDMY}
Silicided OD resistor: {{{RH AND OD} NOT INTERACT RPO} AND RPDMY}
Unsilicided PO resistor: {{RH AND {RPO AND PO}} AND RPDMY}
Silicided PO resistor: {{{RH AND PO} NOT INTERACT RPO} AND RPDMY}
Rule only for unsilicided resistor
RES.W.1 Width of unsilicided OD/PO resistor. A  0.4
RES.S.1 RH space to Gate in source or drain direction for the unsilicided OD resistor C  0.16
RES.L.1 Length of unsilicided OD/PO resistor B  0.4
Square number (length/width) of unsilicided OD/PO resistor.
RES.R.1  1
(This check doesn’t include the region covered by RHDMY1 (117;4) for non-precision usage)
RES.R.2 RPO intersecting {(PO AND RH) AND RPDMY} must form two or more POs
RES.R.3 RPO intersecting {(OD AND RH) AND RPDMY} must form two or more ODs
Recommended to use rectangle shape resistor for the SPICE simulation accuracy.
RES.R.15g DRC can flag {((RH AND OD) AND RPO) AND RPDMY} or {((RH AND PO) AND RPO) AND RPDMY}
which is not a rectangle.
{RPDMY AND {{OD INTERACT CO} AND RPO}} is recommended being identical to {RH AND {{OD
RES.R.16g
INTERACT CO} AND RPO}}, except BJTDMY.
{RPDMY AND {{PO INTERACT CO} AND RPO}} is recommended being identical to {RH AND {{PO
RES.R.17g
INTERACT CO} AND RPO}}
Rule only for silicided resistor
RES.R.18g Recommend: RPDMY intersecting {(OD AND RH) NOT INTERACT RPO} forms two or more ODs.
RES.R.19g Recommend: RPDMY intersecting {(PO AND RH) NOT INTERACT RPO} forms two or more POs.
RES.R.20g {CO BUTTED ((RPDMY AND RH) NOT INTERACT RPO)} is recommended.
Common rule for unsilicided/silicided resistors
RES.S.2 RH space to GATE (overlap is not allowed)  0.08
RES.EN.1 RH enclosure of unsilicided/silicided OD/PO resistor D  0.19
For unsilicided/silicided PO resistor
RES.R.4
{RPDMY AND PO} must be fully covered by RH
For unsilicided/silicided OD resistor
RES.R.5
{RPDMY AND OD} must be fully covered by RH
NP OD resistor is not allowed interacting with NW.
RES.R.21
DRC will flag {(((OD AND NP) AND RH) AND RPDMY) INTERACT NW}
PP OD resistor is only allowed inside NW.
RES.R.22
DRC will flag {(((OD AND PP) AND RH) AND RPDMY) NOT INSIDE NW}
RH
D o g - b o n e a t th e e n d o f O D / p o ly
r e s is to r fo r c o n ta c t p ic k u p is N O T
RPO
re c o m m e n d e d !!
RPDM Y
D
O D or PO
PO
OD
* P + O D /P o ly r e s is to r w ith R P O ( U n s ilic id e d ) * P + O D /P o ly r e s is to r w ith o u t R P O ( S ilic id e d )

RPO
PP and R H PP and R H
0 .2 2
D D
RPDM Y RPDM Y
O D or PO O D or PO
D
D
A W id th
0 .2 2
B L e n g th
> = 0 .1 4
> = 0 .3
U n - r e la te d im p la n ta tio n
(N P .S .7 )
U n - r e la te d R P O
(R P O .S .2 /R P O .S .5 )
* N + O D /P o ly r e s is to r w ith R P O ( U n s ilic id e d ) * N + O D /P o ly r e s is to r w ith o u t R P O ( S ilic id e d )

RPO
N P and R H N P and R H
0 .2 2
D D
RPDM Y RPDM Y
O D or PO O D or PO
D
D
A W id th
0 .2 2
B L e n g th
> = 0 .1 4
> = 0 .3
U n - r e la te d im p la n ta tio n
(P P .S .7 )
U n - r e la te d R P O
(R P O .S .2 /R P O .S .5 )
4.5.24 HVMOS_25 Layout Rules

The present design rules are dedicated for 5V HVMOS which is fabricated with 2.5V IO Gox. Please be
reminded that these rules are only for N45LP/N40LP/N40LP+, and can not be used for N40G and N45/40LPG
process.
4.5.24.1 HVD_N Layout Rules for HVMOS_25

HVD_N (91;1) is used to define HVNMOS drain side where sustains high voltage.
HVD_N25.W.1 Width A  0.47
Channel width of {Gate INTERACT HVD_N} for SPICE accuracy.
HVD_N25.W.2 N  1.00
≤ 1.110um are non-shrinkable. The exact shrinkable dimension is 1.115um for N40.
HVD_N25.S.1 Space B  0.47
HVD_N25.S.2 Space of two HVD_N with different potentials C  1.37
HVD_N25.S.3 Space to NW D  1.6
HVD_N25.S.4 Space to PW STRAP (overlap is not allowed) E  0.3
HVD_N25.S.5 Space to N+ ACTIVE F  0.6
HVD_N25.S.6 Space to DNW (overlap is not allowed) G  3.0
{CO INSIDE PO} space to {OD AND HVD_N} in PO end-cap direction.
HVD_N25.S.7 Q0  0.52
{CO INSIDE PO} can’t overlap HVD_N.
Gate space in drain direction for a multi-finger HVNMOS device.
HVD_N25.S.8 R = 1.26
DRC checks: {{Space of {Gate INTERACT HVD_N}} INSIDE HVD_N} in one OD.
Gate space in source direction for a multi-finger HVNMOS device.
HVD_N25.S.9 S = 0.22
DRC checks: {{Space of {Gate INTERACT HVD_N}} OUTSIDE HVD_N} in one OD.
{Gate INTERACT HVD_N} space to {NW OR NT_N}.
HVD_N25.S.10 T  2.00
{Gate INTERACT HVD_N} can’t overlap {NW OR NT_N}.
{CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_25} [INSIDE HVD_N].
HVD_N25.S.11 W  0.54
0.54 is non-shrinkable. The exact shrinkable dimension is 0.6 for N40.
HVD_N25.S.12 {PO OR OD} space to {OD INTERACT HVD_N} in PO end-cap direction for high Rs concern X  0.60
{Gate INTERACT HVD_N} enclosure by OD2.
HVD_N25.EN.1 U  2.00
{Gate INTERACT HVD_N} must be inside OD2.
HVD_N25.EX.1 Extension on N+ ACTIVE (Drain side must be fully inside HVD_N) I  0.24
Overlap of {I/O NMOS GATE}.
HVD_N25.O.1 J = 0.30
Channel length of {GATE INTERACT HVD_N}.
HVD_N25.L.1 M  0.8
0.8~0.875 are non-shrinkable. The exact shrinkable dimension is 0.88um for N40.
HVD_N25.A.1 Area K  0.64
HVD_N25.A.2 Enclosed area L  0.64
HVD_N25.R.1 Overlap of NW is not allowed.
HVD_N25.R.2 HVD_N edge landing on OD without landing on GATE is not allowed.
HVD_N25.R.3 HVD_N must be fully inside OD_25.
HVD_N25.R.4 {(OD NOT PO) INSIDE one HVD_N} must be the same potential
For better Idsat uniformity with single finger gate, HVD_N is recommended to be located at the same side of
HVD_N25.R.5® U
the gate.
{{OD OR PO} INTERACT HVD_N} overlap of VAR, NT_N, TCDDMY, {OD AND NWDMY}, SRM, ROM,
HVD_N25.R.7
BJTDMY, RH, or POFUSE is not allowed.
HVD_N for HVMOS_25
NW
PW D
H VD _N
E
PO
I
OD2
PO
OD J
OD
OD M
I PO
DNW
G
F
B ,C
OD
F
K
L L A
H VD _N
H VD _N H VD _N A
H VD _N H VD _N
OD2 OD2
PO PO PO PO PO PO
H VD _N H VD _N H VD _N HVD_N
Q0
OD OD
U
U R R
N
N S S
W
S o u rc e
S o u rc e
D r a in D r a in
X
U
U
X
T T X
{N W O R N T _ N }
OD PO
HVD_N
PO
H V D _ N 2 5 .R .4
OD
m u s t b e th e s a m e p o te n tia l
H V D _ N 2 5 .R .4
PO OD OD
PO PO
OD
HVD_N
PO
OD H V D _ N 2 5 .E X .1
U
H V D _ N 2 5 .R .5 ®
Recom m ended Not Recom m ended
HVD_ HVD_
PO PO
N N
OD OD
HVD_ HVD_
PO PO
N N
OD OD
HVD_ HVD_ HVD_
N N N
OD OD OD OD
PO PO PO PO
HVD_
4.5.24.2 HVD_P Layout Rules for HVMOS_25

HVD_P (91;2) is used to define HVPMOS drain side where sustains high voltage.
HVD_P25.W.1 Width A  0.47
Channel width of {Gate INTERACT HVD_P} for SPICE accuracy.
HVD_P25.W.2 N  1.00
≤ 1.110um are non-shrinkable. The exact shrinkable dimension is 1.115um for N40.
HVD_P25.S.1 Space B  0.47
HVD_P25.S.2 Space of two HVD_P with different potentials C  1.2
HVD_P25.S.4 Space to NW STRAP (overlap is not allowed) E  0.24
HVD_P25.S.5 Space to P+ ACTIVE F  0.48
HVD_P25.S.6 {NW INTERACT HVD_P} space to NW with different potentials. G  2.00
{CO INSIDE PO} space to {OD AND HVD_P} in PO end-cap direction.
HVD_P25.S.7 Q0  0.52
{CO INSIDE PO} can’t overlap HVD_P.
{CO INSIDE PO} space to HVD_P in S/D direction.
HVD_P25.S.8 Q1  0.05
Gate space in drain direction for a multi-finger HVPMOS device.
HVD_P25.S.9 R = 1.26
DRC checks: {{Space of {Gate INTERACT HVD_P}} INSIDE HVD_P} in one OD.
Gate space in source direction for a multi-finger HVPMOS device.
HVD_P25.S.10 S = 0.22
DRC checks: {{Space of {Gate INTERACT HVD_P}} OUTSIDE HVD_P} in one OD.
HVD_P25.S.11 {CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_25} [INSIDE HVD_P]. W  0.54
HVD_P25.S.12 {PO OR OD} space to {OD INTERACT HVD_P} in PO end-cap direction for high Rs concern X  0.60
HVD_P25.EX.1 Extension on P+ ACTIVE (Drian side must be fully inside HVD_P) I  0.24
HVD_P25.EN.1 Enclosure by NW D  0.6
HVD_P25.EN.2 Enclosure by DNW  0.6
{Gate INTERACT HVD_P} enclosure by NW.
HVD_P25.EN.3 T  2.00
{Gate INTERACT HVD_P} must be inside NW.
{Gate INTERACT HVD_P} enclosure by OD2.
HVD_P25.EN.4 U  2.00
{Gate INTERACT HVD_P} must be inside OD2.
Overlap of {I/O PMOS GATE}
HVD_P25.O.1 J = 0.25
Channel length of {GATE INTERACT HVD_P}
HVD_P25.L.1 M  0.6
0.6~0.655 are non-shrinkable. The exact shrinkable dimension is 0.66um for N40.
HVD_P25.A.1 Area K  0.64
HVD_P25.A.2 Enclosed area L  0.64
HVD_P25.R.1 HVD_P must be inside NW
HVD_P25.R.2 HVD_P edge landing on OD without landing on GATE is not allowed.
HVD_P25.R.3 HVD_P must be fully inside OD_25.
HVD_P25.R.4 {(OD NOT PO) INSIDE the same HVD_P} must be the same potential
For better Idsat uniformity with single gate, HVD_P is recommended to be located at the same side of the
HVD_P25.R.5® U
gate.
HVD_P25.R.6 HVD_P must be inside DNW
Only HV PMOS is allowed in {NW INTERACT HVD_P}.
HVD_P25.R.8
DRC flags: {(Gate INSIDE (NW INTERACT HVD_P)) NOT INTERACT HVD_P}.
{{OD OR PO} INTERACT HVD_P} overlap of VAR, NT_N, TCDDMY, {OD AND NWDMY}, {NP INTERACT
HVD_P25.R.9
NWDMY}, SRM, ROM, BJTDMY, RH, or POFUSE is not allowed.
HVD_P for HVMOS_25
NW
OD
OD2
PO
NW
T OD2
Q 0 H VD_P PO PO PO PO PO X
G
OD Q1 U H VD_P H VD_P H VD_P
N OD
T
W U R R
N S S
U
S o u rc e
S o u rc e
T D r a in D r a in
X
H V D _ P 2 5 .R .8 U
OD2
PO T X
PO
OD G
OD PO
NW
G
HVD_P
PO
H V D _ P 2 5 .R .4
OD
H V D _ P 2 5 .R .4
PO OD OD
PO PO
OD
HVD_P
PO
OD H V D _ P 2 5 .E X .1
U
H V D _ P 2 5 .R .5 ®
HVD_ HVD_
PO PO
P P
OD OD
HVD_ HVD_
PO PO
P P
OD OD
HVD_ HVD_ HVD_
P P P
OD OD OD OD
PO PO PO PO
HVD_
4.5.25 HVMOS_18 Layout Rules

The present design rules are dedicated for 5V HVMOS_18, which is fabricated with 1.8V IO Gox. HVMOS_18
is only offered for N40LP. None of N45LP, N40LP+, N40G, and N45/N40LPG processes can use HVMOS_18.
4.5.25.1 HVD_N Layout Rules for HVMOS_18

HVD_N (91;1) is used to define HVNMOS drain side where sustains high voltage.
HVD_N18.W.1 Width A  0.47
HVD_N18.W.2 Channel width of {Gate INTERACT HVD_N} for SPICE accuracy. N  0.67
HVD_N18.S.1 Space B  0.47
HVD_N18.S.2 Space of two HVD_N with different potentials C  1.37
HVD_N18.S.3 Space to NW D  1.6
HVD_N18.S.4 Space to PW STRAP (overlap is not allowed) E  0.3
HVD_N18.S.5 Space to N+ ACTIVE F  0.6
HVD_N18.S.6 Space to DNW (overlap is not allowed) G  3.0
{CO INSIDE PO} space to {OD AND HVD_N} in PO end-cap direction.
HVD_N18.S.7 Q0  0.52
{CO INSIDE PO} can’t overlap HVD_N.
Gate space in drain direction for a multi-finger HVNMOS device.
HVD_N18.S.8 DRC checks: {{Space of {Gate INTERACT HVD_N}} INSIDE HVD_N} in R = 1.26
one OD.
Gate space in source direction for a multi-finger HVNMOS device.
HVD_N18.S.9 DRC checks: {{Space of {Gate INTERACT HVD_N}} OUTSIDE HVD_N} S = 0.22
in one OD.
{Gate INTERACT HVD_N} space to {NW OR NT_N}.
HVD_N18.S.10 T  2.00
{Gate INTERACT HVD_N} can’t overlap {NW OR NT_N}.
{CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_18}
HVD_N18.S.11 W  0.6
[INSIDE HVD_N].
{PO OR OD} space to {OD INTERACT HVD_N} in PO end-cap direction
HVD_N18.S.12 X  0.60
for high Rs concern
{Gate INTERACT HVD_N} enclosure by OD2.
HVD_N18.EN.1 U  2.00
{Gate INTERACT HVD_N} must be inside OD2.
HVD_N18.EX.1 Extension on N+ ACTIVE (Drain side must be fully inside HVD_N) I  0.24
HVD_N18.O.1 Overlap of {I/O NMOS GATE}. J = 0.33
HVD_N18.L.1 Channel length of {GATE INTERACT HVD_N}. M  0.88
HVD_N18.A.1 Area K  0.64
HVD_N18.A.2 Enclosed area L  0.64
HVD_N18.R.1 Overlap of NW is not allowed.
HVD_N18.R.2 HVD_N edge landing on OD without landing on GATE is not allowed.
HVD_N18.R.3 HVD_N must be fully inside OD_18.
HVD_N18.R.4 {(OD NOT PO) INSIDE one HVD_N} must be the same potential
For better Idsat uniformity with single finger gate, HVD_N is
HVD_N18.R.5® U
recommended to be located at the same side of the gate.
{{OD OR PO} INTERACT HVD_N} overlap of VAR, NT_N, TCDDMY,
HVD_N18.R.7 {OD AND NWDMY}, SRM, ROM, BJTDMY, RH, or POFUSE is not
allowed.
HVD_N for HVMOS_18
NW
PW D
H VD _N
E
PO
OD2 I
PO
J
OD
OD
I
OD M
I PO
DNW
G
F
B ,C
OD
F
K
L L A
H VD _N
H VD _N H VD _N A
H VD _N H VD _N
OD2 OD2
PO PO PO PO PO PO
Q0 H VD _N H VD _N H VD _N HVD_N
OD OD
U
U R R
N
N S S
W
S o u rc e
S o u rc e
D r a in D r a in
X
U
U
X
T T X
{N W O R N T _ N }
OD PO
HVD_N
PO
H V D _ N 1 8 .R .4
OD
H V D _ N 1 8 .R .4
PO OD OD
PO PO
OD
HVD_N
PO
OD H V D _ N 1 8 .E X .1
U
H V D _ N 1 8 .R .5 ®
HVD_ HVD_
PO PO
N N
OD OD
HVD_ HVD_
PO PO
N N
OD
OD
HVD_ HVD_ HVD_
N OD N OD N OD OD
PO
PO PO PO
HVD_
4.5.25.2 HVD_P Layout Rules for HVMOS_18

HVD_P (91;2) is used to define HVPMOS drain side where sustains high voltage.
HVD_P18.W.1 Width A  0.47
HVD_P18.W.2 Channel width of {Gate INTERACT HVD_P} for SPICE accuracy. N  0.67
HVD_P18.S.1 Space B  0.47
HVD_P18.S.2 Space of two HVD_P with different potentials C  1.2
HVD_P18.S.4 Space to NW STRAP (overlap is not allowed) E  0.24
HVD_P18.S.5 Space to P+ ACTIVE F  0.48
HVD_P18.S.6 {NW INTERACT HVD_P} space to NW with different potentials. G  2.0
{CO INSIDE PO} space to {OD AND HVD_P} in PO end-cap direction.
HVD_P18.S.7 Q0  0.52
{CO INSIDE PO} space to HVD_P in S/D direction.
HVD_P18.S.8 Q1  0.05
Gate space in drain direction for a multi-finger HVPMOS device.
HVD_P18.S.9 DRC checks: {{Space of {Gate INTERACT HVD_P}} INSIDE HVD_P} in one R = 1.82
OD.
Gate space in source direction for a multi-finger HVPMOS device.
HVD_P18.S.10 DRC checks: {{Space of {Gate INTERACT HVD_P}} OUTSIDE HVD_P} in one S = 0.22
OD.
{CO INSIDE drain side OD} space to {HVD GATE OVERLAP OD_18} [INSIDE
HVD_P18.S.11 W  0.88
HVD_P].
{PO OR OD} space to {OD INTERACT HVD_P} in PO end-cap direction for
HVD_P18.S.12 X  0.60
high Rs concern
HVD_P18.EX.1 Extension on P+ ACTIVE (Drian side must be fully inside HVD_P) I  0.24
HVD_P18.EN.1 Enclosure by NW D  0.6
HVD_P18.EN.2 Enclosure by DNW  0.6
{Gate INTERACT HVD_P} enclosure by NW.
HVD_P18.EN.3 T  2.00
{Gate INTERACT HVD_P} must be inside NW.
{Gate INTERACT HVD_P} enclosure by OD2.
HVD_P18.EN.4 U  2.00
{Gate INTERACT HVD_P} must be inside OD2.
HVD_P18.O.1 Overlap of {I/O PMOS GATE} J = 0.28
HVD_P18.L.1 Channel length of {GATE INTERACT HVD_P} M  0.66
HVD_P18.A.1 Area K  0.64
HVD_P18.A.2 Enclosed area L  0.64
HVD_P18.R.1 HVD_P must be inside NW
HVD_P18.R.2 HVD_P edge landing on OD without landing on GATE is not allowed.
HVD_P18.R.3 HVD_P must be fully inside OD_18.
HVD_P18.R.4 {(OD NOT PO) INSIDE the same HVD_P} must be the same potential
For better Idsat uniformity with single gate, HVD_P is recommended to be
HVD_P18.R.5® U
located at the same side of the gate.
HVD_P18.R.6 HVD_P must be inside DNW
Only HV PMOS is allowed in {NW INTERACT HVD_P}.
HVD_P18.R.8 DRC flags: {(Gate INSIDE (NW INTERACT HVD_P)) NOT INTERACT
HVD_P}.
{{OD OR PO} INTERACT HVD_P} overlap of VAR, NT_N, TCDDMY, {OD
HVD_P18.R.9 AND NWDMY}, {NP INTERACT NWDMY}, SRM, ROM, BJTDMY, RH, or
POFUSE is not allowed.
HVD_P for HVMOS_18

PW
NW
N W / D
DNW E
H VD _P
PO
OD2 I
PO
J
OD
I
OD
OD M
I PO
F
B ,C
OD
K F
L L A
H VD _P
A
H VD _P H VD _P
H VD _P
H VD _P
NW
OD2
PO OD
T Q 0 H VD _P NW
OD2
G PO PO PO PO PO X
OD Q1 U
N HVD_P H VD_P HVD_P

T
W OD
U U R R
N S S
S o u rc e
S o u rc e
T D r a in D r a in
X
H V D _ P 1 8 .R .8 U
OD2
PO T X
PO
OD G
OD PO
NW
G
HVD_P
PO
H V D _ P 1 8 .R .4
OD
H V D _ P 1 8 .R .4
PO OD OD
PO PO
OD
HVD_P
PO
OD H V D _ P 1 8 .E X .1
U
H V D _ P 1 8 .R .5 ®
HVD_ HVD_
PO PO
P P
OD OD
HVD_ HVD_
PO PO
P P
OD OD
HVD_ HVD_ HVD_
P OD P OD P OD OD
PO
PO PO PO
HVD_
4.5.26 HVMOS Guard-Ring Rules and Guidelines for

HVMOS_25 and HVMOS_18
It is not allowed placing HV NMOS and HV PMOS inside the same guard-ring (Either P+ or N+ OD
HVD_GR.R.1
guard-ring)
Every HV NMOS must be surrounded by the P+/PW guard-ring as PW strap.
HVD_GR.R.2U
The P+ guard-ring must to be connected to Vss.
Every HV PMOS must be surrounded by the N+/NW guard-ring as NW strap.
HVD_GR.R.3U
The N+ guard-ring must to be connected to Vdd.
HVD_GR.R.4U Please put Contact (CO) as many as possible in the P+ and N+ guard-rings.
Any point inside HV NMOS source/drain {(N+ ACTIVE INTERACT (PO INTERACT HVD_N)) NOT
PO} space to the nearest P+/PW guard-ring (PW STRAP) in the same PW.
HVD_GR.R.5 A  30
Any point inside HV PMOS source/drain {(P+ ACTIVE INTERACT (PO INTERACT HVD_P)) NOT
PO} space to the nearest N+/NW guard-ring (NW STRAP) in the same NW.
HVD_GR.R.6 {{HV N/PMOS OR HVMOS guard-ring} INTERACT RPO} is not allowed.
Recommend reducing the breach region of M1 on guard-ring if using M1 to connect HV N/PMOS
HVD_GR.R.7® U
to outside circuits.
G u a r d -r in g (O D ) G u a r d -r in g (O D )
A
A
A
A A
A
A
4.5.27 MOS Varactor Layout Rules (VAR)

N45LP/N40LP N40LP+ N40LPG N45LPG N40G (= N45GS)
VAR
1.1V 1.8V 2.5V 1.1V 2.5V 0.9V 1.1V 3.3V 0.9V 1.1V 1.8V 0.9V 1.2V 1.8V 2.5V
BB NVAR    X X          
model PVAR X X X X X X X X X X X  X  
RF NVAR    X X X X X X X X  X  
model PVAR * * * X X X X X X X X  X  
*: Only offer in N40LP
NVAR: NMOS in NW
PVAR: PMOS in PW
VAR: Customer must provide this layer (CAD layer: 143) to generate LDD masks by logic operations, if the
MOS varactor is used.
VAR.W.1 Channel length of {gate AND VAR} A  0.2
VAR.W.3 Channel length of {(gate AND OD2) AND VAR} A  0.4
VAR.W.4 Channel width of {gate AND VAR} G  0.32
VAR.S.1 Space to ACTIVE B  0.13
Maximum core unit varactor gate area (um2) (varactor gate area = {((OD AND PO)
VAR.A.1 H  25
AND VAR) NOT OD2}) [for N40G process and LPG G device]
VAR.EN.1 Enclosure of OD (Cut is not allowed) D  0.16
VAR layer must be drawn to fully cover the varactor devices.
VAR.R.1
DRC only checks VAR fully cover gate.
VAR.R.2 Overlap of VTL_N, VTL_P, VTH_N, VTH_P, NT_N, or RPO is not allowed.
VAR.R.3 PP overlap of {(gate AND NW) AND VAR} is not allowed.
VAR.R.3.1 NP overlap of {(gate AND PW) AND VAR} is not allowed.
VAR.R.4 Overlap to {(PO AND ACTIVE) SIZING 0.16 μm} is not allowed
NP must fully cover {(((VAR AND (GATE AND NW)) SIZING 0.19 μm) AND OD)
VAR.R.5
SIZING 0.13 μm }
PP must fully cover {(((VAR AND (GATE AND PW)) SIZING 0.19 μm) AND OD)
VAR.R.5.1
SIZING 0.13 μm }
Table note:
 Due to the intrinsic gate leakage, you need to do SPICE simulation carefully while large area of MOS varactor
is designed in the thin oxide area, and it is recommended to design the varactor in the thick oxide area to
reduce the leakage (AN.R.20mg).
N
NVVA
ARR
D VAR VAR
PO NP PO
X X'
NP
OD OD
G
B NW NW
X -X ' c r o s s -s e c tio n
PO
PO
OD STI STI
NP NP
0 .1 6 0 .1 6 M O S
NW
VAR
V A R .R .4
VAR.A.1
H H
H
P
PVVA
ARR
D VAR VAR
PO PP PO
X X'
PP
OD OD
G
B PW PW
X -X ' c r o s s -s e c tio n
PO
PO
OD STI STI
PP PP
0 .1 6 0 .1 6 M O S
PW
VAR
V A R .R .4
4.5.28 Contact (CO) Layout Rules (Mask ID: 156)

CO.W.1 Width (maximum = minimum) (Except butted CO in SRAMDMY;0 (186;0) region only) A = 0.06
CO.S.1 Space (Except SRAMDMY;0 (186;0) region) B  0.08
CO.S.2 Space to 3-neighboring CO (distance < 0.11 μm) (Except SRAMDMY;0 (186;0) region) C  0.10
CO.S.2.1 Space [different net] (Except SRAMDMY;0 (186;0) region) B1  0.11
Space to GATE (Overlap of GATE is not allowed) [space  0.035 μm is allowed inside SRAM word line driver
CO.S.3 D  0.04
covered by layer 186;5 or 186;4] (Except SRAMDMY;0 (186;0) region)
CO.S.3® Recommended space to gate to reduce the short possibility caused by particle. D  0.05
CO.S.4 {CO inside PO} space to OD (Except SRAMDMY;0 (186;0) region) E  0.05
CO.S.5 {CO inside OD} space to I/O GATE F  0.08
CO.S.6 Space to butted PP/NP edge on OD (overlap of NP/PP boundary on OD is not allowed.) G  0.04
Maximum effective CO space in Source/Drain of device [channel width1 μm] (This check doesn't include
the regions covered by SR_ESD and SDI.)
Definition of effective CO: (1) CO projection space to GATE0.22 μm (D2). (2) {COs INSIDE {HVD_N OR
HVD_P}} which projection space to GATE 1 μm.
CO.S.7® Definition of maximum effective CO space (B3): Channel width – effective CO projection length to GATE. B3  0.29
Besides, if there is no CO in Source/Drain or no CO connected to Source/Drain by OD, it is allowed. {CO
OUTSIDE {HVD_N OR HVD_P}} projection space to PO (without CO shielding) > 0.22 μm or {COs INSIDE
{HVD_N OR HVD_P}} projection space to PO (without CO shielding) > 1 μm for HVMOS drain side will be
flagged on gate.
Enclosure by PO is defined by either {CO.EN.2 and CO.EN.3} or {CO.EN.5 and CO.EN.6}. (Except
CO.EN.0 SRAMDMY;0 (186;0) region)
Enclosure by OD is defined by either {CO.EN.1 and CO.EN.1.1}, {CO.EN.1 and CO.EN.1.2}, or {CO.EN.1.3}.
CO.EN.0® Recommended enclosure by OD is defined by {CO.EN.1® and CO.EN.1.1® }.
CO.EN.1 Enclosure by OD (Except SRAMDMY;0 (186;0) region) H  0.01
CO.EN.1® Recommended enclosure by OD to avoid high Rc H  0.03
Enclosure by OD, except {STRAP NOT VAR} [at least two opposite sides] (Except Butted CO in SRAMDMY;0
CO.EN.1.1 H1  0.03
(186;0) region only)
CO.EN.1.1® Recommended enclosure by OD [at least two opposite sides] H1  0.04
CO.EN.1.2 Enclosure by OD for {STRAP NOT VAR} [at least two opposite sides] H3  0.02
Enclosure by OD [four sides] , except {STRAP NOT VAR} (Except Butted CO in SRAMDMY;0 (186;0) region
CO.EN.1.3 L  0.02
only)
CO.EN.2 Enclosure by PO (Except SRAMDMY;0 (186;0) region) J  0.01
CO.EN.3 Enclosure by PO [at least two opposite sides] (Except SRAMDMY;0 (186;0) region) K  0.02
CO.EN.3® Recommended enclosure by PO [at least two opposite sides] to avoid high Rc. K  0.04
Enclosure by PO [0.005 um at one side and the opposite side is 0.015 um] (Except SRAMDMY;0 (186;0) 0.005
CO.EN.5 J1 
region) / 0.015
CO.EN.6 Enclosure by PO [at least two opposite sides] (Except SRAMDMY;0 (186;0) region) K1  0.03
CO.R.2 Overlap of RPO is not allowed.
CO.R.3 45-degree rotated CO is not allowed.
CO.R.4 CO must be fully covered by M1 and {(OD OR PO) OR SR_DPO}.
Recommended to put contacts at both source side and butted well pickup side to avoid high Rs. DRC can flag
CO.S.6g
if the STRAP is butted on source, one of STRAP and source is without CO.
Recommended to put {CO inside PO} space to GATE as close as possible to avoid unexpected resistance
CO.R.1gU
variation.
Recommend using redundant CO to avoid high Rc wherever layout allows
1. Recommended to use double CO or more on the resistor connection.
2. Double CO on Poly gate to reduce the probability of high Rc
CO.R.5g 3. For large transistor, if it is impossible to increase the CO to gate spacing (CO.S.3® ), limit the number of
source/drain CO: have the number of CO necessary for the current, and then spread them uniformly all
over the Source/Drain area.
4. DRC can flag single CO.
CO
D, F
G C o n ta c t o n N P /P P b o u n d ry
P+
N o n - s a lic id e C o n ta c t
c o n ta c t o n P o ly
PRO
B
O
45 C o n ta c t
N+ P+ P+
E
G
PO
K K
J
H
J
H1 L
H1 L
K1
K L
K1
K
0 .0 0 5 = J 1 J 1 = 0 .0 1 5
J J [o r 0 .0 1 5 ] [o r 0 .0 0 5 ] C
A A A C C C
B B
C C
B B
B 2 - n e ig h b o r in g C O B
C C
C
2 - n e ig h b o r in g C O 2 - n e ig h b o r in g C O s C
A
A
C A
C C
C
C C 3 - n e ig h b o r in g C O
4 - n e ig h b o r in g C O
3 X 3 C O a rra y
B 1
B
B 1
C O s p a c e to n e ig h b o r in g C O in th e
s a m e n e t o r in th e d iffe r e n t n e t
CO.S.7®
S S S S S
G G G G G G G
D D D D D D D
F u lly -C O U n ifo r m -C O P a r tia l-C O P a r tia l-C O P a r tia l-C O P a r tia l-C O
B3 B3  0.29
> 0.29
11
D2
B3 B3  0.29
1
> 0.29
B3 B3  0.29
 0.29 >
B3 B3 OD OD OD
0.29
O O X X PO PO
PO DRC won’t flag it. DRC will flag it.
4.5.29 Metal-1 (M1) Layout Rules (Mask ID: 360)

M1.W.1 Width A  0.07
Width of 45-degree bent M1. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid (refer to
M1.W.2 B  0.17
the guideline, G.6gU, in section 3.7))
Maximum width
M1.W.3 C  4.50
(This check doesn’t include the SEALRING_ALL (162;2) region)
M1.S.1 Space D  0.07
M1.S.1® Recommended space to reduce the short possibility caused by particle D  0.09
M1.S.1.1 Space [any one of Mx connects to > 3.3V and  5V net]  0.09
Space [at least one metal line width > 0.17 μm (W1) and the parallel metal run length > 0.27 μm (L1)] (union
M1.S.2 E  0.08
projection)
M1.S.2.1 E1  0.12
projection)
M1.S.2.2 E2  0.14
projection)
M1.S.2.3 F  0.21
projection)
M1.S.3 G  0.50
projection)
Space at M1 line-end (W < 0.09 μm, Q = 0.07 μm) in a dense-line-end configuration: If M1 has parallel run
length with opposite M1 (measured with T = 0.025 μm extension) along two adjacent edges of M1 [any one
edge < Q distance from the corner of the two edges], then one of the spaces (S1 or S2) needs to be at least
M1.S.5 S1/S2  0.08
this value
(This check doesn't include small jog with edge length < 0.07 um(R))
M1.S.6 Space to 45-degree bent M1 H  0.17
M1.S.8 Space to VIA1 [different net, either VIA1 or M1 connects to 1.8V ~ 3.3V net]  0.1
M1.S.8.1 Space to VIA1 [different net, either VIA1 or M1 connects to  1.5V and < 1.8V net]  0.08
M1.S.8.2 Space to VIA1 [different net, either VIA1 or M1 connects to > 3.3V and  5V net]  0.18
This rule is to check the Metal (A) space with the neighboring VIA1 [either VIA1 or M1 connects to > 3.3V and
 5V net].
The DRC methodology to find Metal (A) is as follows:
Find an edge (B) of the metal line-end [edge length  0.12um]
M1.S.9 S  0.15
Run length (C) from edge (B) inside metal  0.13um
Jog length (D)  0.01um within 0.13um run length
Extend 0.06um outside from edge (B) to form a polygon metal (A)
Metal (A) is defined if conditions 1~4 are all satisfied.
M1.EN.0 Enclosure of CO is defined by either {M1.EN.1 and M1.EN.2} or M1.EN.3 or {M1.EN.3.1 and M1.EN.3.2}.
M1.EN.0® Recommended enclosure of CO is defined by either M1.EN.1® or M1.EN.2® .
M1.EN.1 Enclosure of CO (Except Butted CO in SRAMDMY;0 (186;0) and CSRDMY (166;0) regions) I  0.00
M1.EN.1® Recommended enclosure of CO to avoid high Rc I  0.03
M1.EN.2 Enclosure of CO [at least two opposite sides] (Except SRAMDMY;0 (186;0) and CSRDMY (166;0) regions) J  0.03
M1.EN.2® Recommended enclosure of CO [at least two opposite sides] to avoid high Rc. J  0.05
M1.EN.3 Enclosure of CO [four sides] (Except SRAMDMY;0 (186;0) and CSRDMY (166;0) regions) K  0.02
M1.EN.3.1 Enclosure of CO (Except SRAMDMY;0 (186;0) and CSRDMY (166;0) regions) K1  0.005
M1.EN.3.2 Enclosure of CO [at least two opposite sides] (Except SRAMDMY;0 (186;0) and CSRDMY (166;0) regions) K2  0.025
M1.EN.4 Enclosure of CO [M1 width > 0.7 μm] (except CSRDMY (166;0) region) L  0.03
Enclosure of CO [metal width  0.11μm, space < 0.08 μm and parallel run length > 0.27 μm]
M1.EN.5 M  0.015
(This check doesn't include two or more COs present in the metal intersection)
Recommended Enclosure of CO [metal width  0.11μm, space < 0.08μm] to avoid high Rc
M1.EN.5® M  0.015
M1.A.1 Area (Except SRAMDMY;0 (186;0) region) O  0.0215
M1.A.1® Recommended area to avoid high Rc (except DMx_O) O  0.0351
Area [with all of edge length < 0.17 μm].
M1.A.2 (This check doesn't include the patterns filling 0.07 μm x 0.17 μm rectangular tile) (Except SRAMDMY;0 O  0.055
(186;0) region)
M1.A.3 Enclosed area Q1  0.2
For the following M1.DN.1, M1.DN.1.1, M1.DN.4, and DM1.R.1, please refer to the "Dummy Metal Rules"
M1.DN.0
section in Chapter 8 for the details.
M1.DN.1 Minimum metal density in window 125 μm x 125 μm, stepping 62.5 μm  10%
M1.DN.1.1 Maximum metal density in window 125 μm x 125 μm, stepping 62.5 μm  85%
The metal density difference between any two neighboring checking windows including DMxEXCL [window
200 μm x 200 μm, stepping 200 μm]
M1.DN.4  50%
Anticipate metal density gradient from layout of small cell by targeting density ~40% (this way, it will limit the
risk of low density and of high gradient)
Metal density  1%must be followed for items (A) to (C).
(A) Metal density [window 80 μm x 80 μm, stepping 40 μm]  1%
(B) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density <
1%] ≤ 6400um2, except the merged low density windows width ≤ 30um.
(C) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density <
M1.DN.6 1%] ≤ 18000um2.
1. The following special regions are excluded while the density checking:
- Chip corner triangle empty areas if sealring is added by tsmc.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is  40um for (A) and
 5um for both (B)/(C).
Recommend metal density  1% for IP level. Items (A) to (C) are recommended.
(A) For IP level, recommend metal density [window 40 μm x 40 μm, stepping 40 μm]  1%. This item is applied
for {IP NOT (IP SIZING -40um)} region when the width of IP is  40um.
(B) For IP level, recommend maximum area of merged low density windows [checking window 10umx10um,
stepping 5um, density < 1%] ≤ 1600um2, except the merged low density windows width ≤ 30um. This item is
applied for {IP NOT (IP SIZING -10um)} region when the width of IP is  10um.
(C) For IP level, recommend maximum area of merged low density windows [checking window 10umx10um,
M1.DN.6®
stepping 5um, density < 1%] ≤ 4500um2. This item is applied for {IP NOT (IP SIZING -10um)} region when the
width of IP is  10um.
- LOWMEDN
DM1.R.1 DM1 is a must. The DM1 CAD layer must be different from the M1 CAD layer.
M1.R.1U M1 line-end must be rectangular. Other shapes are not allowed.
M1.R.2 Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
Table Notes:
 Although tsmc provides 5V metal and Via related rules, tsmc does not offer any 5V device for FEOL,
except HVMOS (only drain side can be applied to 5V).
 To improve the metal CMP process window, you must fill the DM1 globally and uniformly even if the originally
drawn M1 has already met the density rules (M1.DN.1 and M1.DN.1.1). For sensitive areas with auto-fill operations
blocked by the DM1EXCL layer, it is recommended filling dummy pattern evenly by manual operations to gain a
better process window and electrical performance.
 During IP/macro design, it is important to put certain density margin to avoid the possibility of high density
violations (M1.DN.1, M1.DN.1.1) during placement. It may have unexpected violation during the IP/macro
placement due to the environment, even if the IP/macro already pass the high density rule check. Therefore, you
need to carefully design the dimension of the width/space for wide metal (eg, power/ground bus), under the proper
high density limit.
 M1.DN.6®: For IP level, recommend metal density ≥ 1% to reduce M1.DN.6 DRC violation in chip level.
 M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9.
o Make sure to add correct marker layers to let DRC check the high voltage rules correctly.
 Data-types 200 to 218 of each metal layer are reserved for the nets of voltage ranging from 0V to 1.8V in
0.1V step. Data-types 219, 220, and 221 are assigned for I/O voltage 2.5V, 3.3V, and 5V, respectively.
 The net voltage is defined by the corresponding marker layers. The net voltage cannot be recognized by
incorrect marker layers. That means, if a marker layer (33;218) is on M3, then this net will be recognized as
an 1.8V net, but it cannot be recognized if a marker layer (32;218) is on M3.
 Higher voltage marker layers have higher priority, e.g. the M3 net will be recognized as an 1.8V net if there
are two marker layers as (33;215) and (33;218) on it.
o The DRC methodology for the high voltage check:

 Marker layers have higher priority than MOS connection.
 The M3 net will be recognized as an 1.8V net if there is (33;218), even if this net does not connect to a
MOS inside OD2.
 The M3 net will be recognized as a low-voltage net ( 1.2V) if there is a marker layer of
(33;200~212), even if this net connects to a MOS inside OD2.
 The M3 net will be recognized as an 1.8V net if there is (33;218) and this net connects to a MOS inside
OD2 and a core MOS simultaneously.
 M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9 will be checked for the nets with voltage > 1.2V
defined by marker layers. Nets with voltage  1.2V will be excluded.
 If a net without any marker layers,
 M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9 will be checked when the net connects only to a MOS
inside OD2.
 If a net connects to an IO MOS & a core MOS simultaneously,
o If the DRC option of Mx_S_8_IO_NET is off (default), it will be recognized as low voltage and will
not check M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9.
o If the DRC option of Mx_S_8_IO_NET is on (not default), it will be recognized as a high voltage net
and will check M1.S.1.1, M1.S.8, M1.S.8.1, M1.S.8.2, and M1.S.9.
 The following summary tables list the high/low voltage net recognition results for the different combinations
of high voltage marker layers and the DRC option:
Mx net connection if Mx_S_8_IO_NET is OFF
Voltage net recognition
Core MOS IO MOS Metal high voltage markers (Data-types 213~221)
Y Y Y
Y N Y
High voltage
N Y Y
N Y N
Y Y N
Low voltage
Y N N
Mx net connection if Mx_S_8_IO_NET is ON

Y Y Y
Y N Y
N Y Y High voltage
N Y N
Y Y N
Y N N Low voltage
 The net without any marker layers will be recognized as a VSS net if there is PW STRAP connected, even
if the PW STRAP is inside OD2. But PW STRAP inside DNW (RW STRAP) will be excluded.
{PW NOT RW} w/o marker RW w/o marker
Core Low voltage
VSS
IO High voltage
o For the IP design:

DRC uses the connections of IO MOS devices in OD2 to identify high voltage nets if these nets do not have the
high voltage marker layers. If your high voltage net is not connected to an IO MOS, you have to mark the proper
marker layer manually.
o For the P&R stage:
(1) During P&R, you have to follow the high voltage metal space rules for the high voltage nets.
(2) After P&R, you have to manually define the specific marker layers for the high voltage nets before GDS
stream out.
(3) You have to use the highest-voltage marker layer for the net with a range of voltages.
M3 1 .8 V N et V IA 2 M2 1 .8 V N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M3 1 .5 V N et V IA 2 M2 1 .5 V N et
C h e c k M 2 .S .8 .1
M 3 1 .5 V M a r k e r L a y e r (3 3 ;2 1 5 )
M3 1 .0 V N et V IA 2 M2 1 .0 V N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
M 3 1 .0 V M a r k e r L a y e r (3 3 ;2 1 0 )
# T h e N e t v o lta g e is d e fin e d b y c o r r e s p o n d in g m a r k e r la y e r s
M 3 1 .8 V N et V IA 2 M 2 1 .8 V N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M 3 1 .8 V N et V IA 2 M 2 1 .8 V N et
C h e c k M 2 .S .8
M 3 1 .5 V M a r k e r L a y e r (3 3 ;2 1 5 )
# H ig h v o lta g e m a r k e r la y e r h a s h ig h e r p r io r ity
M3 ?V N et V IA 2 M2 ?V N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
M 2 1 .8 V M a r k e r L a y e r (3 2 ;2 1 8 )
# O n ly r e la tiv e m a r k e r la y e r c a n b e u s e d to d e fin e th e N e t v o lta g e
M3 1 .8 V N et V IA 2 M2 1 .8 V N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M3 1 .8 V N et V IA 2 M2 1 .8 V N et
C h e c k M 2 .S .8
M 2 1 .0 V M a r k e r L a y e r (3 2 ;2 1 0 )
M3 1 .0 V N et V IA 2 M2 1 .0 V N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
# M a r k e r la y e r c o u ld b e u s e d d e fin e th e v o lta g e fo r s e v e r a l N e ts .
D A
E /E 1 /E 2 /F /G
M 1 M 1
H
N
B
A /C D
> L 1 ,L 2 ,L 3 ,L 4 ,L 5 B
H
H
> W 1 ,W 2 ,W 3 ,W 4 ,W 5
D
M 1 .E N .1 / M 1 .E N .2 / M 1 .E N .3 / M 1 .E N .4
I I I K, L
I I
J J K ,L
J J K ,L
J
J
M 1 M 1 M 1 M 1 M 1
M 1 .S .5
S1 S1 S1
D
S1 S1 D
R
< Q
S2 S2 S2 S2
R e g io n 1 o r 2 c a n n o t h a v e o th e r M 1 p a tte r n s a t
T T
th e s a m e tim e . O n e o f th e m w ith o th e r M 1
p a tte r n s is a llo w e d .
S1
T R e g io n 1 R e g io n 2
Q = 0 .0 7 W < 0 .0 9
T T
T
S2
M 1 .E N .5
Q = 0 .0 7
W < 0 .0 9 S1
S2
M 1 .A .1 / M 1 .A .2 / M 1 .A .3 M 1 .R .1
> 0 .2 7
Q1
Q1 M
O
O
> = 0 .1 1
M 1
M 1 M 1
< 0 .0 8
M 1 .E N .5
M1.S.9
4.5.30 VIAx Layout Rules (Mask ID: 378, 379, 373, 374,
375, 376, 377)
For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
Width (maximum = minimum) (Except SEALRING_ALL (162;2) and {VIAx bar INSIDE {LOWMEDN NOT
VIAx.W.1 A = 0.07
(LOWMEDN SIZING -4 µm)}} region)
VIAx.S.1 Space B  0.07
VIAx.S.1.1 Space [any one of VIAx connects to > 3.3V and  5V different net]  0.2
VIAx.S.2 Space to 3-neighboring VIAx (distance < 0.098 μm) C  0.09
VIAx.S.3 Space to neighboring VIAx [different net] B1  0.095
VIAx.S.3.1 Space to neighboring VIAx [different net and common parallel run length > 0 μm] B2  0.11
VIAx.EN.0 Enclosure by Mx or M1 is defined by either {VIAx.EN.1 and VIAx.EN.2} or {VIAx.EN.4 and VIAx.EN.4.1}
VIAx.EN.0® Recommended enclosure by Mx or M1 is defined by either VIAx.EN.1® or VIAx.EN.2® .
VIAx.EN.1 Enclosure by Mx or M1 D  0.00
VIAx.EN.1® Recommended enclosure by Mx or M1 to avoid high Rc. D  0.03
VIAx.EN.2 Enclosure by Mx or M1 [at least two opposite sides] E  0.03
VIAx.EN.2® Recommended enclosure by Mx or M1 [at least two opposite sides] to avoid high Rc. E  0.05
VIA1 Enclosure by M1 [metal width  0.11 μm, space < 0.08 μm and parallel run length > 0.27 μm] (This
VIAx.EN.3.1 F  0.015
check doesn't include two or more via1 present in the metal intersection)
VIAx.EN.4 Enclosure by Mx or M1 D  0.01
VIAx.EN.4.1 Enclosure by Mx or M1 [at least two opposite sides] E  0.02
VIAx.R.1 45-degree rotated VIAx is not allowed.
At least two VIAx with space  0.14 μm (S1), or at least four VIAx with space
VIAx.R.2  0.63 μm (S1’) are required to connect Mx and Mx+1 when one of these two metals has width and length >
0.21 μm (W1). (Except VIA bar region and VIA1.R.2 except SRAMDMY;0 (186;0) region)
At least four VIAx with space  0.14 μm (S2), or at least nine VIAx with space  0.83 μm (S2’) are required to
VIAx.R.3 connect Mx and Mx+1 when one of these two metals has width and length > 0.55 μm (W2). (Except VIA bar
region)
At least two VIAx must be used for a connection that distance  1.14 μm (D) away from a metal plate (either
VIAx.R.4 Mx or Mx+1) with length > 0.21 μm (L) and width > 0.21 μm (W). (Except VIA bar region and VIA1.R.4 except
SRAMDMY;0 (186;0) region)
VIAx.R.5
Mx or Mx+1) with length > 1.4 μm (L) and width > 1.4 μm (W). (Except VIA bar region)
VIAx.R.6
Mx or Mx+1) with length > 7 μm (L) and width > 2.1 μm (W). (Except VIA bar region)
VIAx.R.7 VIAx must be fully covered by Mx and Mx+1.
Recommended maximum consecutive stacked VIAx layer, which has only one via for each VIAx layer to
avoid high Rc. (Except {LOWMEDN NOT (LOWMEDN SIZING -4 um)})
VIAx.R.8® (Example: VIA1~VIA4, VIA2~VIA5, VIA3~VIA6, VIA4~VIA7. This rule does not apply to top via. It is allowed to  4
stack from VIA4 to VIA9 because VIA8 and VIA9 are top via. It is allowed to stack more than four VIAx layers
if two or more vias in each VIAx layer are on the same metal.)
Single VIAx is not allowed in “H-shape" Mx+1 when all of the following conditions come into existence:
(1) The Mx+1 has “H-shape" interact with two metal holes: both two metal hole length  5 μm (L2) and two
VIAx.R.11 metal hole area  5 μm2
(2) The VIAx overlaps on the center metal bar of this “H-shape” Mx+1
(3) The center metal bar length  1 μm (L) and the metal bar width  0.21 μm.
VIAx.R.12 VIAx connected to DMx, DMx_O, DMx+1, DMx+1_O is not allowed.
Maximum area ratio of M1/Mx to upper VIAx in the same net [connects to gate with area > 19200um2, and
VIAx.R.13 does not connect to OD].  350000
Maximum area ratio of IO gate [NOT INSIDE NW] to single layer VIAx in the same net (Except the protection
OD area  0.25 µm2)
VIAx.R.13.1  300000
This rule is checked by the DRC command files in ANTENNA_DRC directory.
Maximum area ratio of IO gate [INSIDE NW] to single layer VIAx in the same net (Except the protection OD
area  0.25 µm2)
VIAx.R.13.2  2000000
DVIAx is a must for Flip Chip.
DVIAx.R.3 To comply tsmc dummy utility, DRC will flag as violation when the area ratio of (DVIAx to DMx) & (DVIAx to
DMx+1) are < 1% at the same time.
Recommend using redundant vias to avoid high Rc wherever layout allows. (Except {LOWMEDN NOT
VIAx.R.9gU
(LOWMEDN SIZING -4 um)}) Please refer to section “Via Layout Recommendations”
Table Notes:
E D A
A
A
B B
B B
B B
2 - n e ig h b o r in g V ia
2 - n e ig h b o r in g V ia 2 - n e ig h b o r in g V ia
E C
A
C
M 2~7 B C C
3 X 3 V ia a r r a y
A
D
C
M 1
E E C C C C
A A C C
E E C
B B
E E
C C C
C
E E 4 - n e ig h b o r in g V ia
D D
V IA x .E N .3 .1 M x /M x + 1
M 1
V IA 1 B
B1
> 0 .2 7 B
F
B2
> = 0 .1 1
M x /M x + 1
V ia s p a c e to n e ig h b o r in g v ia in th e
< 0 .0 8 s a m e n e t o r in th e d iffe r e n t n e t
From the EM spec, at least two vias are needed. It is strongly suggested
to use  two vias in each VIAx layer for stacked via structures.
Illustration of VIAx.R.8®
M 10 M 10 M 10 M 10 M 10 M 10 M 10
V9 V9 V9 V9 V9 V9 V9
M 9 M 9 M 9 M 9 M 9 M 9 M 9
V8 V8 V8 V8 V8 V8 V8
M 8 M 8 M 8 M 8 M 8 M 8 M 8
V7 V7 V7 V7 V7 V7 V7 V7
M 7 M 7 M 7 M 7 M 7 M 7 M 7
V6 V6 V6 V6 V6 V6
M 6 M 6 M 6 M 6 M 6 M 6 M 6
V5 V5 V5 V5 V5 V5 V5
M 5 M 5 M 5 M 5 M 5 M 5 M 5
V4 V4 V4 V4 V4 V4 V4 V4
M 4 M 4 M 4 M 4 M 4 M 4 M 4
V3 V3 V3 V3 V3 V3 V3
M 3 M 3 M 3 M 3 M 3 M 3 M 3
V2 V2 V2 V2 V2 V2 V2
M 2 M 2 M 2 M 2 M 2 M 2 M 2
V1 V1 V1 V1 V1
M 1 M 1 M 1 M 1 M 1 M 1 M 1
> = 2 v ia s in e a c h V IA x la y e r
S ta c k > 4 V IA x is n o t S ta c k < = 4 V IA x is
o n th e s a m e m e ta l is
re c o m m e n d e d re c o m m e n d e d .
re c o m m e n d e d .
Illustration of VIAx.R.2, VIAx.R.3 Rules

<= W 1 <= W 1
F ig . a n e t w ith F ig . b n e t w ith * a ls o th e c a s e w ith
< 4 V ia s > = 4 V ia s exchanged M x / M x+ 1
F ig . f3
<=S1
F ig . f1
<=S1 <=S1'
F ig . e 2 F ig . f2 S1 <= S1
W 1 > = 4 V ia s
F ig . e 1 M x+1
M x F ig . f4
<= W 1 > S1
a llo w e d
> S 1 ' a llo w e d
N o t a llo w e d V ia s
Fig. c net with Fig. d net with

< 9 Vias >= 9 Vias
Fig. e3 W1
<=S2 <=S2'
Follow
W2 >=9 Vias VIAx.R.4,5,6
Follow
VIAx.R.7
>S2' allowed
Rule VIAx.R.2 Rule VIAx.R.3

0.21 μm < W1  0.55 μm W2 μm > 0.55 μm
Fig. a Fig. b Fig. c Fig. d
< 4 vias  4 vias < 9 vias  9 vias
S1 = 0.14 μm S1’ = 0.63 μm S2 = 0.14 μm S2’ = 0.83 μm
Fig. a. At least two vias with spacing  S1 μm inside the same overlapped metal region (Mx AND Mx+1).
Fig. b. At least four vias with spacing  S1’ μm.
Fig. c. At least four vias with spacing  S2 μm inside the same overlapped metal region (Mx AND Mx+1).
Fig. d. At least nine vias with spacing  S2’ μm.
Fig. e1 A single via is allowed inside metal of width  W1 μm. However, it is a violation if the via is located on the
boundary between metal segments of width  W1 μm and width > W1 μm as shown in fig f1.
Fig. e2 A via or vias located on  W1 (W2) metal but near > W1 (W2) metal can be counted in for the rule.
Fig. e3 Indicates the rules that the areas within the vias should follow.
Layout violation examples:
Fig. f2.Two vias with spacing > S1 μm.
Fig. f3.Two vias with spacing  S1 μm but belonging to different nets.
Fig. f4.Two vias with spacing  S1 μm on the same net but not inside the same overlapped metal region (Mx AND
Mx+1).
Illustration of VIAx.R.4/VIAx.R.5/VIAx.R.6 Rules

Rule No VIAx.R.4 VIAx.R.5 VIAx.R.6
Wide Metal Mx or Mx+1 Mx or Mx+1 Mx or Mx+1
Metal connection Mx+1 or Mx Mx+1 or Mx Mx+1 or Mx
W > 0.21 μm > 1.4 μm > 2.1 μm
L > 0.21 μm > 1.4 μm > 7 μm
D > 1.14 μm > 2.8 μm > 7.1 μm
(a) ~ (f) is ok but (g) ~ (j) is not allowed
(e ) (f)
(a ) (b )
(c ) (d )
M e ta l C o n n e c tio n
< = 0 .1 4
< = 0 .1 4
W < = 0 .1 4
W id e M e ta l
(h )
(i)
M e ta l C o n n c e tio n
(g ) (j)
W
W id e M e ta l
4.5.31 Mx Layout Rules (Mask ID: 380, 381, 384, 385,

386, 387, 388)
Mx.W.1 Width A  0.07
Width of 45-degree bent Mx. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid (refer to
Mx.W.2 B  0.17
Maximum width
Mx.W.3 C  4.50
Mx.S.1 Space D  0.07
Mx.S.1® Recommended space to reduce the short possibility caused by particle D  0.09
Mx.S.1.1 Space [any one of Mx connects to > 3.3V and  5V net]  0.09
Mx.S.2 E  0.1
projection)
Mx.S.2.1 E1  0.12
projection)
Mx.S.2.2 E2  0.15
projection)
Mx.S.2.3 F  0.21
projection)
Mx.S.3 G  0.50
projection)
Space at Mx line-end (W < 0.10 μm (Q)) in a dense-line-end configuration: If Mx has parallel run length with
opposite Mx (measured with T = 0.035 μm extension) along two adjacent edges of Mx [any one edge <Q
Mx.S.5 distance from the corner of the two edges], then one of the spaces (S1 or S2) needs to be at least this value S1/S2  0.10
(This check doesn't include small jog with edge length < 0.07 μm(R)) (M2.S.5 except SRAMDMY;0 (186;0)
region)
Space at Mx line-end (W < 0.10 μm (Q)) in a dense-line-end configuration: If Mx has parallel run length with
opposite Mx (measured with T = 0.035 μm extension) along two adjacent edges of Mx [any one edge < Q
distance from the corner of the two edges], and Mx enclose Vx-1 < 0.05 μm at the line-end, then one of the
spaces (S1 or S2) needs to be at least this value.
This check doesn't include the following areas:
(1) Small jog with edge length < 0.07 μm (R).
(2) Two or more VIAx (at least one VIA does not violate this rule , i.e. either one of the two line-end vias follows
the rule, and DRC will treat the other one does not violate this rule) present in the metal intersection.
Mx.S.5.1 (3) The following conditions can pass the check flow. S1/S2  0.12
(i) S1/S2  0.12 μm and Mx enclosure Vx-1  0.03 μm
(ii) S1/S2 < 0.12 μm and Mx enclosure Vx-1  0.05 μm
(iii) Sum of S1 and Mx enclosure of Vx-1  0.15 μm with five combinations (S1/Mx enclosure Vx-1):
(a) space  0.120 μm / enclosure  0.030 μm,
(b) space  0.115 μm / enclosure  0.035 μm,
(c) space  0.110 μm / enclosure  0.040 μm,
(d) space  0.105 μm / enclosure  0.045 μm,
(e) space  0.100 μm / enclosure  0.050 μm.
Mx.S.6 Space to 45-degree bent Mx H  0.17
Mx.S.8 Space to {VIAx-1 OR VIAx} [different net, any one of VIAx-1, VIAx or Mx connects to 1.8V ~ 3.3V net]  0.1
Mx.S.8.1 Space to {VIAx-1 OR VIAx} [different net, any one of VIAx-1, VIAx or Mx connects to  1.5V and < 1.8V net]  0.08
Mx.S.8.2 Space to {VIAx-1 OR VIAx} [different net, any one of VIAx-1, VIAx or Mx connects to > 3.3V and  5V net]  0.18
This rule is to check the Metal (A) space with the neighboring VIAx [either VIAx or Mx connects to > 3.3V and 
5V net].
The DRC methodology to find Metal (A):
Find an edge (B) of the metal line-end [edge length  0.12um]
Mx.S.9 S  0.15
Run length (C) from edge (B) inside metal  0.13um
Jog length (D)  0.01um within 0.13um run length
Extend 0.06um outside from edge (B) to form a polygon metal (A)
Metal (A) is defined if conditions 1~4 are all satisfied.
Mx.EN.0 Enclosure of VIAx-1 is defined by either {Mx.EN.1 and Mx.EN.2} or {Mx.EN.3 and Mx.EN.3.1}
Mx.EN.0® Recommended enclosure of VIAx-1 is defined by either Mx.EN.1® or Mx.EN.2® .
Mx.EN.1 Enclosure of VIAx-1 I  0.00
Mx.EN.1® Recommended enclosure of VIAx-1 to avoid high Rc. I  0.03
Mx.EN.2 Enclosure of VIAx-1 [at least two opposite sides] (except SEALRING_ALL (162;2) regions) J  0.03
Mx.EN.2® Recommended enclosure of VIAx-1 [at least two opposite sides] to avoid high Rc. J  0.05
Mx.EN.3 Enclosure of VIAx-1 (except SEALRING_ALL (162;2) regions) I  0.01
Mx.EN.3.1 Enclosure of VIAx-1 [at least two opposite sides] (except SEALRING_ALL (162;2) regions) J  0.02
Mx.A.1 Area (except M2 (M2.A.1) in SRAMDMY;0 (186;0) region) O  0.027
Mx.A.1® Recommended area to avoid high Rc (except DMx_O) O  0.0351
Area [with all of edge length < 0.17 μm]
Mx.A.2 (This check doesn't include the patterns filling 0.07 μm x 0.17 μm rectangular tile) (except M2 (M2.A.2) in O  0.06
SRAMDMY;0 (186;0) region)
Mx.A.3 Enclosed area Q1  0.2
For the following Mx.DN.1, Mx.DN.1.1, Mx.DN.4, and DMx.R.1, please refer to the "Dummy Metal Rules" in
Mx.DN.0
Chapter 8 for the details.
Mx.DN.1 Minimum metal density in window 125 μm x 125 μm, stepping 62.5 μm  10%
Mx.DN.1.1 Maximum metal density in window 125 μm x 125 μm, stepping 62.5 μm  85%
The metal density difference between any two neighboring checking windows including DMxEXCL [window 200
μm x 200 μm, stepping 200 μm].
Mx.DN.4  50%
risk of low density and of high gradient.)
It is not allowed to have local density > 85% of all 3 consecutive metal (Mx, Mx+1, and Mx+2) over any window
62.5 μm x 62.5 μm (stepping 31.25 μm), i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local
density  85%.
Mx.DN.5
1. The metal layers include M1/Mx and dummy metals.
2. The check does not include chip corner stress relief pattern, SEALRING_ALL (162;2) and top two metals at
the CUP area.
Metal density  1% must be followed for items (A) to (C).
(A) Metal density [window 80 μm x 80 μm, stepping 40 μm]  1%.
(B) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density <
1%] ≤ 6400um2, except the merged low density windows width ≤ 30um.
(C) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density <
Mx.DN.6 1%] ≤ 18000um2.
- LOWMEDN
stepping 5um, density < 1%] ≤ 1600um2, except the merged low density windows width ≤ 30um. This item
is applied for {IP NOT (IP SIZING -10um)} region when the width of IP is  10um.
Mx.DN.6®
stepping 5um, density < 1%] ≤ 4500um2. This item is applied for {IP NOT (IP SIZING -10um)} region when
the width of IP is  10um.
- LOWMEDN
It is not allowed to have local density < 5% of all 3 consecutive metal (Mx, Mx+1 and Mx+2) over any 30um x
30um (stepping 15um), i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local density ≥ 5%.
Mx.DN.7 2. The following special regions are excluded while the density checking:
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding region) is  15 μm.
It is not recommended to have local density < 5% of all 3 consecutive metal (Mx, Mx+1 and Mx+2) over any
15um x 15um (stepping 15um) for IP level, i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local
density ≥ 5%.
Mx.DN.7® 2. The following special regions are excluded while the density checking:
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding region) is ≥ 7.5μm and for
{IP NOT (IP SIZING -15um)} region when the width of IP is  15um.
Total Mx island (for all Mx layers) density < 6.5E+04 ea/mm2 in whole chip
The definition of counts of small Mx island:
Mx.DN.8® 1. Mx width == 0.07um
2. Mx length  0.52um
3. Mx has two segments with space == 0.07um with the parallel run length (0.209  parallel run length < 0.52)
DMx.R.1 DMx is a must. The DMx CAD layer must be different from the Mx CAD layer.
It is important to insert the DMx & DVIAx uniformly to avoid white space. You should use tsmc standard
DMx.R.4® U
backend utility to insert the backend dummy pattern. The usage of DMxEXCL needs to be minimized.
Mx.R.1U Mx line-end must be rectangular. Other shapes are not allowed.
For the small space, recommended to enlarge the metal space, by using Wire Spreading function of EDA tool,
Mx.R.2gU to reduce the wire capacitance and the possibility of metal short. Please refer to section 9.1.1 and TSMC
Reference Flow.
Mx.R.3 Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
Table Notes:
 To improve the metal CMP process window, you must fill the DMx globally and uniformly even if the originally
drawn Mx has already met the density rules (Mx.DN.1 and Mx.DN.1.1). For sensitive areas with auto-fill operations
blocked by the DMxEXCL layer, it is recommended filling dummy pattern evenly by manual operations to gain a
violations (Mx.DN.1, Mx.DN.1.1, Mx.DN.5) during placement. It may have unexpected violation during the
IP/macro placement due to the environment, even if the IP/macro already pass the high density rule check.
Therefore, you need to carefully design the dimension of the width/space for wide metal (eg, power/ground bus),
under the proper high density limit.
 Mx.DN.6®: For IP level, recommend metal density ≥ 1% to reduce Mx.DN.6 DRC violation in chip level.
 Mx.DN.7 Layout suggestion: increase the density of all 3 consecutive Mx layers (1 st priority), or increase the
density of the uppermost layer (2nd priority) instead of modifying only the density of the bottom layer to pass the
rule check.
 Ex: M4.DN.7 represent the low M4/M5/M6 density violation: the 1st choice is to increase the Mx density of
M4/M5/M6 at violation window, or increase the M6 density at violation window.
 Mx.DN.7® : For IP level, it is not recommended to have local density < 5% of all 3 consecutive metal (Mx, Mx+1
and Mx+2) over any 15 μm x 15 μm (stepping 15 μm) to reduce Mx.DN.7 DRC violation in chip level.
 Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9.
o Make sure to add correct marker layers to let DRC check the high voltage rules correctly.
 Data-types 200 to 218 of each metal layer are reserved for the nets of voltage ranging from 0V to 1.8V in
0.1V step. Data-types 219, 220, and 221 are assigned for I/O voltage 2.5V, 3.3V, and 5V, respectively.
 The net voltage is defined by the corresponding marker layers. The net voltage cannot be recognized by
incorrect marker layers. That means, if a marker layer (33;218) is on M3, then this net will be recognized as
an 1.8V net, but it cannot be recognized if a marker layer (32;218) is on M3.
 Higher voltage marker layers have higher priority, e.g. the M3 net will be recognized as an 1.8V net if there
are two marker layers as (33;215) and (33;218) on it.
o The DRC methodology for the high voltage check:
 Marker layers have higher priority than MOS connection.
 The M3 net will be recognized as an 1.8V net if there is (33;218), even if this net does not connect to a
MOS inside OD2.
 The M3 net will be recognized as a low-voltage net ( 1.2V) if there is a marker layer of
(33;200~212), even if this net connects to a MOS inside OD2.
 The M3 net will be recognized as an 1.8V net if there is (33;218) and this net connects to a MOS inside
OD2 and a core MOS simultaneously.
 Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9 will be checked for the nets with voltage > 1.2V
defined by marker layers. Nets with voltage  1.2V will be excluded.
 If a net without any marker layers,

 Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9 will be checked when the net connects only to a
MOS inside OD2.
 If a net connects to an IO MOS & a core MOS simultaneously,
o If the DRC option of Mx_S_8_IO_NET is off (default), it will be recognized as low voltage and will
not check Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9.
o If the DRC option of Mx_S_8_IO_NET is on (not default), it will be recognized as a high voltage net
and will check Mx.S.1.1, Mx.S.8, Mx.S.8.1, Mx.S.8.2, and Mx.S.9.
 The following summary tables list the high/low voltage net recognition results for the different combinations
of high voltage marker layers and the DRC option:
Mx net connection if Mx_S_8_IO_NET is OFF
Y Y Y
Y N Y
High voltage
N Y Y
N Y N
Y Y N
Low voltage
Y N N
Mx net connection if Mx_S_8_IO_NET is ON

Y Y Y
Y N Y
N Y Y High voltage
N Y N
Y Y N
Y N N Low voltage
 The net without any marker layers will be recognized as a VSS net if there is PW STRAP connected, even
if the PW STRAP is inside OD2. But PW STRAP inside DNW (RW STRAP) will be excluded.
{PW NOT RW} w/o marker RW w/o marker
Core Low voltage
VSS
IO High voltage
o For the IP design:
DRC uses the connections of IO MOS devices in OD2 to identify high voltage nets if these nets do not have the
high voltage marker layers. If your high voltage net is not connected to an IO MOS, you have to mark the proper
marker layer manually.
o For the P&R stage:
(1) During P&R, you have to follow the high voltage metal space rules for the high voltage nets.
(2) After P&R, you have to manually define the specific marker layers for the high voltage nets before GDS
stream out.
(3) You have to use the highest-voltage marker layer for the net with a range of voltages.
M3 1 .8 V N et V IA 2 M2 1 .8 V N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M3 1 .5 V N et V IA 2 M2 1 .5 V N et
C h e c k M 2 .S .8 .1
M 3 1 .5 V M a r k e r L a y e r (3 3 ;2 1 5 )
M3 1 .0 V N et V IA 2 M2 1 .0 V N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
M 3 1 .0 V M a r k e r L a y e r (3 3 ;2 1 0 )
# T h e N e t v o lta g e is d e fin e d b y c o r r e s p o n d in g m a r k e r la y e r s
M 3 1 .8 V N et V IA 2 M 2 1 .8 V N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M 3 1 .8 V N et V IA 2 M 2 1 .8 V N et
C h e c k M 2 .S .8
M 3 1 .5 V M a r k e r L a y e r (3 3 ;2 1 5 )
# H ig h v o lta g e m a r k e r la y e r h a s h ig h e r p r io r ity
M 3 ?V N et V IA 2 M 2 ?V N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
M 2 1 .8 V M a r k e r L a y e r (3 2 ;2 1 8 )
# O n ly r e la tiv e m a r k e r la y e r c a n b e u s e d to d e fin e th e N e t v o lta g e
M3 1 .8 V N et V IA 2 M2 1 .8 V N et
C h e c k M 2 .S .8
M 3 1 .8 V M a r k e r L a y e r (3 3 ;2 1 8 )
M3 1 .8 V N et V IA 2 M2 1 .8 V N et
C h e c k M 2 .S .8
M 2 1 .0 V M a r k e r L a y e r (3 2 ;2 1 0 )
M3 1 .0 V N et V IA 2 M2 1 .0 V N et
N ot C heck
M 2 .S .8 o r
M 2 .S .8 .1
# M a r k e r la y e r c o u ld b e u s e d d e fin e th e v o lta g e fo r s e v e r a l N e ts .
D A
E /E 1 /E 2 /F /G
M x M x
H
N
B
A /C D
> L 1 ,L 2 ,L 3 ,L 4 ,L 5 B
H
H
> W 1 ,W 2 ,W 3 ,W 4 ,W 5
D
M x .E N .1 / M x .E N .2
I I I
I I
J J
J J
J
J
M x M x M x M x
M x .S .5
S1 S1 S1
D
S1 S1 D
R
< Q
S2 S2 S2 S2
R e g io n 1 o r 2 c a n n o t h a v e o th e r M x p a tte r n s a t
M x .S .5 .1 T T
th e s a m e tim e . O n e o f th e m w ith o th e r M x
M x e n c l o su r e
S1 S2 p a tte r n s is a llo w e d .
o f V x -1 S1
T R e g io n 1 R e g io n 2
0 .1 2 0 0 .0 7 0 .0 3 0
Q = 0 .1 W < 0 .1
0 .1 1 5 0 .0 7 0 .0 3 5
T T
T
0 .1 1 0 0 .0 7 0 .0 4 0 S2
Q = 0 .1
0 .1 0 5 0 .0 7 0 .0 4 5 W < 0 .1 S1
0 .1 0 0 0 .0 7 0 .0 5 0 S2
M x .A .1 / M x .A .2 / M x .A .3 M x .R .1
0 .1 0 .1 2
Q1
Q1
0 .0 5 0 .0 3 O O
0 .0 7 0 .0 7
M x
M x M x
An example for condition 2 of Mx.S.5.1:

(2) two or more viax (at least one via does not violate this rule , i.e. either one of the two line-end vias follows the rule, and
DRC will treat the other one does not violate this rule).
Mx.S.9
4.5.32 LOWMEDN Layout Rules

This layer, LOWMEDN (255;15), is used for inductor, LOGO, and so on.
LOWMEDN.W.1 Width of {(M1, DM1, DM1_O) AND LOWMEDN} A1  0.14
LOWMEDN.W.2 Width of {Mx, DMx, DMx_O AND LOWMEDN} A2  0.14
LOWMEDN.S.1 Space of {M1, DM1, DM1_O AND LOWMEDN} B1  0.14
LOWMEDN.S.2 Space of {Mx, DMx, DMx_O AND LOWMEDN} B2  0.14
Protection ring must be inside {LOWMEDN NOT (LOWMEDN SIZING -1 µm)}.
LOWMEDN.R.1
The protection ring must include all Mx/all VIAx/…/V1/M1 layers.
There must be continuous VIAx bar as a ring within {LOWMEDN NOT (LOWMEDN SIZING -4 µm)}.
LOWMEDN.R.2
(except {LOWMEDN INTERACT INDDMY})
LOWMEDN.R.3 VIAx bar is allowed in {LOWMEDN NOT (LOWMEDN SIZING -4 µm)}.
LOWMEDN.R.4 A 0.005 um checking tolerance is allowed for 45-degree protection ring for VIAx.EN.8/ Mx.EN.4.
For {LOWMEDN INTERACT INDDMY}, there must be either only one breach (C-shape ring) of
metal/Via with via space ≤ 4um or VIAx bar must be continuous within {LOWMEDN NOT (LOWMEDN
LOWMEDN.R.5 SIZING -4 µm)}.
Remark: Inductor simulation comparison between with and without protection ring is important.
Especially to account for its impact on the performance and the possibility of resonance.
For C-shape ring, at least 2 protection rings are must in {LOWMEDN INTERACT INDDMY}. At least 2
LOWMEDN.R.6
VIAx bar in {LOWMEDN NOT (LOWMEDN SIZING -4 µm)} for the protection ring with the breach.
LOWMEDN.R.7U Metal/Via breach must be on the opposite sides for double protection rings
Recommend dummy metal is not inserted between protection rings or in the breach of protection ring.
LOWMEDN.R.8® U
Please use DMxEXCL to aviod dummy metal insertion.
Width of VIAx bar in protection ring [INSIDE LOWMEDN]
Checking tolerance for 45-degree protection ring: 0.070 or
VIAx.W.6 C =
0.005um [Width = 0.070um] 0.075
0.010um [Width = 0.075um]
VIAx.S.7 Space of VIAx bar in LOWMEDN to VIAx hole D  0.365
VIAx.S.8 Space of VIAx bar in LOWMEDN E  0.74
VIAx.EN.8 VIAx bar enclosure by M1/Mx in LOWMEDN F  0.21
Mx.EN.4 Enclosure of VIAx-1 bar in LOWMEDN G  0.21
L O W M E D N .R .1
LOW M EDN
I f t h e L O W M E D N is b u t t e d , D R C c a n n o t a v o id it t o f la g t h is la y o u t. B u t th is
la y o u t is a llo w e d f o r p r o c e s s .
LOWMEDN
LOWMEDN
A1/A2 A1/A2 USG
M8
V7
B1/B2 M7
V6
M6
V5
G M5
ELK V4
F M4
V3
M3
V2
M2
V1
M1
D=0.07 via bar
C
LOWMEDN
F
VIAx
{ L O W M E D N in te r a c t IN D D M Y }
V IA b a r
b re a c h b re a c h
4.5.33 VIAy Layout Rules (Mask ID: 379, 373, 374, 375,
376, 377, 372, 37A)
VIAy.W.1 Width (maximum = minimum), except SEALRING_ALL (162;2) region A = 0.14
VIAy.S.1 Space B  0.14
VIAy.S.2 Space to 3-neighboring VIAy (distance < 0.175 μm) C  0.16
VIAy.EN.1 Enclosure by Mx or My D  0
VIAy.EN.1® Recommended enclosure by Mx or My to avoid high Rc. D  0.045
VIAy.EN.2 Enclosure by Mx or My [at least two opposite sides] E  0.045
VIAy.EN.2® Recommended enclosure by Mx or My [at least two opposite sides] to avoid high Rc. E  0.075
VIAy.R.1 45-degree rotated VIAy is not allowed.
At least two VIAy with space  0.29 μm (S1), or at least four VIAy with space
 0.57 μm (S1’) are required to connect My and My+1 when one of these two metals has width and length
VIAy.R.2
> 0.42 μm (W1).
At least four VIAy with space  0.29 μm (S2), or at least nine VIAy with space  0.77 μm (S2’) are required
VIAy.R.3 to connect My and My+1 when one of these two metals has width and length > 1.14 μm (W2).
At least two VIAy must be used for a connection that distance  1.4 μm (D) away from a metal plate (either
VIAy.R.4 My or My+1) with length > 0.7 μm (L) and width > 0.7 μm (W).(This check doesn’t include the
SEALRING_ALL (162;2) region)
VIAy.R.5 My or My+1) with length > 2 μm (L) and width > 2 μm (W).
VIAy.R.6 My or My+1) with length > 10 μm (L) and width > 3 μm (W).
VIAy.R.7 VIAy must be fully covered by {Mx AND My+1} or {My AND My+1}.
Single VIAy is not allowed in “H-shape" My+1 when all of the following conditions come into existence:
(1) The My+1 has “H-shape" interact with two metal holes: both two metal hole length  5um (L2) and two
VIAy.R.11 metal hole area  5um2
(2) The VIAy overlaps on the center metal bar of this “H-shape” My+1
(3) The center metal bar length  1μm (L) and the metal bar width  0.42um.
Maximum area ratio of Mx/My to upper VIAy in the same net [connects to gate with area > 19200um 2, and
VIAy.R.13 does not connect to OD].  350000
Maximum area ratio of IO gate [NOT INSIDE NW] to single layer VIAy in the same net (Except the
protection OD area  0.25 µm2)
VIAy.R.13.1  300000
Maximum area ratio of IO gate [INSIDE NW] to single layer VIAy in the same net (Except the protection OD
area  0.25 µm2)
VIAy.R.13.2  2000000
U Recommend using redundant vias to avoid high Rc wherever layout allows. Please refer to section “Via
VIAy.R.9g
Layout Recommendations”
VIAy.R.10 VIAy connected to DMx, DMy is not allowed.
E D
A
A
B
B B B
2 -n e ig h b o r in g V ia 2 -n e ig h b o r in g V ia
A
E
A
A
B
M y B
B
C
C
2 -n e ig h b o r in g V ia
D
A
M x
E E
A A C
E E C
B B
C C
E E
C C
D D
3 X 3 V ia a r r a y
C C C
C C
C C C
From the EM spec, at least two vias are needed. It is strongly suggested
to use  two vias in each VIAx layer for stacked via structures.
Illustration of VIAy.R.2, VIAy.R.3 Rules

<= W 1 <= W 1
F ig . a n e t w ith F ig . b n e t w ith * a ls o th e c a s e w ith
< 4 V ia s > = 4 V ia s exchanged M x / M x+ 1
F ig . f3
<=S1
F ig . f1
<=S1 <=S1'
F ig . e 2 F ig . f2 S1 <= S1
W 1 > = 4 V ia s
F ig . e 1 M x+1
M x F ig . f4
<= W 1 > S1
a llo w e d
> S 1 ' a llo w e d
Fig. c net with Fig. d net with

< 9 Vias >= 9 Vias
Fig. e3 W1
<=S2 <=S2'
Follow
W2 >=9 Vias VIAx.R.4,5,6
Follow
VIAx.R.7
>S2' allowed
Rule VIAy.R.2 Rule VIAy.R.3

0.42 μm < W1  1.14 μm W2 μm > 1.14 μm
Fig. a Fig. b Fig. c Fig. d
< 4 vias  4 vias <9 vias  9 vias
S1 = 0.29μm S1’ = 0.57μm S2 = 0.29μm S2’ = 0.77μm
Fig. a. At least two vias with spacing  S1 μm inside the same overlapped metal region (My AND My+1).
Fig. b. At least four vias with spacing  S1’ μm.
Fig. c. At least four vias with spacing  S2 μm inside the same overlapped metal region (My AND My+1).
Fig. d. At least nine vias with spacing  S2’ μm.
Fig. e1 A single via is allowed inside metal of width  W1 μm. However, it is a violation if the via is located on the
boundary between metal segments of width  W1 μm and width > W1 μm as shown in fig f1.
Fig. e3 Indicates the rules that the areas within the vias should follow.
Layout violation examples:
Fig. f2.Two vias with spacing > S1 μm.
Fig. f3.Two vias with spacing  S1 μm but belonging to different nets.
Fig. f4.Two vias with spacing  S1 μm on the same net but not inside the same overlapped metal region (My AND
My+1).
Illustration of VIAy.R.4/VIAy.R.5/VIAy.R.6 Rules

Rule No VIAy.R.4 VIAy.R.5 VIAy.R.6
Wide Metal My or My+1 My or My+1 My or My+1
Metal connection My+1 or My My+1 or My My+1 or My
W > 0.7 μm > 2 μm > 3 μm
L > 0.7 μm > 2 μm > 10 μm
D > 1.4 μm > 2.8 μm > 7.1 μm
(e ) (f)
(a ) (b )
(c ) (d )
M e ta l C o n n e c tio n
< = 0 .2 9
< = 0 .2 9
W < = 0 .2 9
W id e M e ta l
(h )
(i)
M e t a l C o n( g n
)
c e tio n
(j)
W
W id e M e ta l
4.5.34 My Layout Rules (Mask ID: Second Inter-layer

Metal (385, 386, 387, 388) and Top Metal (381,
384, 385, 386, 387, 388, 389, 38A))
My.W.1 Width A  0.14
Width of 45-degree bent My. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid (refer to
My.W.2 B  0.40
My.W.3 Maximum width C  12
My.S.1 Space D  0.14
My.S.2 E2  0.19
projection)
My.S.3 F  0.50
projection)
My.S.4 F  1.50
projection)
My.S.5 Space to 45-degree bent My H  0.40
My.EN.0 Enclosure of VIAy-1 is defined by {My.EN.1 and My.EN.2}
My.EN.0® Recommended enclosure of VIAy-1 is defined by either My.EN.1® or My.EN.2® .
My.EN.1 Enclosure of VIAy-1 I  0
My.EN.1® Recommended enclosure of VIAy-1 to avoid high Rc. I  0.045
My.EN.2 Enclosure of VIAy-1 [at least two opposite sides] J  0.045
My.EN.2® Recommended enclosure of VIAy-1 [at least two opposite sides] to avoid high Rc. J  0.075
My.A.1 Area K  0.07
My.A.2 Enclosed area L  0.2
For the following My.DN.1, My.DN.1.a, My.DN.1.1, My.DN.4, and DMy.R.1, please refer to the "Dummy Metal
My.DN.0
Rules" in Chapter 8 for the details.
Minimum Metal density in window 125 μm x 125 μm, stepping 62.5 μm. when My as inter-metal. (Except
INDDMY_MD)
The following special regions are excluded while the density checking:
My.DN.1 - Chip corner stress relief area and seal-ring  10%
- LOGO/INDDMY/INDDMY_MD
This rule is only applied when the width of (checking window NOT excluded region) is ≥ 1/4 checking window
width (31.25um).
Minimum Metal density in window 125 μm x 125 μm, stepping 62.5 μm when My as top metal.
The following special regions are excluded while the density checking:
- Chip corner stress relief area and seal-ring
My.DN.1.a  20%
This rule is only applied when the width of (checking window NOT excluded region) is ≥ 1/4 checking window
width (31.25um).
My.DN.1.1 Maximum Metal density in window 125 μm x 125 μm, stepping 62.5 μm  85%
The metal density difference between any two neighboring checking windows including DMxEXCL [window
200 μm x 200 μm, stepping 200 μm]
My.DN.4  50%
risk of low density and of high gradient).
DMy.R.1 DMy is a must. The DMy CAD layer must be different from the My CAD layer.
My.R.1U My line-end must be rectangular. Other shapes are not allowed.
My.R.2gU
to reduce the wire capacitance. Please refer to section 9.1.1 and TSMC Reference Flow.
My.R.3 Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
Table Notes:
 To improve the metal CMP process window, you must fill the DMy globally and uniformly even if the originally
drawn My has already met the density rules (My.DN.1 and My.DN.1.1). For sensitive areas with auto-fill operations
blocked by the DMxEXCL layer, it is recommended filling dummy pattern evenly by manual operations to gain a
 During IP/macro design, it is important to put certain density margin to avoid the possibility of high-density
violations (My.DN.1, My.DN.1.1) during placement. It may have unexpected violation during the IP/macro
need to carefully design the dimension of the width/space for wide metal (eg, power/ground bus), under the proper
high-density limit.
M y M y
A /C D
> L 1 ,L 2 ,L 3 ,L 4
L L
E /E 1 /F /G
> W 1 ,W 2 ,W 3 ,W 4
M y
M y M y
I I I M y .R .1
J I I J
J J >=J
>=J
M y M y M y M y
D A
B H
H H
B
Illustration of My.EN.1®
B e tte r
0 .0 4 5
0 .0 0
0 .0 4 5 0 .0 4 5 0 .0 4 5 0 .0 4 5
B e tte r
0 .0 4 5
0 .0 4 5
4.5.35 Top VIAz Layout Rules (Mask ID: 379, 373, 374,
375, 376, 377, 372, 37A)
VIAz.W.1 Width (maximum = minimum), except SEALRING_ALL (162;2) region A = 0.36
VIAz.S.1 Space B  0.34
VIAz.S.2 Space to 3-neighboring VIAz (distance < 0.56 μm) C  0.54
Enclosure by Mx or My or Mz
VIAz.EN.1 D  0.02
VIAz.EN.2 Enclosure by Mx or My or Mz [at least two opposite sides] E  0.08
VIAz.R.1 45-degree rotated VIAz is not allowed.
At least two VIAz with spacing  1.7 μm are required to connect Mz and Mz+1 when
VIAz.R.2 one of these metals has a width and length > 1.8 μm.
At least two VIAz must be used for a connection that distance  5 μm (D) away from
VIAz.R.3 a metal plate (either Mz or Mz+1) with length > 10 μm (L) and width > 3 μm (W).
VIAz.R.4 VIAz must be fully covered by Mz and Mz+1.
Recommend using redundant vias to avoid high Rc wherever layout allows.. Please
VIAz.R.5gU
refer to section “Via Layout Recommendations”
VIAz.R.6 VIAz connected to DMx, DMy, DMz, DMu is not allowed.
Maximum area ratio of Mx/My/Mz to upper VIAz in the same net [connects to gate
VIAz.R.13 with area > 19200um2, and does not connect to OD].  350000
Maximum area ratio of IO gate [NOT INSIDE NW] to single layer VIAz in the same
VIAz.R.13.1 net (Except the protection OD area  0.25 µm2)  300000
Maximum area ratio of IO gate [INSIDE NW] to single layer VIAz in the same net
VIAz.R.13.2 (Except the protection OD area  0.25 µm2)  2000000
V IA 8 ,9
E A A
A
M 9 ,1 0
B B B
C
B
D
2 - n e ig h b o r in g V ia C
V IA 8 ,9
E A C A
C C C C
C
M 9 ,1 0 B
C C C
D 3 - n e ig h b o r in g V ia C C C
V IA 8 ,9 C
C
C C
A
D
E
A 3 X 3 V ia a r r a y
V IA 8
E
B C
E
M8
V IA 8 E C
Illustration of VIAz.R.2 Rule

< = 1 .8 < = 1 .8
F ig . a n e t w ith * a ls o th e c a s e w ith
< 4 V ia s e x c h a n g e d M 9 / M 1 0 , M 8 /M 9
F ig . f3
< = 1 .7
F ig . f1
< = 1 .7
F ig . e 2 F ig . f2 1 .7 < = 1 .7
1 .8
F ig . e 1 M 10
M 9 F ig . f4
< = 1 .8
> 1 .7
a llo w e d
Fig. a At least two vias with spacing  1.7 μm inside the same overlapped metal region (M8 AND M9) or (M9 AND
M10).
Fig. e1 A single via is allowed inside metal of width  1.8 μm. However, it is a violation if the via is located on the
boundary between a metal segment of width  1.8 μm and a segment of width > 1.8 μm as in Fig. f1.
Fig. e2 A via or vias that are located on  1.8 metal but near >1.8 metal can be counted in for the rule.
Violated layout examples:
Fig. f2 Two vias with spacing > 1.7 μm.
Fig. f3 Two vias with spacing  1.7 μm but belonging to different nets.
Fig. f4 Two vias with spacing  1.7 μm on the same net but not inside the same overlapped metal region (M8 AND
M9) or (M9 AND M10).
Illustration of VIAz.R.3 Rule

(e ) (f)
(a ) (b )
(c ) (d )
M 10 or M 9
D = 5
< = 1 .7
< = 1 .7
W > 3 < = 1 .7
M 9 or M 10
L > 10
(h )
M 10 or M 9 (i)
(g ) (j)
D = 5
W > 3
M 9 or M 10
L > 10
4.5.36 Top Mz Layout Rules (Mask ID: 381, 384, 385,

386, 387, 388, 389, 38A)
Mz.W.1 Width A  0.4
Maximum width [except bond pad and INDDMY_MD]
Mz.W.2 (This check doesn’t include the regions covered by layers of LMARK, {INDDMY B  12
SIZING 22 μm}, CB, and {UBM INTERACT CBD}.)
Recommended Mz width [Mz on (((Mz-1 OR DMz-  5 μm x 5
Mz.W.3® J  0.42
μm) SIZING 1 μm)] for CMP dishing concern.
Mz.S.1 Space C  0.4
Space [at least one metal line width > 1.5 μm (W1) and the parallel metal run
Mz.S.2 D  0.50
length > 1.5 μm (L1)]
Space [at least one metal line width > 4.5 μm (W2) and the parallel metal run
Mz.S.3 E  1.50
length > 4.5 μm (L2)]
Enclosure of VIAz-1
Mz.EN.1 F  0.02
Mz.EN.2 Enclosure of VIAz-1 [at least two opposite sides] G  0.08
Mz.A.1 Area H  0.565
Mz.A.2 Enclosed area I  0.565
For the following Mz.DN.1, Mz.DN.4, and DMz.R.1, please refer to the "Dummy
Mz.DN.0
Metal Rules" in Chapter 8 for the details.
Minimum Mz density in window 125 μm x 125 μm, stepping 62.5 μm. The
following special regions are excluded while the density checking:
Mz.DN.1  20%
This rule is only applied when the width of (checking window NOT excluded
region) is ≥ 1/4 checking window width (31.25um).
Maximum Mz density in window 125 μm x 125 μm, stepping 62.5 μm. (This
Mz.DN.1.1  85%
check doesn’t include bond pad and INDDMY_MD.)
The metal density difference between any two neighboring checking windows
including DMxEXCL [window 200 μm x 200 μm, stepping 200μm] Anticipate
Mz.DN.4  50%
metal density gradient from layout of small cell by targeting density ~40% (this
way, it will limit the risk of low density and of high gradient).
DMz.R.1 DMz is a must. The DMz CAD layer must be different from the Mz CAD layer.
Mz.R.1U Mz line-end must be rectangular. Other shapes are not allowed.
Mz.R.2 Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
Table Notes:
 For RF/Mixed-signal applications, some metal rules are different from Logic rules. Please refer to RF/Mixed-
signal design rules for details.
 To improve the metal CMP process window, you must fill the DMz globally and uniformly even if the originally
drawn Mn has already met the density rules (Mz.DN.1 and Mz.DN.1.1). For sensitive areas with auto-fill
operations blocked by the DMxEXCL layer, it is recommended filling dummy pattern evenly by manual operations
to gain a better process window and electrical performance.
violations (Mz.DN.1, Mz.DN.1.1) during placement. It may have unexpected violation during the IP/macro
need to carefully design the dimension of the width/space for wide metal (eg, power/ground bus), under the
proper high density limit.
M z M z
A /B C
> L 1 ,L 2
D /E > W 1 ,W 2
I
H I Illu s tr a tio n o f M z .W .3 R
M 10
<=1 um
M z
M z M z
F
>=5 um
F G
M z .R .1 M 9 M 9
J
G G
>=5 um
M 10 J A /B
M z M z
M 9 J
4.5.37 Top VIAr Layout Rules (Mask ID: 375, 376, 377,
372, 37A)
VIAr.W.1 Width (square)(maximum = minimum), except SEALRING_ALL (162;2) region A = 0.46
VIAr.S.1 Space B  0.44
VIAr.S.2 Space to 3-neighboring VIAr (distance  0.66 μm) C  0.66
VIAr.S.2.1 Space of 2*2 array on same net C1  0.54
Enclosure by Mx or Mr
VIAr.EN.1 D  0.02
VIAr.EN.2 Enclosure by Mx or Mr [at least two opposite sides] E  0.08
VIAr.R.1 45-degree rotated VIAr is not allowed.
At least two VIAr with spacing  1.7 μm are required to connect Mr and Mr+1
VIAr.R.2 when one of these metals has a width and length > 1.8 μm.
At least two VIAr must be used for a connection that distance  5 μm (D) away
from a metal plate (either Mr or Mr+1) with length > 10 μm (L) and width > 3
VIAr.R.3
μm (W).
VIAr.R.4 VIAr must be fully covered by Mx and Mr.
VIAr.R.5gU Recommend using redundant vias wherever layout allows.
VIAr.R.6 VIAr connected to DMx, DMr is not allowed.
Maximum area ratio of Mx/Mr to upper VIAr in the same net [connects to
VIAr.R.13 gate with area > 19200um 2, and does not connect to OD].  350000
Maximum area ratio of IO gate [NOT INSIDE NW] to single layer VIAr in the
same net (Except the protection OD area  0.25 µm2)
VIAr.R.13.1  300000
This rule is checked by the DRC command files in ANTENNA_DRC
directory.
Maximum area ratio of IO gate [INSIDE NW] to single layer VIAr in the same
net (Except the protection OD area  0.25 µm2)
VIAr.R.13.2  2000000
This rule is checked by the DRC command files in ANTENNA_DRC
directory.
E
V IA r
A
B
M r
B B B
D
A A
E
C /C 1 C /C 1 C
A
V IA r , B
C
M r B 3 -n e ig h b o r in g V ia
D
A
V IA r ,9 C
C C
D
E
C
C C
V IA r A 4 -n e ig h b o r in g V ia 3 X 3 V ia a r r a y
C
B
E
C C C
M x or M r
C C
E
V IA r
D C C C
E
C
Illustration of VIAr.R.2, Rule

< = 1 .8 < = 1 .8
F ig . a n e t w ith * a ls o th e c a s e w ith
< 4 V ia s e x c h a n g e d M 8 /M 9 , M 7 /M 8
F ig . f3
< = 1 .7
F ig . f1
< = 1 .7
F ig . e 2 F ig . f2 1 .7 < = 1 .7
1 .8
F ig . e 1 M 9
M 8 F ig . f4
< = 1 .8
> 1 .7
a llo w e d
Fig. a At least two vias with spacing  1.7 μm inside the same overlapped metal region (M7 AND M8) or (M8
AND M9).
Fig. e1 A single via is allowed inside metal of width  1.8 μm. However, it is a violation if the via is located on
the boundary between a metal segment of width  1.8 μm and a segment of width > 1.8 μm as in Fig. f1.
Fig. e2 A via or vias that are located on  1.8 metal but near >1.8 metal can be counted in for the rule.
Violated layout examples:
Fig. f2 Two vias with spacing > 1.7 μm.
Fig. f3/f4 Two vias with spacing  1.7 μm on the same net but not inside the same overlapped metal region
(M7 AND M8) or (M8 AND M9).
Illustration of VIAr.R.3 Rule

(e ) (f)
(a ) (b )
(c ) (d )
M 9 or M 8
D = 5
< = 1 .7
< = 1 .7
W > 3 < = 1 .7
M 8 or M 9
L > 10
(h
)
(i
M 8 or M 9 )
(g (j
) )
D = 5
W > 3
M 8 or M 9
L > 10
4.5.38 Top Mr Layout Rules (Mask ID: 386, 387, 388,

389, 38A)
Mr.W.1 Width A  0.50
Mr.W.2 Maximum width [except bond pad and INDDMY_MD] B  12
Recommended Mr width [Mr on (((Mr-1 OR DMr-1) with space  5 μm x 5
Mr.W.3® J  0.55
μm) SIZING 1 μm)]
Mr.S.1 Space C  0.50
Space [at least one metal line width > 1.5 μm (W1) and the parallel metal
Mr.S.2 D  0.65
run length > 1.5 μm (L1)]
Space [at least one metal line width > 4.5 μm (W2) and the parallel metal
Mr.S.3 E  1.50
run length > 4.5 μm (L2)]
Enclosure of VIAr-1
Mr.EN.1 F  0.02
Mr.EN.2 Enclosure of VIAr-1 [at least two opposite sides] G  0.08
Mr.A.1 Area H  1.0
Mr.A.2 Enclosed area I  1.0
For the following Mr.DN.1, Mr.DN.4, and DMr.R.1, please refer to the
Mr.DN.0
"Dummy Metal Rules" in Chapter 8 for the details.
Minimum Mr density in window 125 μm x 125 μm, stepping 62.5 μm. The
Mr.DN.1  20%
region) is ≥ 1/4 checking window width (31.25um).
Maximum Mr density in window 125 μm x 125 μm, stepping 62.5 μm. (This
Mr.DN.1.1  85%
check doesn’t include bond pad and INDDMY_MD.)
The metal density difference between any two neighboring checking
windows including DMrEXCL [window 200 μm x 200 μm, stepping 200 μm]
Mr.DN.4 Anticipate metal density gradient from layout of small cell by targeting  50%
density ~40% (this way, it will limit the risk of low density and of high
gradient).
Mr.R.1U Mr line-end must be rectangular. Other shapes are not allowed.
Mr.R.2 Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
DMr.R.1 DMr is a must. The DMr CAD layer must be different from the Mr CAD layer.
Table Notes:
 To improve the metal CMP process window, you must fill the DMr globally and uniformly even if the originally drawn
Mr has already met the density rules (Mr.DN.1 and Mr.DN.1.1). For sensitive areas with auto-fill operations blocked
by the DMrEXCL layer, it is recommended filling dummy pattern evenly by manual operations to gain a better
process window and electrical performance.
 During IP/macro design, it is important to put certain density margin to avoid the possibility of high density violations
(Mr.DN.1, Mr.DN.1.1) during placement. It may have unexpected violation during the IP/macro placement due to the
environment, even if the IP/macro already pass the high density rule check. Therefore, you need to carefully design
the dimension of the width/space for wide metal (eg, power/ground bus), under the proper high-density limit.
A
M r M r M r .R .1
/B
C D /E
> L 1 ,L 2
H
M r I M r
> W 1 ,W 2
M r
G
<=1um
C1 F
J
F G
M9
G
M r M8 M8
>=5um
M r
F ig . b >=5um
F ig . a
5um
M9
J A /B
M9 J
4.5.39 RV Layout Rules (Mask ID: 306)

 CB-VD mask (306) is generated by the logical operation of CB (CAD layer: 76) and RV (CAD layer: 85).
 It is a must to consider sufficient RV counts to provide enough current for EM and ESD protection.It is
recommended to put as many RV holes as possible.
Width (maximum = minimum) (Except SEALRING_ALL (162;2))
(It is allowed to have both via dimensions in the same chip.)
RV.W.1 A = 3 or 2
RV 2μm x 2μm is only allowed in polyimide process. DRC flags RV 2μm x 2μm
without PM layer in chip level, except SEALRING_ALL (162;2).
RV.S.1 Space B  2
RV.EN.1 Enclosure by top metal C  0.5
A 45-degree rotated RV is not allowed (Except {(INDDMY OR INDDMY_MD)
RV.R.1
SIZING 22um})
RV.W.1, RV.S.1, and RV.EN.1 allow 0.01 μm tolerance on 45-degree rotated RV
RV.R.2
in (INDDMY OR INDDMY_MD).
RV
C C
C
RV Mtop C C B RV
A RV C C RV
C B
E
B RV
CB/CB2 Mtop
C Mtop
A C RV
C
C
A
Mtop
4.5.40 Al Redistributional Layer (AP RDL) Layout

AP.W.1 Width (as interconnect) A  2
Maximum width by {{AP/AP-MD SIZING 0.995um} SIZING -0.995um} (as
AP.W.2 A1  35
interconnect) {NOT INSIDE UBM, CB or CB2}
AP hole width for 28KÅ AP, except < 100 inner 90-degrees vertex of AP holes
AP.W.5 H  3
[width < 3um] within window 100μm x 100μm, stepping 50μm.
Space
(Except following conditions in the same polygon:
1. {{AP AND {AP_PAD SIZING 2 um}} NOT AP_PAD} [INTERACT AP_PAD]
2. Jog length ≤ 1 um
AP.S.1 B  2
3. AP hole [Width < 2 μm])
Definition of AP_PAD:
Width of AP [INTERACT {CB2_WB OR CB2_FC}] > 35 um
Space of metal pad, or space of metal pad to metal line [different nets]
AP.S.1.1 The definition of metal pad: B1  2.5
The width of {AP INTERACT CB2_WB} > 35um.
AP.EN.1 Enclosure of RV C  0.5
AP.DN.1 Minimum AP density across full chip  10%
AP.DN.1.1 Maximum AP density across full chip  70%
AP.W.2® U Recommended total width of BUS line [Connect with bump pad] A’  16
AP.W.1, AP.S.1 allow 0.01 μm tolerance on 45-degree bent AP in (INDDMY OR
INDDMY_MD).
AP.R.1
AP.EN.1 allows 0.01 μm tolerance on 45-degree rotated RV in (INDDMY OR
INDDMY_MD).
AP-MD
CB/CB2
C
C RV A, A1, A’ AP-MD
C
B
AP -MD CB/CB2
Mtop C C
C
RV A, A1, A’
C
Waive condition 1: Surround PAD
X
X
2 um (AP.S.1)
Waive condition 2: Jog length <= 1um
Jog length Jog length

<2 um ≤ 1 um ≤ 1 um <2 um
Waive condition 3: AP hole < 2um

<2 um
AP Hole
4.5.41 Via Layout Recommendations

For better yield and reliability, use of a commercial auto router is recommended to add redundant vias
wherever the layout allows. Please refer to the most updated “T-N45-CL-DR-001-X4, TSMC 45NM CMOS
LOGIC DFM REDUNDANT VIA UTILITY”. You can also download the document from TSMC Online (Design
Portal—Reference Flow) for the reference of redundant via insertion with an auto router.
In the DFM redundant VIA utility, the following layers are excluded to modify redundant vias:
1. DFMEXCL (153;20) is the blockage layer for all DFM layout enhancements.
A user can draw this layer to exclude areas in which an automatic enhancer is not wanted, that is
redundant-vias will not enter this layer.
2. COEXCL(153;0)/VIAxEXCL(153;x), x=1-9, are the blockage layers for via related layout enhancement.
A user can draw these layers to exclude vias which do not want to have a redundant-via. Take VIA1EXCL
as an example, redundant VIA1 will not enter VIA1EXCL region.
3. In addition, this utility does not enhance layout in the following areas:
CB(76), SEALRING(162), CSRDMY(166), LOGO(158), LMARK(109), INDDMY(144), and RMDMY(116;x)
x=1-10. In the area of SRAMDMY(186;0), only VIA1/VIA2 are not enhanced
4.5.42 MOM Layout Rules

 MOM is a fringe Metal-Oxide-Metal capacitor. It is based on the capacitance between parallel metal lines
separated by the inter-level dielectric. The device does not require any additional mask.
 Although any kind of metal combination, M1/Mx/My/Mz/Mr/Mu/AP, is allowed to build a MOM element in
terms of process, TSMC only provides a specific MOM SPICE model and the associated PDK cell named
RTMOM (Rotated Metal Oxide Metal) which is covered by MOMDMY (CAD layer: 155;0) and FMOM
(Finger Metal Oxide Metal) which is covered by MOMDMY (CAD layer: 155;100).
Non-TSMC MOM structure TSMC MOM structure
SPICE PDK Process SPICE PDK Process
M1 X X O O O O
Mx X X O O O O
My/Mz/Mr/Mu/AP X X O X X O
O: available X: not available
*Mu is the ultra thick metal for the interconnection and inductor in the MS/RF process. Please refer to
section 2.5 for the thicknesses.
 MOMDMY_n (n=1~10/AP) is a dummy layer for DRC/LVS to recognize the MOM region.
Layer name CAD layer Description Non-TSMC MOM structure TSMC MOM structure
MOMDMY_1 155;1 M1 MOM region O O
MOMDMY_2 155;2 M2 MOM region O O for Mx
MOMDMY_9 155;9 M9 MOM region O
MOMDMY_10 155;10 M10 MOM region O
MOMDMY_AP 155;20 AP MOM region O
 In order to have a good DRC check, you need to draw the MOMDMY_n carefully. The following examples
are for your reference.
M O M DM Y_n M O M DM Y_n M O M DM Y_n M O M DM Y_n
(G o o d ) (O K ) ( N o t a llo w e d ) ( N o t a llo w e d )
 You need to pay attention to meet the metal local density rule above/under the MOM element. Therefore,
if you want to design a RF MOM circuit with a large area, it is recommended to connect several smaller
MOM elements. And each element should be surrounded with dummy metals.
 The Multi-X Couple layout is recommended for large pair capacitor design to improve the matching
performance (see the section of MOM (Metal Oxide Metal) PDK Capacitor Guidelines).
 Use symmetrical dummy metals around the matched pairs instead of automatically generated dummy
metals.
 Carefully design wire access to capacitor terminals, and consider access to external metal lines to ensure
an optimal symmetry of the device environment.
MOM.S.2 Space of metal (M1/Mx) line-end in MOMDMY_n B  0.10
Maximum sidewall area of total metals in MOM without Via.
MOM.A.1** For the definition of the sidewall area of total metals, please refer to the C  1.31E+06
following figure
Recommend metal density inside {MOMDMY_n SIZING 10um}. (For M1/Mx
MOM.DN.1®  30%
layers)
MOM.R.1 VIA in MOMDMY is not allowed.
Each MOM cell must be covered by MOMDMY_n (n = 155;0~10/20/21/100).
MOM.R.2 DRC only flags no MOMDMY_n (n = 155;0~10/20/21/100) in the chip. But if
there is no MOM cell in the chip, the violation can be waived.
Poly shielding and underneath NW or PW must bias at same
potential for reliability consideration. If poly shielding terminal could
not be tied to the underneath NW or PW, customer should keep bias
between poly terminal and underneath well within thin gate oxide
(Without OD2) or thick gate oxide (With OD2) maximum applied
voltage for reliability consideration.
DRC only check following conditions:
MOM.R.6 {{SR_DPO INTERACT {{OD OR DOD} NOT INSIDE OD2}}
INTERACT {{MOMDMY(155;100) OR MOMDMY(155;0)} NOT
{MOMDMY(155;27) OR MOMDMY(155;28) OR MOMDMY(155;31)
OR MOMDMY(155;32) OR MOMDMY(155;33)}}} [Poly shielding
MOM with dummy OD underneath] and underneath NW or PW must
bias at same potential through metal connection (All resistors and
DNW are treated as broken; all LV N/P well are treated as
connected)
Note for MOM.A.1**:
(1) DRC deck is always turn on (Default) #DEFINE MOM_33V (Turn on if max voltage applied on MOM is
3.3V, or 5.0V). If customer uses different bias range, please turn on related switch.
(2) The rule value of MOM.A.1.a and corresponding space and applied voltage is listed in rule table. If your
layout violates the rule and you apply different operation voltage on MOM, please consult TSMC in
advance if there is any special requirement.
N45 Applied voltage
5.0V 3.3V 2.5V 1.8V 1.2V 1.1V 0.9V
MOM without Via 1.31E+6 1.31E+6 2.27E+07 4.15E+08
M O M w ith o u t V ia
M O M .A .1
’
Z
Li
Z
B
Z’
Hi
C = T o ta l m e ta l s id e w a ll a r e a
M O M DM Y_n n
Z =  Hi x Li
i= 1
L i= f in g e r le n g t h
H i= m e ta l t h ic k n e s s
n = t o ta l m e ta l f in g e r n u m b e r - 1
Figure 4.5.42.1
M O M w ith V ia M O M .A .2
Z Z’
Vw i
Vhi
B Hi
Z’
Li
M O M DM Y_n
F = V ia t o ta l s id e w a ll a r e a +
M O M .R .1 g : M e ta l t o ta l s id e w a ll a r e a
Figure 4.5.42.2 n n
R e c o m m e n d e d th e ra n k
= Vwi x Vhi x m +  Hi x Li
i= 1 i= 1
o f V I A a r r a y in M O M
r e g io n is r e c ta n g u la r
V w i= v ia w id t h
Z
V h i= v ia h e ig h t
H i= m e ta l t h ic k n e s s
L i= m e ta l le n g t h
m = t o ta l v ia n u m b e r p e r f in g e r
n = t o ta l m e ta l f in g e r n u m b e r - 1
N o t re c o m m e n d e d fo r
M O M .R .1 g F ig u r e 4 .5 .3 5 .2
4.5.42.1 MOM (Metal Oxide Metal) PDK Capacitor

Guidelines
This section lists the guidelines for TSMC offered MOM. The offered MOM is a fringe Metal-Oxide-Metal
capacitor. It is based on the capacitor between parallel metal lines separated by the inter-level dielectric. The
device does not require any additional masks.
1. Although any kind of metal combination, M1/Mx/My/Mz/Mr/Mu/AP, is allowed to build a MOM element in
terms of process, TSMC only provides a specific MOM SPICE model and the associated PDK cell named
RTMOM which is covered by MOMDMY (CAD layer: 155;0) and FMOM which are covered by MOMDMY
(CAD layer: 155;100). (The TSMC offered PDK RTMOM and FMOM are implemented by “Mx” or “Mx/M1”,
at least three layers are required).
Non-TSMC MOM structure TSMC MOM structure
SPICE PDK Process SPICE PDK Process
M1 X X O O O O
Mx X X O O O O
My/Mz/Mr/Mu/AP X X O X X O
O: available X: not available
*Mu is the ultra thick metal for the interconnection and inductor in the MS/RF process. Please refer to
section 2.5 for the thicknesses.
2. In order to avoid an OD density violation, PDK MOM cell has pre-inserted dummy OD pattern underneath
MOM to meet design rule requirement.
3. For layout flexibility at I/O region, an option of OD2 enclosing floating dummy OD is also available in MOM
PDK cell.
4. The variables of the PDK MOM structure are listed as the following,
˙Finger Width = the width of metal fingers
˙Finger Space = the space between metal fingers
˙Number of horizontal fingers = the finger number of even metal layer(s) (limited to even number).
˙Number of vertical fingers = the finger number of odd metal layer(s) (limited to even number).
˙Fingers Length = the length of metal fingers (for FMOM)
˙MOM Bottom Metal Layer = the start metal layer of MOM structure.
˙MOM Top Metal Layer = the stop metal layer of MOM structure.
˙Array X = the number of MOM unit on x-direction
˙Array Y = the number of MOM unit on y-direction
5. In order to make sure of the offered MOM SPICE model accuracy, the dummy metal exclusive layers
(DMxEXCL) are adopted below/above MOM to avoid dummy insertion. It is not recommended to manually
place any dummy metal patterns or routing into the regions below/above the MOM. PDK offered MOM also
supports dummy metal insertion in unused M1 and Mx layers by using parameter “dmflag=1” to turn on
dummy metal insertion and “dmflag=0” to turn off. If manually dummy metal or routing (not generated by
PDK itself) is added into the region below/above the PDK generated MOM, the resulting extra parasitic and
model inaccuracy impact must be taken into consideration by designers.
6. If the metal density rule is violated due to the large empty regions above/below MOM structures, parallel
connected small MOMs array with dummy metals between individual MOM is recommended as shown
below.
S m a ll A r e a S m a ll A r e a
RTM OM RTM OM
L a rg e a re a D u m m y p a tte rn re g io n
D u m m y p a tte rn re g io n
RTM O M
S m a ll A r e a S m a ll A r e a
RTM OM RTM OM
DM xEXCL
FFigure
i g u r e 44.5.42.1.1
.5 .3 9 .1 .1
7. The Multi-X Couple layout is recommended for large-pair capacitor design, which can improve the matching
performance. The Parallel and Multi-X Couple layout for match pairs is illustrated.
 The unit cell C1 and the unit cell C2 of the Multi-X Couple MOM are placed in an array with alternate
pattern placement in each row and each column.
 If the total capacitance C > 400fF is required, it is recommended to use Multi-X Couple layout type
with unit cell < 200fF, to improve the matching performance. It is not recommended to use 2x200fF
Parallel MOM design.
M u lti - X
P a r a lle l u n it c e ll o f C 1 C1 C2 C1 C2 u n it c e ll o f C 2
(+ ) (+ ) (+ ) (+ )
C1 (+ ) (+ ) C2
(-)
(-) (-)
Figure
F i g u r e4.5.42.1.2
4 .5 .3 9 .1 .2 Figure
F i g u r e 4.5.42.1.3
4 .5 .3 9 .1 .3
8. Figure 4.5.42.1.4 shows the mismatching (one sigma of delta capacitance) versus 1/C0.5 of a parallel MOM
pair with 2um fixed distance. The SPICE model shot on median value of lots will be optimistic compared to
process variation, therefore it is recommended to reserve enough design margins to cover process variation.
Figure 4.5.42.1.4 is for reference only, please refer to the SPICE document, “T-N45-CM-SP-003” for the
most updated figure.
9. The parallel MOM mismatching will increase dramatically with the distance between the MOM pair larger
than 200um, as shown in Figure 4.5.42.1.5. It is recommended to use the MOM pair with distance less than
200um for optimized mismatching performance.
10. It is recommended putting MOM device with surrounding pattern density ≥ 30% (MOM.DN.1® ) checked by
MOMDMY_n sizing 10um area to migrate local pattern density effect.
0.40 0.7
Lot 1 NV/NH=24/24 (lot1)

0.35 NV/NH=48/48 (lot1)
Lot 2 0.6 NV/NH=72/72 (lot1)
Lot 3 NV/NH=144/144 (lot1)
0.30 NV/NH=24/24 (lot2)
m odel 0.5 NV/NH=48/48 (lot2)
NV/NH=72/72 (lot2)
s of (dC/C)(%)
s of (dC/C)(%)
0.25 NV/NH=144/144 (lot2)
0.4
0.20
0.3
0.15
0.2
0.10
0.1
0.05
0.00 0.0
0.00 0.05 0.10 0.15 0.20 1 10 100 1000 10000
1/(Cmom_mean)0.5(fF-0.5) Distance (um)
Figure 4.5.39.1.4 Figure 4.5.39.1.5

Figure 4.5.42.1.4 Figure 4.5.42.1.5
11. The following guidelines are provided for both modeling accuracy and safe device operation for MOM with
poly shielding usage:
 Leaving shielding poly floating is not recommended, it is recommended to connect shielding poly to
AC ground for shielding purpose.
 Local OD density must meet the design rule check requirement.
 TSMC strongly recommends to tie shielding poly terminal to the underneath well to avoid any
reliability and model accuracy concern.
 If shielding poly terminal could not be tied to the underneath well, for reliability consideration,
customer must keep bias between poly terminal and underneath well within thin(Without OD2) or
thick(With OD2) gate oxide maximum applied voltage.
4.5.43 Top VIAu Layout Rules (Mask ID: 373, 374, 375,
376, 377, 372, 37A)
 For the specification of metals/vias stacking sequence and associated mask ID, please refer to section 2.5.
 CAD layer datatype of VIAu is “40” (the same as that of VIAz due to the same via size).
 VIAu is designed to connect between Mu and Mu-1. This section doesn’t define the VIAu rules specifically. You
have to follow VIAz rules and Mu rules (only Mu.EN.1, Mu.EN.2, Mu.R.1) for VIAu design.
4.5.44 Mu (Ultra Thick Metal) Layout Rules

 Mu (UTM: 35KÅ ) is only allowed as the most top metal layer and only one Mu layer is allowed in a chip.
 Mu can not co-exist with other different thickness top metal layer(s) (such as Mz, My or Mr) on the same metal
layer.
 Mu above Mr metal (12.5KA) is not allowed.
 CAD layer datatype of Mu metal is “60” (that of dummy Mu layer is “61”), and CAD layer datatype of its
Mu.W.1 Width A  2.00
Maximum width [except bond pad and INDDMY_MD]
Mu.W.2 (This check doesn’t include the regions covered by layers of LMARK, {INDDMY B  12.00
SIZING 22 μm}, CB, and {UBM INTERACT CBD}.)
Mu.S.1 Space C  1.00
Mu.EN.1 Enclosure of VIAu D, E  0.30
Mtop-1 enclosure of VIAu
Mu.EN.2 F  0.08
Mu.A.1 Area G  9.00
Mu.A.2 Enclosed area H  9.00
At least 2 VIAu with space  1.7 µm are required to connect [Mu to Mz], [Mu to
Mu.R.1 top My(2XTM)], [Mu to inter My] or [Mu to Mx] (Please put as many vias as I  1.70
possible for reliability and RF applications).
Mu.R.2U Mu line-end must be rectangular. Other shapes are not allowed.
Mu.DN.1 Minimum metal density over the whole chip (include INDDMY)  20%
Mu.DN.1.1 Maximum metal density over the whole chip (include INDDMY)  50%
Minimum Mu density range in window 125 µm x 125 µm, stepping 62.5 µm. The
Mu.DN.2
- LOGO/INDDMY/INDDMY_MD  20%
region) is  1/4 checking window width (31.25um).
Maximum Mu density range in window 125 µm x 125 µm, stepping 62.5 µm. The
- Bond pad
Mu.DN.2.1 - Chip corner stress relief area and seal-ring  85%
- LMARK/LOGO/INDDMY/INDDMY_MD
region) is  1/4 checking window width (31.25um).
Mu.R.3U Mu above Mr metal is not allowed.
A 0.06um2 ((3.0*3.0)-(2.99*2.99)) checking tolerance is allowed for the rules
Mu.R.4
within the region of (INDDMY SIZING 16 µm): Mu.A.1 and Mu.A.2.
Mu.R.5 Each Metal(pin) layer can only interact with one related Metal(drawn) layer.
DMu.R.1 DMu is a must. The DMu CAD layer must be different from the Mu CAD layer.
A
E
/B M u .R .2
IN D .R .1 1
C C1 D
D E
E
H
G M u
H M u
F ig . b
Mu Mu F ig . a
Mu
F o r p r o d u c t y ie ld c o n c e r n ,
F ig . a is p r e fe r r e d .
M
Muu
Illustration of Mu.R.1, IND.R.2, IND.R.3 and IND.R.4 Rules

I
M9 M9
I F
M9 I
M10  2.0 μm
I M9
I II III
Isolated single VIAu(VIAz/VIAr) is not allowed.
I: Two Vu space > 1.7 μm.

II: Two Vu space < 1.7 μm but belong to different nets.
III: Two Vu on the same net but not inside the same overlapped metal region (Mtop-1 and Mu).
4.5.45 Inductor Layout Rules

TSMC offered 3 kinds of inductor rules, including standard low metal density spiral inductor rules
(INDDMY) and logic inductor rules (INDDMY_MD and INDDMY_HD), according to different device/circuit
applications. But TSMC only provided a specific inductor device SPICE model /PDK for Low-density inductor
(identified by INDDMY) design.
Different INDDMY dummy layers are defined to recognize the three types inductors: Low-density,
Medium-density and High-density. In order to have a correct DRC check, you need to draw the corresponding
inductor dummy layers carefully.
Rule Type SPICE PDK LVS Process

Low-density INDDMY (INDDMY) ○ ○ ○ ○
Medium-density INDDMY (INDDMY_MD) ╳ ╳ ╳ ○
High-density INDDMY (INDDMY_HD) ╳ ╳ ╳ ○
○: available ╳: not available
1. Low-density INDDMY (INDDMY): INDDMY is offered to allow very low metal density within an inductor to
achieve better inductor performance. The dummy generation utility does not insert floating dummy
OD/PO/metal into INDDMY by default and provides an option to generate DOD/DPO within INDDMY. In
the INDDMY layer, the inter-via(both Vx and Vy) and top via Vy(2XTM) are all not allowed. It is required to
refer to section 4.5.32 LOWMEDN layout rules, for the usage of Inductor with protection ring when no
dummy metals (M1/Mx) are filled within INDDMY.
2. Medium-density INDDMY (INDDMY_MD): Special inductor dummy utility provides an option to auto-
generate specific dummy metal (DM1 and DMx) and DOD/DPO within INDDMY_MD to lower the inductor
performance degradation caused by dummy fill. In the INDDMY_MD layer, the inter-via(both Vx and Vy)
and top via Vy(2XTM) are all not allowed. Inductor with protection ring and LOWMEDN is not required.
The real inductor performance impact by the extra-added dummy pattern must be taken care by designers.
3. High-density INDDMY (INDDMY_HD): Special inductor dummy utility provides an option to auto-generate
specific dummy metal (DM1, DMx, DMy, DMz, DMr and DMu) and DOD/DPO within INDDMY_HD to lower
the inductor performance degradation caused by dummy fill. In the INDDMY_HD layer, the inter-via(both Vx
and Vy) and top via Vy(2XTM) are allowed on the premise that all the related logic design rules has been
followed well. Inductor with protection ring and LOWMEDN is not required. The real inductor performance
impact by the extra-added dummy pattern must be taken care by designers.
Table 4.5.45 Inductor Rule Summary

Rule Type INDDMY INDDMY_MD INDDMY_HD
Metal Dummy inserted by dummy DM1, DMx, DMy,
NO DM1/DMx
generation utility DMz, DMr and DMu
DOD/DPO inserted by dummy
YES YES YES
generation utility
Dummy Via inserted by dummy
NO NO NO
generation utility
Inter-via(both Vx and Vy) and top via
Not Allowed Not Allowed Allowed
Vy(2XTM)
Not allowed except the Mx or My
Inter-metal layer (Mx/My) layer (one layer only) directly Allowed Allowed
below [Mz, Mr or Mu],
ACTIVE device, ACTIVE OD/PO
Not Allowed Not Allowed Allowed
and interconnection OD/PO
Protection ring and LOWMEDN Required Not Required Not Required
4.5.45.1 INDDMY Layer Identified Inductor Layout Rules

 For eddy current reduction to achieve better inductor performance, a special metal (and OD/PO) dummy block layer
called “INDDMY” (CAD layer: 144) is offered to allow very low metal density within an inductor, provided a proper
surrounding (dummy) metal scheme requirement is satisfied. When an “INDDMY” layer is used to construct inductors,
one must follow the additional process-related design rules listed below. Please note that “INDDMY” can only be used
for inductor devices, TSMC does not support non-inductor devices constructed with “INDDMY”.
 Inductor devices offered in TSMC PDK can fit the design rules listed below.
 For the INDDMY layer identified low metal density inductor regions, the inter-via (both Vx and Vy) and top via Vy
(2XTM) are all not allowed. Please refer to the rules below for details.
IND.W.1 M1, DM1, DM1_O width in (INDDMY SIZING 16 µm) A1  0.28
IND.W.2 Mx, DMx, DMx_O width in (INDDMY SIZING 16 µm) A2  0.28
IND.W.3 My, DMy width in (INDDMY SIZING 16 µm) A3  0.40
IND.W.4 Mz, DMz width in (INDDMY SIZING 16 µm) A4  0.40
IND.W.5 Mr, DMr width in (INDDMY SIZING 16 µm) A5  0.55
IND.W.6 Mu, DMu width in (INDDMY SIZING 16 µm) A6  2.0
IND.W.7 M1, DM1, DM1_O/Mx, DMx, DMx_O maximum width in (INDDMY SIZING 16 µm) B1  4.5
IND.W.8 My, DMy maximum width inside (INDDMY SIZING 22 µm) (for inductor application only) B2  12.00
IND.W.9 Mz, DMz/Mr, DMr/Mu, DMu maximum width inside (INDDMY SIZING 22 µm) (for inductor application only) B3  30.00
IND.W.10 Maximum dimension (either width or length) of an INDDMY region C  600.00
IND.S.1 M1, DM1, DM1_O space in (INDDMY SIZING 16 µm) D1  0.28
IND.S.2 Mx, DMx, DMx_O space in (INDDMY SIZING 16 µm) D2  0.28
IND.S.3 My, DMy space in (INDDMY SIZING 16 µm) D3  0.40
IND.S.4 Mz, DMz space in (INDDMY SIZING 16 µm) D4  0.40
IND.S.5 Mr, DMr space in (INDDMY SIZING 16 µm) D5  0.55
IND.S.6 Mu, DMu space in (INDDMY SIZING 16 µm) D6  1.0
M1, DM1, DM1_O/Mx, DMx, DMx_O/My, DMy/Mz, DMz space in (INDDMY SIZING 16 µm) [at least one metal
IND.S.7 E1  0.5
line width > 1.5 µm (W1) and the parallel metal run length > 1.5 µm (L1)]
Mr, DMr space in (INDDMY SIZING 16 µm) [at least one metal line width > 1.5 µm (W2) and the parallel metal
IND.S.8 E2  0.65
run length > 1.5 µm (L2)]
My, DMy/Mz, DMz/Mr, DMr space in (INDDMY SIZING 16 µm) [at least one metal line width > 4.5 µm (W3) and
IND.S.9 E3  1.5
the parallel metal run length > 4.5 µm (L3)]
Mu, DMu space in (INDDMY SIZING 16 µm) [at least one metal line width > 12 µm (W4) and the parallel metal
IND.S.10 E4  2.0
run length > 12 µm (L4)]
In the region of (INDDMY SIZING 16 µm), inter-via Vx, Vy and top via Vy (2XTM) are all not allowed. (Except
IND.R.1
TLDMY region and Vx in {LOWMEDN NOT (LOWMEDN SIZING -4 µm)})
At leastfour VIAz with space  1.7 µm are required to connect [two Mz layers], [Mz to inter-My] or [Mz to Mx] in
IND.R.2 I1  1.70
(INDDMY SIZING 16 µm).
At leastfour VIAu with space  1.7 µm are required to connect [Mu to Mz], [Mu to inter-My], [Mu to top My
IND.R.3 I2  1.70
(2XTM)] or [Mu to Mx] in (INDDMY SIZING 16 µm).
At leastfour VIAr with space  1.7 µm are required to connect [two Mr layers] or [Mr to Mx] in (INDDMY SIZING
IND.R.4 I3  1.70
16 µm)
In the INDDMY identified region “a”, except the inter-metal Mx or My layer (one layer only) directly below [top
My, Mz, Mr or Mu], any other inter-metal layer (Mx/My) is not allowed. (e.g. for a 1P6M process with 0.9 µm of
IND.R.5 M6 (Mz), then Mx of M5 is allowed, but other lower Mx metal layers are not allowed for the INDDMY identified
inductor.) (Except TLDMY region and Mx in {(LOWMEDN NOT (LOWMEDN SIZING -5 µm)) INTERACT VIAx
bar})
In the INDDMY identified region “a”, except the needed patterns for inductor structure itself (such as OD, PO,
IND.R.6U PP, CO, M1, VIAz, Mz,…), any active device, active OD/PO, interconnection OD/PO or resistance sensitive
metal routing is not allowed. (This rule cannot be checked by DRC.)
In the ring region “b” of {(INDDMY SIZING 16µm) NOT INDDMY} with 16 µm in width, except the straight metal
line (metal port leading) that connects the inductor to the circuits outside INDDMY region and the needed
patterns for inductor structure itself (such as OD, PP, CO and M1 for guard-ring…), any active device, active
IND.R.7U
OD/PO, interconnection OD/PO or resistance sensitive metal routing is not allowed in this region. The metal port
leading is defined as the metal line that goes through the region “a” and 16 µm wide ring region “b” for
interconnect. (This rule cannot be checked by DRC.)
IND.R.8 A 45-degree rotated RV is allowed inside (INDDMY SIZING 22 µm)
Guard-ring enclosure of inductor metal spirals.
1. The larger distance (such as 50 µm) from inductor metal spirals to guarding-ring would make better inductor
electrical performance and reduce the coupling on/between components nearby. Please take the impact of the
IND.R.9U
guard-ring enclosure of inductor metal spirals into consideration.
2. Keep the INDDMY regions of separate inductors located as uniform as possible over the whole chip area to
maintain CMP uniformity.
IND.DN.1 Maximum density of {(INDDMY OR INDDMY_MD) OR TLDMY} on a whole chip  5%
Maximum M1/Mx/Inter-My density within (INDDMY SIZING 16 µm) in window 125 µm x 125 µm, stepping 62.5
IND.DN.2  85%
µm
IND.DN.3 M1/Mx/My/Mz/Mr metal density over the whole chip (include INDDMY)  20%
The metal density difference between any two neighboring checking windows including DMxEXCL (window 200
IND.DN.5U µm x 200 µm, stepping 200 µm). Anticipate metal density gradient from layout of small cell by targeting density  60%
~60% (this way, it will limit the risk of low density and high gradient.)
IND.DN.7 Maximum density of (INDDMY OR INDDMY_MD) in window 1600 µm x 1600 µm, stepping 800 µm  14%
IND.DN.8® Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY  20%
IND.DN.9® Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY  15%
A 0.01um checking tolerance is allowed for the rules: IND.W.1, IND.W.2, IND.W.3, IND.W.4, IND.W.5, IND.W.6,
IND.R.10 IND.W.7, IND.W.8, IND.W.9, IND.W.10, IND.S.1, IND.S.2, IND.S.3, IND.S.4, IND.S.5, IND.S.6, IND.S.7,
IND.S.8, and IND.S.9.
A 0.01 μm checking tolerance in the region of [INDDMY SIZING 22 μm] is allowed for the rules of RV.W.1,
IND.R.14 RV.S.1, RV.EN.1, AP.W.1, AP.W.2, AP.S.1, and AP.EN.1.
Note: DRC implement 0.01 μm tolerance on Vertical, Horizontal and 45-degree bent.
IND.R.15gU Recommend putting NT_N to fully cover the inductor (metal) region to achieve high quality factor.
Table Notes:
1. The INDDMY layer blocks the automated dummy pattern generation.
2. The dummy generation utility inserts floating dummy OD/PO/metal patterns into the region outside INDDMY.
3. For TSMC PDK offered inductor, a native substrate region is created under the inductor coil to minimize eddy
currents. This region is specified/implemented by the implant blocking NT_N layer (CAD layer:11). The NT_N
drawn layer adds no process cost and no extra mask.
4. TSMC offered PDK inductor is an octagonal type, the square type inductor in the following figure is only for rule
illustration.
5. If designers want to design the inductors with inter-layer metal and/or inter-layer via, all the related regular logic
design rules must be followed well, especially for the inter-layer metal density rules.
6. For an inductor to be inserted into dummy OD/PO/Metal patterns , the INDDMY dummy layer should be removed
to allow the dummy utility’s dummy pattern generation.
7. Please put in as many vias as possible for reliability and RF applications for IND.R.2, IND.R.3 and IND.R.4.
8. The following inductor rule description is based on the concept of different regions (a and b) from center to edge to
achieve the flexibility of design easiness and maintaining density for uniformity. See the following figure.
9. IND.DN.8® and IND.DN.9® : Inductor PDK has already added OD/PO into INDDMY.
10. It is important to refer to section 4.5.32, LOWMEDN Layout Rules, for the usage of inductor with protection ring.
1 6 u m (r e g io n “ b ” ) IN D D M Y
M e ta l IN D D M Y
IN D .S .7 ~ 1 0
In d u c to r (m e ta l)
C o r e c ir c u it D A /B > L 1 /L 2 /L 3 /L 4
E 1 /E 2 /E 3 /E 4
R e g i o n " a” "
> W 1 /W 2 /W 3 /W 4
16um 1 61 6 u m ( r e g i o n “ b ” )
C : M a x im u m d im e n s io n o f IN D D M Y
M e ta l p o r t le a d in g :
m e ta l c o n n e c ts th e in d u c to r
to c ir c u its o u ts id e IN D D M Y .
1 6 u m (r e g io n “ b ” )
D u m m y g e n e r a tio n u tility in s e r ts flo a tin g d u m m y

O D /P O /M e ta l p a tte r n s in to th e r e g io n o u ts id e IN D D M Y .
R e g io n “ b ” w ith 1 6 u m in w id th
Figure 4.5.45.1
4.5.45.2 INDDMY_MD Layer Identified Inductor Layout

Rules
For better process uniformity and reliability, a special dummy layer called “INDDMY_MD” (CAD layer: 144;42)
is offered to generate specific dummy metal (DM1 and DMx) and DOD/DPO within INDDMY_MD. When
“INDDMY_MD” layer is used to construct inductors, one must follow the additional process-related design rules
listed below. Please be noted that “INDDMY_MD” can only be used for inductor devices, and TSMC does not
support for non-inductor devices constructed with “INDDMY_MD ”. Please take care the SPICE model /LVS
flow by yourselves when using INDDMY_MD layer to design inductor.
IND_MD.W.1 M1, DM1, DM1_O width in (INDDMY_MD SIZING 16 µm) A1  0.28
IND_MD.W.2 Mx, DMx, DMx_O width in (INDDMY_MD SIZING 16 µm) A2  0.28
IND_MD.W.3 My, DMy width in (INDDMY_MD SIZING 16 µm) A3  0.40
IND_MD.W.4 Mz, DMz width in (INDDMY_MD SIZING 16 µm) A4  0.40
IND_MD.W.5 Mr, DMr width in (INDDMY_MD SIZING 16 µm) A5  0.55
IND_MD.W.6 Mu, DMu width in (INDDMY_MD SIZING 16 µm) A6  2.0
IND_MD.W.7 M1, DM1, DM1_O/Mx, DMx, DMx_O maximum width in (INDDMY_MD SIZING 16 µm) B1  4.5
IND_MD.W.8 My, DMy maximum width inside (INDDMY_MD SIZING 22 µm) (for inductor application only) B2  12.00
Mz, DMz/Mr, DMr/Mu, DMu maximum width inside (INDDMY_MD SIZING 22 µm) (for inductor application
IND_MD.W.9 B3  30.00
only)
IND_MD.W.10 Maximum dimension (either width or length) of an INDDMY_MD region C  600.00
IND_MD.S.1 M1, DM1, DM1_O space in (INDDMY_MD SIZING 16 µm) D1  0.28
IND_MD.S.2 Mx, DMx, DMx_O space in (INDDMY_MD SIZING 16 µm) D2  0.28
IND_MD.S.3 My, DMy space in (INDDMY_MD SIZING 16 µm) D3  0.40
IND_MD.S.4 Mz, DMz space in (INDDMY_MD SIZING 16 µm) D4  0.40
IND_MD.S.5 Mr, DMr space in (INDDMY_MD SIZING 16 µm) D5  0.55
IND_MD.S.6 Mu, DMu space in (INDDMY_MD SIZING 16 µm) D6  1.0
M1, DM1, DM1_O/Mx, DMx, DMx_O/My, DMy/Mz, DMz space in (INDDMY_MD SIZING 16 µm) [at least
IND_MD.S.7 E1  0.5
one metal line width > 1.5 µm (W1) and the parallel metal run length > 1.5 µm (L1)]
Mr, DMr space in (INDDMY_MD SIZING 16 µm) [at least one metal line width > 1.5 µm (W2) and the
IND_MD.S.8 E2  0.65
parallel metal run length > 1.5 µm (L2)]
My, DMy/Mz, DMz/Mr, DMr space in (INDDMY_MD SIZING 16 µm) [at least one metal line width > 4.5 µm
IND_MD.S.9 E3  1.5
(W3) and the parallel metal run length > 4.5 µm (L3)]
Mu, DMu space in (INDDMY_MD SIZING 16 µm) [at least one metal line width > 12 µm (W4) and the
IND_MD.S.10 E4  2.0
parallel metal run length > 12 µm (L4)]
In the region of (INDDMY_MD SIZING 16 µm), inter-via Vx, Vy and top via Vy (2XTM) are all not allowed.
IND_MD.R.1
(Except TLDMY region and Vx in {LOWMEDN NOT (LOWMEDN SIZING -4 µm)})
At least four VIAz with space  1.7 µm are required to connect [two Mz layers], [Mz to inter-My] or [Mz to
IND_MD.R.2
Mx] in (INDDMY_MD SIZING 16 µm).
At least four VIAu with space  1.7 µm are required to connect [Mu to Mz], [Mu to inter-My], [Mu to top My
IND_MD.R.3
(2XTM)] or [Mu to Mx] in (INDDMY_MD SIZING 16 µm).
At least four VIAr with space  1.7 µm are required to connect [two Mr layers] or [Mr to Mx] in (INDDMY_MD
IND_MD.R.4
SIZING 16 µm)
IND_MD.R.5 In the INDDMY_MD identified region “a”, except the Mx or My layer (one layer only) directly below [Mz, Mr
or Mu], any other inter-metal layer (Mx/My) is not allowed. (e.g., for a 1P6M process with 0.9 µm of M6
(Mz), then Mx of M5 is allowed, but other lower Mx metal layers are not allowed for the INDDMY_MD
identified inductor.)
Except the following condition:
1. TLDMY region
2. Mx in {{LOWMEDN NOT {LOWMEDN SIZING –5 μm}} INTERACT VIAx bar}
3. Inter-metal Mx in INDDMY_MD is allowed if the metal density of all M1/Mx layer in region "a" are all
larger than 10% in window 125um x 125um, stepping 62.5um (M1.DN.1 and Mx.DN.1)
4. Inter-metal My in INDDMY_MD is allowed if the metal density of all M1/Mx/My layer in region "a" are all
larger than 10% in window 125um x 125um, stepping 62.5um (M1.DN.1, Mx.DN.1 and My.DN.1)
In the INDDMY_MD identified region “a”, except the needed patterns for inductor structure itself (such as
IND_MD.R.6U OD, PO, PP, CO, M1, VIAz, Mz,…), any active device, active OD/PO, interconnection OD/PO or resistance
sensitive metal routing is not allowed. (This rule cannot be checked by DRC.)
In the ring region “b” of {(INDDMY_MD SIZING 16µm) NOT INDDMY_MD} with 16 µm in width, except the
straight metal line (metal port leading) that connects the inductor to the circuits outside INDDMY_MD region
and the needed patterns for inductor structure itself (such as OD, PP, CO and M1 for guard-ring…), any
IND_MD.R.7U
active device, active OD/PO, interconnection OD/PO or resistance sensitive metal routing is not allowed in
this region. The metal port leading is defined as the metal line that goes through the region “a” and 16 µm
wide ring region “b” for interconnect. (This rule cannot be checked by DRC.)
IND_MD.R.8 A 45-degree rotated RV is allowed inside (INDDMY_MD SIZING 22 µm)
Guard-ring enclosure of inductor metal spirals.
1. The larger distance (such as 50 µm) from inductor metal spirals to guarding-ring would make better
inductor electrical performance and reduce the coupling on/between components nearby. Please take
IND_MD.R.9U
the impact of the guard-ring enclosure of inductor metal spirals into consideration.
2. Keep the INDDMY_MD regions of separate inductors located as uniform as possible over the whole chip
area to maintain CMP uniformity.
IND_MD.DN.1 Maximum density of {INDDMY_MD OR TLDMY OR INDDMY} on a whole chip  5%
Maximum M1/Mx/Inter-My density within (INDDMY_MD SIZING 16 µm) in window 125 µm x 125 µm,
IND_MD.DN.2  85%
stepping 62.5 µm
IND_MD.DN.3 M1/Mx/My/Mz/Mr metal density over the whole chip (include INDDMY_MD OR INDDMY)  20%
The metal density difference between any two neighboring checking windows including DMxEXCL (window
IND_MD.DN.5U 200 µm x 200 µm, stepping 200 µm). Anticipate metal density gradient from layout of small cell by targeting  60%
density ~60% (this way, it will limit the risk of low density and high gradient.)
IND_MD.DN.7 Maximum density of (INDDMY_MD OR INDDMY) in window 1600 µm x 1600 µm, stepping 800 µm  14%
IND_MD.DN.8® Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY_MD  20%
IND_MD.DN.9® Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY_MD  15%
A 0.01um checking tolerance is allowed for the rules: IND_MD.W.1, IND_MD.W.2, IND_MD.W.3,
IND_MD.W.4, IND_MD.W.5, IND_MD.W.6, IND_MD.W.7, IND_MD.W.8, IND_MD.W.9, IND_MD.W.10,
IND_MD.R.10
IND_MD.S.1, IND_MD.S.2, IND_MD.S.3, IND_MD.S.4, IND_MD.S.5, IND_MD.S.6, IND_MD.S.7,
IND_MD.S.8, IND_MD.S.9 and IND_MD.S.10.
A 0.01 μm checking tolerance in the region of [INDDMY_MD SIZING 22 μm] is allowed for the rules of
IND_MD.R.14 RV.W.1, RV.S.1, RV.EN.1, AP.W.1, AP.W.2, AP.S.1, and AP.EN.1.
Note: DRC implement 0.01 μm tolerance on Vertical, Horizontal and 45-degree bent.
IND_MD.R.15gU Recommend putting NT_N to fully cover the inductor (metal) region to achieve high quality factor.
IND_MD.R.18 INDDMY overlap with (INDDMY_HD OR INDDMY_MD) is not allowed.
IND_MD.R.19 INDDMY_HD overlap with INDDMY_MD is not allowed.
IND_MD.R.15gU
Table Notes:
1. Special inductor dummy utility provides an option to auto-generate specific dummy metal (DM1 and DMx)
and DOD/DPO within INDDMY_MD to lower the inductor performance degradation caused by dummy fill.
The real inductor performance impact by the extra-added dummy pattern must be taken care by designers.
2. Inductor with protection ring and LOWMEDN is not required.
3. Please put in as many vias as possible for reliability and RF applications for IND_MD.R.2, IND.R_MD.3
and IND_MD.R.4
4. The following inductor rule description is based on the concept of different regions (a and b) from center to
edge to achieve the flexibility of design easiness and maintaining density for uniformity. See the following
figure.
Figure 4.5.45.2
4.5.45.3 INDDMY_HD Layer Identified Inductor Layout

Rules
For better process uniformity and reliability, a special dummy layer called “INDDMY_HD” (CAD layer:
144;43) is offered to generate specific dummy metal (DM1, DMx, DMy, DMz, DMr and DMu) and DOD/DPO
within INDDMY_HD to lower the inductor performance degradation caused by dummy fill. The real inductor
performance impact by the extra-added dummy pattern must be taken care by designers. Please be noted that
“INDDMY_HD” can only be used for inductor devices, and TSMC does not support for non-inductor devices
constructed with “INDDMY_HD ”. Please take care the SPICE model /LVS flow by yourselves when using
INDDMY_HD layer to design inductor.
All the layout rules for Inductors identified with INDDMY_HD follow general logical rules, for example, to
follow 10% minimum metal density rule in INDDMY_HD.
Table Notes:
1. For the INDDMY_HD layer identified inductor region, the inter-via(both Vx and Vy) and top via Vy(2XTM)
are allowed on the premise that all the related logic design rules has been followed well.
2. Inductor with protection ring and LOWMEDN is not required.
3. When other device, patterns or metal routing are put within INDDMY_HD, the extra parasitic, device
couplings and model accuracy issue also must be taken into consideration by designers.
4.5.46 Introduction of Inductor and Transmission Line

4.5.46.1 INDDMY Layer Identified TSMC PDK Inductor
Introduction
TSMC offered a variety of ways to construct inductor devices for RF/MS circuit design need:
1. To achieve lower inductor series resistance, a thickness larger than 3 µm ultra thick Cu metal (Mu) process
is offered and its associated process design rule is listed in the section 4.5.46.1.
2. In section 4.5.46.1 below, we used the inductor offered in TSMC PDK as examples to briefly illustrate the
basic guidelines and elements for constructing various inductors such as standard (simple spiral),
symmetric and center-tap inductors.
4.5.46.1.1 Introduction to PDK Inductor

1. TSMC PDK offered octagonal inductor varieties in the 45nm/40nm technology node mainly include three
different layout configurations for different top metal schemes (as summarized in the section of RTMOM
(Rotated Metal Oxide Metal)): standard (STD), symmetric (SYM) and center-tap (CT).
2. The offered inductors are fabricated on top of P-substrate that specified/implemented by an NT_N
implantation-blocking layer (CAD layer:11, that adds no extra mask/process cost). The offered inductor is 3-
Terminal including two signal terminals and the third terminal for grounded guard-ring (Center-tap inductor
has the fourth terminal for center-tap connection).
3. The INDDMY dummy layer(s) (CAD layer:144) is needed to identify the inductor with very low metal density
within the inductor, the DRC (design rule check) deck will check the INDDMY identified region by inductor
related/specific rules (the section of INDDMY Layer Identified Inductor Layout Rules). The INDDMY layer
cannot be used for other applications (for inductor only), and allowed maximum density of INDDMY in
whole chip is 5% (rule IND.DN.1).
4. The INDDMY dummy layer blocks the automated generation of dummy OD/PO/Metal patterns (dummy Al-
RDL patterns will not be generated).
5. The dummy OD/PO/Metal patterns make better pattern uniformity and better metal CMP uniformity over the
silicon wafer.
6. From the inductor model accuracy point of view, other devices or metal patterns is not allowed to be placed
below/above the offered inductors, as the magnetic flux and the resulted inductor performance will be
affected by the extra-added parts. If other devices, patterns or metal routing (not generated by PDK itself)
are added into the region below/above the PDK inductor, the resulted extra parasitic and model inaccuracy
must be taken into consideration by designers.
7. Table 4.5.46.2 shows the TSMC PDK inductor layout parameters. The corresponding temperature effect
and corner cases are also included; please refer to the model documents for model scope and other details.
S ta n d a rd S y m m e tr ic C e n te r-T a p
P o rt1 P o rt2 P o rt1 P o rt2
N = 3 .5 N=3 N=3
G D IS
2R P o rt2 G D IS
P o rt1 2R 2R
W s
IN D D M Y e d g e
CT
GND GND GND
Figure 4.5.46.1 PDK inductor top-view illustration
Table 4.5.46.1 TSMC offered three kinds of Mz, Mz+Mu, Mu inductor structure options
T o p M e ta l S c h e m e Nam e Type S p ir a l C o il C ro s s P a s s C ta p
Mz s p ir a l_ s td _ m z _ a STD M z (M to p ) M z (M to p ) / A L -R D L
Mz s p ir a l_ s y m _ m z _ a SYM M z (M to p ) M z (M to p ) / A L -R D L
Mz s p ir a l_ s y m _ c t_ m z _ a _ x CT M z (M to p ) M z (M to p ) / A L -R D L M x (M to p -1 )
Mz s p ir a l_ s td _ m z a _ a STD M z (M to p ) // A L -R D L M z (M to p ) / A L -R D L
Mz s p ir a l_ s y m _ m z a _ a SYM M z (M to p ) // A L -R D L M z (M to p ) / A L -R D L
Mz s p ir a l_ s y m _ c t_ m z a _ a _ x CT M z (M to p ) // A L -R D L M z (M to p ) / A L -R D L M x (M to p -1 )
Mz s p ir a l_ s y m _ m z _ a x SYM M z (M to p ) M z (M to p ) / [M x (M to p -1 ) // A L -R D L ]
Mz s p ir a l_ s y m _ c t_ m z _ a x _ a CT M z (M to p ) M z (M to p ) / [M x (M to p -1 ) // A L -R D L ] A L -R D L
Mz + Mz s p ir a l_ s td _ m 2 z a _ z a STD M z (M to p -1 ) // M z (M to p ) // A L -R D L [(M z (M to p ) // A L -R D L ] / M z (M to p -1 )
Mz + Mz s p ir a l_ s y m _ m 2 z a _ z SYM M z (M to p -1 ) // M z (M to p ) // A L -R D L M z (M to p ) / M z (M to p -1 )
Mz + Mz s p ir a l_ s y m _ c t_ m 2 z a _ z _ a CT M z (M to p -1 ) // M z (M to p ) // A L -R D L M z (M to p ) / M z (M to p -1 ) A L -R D L
Mu s p ir a l_ s td _ m u _ x STD M u (M to p ) M u / M x (M to p -1 )
Mu s p ir a l_ s y m _ m u _ x SYM M u (M to p ) M u / M x (M to p -1 )
Mu s p ir a l_ s y m _ c t_ m u _ x _ a CT M u (M to p ) M u / M x (M to p -1 ) A L -R D L
Mz + Mu s p ir a l_ s td _ m u _ z STD M u (M to p ) M u / M z (M to p -1 )
Mz + Mu s p ir a l_ s y m _ m u _ z SYM M u (M to p ) M u / M z (M to p -1 )
Mz + Mu s p ir a l_ s y m _ c t_ m u _ z _ x CT M u (M to p ) M u / M z (M to p -1 ) M x (M to p -2 )
Table 4.5.46.2 TSMC offered inductor structure geometry parameters

W (w )(u m ) s p ir a l tr a c k w id th
N (n r) n u m b e r o f tu rn s
R (ra d )(u m ) in n e r r a d iu s
S (s p a c in g )(u m ) s p a c in g o f s p ir a l tr a c e s
G D IS (g d is )(u m ) d is ta n c e fr o m s p ir a l o u te r e d g e to [g u a r d -r in g o u te r e d g e + 2 .5 u m )]
C T a p W (c ta p w )(u m ) r a tio o f c e n te r -ta p w id th o v e r s p ir a l tr a c k w id th
C T a p L a y (c ta p la y )(u m ) c e n te r -ta p s ta c k la y e r n u m b e r (s )
1 P x M (la y ) to p m e ta l la y e r
4.5.46.2 TLDMY Layer Identified TSMC PDK T-line

Introduction
TSMC offered a variety of ways to construct transmission line (T-line) devices for RF/MS circuit design need:
1. To achieve lower T-line series resistance, a thickness larger than 3 µm ultra thick Cu metal (Mu) process is
offered. Since a T-line structure will be regarded as another type of inductors and its associated process
design rule is listed in the section 4.5.45.
2. We used the T-line offered in TSMC PDK as examples to briefly illustrate the basic guidelines and elements
for constructing various T-lines such as coplanar waveguide (CPW), and microstrip lines (MS).
4.5.46.2.1 Introduction to PDK T-line

1. TSMC PDK offered two T-line configurations, including coplanar waveguide (CPW), and microstrip lines
(MS), as shown in Figure 4.5.46.2.
2. The offered T-lines are fabricated on top metal, and are 3-terminal devices including two signal terminals
and the third grounded terminal.
3. The INDDMY dummy layer(s) (CAD layer: 144) is needed to identify the T-line with very low metal density
within the T-line, as illustrated in Figure 4.5.46.3. The DRC (design rule check) deck will check the INDDMY
identified region by inductor related/specific rules (the section of INDDMY Layer Identified Inductor Layout
Rules). The INDDMY layer cannot be used for other applications (for inductor and transmission line only),
and the allowed maximum density of INDDMY in whole chip is 5% (rule IND.DN.1).
4. The TLDMY dummy layer(s) (CAD layer: 116) is needed to identify the T-line as illustrated in Figure 4.5.46.3.
The DRC (design rule check) deck will check the TLDMY identified region by T-line rules. The TLDMY layer
cannot be used for other applications (for transmission line only).
5. The INDDMY dummy layer blocks the TSMC automated generation of dummy Metal patterns (TSMC utility
does not support dummy Al-RDL patterns). TSMC utility will insert dummy OD/PO patterns into INDDMY
regions, if neither ODBLK dummy layer nor POBLK dummy layer is drawn to overlap INDDMY and the
related switch is turned ON (default).
6. However, dummy OD/PO/Metal patterns should be taken care, since the dummy OD/PO/Metal patterns
make better pattern uniformity and better metal CMP uniformity over the silicon wafer.
7. From the T-line model accuracy point of view, other devices or metal patterns are not allowed to be placed
below/above the offered T-lines, as the magnetic flux and the resulted T-line performance will be affected by
the extra-added parts. If other devices, patterns or metal routing (not generated by PDK itself) are added
into the region below/above the PDK T-line, the resulted extra parasitic and model inaccuracy must be taken
into consideration by designers.
8. CPW and MS T-lines cannot share the same ground line and T-lines cannot overlap with each other. If the
customers violate the above recommendations, the designers must take the model inaccuracy into
consideration.
9. Table 4.5.46.3 shows the TSMC PDK T-line layout parameters.
CPW MS
Figure 4.5.46.2 PDK T-line schematic illustrations
IN D D M Y
CPW
TLDM Y
IN D D M Y
MS
TLDM Y
Figure 4.5.46.3 PDK T-line top-view illustrations
Table 4.5.46.3 TSMC offered transmission line structure geometry parameters
W id t h ( u m ) S ig n a l lin e w id t h
S p a c e ( u m ) S p a c in g b e t w e e n a s ig n a l lin e a n d g r o u n d lin e s
4.5.47 SRAM Rules

This section contains the SRAM truth tables for N40G/N45LP/N45LPG/N40LP/N40LP+/N40LPG.
The following provides a legend for the following SRAM truth table.
0 Restrict to use the layer inside its array.
1 Must contain the layer inside its array.
* Depends on LP/LP+/LPG and GS process
a. (186;4) is for LP/LP+/LPG and (186;5) is for GS.
b. For (50;1/2) usage in 0.374/0.741um^2 cells, GS process must contain (50;1/2) and LP/LPG
process is based on which cell you choose (with cell implant or without cell implant).
SRAM special layer truth table

Table 4.5.47.1 lists SRAM cells used in CLN45 official offering. Each individual cell should contain and restrict
those listed layers inside its array. Using HD 0.299um^2 array for example (Recognition layer: 80;14), it must
contain SRM;0 and restrice to SRM_RP inside 80;14. TSMC offering cells must meet to the layer usage in
truth table. Any violation is not allowed.
Please refer section 3.4 “Special Recognition CAD Layer Summary” for detailed special layer information.
Table 4.5.47.1 SRAM Truth Table in TSMC offering cells

TSMC HD HC DP HCDP
Special Layer Tape out
Default DRC 0.299um^2 0.374um^2 0.589um^2 0.741um^2
Name required layer
CAD Layer 80;14 80;13 80;0 80;16
SRM;0 50;0 V V 1 1 1 1
SRM;1 50;1 V V 1 1/0* 1 1/0*
SRM;2 50;2 V V 1 1/0* 1 1/0*
SRM_RP 50;5 V V 0 0 0 0
ROM 50;6 V 0 0 0 0
SRAM_HS 50;7 V V 0 0 0 0
NPreDOSRM 50;21 V V 1 1 1 1
SRAMDMY;0 186;0 V V 1 1 1 1
SRAMDMY;1 186;1 V V 1 1 1 1
SRAMDMY;4 * 186;4 V V 0 0 0 0
SRAMDMY;5 * 186;5 V V 0 0 0 0
CO;11 30;11 V V 1 1 1 1
DPSRM 80;0 V V 0 0 1 0
PRSRM 80;11 V V 1 1 1 1
SRM_UHD 80;12 V V 0 0 0 0
SRM_HC 80;13 V V 0 1 0 0
SRM_HD 80;14 V V 1 0 0 0
SRM_LV 80;15 V V 0 0 0 0
SRM_HCDP 80;16 V V 0 0 0 1
SRM_8TTP 80;17 V V 0 0 0 0
SRM_10TTP 80;18 V V 0 0 0 0
82;1 V V 1 1 1 1
82;2 V V 1 1 1 1
82;3 V V 1 1 1 0
82;4 V V 1 1 1 0
82;5 V V 1 1 1 0
82;6 V V 1 1 1 0
82;7 V V 1 1 1 0
DUMMYOD1
82;8 V V 1 1 1 0
~
82;9 V V 1 1 1 1
DUMMYOD16
82;10 V V 1 1 1 1
82;11 V V 1 1 1 1
82;12 V V 1 1 1 1
82;13 V V 1 0 1 1
82;14 V V 1 0 1 1
82;15 V V 0 0 0 0
82;16 V V 1 1 1 1
TSMC HD HC DP HCDP
Special Layer Tape out
Default DRC 0.299um^2 0.374um^2 0.589um^2 0.741um^2
Name required layer
CAD Layer 80;14 80;13 80;0 80;16
83;1 V V 1 1 1 1
83;2 V V 1 1 1 1
DUMMYPO1 83;3 V V 1 1 1 1
~ 83;4 V V 1 1 1 1
DUMMYPO7 83;5 V V 1 1 1 1
83;6 V V 0 0 0 0
83;7 V V 1 1 1 1
CO2 100;0 V V 1 1 1 1
IP 63;63 1 1 1 1
RODMY 49;0 V 1 1 1 1
Mask information
 N45LP/LPG-LP: NCI SRAM PMOS follows core-PMOS LVT setting. If no core-PMOS LVT in the mask
tape out, there will need additional PLDD mask for SVT-PMOS delta-dose (11C).
 N40G (0.9V) and N40GL (0.8V):
● 11C is a must if N40G 0.9V and N40GL 0.8V SRAM cells are both used.
● The mix run of the same SRAM cells is forbidden (For example, N40G HC and N40GL HC), i.e. the
same SRAM cell of N40G and N40GL cannot co-exist in one chip. Please refer to the following table in
details.
N40G (0.9V)
N40G and N40GL SRAM Cell
D299 (HD) D374 (HC) D589 (DP) D741 (HCDP)
D374 (HC) O X O O
N40GL (0.8V)
D741 (HCDP) O O O X
Note: O: Can co-exist in one chip.
X: Can NOT co-exist in one chip.
Warning: There are two ways for SRAM design.

1. Use TSMC standard SRAM array. None of FEOL and BEOL layouts for TSMC
SRAM is allowed to be changed (SRAM.R.1U).
2. Complying with the logic rules and using logic SPICE model to design SRAM
are only allowed when you want to design SRAM cell by yourself (SRAM.R.2U).
Warning: You can’t design SRAM layout just by complying with the following the rules. The
SRAM rules in this document are used to prevent unexpected layout errors during
macro or chip implementation, but not used for SRAM design.

SRM width. The SRM edge should be aligned to the boundary of the cell array, which may include storage,
SRAM.W.1 A  0.19
strapping, and dummy edge cells.
SRAM.S.1 SRM space B  0.19
SRAM.S.2 SRM space to {GATE NOT INTERACT SRM} C  0.14
SRAM.BTC.S.1 BTC space [different nets] S1  0.090
SRAM.BTC.S.2 BTC space to M1 [different nets] S2  0.055
SRAM.BTC.S.3 BTC space to CO [different nets] S3  0.067
SRAM.EN.1 SRM enclosure of GATE in S/D direction. E  0.14
SRAM.EN.2 SRM enclosure of GATE in PO endcap direction. E1  0.09
SRAM.EX.1 SRM extension on NW (INTERACT with OD). Extension = 0 is allowed. D  0.19
SRAM.A.1 SRM;0 (50;0) Area  11
SRAM.O.1 SRM overlap of NW (INTERACT with OD) (for VTC_N, VTC_P). Extension = 0 is allowed. F  0.19
TSMC SRAM array is forbidden to be changed: It is required to use the standard TSMC SRAM array
SRAM.R.1U including edge cells, strap cells, and etc. None of FEOL and BEOL layouts for TSMC SRAM is allowed to
be changed.
Customer-designed SRAM cell designed by logic rules: Complying with logic rules (186;0 and 50;0
can’t be used) and using logic SPICE model to design SRAM are only allowed when you want to design
SRAM.R.2U SRAM cell by yourself.. For the SRAM layout designed by logic rules, it must be review by TSMC’s PE.
[Customer's product: need silicon to verify its function, performance, speed and Vccmin before product
tape-out.]
Array delay-tracking bit cells: This kind of bit cell should be embedded inside an array. If a delay-tracking
SRAM.R.5U
cell is to be placed outside an array, it should be fully surrounded by dummy bit cells.
Dummy layouts for embedded SRAM: To minimize proximity and loading effects during processing, you
must add dummy layouts to provide a similar surrounding for every cell.
SRAM.R.6U To add dummy layouts, please refer to SRAM cell layout documents listed in section 1.2, Reference
Document, for the guidelines and GDS examples. Those documents provide instructions for adding
dummy layouts in both columns and rows, at array edges, and at the connection/tap in-between arrays.
SRAMDMY;5 (186;5)/ SRAMDMY;4 (186;4): Can only use in the word-line driver of TSMC SRAM. This
SRAM.R.7U
layer is only to waive CO.S.3 and G.1.
SRAM.R.12 SRAMDMY;5 (186;5)/ SRAMDMY;4 (186;4) overlap of SRAMDMY;0 (186;0) is not allowed.
SRAM.R.13 SRM must fully cover GATE.
SRAMDMY;0 (186;0) is a must for any SRAM cell with rule pushed layout.
SRAM.R.14 It waives SRAM DRC violations in {(SRAMDMY;0 (186;0) NOT RAM1TDMY (160;0))} as listed in table
4.5.47.2.
CO;11 (30;11) is a must for CO mask tape-out in SRAM. (Except RAM1TDMY (160;0) region)
1. If CO;11 exists, it must cover CO;0
2. CO;11 must be 0.06μm x 0.06μm
SRAM.R.15
3. CO;11 must be exactly the same as CO;0.
4. CO;11 must be fully covered by SRM (50;0) and SRAMDMY;0 (186;0)
5. Square CO;0 in SRAM must cover CO;11 in 50;0 region
SRAM IP tag name and hierarchy should follow TSMC layout such as strap cell, strap_edge cell, column
SRAM.R.16U edge cell and row edge cell. The detail is described in SRAM cell layout and model documents listed in
section 1.2, Reference Document.
SRAM.R.17 SRAMDMY;0 (186;0) and SRM (50;0) must fully cover OD, CO, VIA1.
SRAM dummy layers can exist only in SRM (50;0) region. And in logic region, no SRAM dummy layer can
be used. SRAM dummy layers are listed below :
SRAM.R.19
DMMYOD1~16, DUMMYPO1~7, SRM;1~2, NPreDOSRM, SRAMDMY;0~1, CO;11, CO2, DPSRM,
PRSRM, SRM_LOP;12~14, LV_LOP, HCDP_LOP, 8TTP_LOP and 10TTP_LOP.
SRAM.R.20 Inside of SRAM array, SRM (50;0), SRAMDMY;0 (186;0) can not have any holes in them.
SRAM.R.21 SRM (50;0) and SRAMDMY;0 (186;0) must be drawn identically (Except RAM1TDMY (160;0) region)
SRAM.R.22 (80;x) must overlap PRSRM (80;11). x = 0, 12~18.
SRAM.R.23 if PRSRM (80;11) interacts (80;x). It must be fully covered by (80;x). x = 0, 12~18.
(80;x) interact SRM (50;0) must be identical to SRM;0 (50;0), except SRM_LV (80;15) and SRM_8TTP
SRAM.R.24
(80;17), x = 0, 12~18.
(80;x) can’t interact each other, x = 0, 12~18. Only SRM_LV (80;15) interacting with SRM_8TTP (80;17) is
SRAM.R.25
allowed.
SRM;0 (50;0) must cover NMOS gate and PMOS gate at the same time.
DRC will check the following two conditions at the same time.
SRAM.R.26
(1) {SRM NOT INTERACT (NP AND GATE)}
(2) {SRM NOT INTERACT (PP AND GATE)}
SRAM.R.27 For GS, SRM;0(50;0) must include both SRM;1(50;1) and SRM;2(50;2).
SRAM.R.28 For LP/LPG, {SRM;0(50;0) AND SRM_HD(80;14)} must include both SRM;1(50;1) and SRM;2(50;2).
SRAM.R.29 For LPG, {SRM;0(50;0) AND DPSRM(80;0)} must include both SRM;1(50;1) and SRM;2(50;2).
SRAM.R.30U The same SRAM cell for N40G and N40GL SRAM can not coexist in one chip.
At least two VIAx with space ≤ 0.14 μm (S1), or at least four VIAx with space ≤ 0.63 μm (S1') are required
SRAM.R.31 to connect Mx and Mx+1 when one of these two metals has width and length > 0.3 μm (W1). [INSIDE
SRAMDMY;0 (186;0)]
At least two VIAx must be used for a connection that distance ≤ 1.14 μm (D) away from a metal plate
SRAM.R.32
(either Mx or Mx+1) with length > 0.3 μm (L) and width > 0.3 μm (W). [INSIDE SRAMDMY;0 (186;0)]
(80;X) must fully cover CO;11 (30;11), (50;0), (50;21),(82;Y); (83;Z), (186;0), (186;1), and (100;0).
X = 0,14,16.
SRAM.R.33
Y = 1,2,9,10,11,12,16.
Z = 1,2,3,4,5,7.
SRAM.R.34 (80;X) must not have SRM_RP (50;5), (50;7), (82;15), (83;6), (186;4), (186;5) x = 0, 13, 14, 16.
SRAM.R.35 (80;X) must fully cover (82;Y). X = 0, 13, 14. Y = 3,4,5,6,7,8
SRAM.R.36 (80;16) must not have (82;Y). Y = 3,4,5,6,7,8
SRAM.R.37 No ROM (50;6) can be used in SRAM region (SRM(50;0)).
(80;X) must fully cover DUMMYOD13 (82;13) and DUMMYOD14 (82;14)
SRAM.R.38
X = 0;14;16
SRAM.R.39 (80;13) must not have DUMMYOD13 (82;13) and DUMMYOD14 (82;14)
(80;13) must fully cover CO;11 (30;11), (50;0), (50;21),(82;Y); (83;Z), (186;0), (186;1), and (100;0).
SRAM.R.40 Y = 1,2,9,10,11,12,16
Z = 3,4,5,7.
SRAM.R.41 NMOS gate in SRM (50;0) must be fully covered by NPreDOSRM (50;21) (Except RODMY (49;0) region)
BTC in NW in one unit cell must be a pair, except DPSRM (80;0), SRM_HCDP (80;16), and SRM_10TTP
(80;18) cells.
SRAM.R.42
DRC only checks: {{{{BTC AND NW} NOT {{DPSRM OR SRM_HCDP} OR SRM_10TTP}} SIZING 0.05
μm} INTERACT BTC} = 2
Poly gates of all SRAM cells (50;0 OR 186;0) must be uni-directional in a chip.
PO.R.7 (This check doesn’t include the regions covered by layer 49 (RODMY) and RAM1TDMY (160;0))
Chips on MPW or shuttles may be rotated due to this rule
Sense-amp and decoder redundancy: In addition to bit-row and/or bit-column redundancy design,
redundancy in peripheral array elements, such as sense amplifiers and decoders, is recommended.
SRAM.R.9gU
Architectural efficiency can minimize the added overhead area entailed by this additional redundancy.
Peripheral element redundancy is especially important for high-density memory blocks.
SRAM.R.11gU Guardring: It is recommended to have an additional VSS (PW) guardring around the memory circuit block.
Warning: It is important to add different redundancies according to different memory densities, if the total
SRAM area for only N40GL (Vnom = 0.8V usage) in one chip is > 3,231,000um2 (e.g. 8Mb of N40GL
0.374um2 cell), or if the total SRAM area for all cells (including N40GL 0.8V usage) in one chip is >
SRAM.WARN.1 5,168,000um2 (e.g. 16Mb of 0.299um2 cell).
Please refer to T-000-CL-RP-002, TSMC EMBEDDED SRAM REDUNDANCY IMPLEMENTATION RULE
AND ECC GUIDELINE, for the details.
DRC only flags the total SRM (50;0) area in one chip > 5,168,000um2.
Warning: It is important to add ECC (Error Correcting-Code), if the total SRAM area for all cells in one chip
is > 10,336,000μm2 (e.g. 32Mb of 0.299um2 cell).
Please refer to T-000-CL-RP-002, TSMC EMBEDDED SRAM REDUNDANCY IMPLEMENTATION RULE
SRAM.WARN.2
AND ECC GUIDELINE, for the details.
DRC only flags the total SRM (50;0) area in one chip > 10,336,000μm2.
For ECC implementation, please consult TSMC QR based on product operation spec.
 Table 4.5.47.2 Rule List Waived by SRAMDMY;0 (186;0)

Layout Rule Rule List Waived by SRAMDMY;0 (186;0)
Grid Rule G.4 for PP and NP layer only
OD.W.1, OD.W.2, OD.S.1, OD.S.3, OD.S.3.1, OD.A.1, and OD.A.2.
OD Layout Rule
OD.S.1® , and OD.W.1®
NW Layout Rule NW.W.1, NW.S.6, NW.S.6.1, NW.EN.1, and NW.EN.2.
DCO Layout Rule DCO.S.8, DCO.O.1
OD2 Layout Rule OD2.W.2
PO.W.6, PO.S.1, PO.S.4, PO.S.6, PO.EX.1, PO.EX.2, PO.EX.3, PO.S.2, and PO.S.2.1.
PO.S.1® , PO.S.2.LP® , PO.S.5.LP® , PO.S.5.GS® , PO.S.6.LP® , PO.S.6.GS® ,
PO Layout Rule
PO.EX.1® , and PO.EX.2® Only waive PO.S.2.1.1, PO.EX.2.1 and PO.R.4 in RODMY
(49;0) region.
PP Layout Rule PP.S.1, PP.S.2, PP.EN.1, PP.EX.1, PP.EX.2, PP.A.1, and PP.R.1.
NP Layout Rule NP.W.1, NP.S.2, NP.S.4, NP.EX.1, NP.A.2, and NP.R.1.
CO.S.1, CO.S.2, CO.S.2.1, CO.S.3, CO.S.4, CO.EN.1, and CO.EN.0 for square CO
CO Layout Rule CO.W.1, CO.EN.1.1, CO.EN.1.3, and M1.EN.1 for butted CO only
CO.S.3® , CO.EN.1® , CO.EN.1.1® , CO.EN.3® , and CO.R.5g
M1.S.5, M1.EN.2, M1.EN.3, M1.EN.3.1, M1.EN.3.2, M1.A.1, and M1.A.2.
M1 Layout Rule
M1.S.1® , M1.A.1® , M1.EN.1® , M1.EN.2® , and M1.EN.5®
VIA1.R.2 and VIA1.R.4
Via1 Layout Rule
VIA1.EN.1® ,and VIA1.EN.2®
M2.S.5, M2.A.1, and M2.A.2.
M2 Layout Rule
M2.S.1® , M2.A.1® , M2.EN.1® , and M2.EN.2®
Via2 Layout Rule VIA2.EN.1® , and VIA2.EN.2®
M3 Layout Rule M3.S.1® , M3.A.1® , M3.EN.1® ,and M3.EN.2®
A
SR M
SR M
SR M B N W
D
N W
A F
N W
<D
C D D
O D
SR M
E1
E
S R A M .R .1 7
SR M
SR M
N P
E1
G
<A
O D
Dummy layouts Dummy layouts
Dummy layouts
Dummy layouts
Dummy layouts
Dummy layouts
SRAM cell array SRAM cell array
Dummy layouts
Dummy layouts
Dummy layouts
Dummy layouts
SRAM cell array SRAM cell array
S R A M .R .2 2
S R A M .R .2 4 S R A M .R .2 5
S R A M .R .2 3
M u s t b e d r a w n id e n tic a lly
(8 0 ; x )
8 0 ;x
5 0 ;0 80;x 8 0 ;1 7
(8 0 ;1 1 )
80;x' 8 0 ;1 5
5 0 ;0 5 0 ;0
X=0; 12~18 X=0, 12~18

e x c e p t (8 0 ;1 5 ) a n d (8 0 ;1 7 ) X’ =0, 12~18
X is n o t e q u a l to X ’
4.5.48 NPreDOSRM (50;21) Layout Rules

NPreDOSRAM is a drawn layer in SRAM region to generate N+ predoping mask (mask ID 196). The
NPreDOSRM (50;21) layout rules are nearly identical to NP layout rules. It exists only in SRM (50;0) region
and is forbidden in logic region. Neither changing NPreDOSRM of TSMC SRAM nor designing NPreDOSRM
by logic rules is allowed.
Warning: None of FEOL and BEOL layouts for TSMC SRAM is allowed to be changed. You
can’t design SRAM layout just by complying with the following the rules. The SRAM
rules in this document are used to prevent unexpected layout errors during macro
or chip implementation, but not used for SRAM design.
NPre.W.1 Width A  0.2
NPre.S.1 Space B  0.18
NPre.S.2 Space to P+ ACTIVE (non-butted) C  0.08
NPre.S.3 Space to {P+ ACTIVE OR PW STRAP} (butted) D  0
NPre.S.4 Space to PW STRAP (non-butted) E  0.02
NPre.S.5 {NPre edge on OD} space to PMOS GATE F  0.23
NPre.S.7 Space to P-type unsilicided OD/PO resistor H  0.14
{NPre edge on OD} extension on NMOS GATE in SRM (50;0) (Except
NPre.EX.4 M  0.03
RODMY (49;0) region)
NPre.O.1 Overlap of OD N  0.01
NPre.A.1 Area O  0.11
NPre.A.2 Enclosed area P  0.11
NPre.R.2 Overlap of PP is not allowed.
NPre.L.1 45-degree edge length  0.5
N P re D O S R M
PO
R P P
O
J
N P re D O S R M
N N P re D O S R M N P re D O S R M
+
A P
+
P
OD
OD
+
P
OD
E I I I
D I I
M
+
N + PO PO PO
N
OD
OD
NW
PW
N ty p e
P lo y
r e s is to r
+
P
OD
J1
PO N P re D O S R M
L H
C
D F
+
+ P
N
OD
OD
P ty p e P lo y
r e s is to r
4.5.49 SRAM Periphery (Word Line Driver) Rules

The following rules only apply to word line driver covered by SRAMDMY (186;5) or (186,4).
WLD.R.2 {CO AND SRAMDMY (186;4/5)} space to PO. B  0.035
CO space on the same OD [(inside SRAMDMY;4 (186;4) or
WLD.R.3  0.10
SRAMDMY;5 (186;5)) and CO space to gate = 0.035um]
WLD.R.6 SRAMDMY (186;4/5) edge cut CO is not allowed.
SRAMDMY;0 (186;0) SIZING 100 μm must cover SRAMDMY;5 (186;5)
WLD.R.7
or SRAMDMY;4 (186;4)
Gate direction on the WL driver must be same as gate on the SRAM
WLD.R.8
(Unique direction)
At least 2 COs are required at both source and drain side on WL driver
WLD.R.9
(186;4/5) region
C O a rra y m x n
W o r d L in e D e c o d e r
S R A M D M Y (1 8 6 ;5 ) o r (1 8 6 ,4 )
OD
C O a rra y 1 x n
C O a rra y 1 x n
B CO
PO
C O a rra y 1 x n
W L D .R .6
4.5.50 SRAM CO2 (100;0) Layout Rule for Embedded

DRAM (eDRAM) Process
 In the TSMC eDRAM process, capacitor and CO2 modules are inserted between contact and M1 layers
of the TSMC logic process.
 For eDRAM related IP/Macro design or products with eDRAM IP/Macro, please notice contact-contact
capacitance and contact resistance are higher than those in pure logic process. You need to use the
eDRAM SPICE model and RC extraction deck to specially handle the extra CT-CT coupling capacitance
and resistance from eDRAM process for both eDRAM and non-eDRAM portions.
 You have to add CO2 (100;0) layout in SRAM bit cell if your product has SRAM designed by logic rules
and eDRAM at the same time. TSMC SRAM bit cell already has this option.
CO2.W.1 CO2 (100;0) width (maximum=minimum) A = 0.06
CO2.R.1 CO2 (100;0) layout must exist in the SRAM bit cell for the eDRAM process.
BTC must overlap CO2, and CO2 must overlap BTC.
CO2 (100;0) must be inside {M1 AND SRM} and BTC ((30;0 NOT 30;11) AND
50;0). The following conditions can be waived.
CO2.R.2 a. Butted contact (BTC) without interacting with M1.
b. The area of {CO2 NOT M1} is smaller than or equal to 0.015 x 0.005 um2 in
SRM_LV (80;15). In the other SRAMs, CO2 must be fully inside M1 (the
area of {CO2 NOT M1} should be equal to 0um2).
Customer-designed SRAM bit cell designed by logic rules: It is required
CO2.R.3U to be reviewed by TSMC’s PE before using a customer-designed SRAM bit
cell designed by logic rules for the eDRAM process.
B T C (3 0 ;0 N O T 3 0 ;1 1 )
M 1 (3 1 ;0 )
C O 2 (1 0 0 ;0 )
C O (3 0 ;0 A N D 3 0 ;1 1 )
A
S R M (5 0 ;0 )
4.5.51 ROM Rules

ROM (CAD layer: 50;6) is used for ROM circuit design and is a tape-out required layer for N40G. ROM can
only be designed by SVT NMOS, and not allowed for other VTs.
ROM.W.1 Channel width A = 0.12~0.35
ROM.W.2 Channel length B = 0.045, 0.05
ROM.R.1U All ROM cells must be covered by 50;6.
ROM.R.2® U Recommend to insert dummy PO between two ROM bits on different OD.
Each ROM cell must be covered by ROM(50;6).
ROM.R.3® DRC only flags no ROM(50;6) in the chip. But if there is no ROM cell in the
chip, the violation can be waived.
Only SVT NMOS is allowed in the ROM region for SPICE model support.
ROM.R.4 DRC flags that ROM overlaps {NW AND OD}/{HVD_N AND OD}/{VTH_N
AND OD}/{VTL_N AND OD}.
R O M C e ll
PO B
OD
In T S M C R O M c e ll, th is d u m m y p o ly is
D u m m y P o ly d r a w n b y a p o ly la y e r (1 7 ;0 ) w h ic h fo llo w s
p o ly r e la te d r u le s .
PO
OD
5 0 ;6
4.5.52 Antenna Effect Prevention (A) Layout Rules

 A protection OD means diode, STRAP, source, drain, and so on.
Antenna prevention without protection ODrules: A.R.1, A.R.2, A.R.3, A.R.4, A.R.6, A.R.6.1,
A.R.6.2, A.R.9, A.R.10, AR.11
A.R.0
Antenna prevention with protection ODrules: A.R.7, A.R.8, A.R.8.1, A.R.8.3, A.R.8.3.1,
A.R.8.3.2, A.R.8.7, A.R.12, A.R.13
A.R.1 Drawn ratio of the poly top area to the active poly gate area that is connected directly to it  250
A.R.2 Drawn ratio of the poly sidewall area to the active poly gate area that is connected directly to it  500
A.R.3 Drawn ratio of the poly contact area to the active poly gate area that is connected directly to it  10
A.R.4 Single-layer drawn ratio of a via area to the active poly gate area that is connected directly to it  20
Ratio of cumulative metal top area (from M1 to M10) to an active poly gate area [1.8V IO in OD2/
A.R.6  1000/5000/5000
except 1.8V IO in OD2/ NOT in OD2]
Ratio of the cumulative metal top area (from M1 to top metal ) to the cumulatively connected 
A.R.6.1 6E5 x (GATE area)(-0.767)
GATE area [I/O in OD2, 4000 μm2 < Gate area ≤ 1000K μm2]
Maximum cumulative IO gate [in OD2] area in same connection 
A.R.6.2 1000000
This rule is checked by the cumulative connections (from M1 to top metal respectively)
Ratio of cumulative via area (from VIA1 to VIA9) to an active poly gate area [in OD2/ NOT in
A.R.9  50/NA
OD2]
Drawn ratio of RV area to the active poly gate area that is connected directly to it [in OD2/ NOT in
A.R.10  20/200
OD2]
Drawn ratio of AP sidewall area to the active poly gate area that is connected directly to it [in
A.R.11  1000/2000
OD2/ NOT in OD2]
Drawn ratio of cumulative via area (from VIA1 to VIA9) to the active poly gate area with a
A.R.7  OD area x 210 + 900
protection OD.
Drawn ratio of cumulative metal top area (from M1 to Last Metal-1) to the active poly gate area
A.R.8  OD area x 456 + 43000
with a protection OD.
Mn_pad_floating space to Mn [connects to OD ,from M1 to AP] ≤ 0.100 µm is not allowed
Definition of Mn_pad_floating: the metal (from M1 to AP) follows the following conditions:
A.R.8.7 (1) does not connect to OD, and
(2) connect to AP_PAD [width of AP interact {CB2_WB OR CB2_FC} > 35 um]
This rule is checked from M1 to AP respectively

A.R.8.1 Drawn ratio of last metal top area to the active poly gate with a protection OD.  OD area x 8000 + 50000
Risk_Floating_net space to Mn (from M1 to Mtop) [connects to OD] < 0.17 μm, ≥ 0.07 μm is not
allowed
Definition:
1. Risk_Floating_net: cumulative floating metal and VIA top area [cumulative area > 7.50E+05
A.R.8.3
μm2, from M1 to top metal and VIA1 to top VIA, and does not connect to OD]
2. floating metal and VIA: metal and VIA does not connect to OD
This rule is checked by the cumulative connections (from M1 to top metal and VIA1 to top VIA
respectively)
allowed
Definition:
A.R.8.3.1
respectively)
allowed
Definition:
A.R.8.3.2
respectively)
A.R.12 Drawn ratio of RV area to the active poly gate area with a protection OD.  OD area x 83 + 400
A.R.13 Drawn ratio of AP sidewall area to the active poly gate area with a protection OD.  OD area x 8000 + 30000
Table Notes:
1. It is recommended having OD connection to the poly gate through metal lines for all devices.
2. All N+ OD and P+ OD areas connected to metal or via do contribute to the OD area. (Including source or drain
diffusion of MOSFET and Strap areas)
3. If a large OD is needed, it is recommended having one big diffusion area with multiple contacts. Avoid covering
the entire OD area with metal.
4. The Antenna rules apply separately to both thin (core) and thick (I/O) gate oxides.
5. RDL designs should take antenna rules into account.
6. Gate poly thickness is 800 angstrom (Å ) for both core and I/O gates.
7. All of the ODs in the same net can be treated as effective protection OD(s) against plasma charging.
8. In order to avoid the antenna ratio mismatch between the paired devices, metal lines need to be as symmetry as
possible.
9. The transistors in mismatch sensitive configurations shall be tied to an active region by M1 to prevent process-
induced damage.
10. When an error is detected at DRC, antenna ratio can be reduced by the following suggestion; connect the node to
a protection OD, connect the gate to the highest metal level as close to the gate as possible, or connect the node
to the output of the driver with a lower metal level.
11. DRC implementation for calculations of metal to gate area ratio in cumulative antenna rules,
 “Cumulated Ratio” of A.R.4 and A.R.6 rules is defined as:
Area(Mx(n))/Area(GATE(n)) + Area(Mx-1(n-1))/Area(GATE(n-1)) + ... + Area(M1(1))/Area(GATE(1))
 Where GATE(n) is the total GATE area in a particular net constructed by the incremental connections up
to current nth stage.
 Mx(n) is the whole area of metal x (x = 1~ top) in the same net.
 Definition of the protection OD for antenna rules:
Total area of (OD NOT POLY) INTERACT CONTACT on the same net
12. Failure Criterion
 Tailing percentage of 20% changes in gate current in Log-normal distribution (which is expressed with the
following equation) is less than 5%.
Ig(n)  Ig(n  1)
 Ig (%)   100%
Ig(n  1)
4.5.52.1 Poly Antenna Ratio

The definition of the poly top area antenna ratio for each layer is:
ratio = (Lp x Ld + Lpe x Wpe) / (Wd x Ld)
The definition of the poly sidewall area antenna ratio for each layer is:
ratio = 2 x [(Lpe +Wpe + Lp ) x t ] / (Wd x Ld)
Lp: length of field poly connected to gate
Wp: width of field poly connected to gate
Lpe: length of field poly extension connected to gate
Wpe: width of field poly extension connected to gate
t: poly thickness
Wd: transistor channel width
Ld: transistor channel length
4.5.52.2 M1-M10 Antenna Ratio

The definition of the M1-M10 antenna ratio for each layer is:
ratio = (Wm x Lm ) / (Wd x Ld)
Lm: length of metal line connected to gate
Wm: width of metal line connected to gate
4.5.52.3 CO Via1 – Via9 Antenna Ratio

The definition of CO, VIA1-VIA9 antenna ratio is:
ratio = {total contact (via) area}/ Wd x Ld
Lm
M e t a l_ 1
W m
Lpe
W pe
t
Lp
W d
P o ly
STI STI
Ld
4.5.53 Product Labels and Logo Rules

1. Use any of the following product labels:
 Copyright and year
 Company logo
 Part number
 Mask level names
 Other similar labels
2. Make sure there is a dummy layer LOGO (CAD layer no. 158) to do DRC for product labels.
Product labels must be fully covered by LOGO dummy layer.
3. Form the product labels for the CO/Via layer by using squares with minimum width.
A big CO/Via polygon for a character (or a numeral) is not allowed.
4. Don’t use minimum rules for the product labels, except for CO/Vias.
It is best to have greater than, or equal to, 1μm of width and space. If the minimum width and space is
greater than 1μm in the rule (for example, 30K thick metal) please use at least the minimum width and
space.
5. To protect the product labels, do not use a dummy Metal in the LOGO demarcated regions.
For process uniformity, keep the LOGO layer and the corresponding product labels at least 10μm distant
from the OD/PO/Metal geometry. Add dummy fill in this 10μm border region. (The TSMC dummy pattern
utility will insert dummy pattern geometry in the 10μm LOGO border region to minimize the process impact
on the circuit OD/PO/Metal geometry that is near the LOGO.)
Space to OD, PO, or Metals (non-dummy patterns, and non-dummy TCD)
LOGO.S.1 (This check doesn’t include the M1/ Mx protection ring inside {LOWMEDN NOT A  10
(LOWMEDN SIZING -4 um)} region, seal-ring region, and CSR region)
LOGO.O.1 Overlap of CB, CBD, PM, UBM is not allowed.
LOGO.R.1U A circuit in the LOGO is not allowed.
The rules of OD.DN.4® , OD.DN.5® , OD.DN.6® , OD.DN.7® , PO.DN.4® ,
PO.DN.5® , PO.DN.6® , PO.DN.7® , PO.EX.1, PO.EX.1® , PO.EX.2, PO.EX.2® ,
LOGO.R.2
PO.EX.3, PO.R.1, PO.R.4, PO.W.6, OD.W.2.1, OD.W.2.2, and OD.R.1 can be
exempted from DRC in LOGO area.
LO G O
O D /P O L Y /M e ta l A
4.5.54 Seal Ring Overview

 The general N45 seal ring structure consists of three major parts: (i) assembly isolation; (ii) corner stress
relief (CSR) pattern; and (iii) seal ring wall. In addition, the seal ring is surrounded by 8-μm-wide scribe
line dummy bar (SLDB). Fig. 4.5.54.1 shows the details.
 The seal ring structure can protect the chip from the die saw damage in order to manage the saw quality.
It can reduce the impact of damage induced by thermal stress during packaging and field applications.
 To add a seal ring, triangle empty areas (74 μm) at four chip corners must be reserved and no layout is
allowed inside. The triangle empty rule, CSR.R.1, must be folowed.
 The DMV described in this section means dummy metal and VIA in seal ring, assembly isolation, and
SLDB region.
Warning: Violation of this rule, CSR.R.1, may result in serious

layout mistakes, thus the corrections of many masks may be
required!
Fig. 4.5.54.1. Three major parts of the seal ring and the scribe line dummy bar: (i) assembly isolation;
(ii) seal ring wall; (iii) corner stress relief (CSR) pattern; (iv) scribe line dummy bar (SLDB).
CSR
C S R .R .1 :
T r ia n g le e m p ty a r e a
6um 10um 8um
A s s e m b ly Seal S c r ib e lin e
is o la tio n r in g dum m y bar
w a ll (S L D B )
4.5.54.1 Guidelines for Placing Seal Ring

There are two ways to mount the seal ring structure into your design:
1. Added by TSMC: Customers can request TSMC to add the seal ring and the SLDB during post tape out
data preparation. CSR.R.1 must be followed if this option is selected.
2. Added by Customer: Customers can choose to add the seal ring and SLDB before tape out. Four sample
GDS files (archived along with this document) are prepared for this purpose. Please select the proper GDS
layers matching with the metal scheme of your design by following the seal ring rules and SLDB rules in the
following.
1P10M sample GDS file for using Mz as top metal: TSMC_N45_SRDRM_BIB_Mz_AP_4um_PBO1_4D3.gds

1P10M sample GDS file for using My as top metal: TSMC_N45_SRDMB_BIB_My_20090923_AP plus 4.0.gds
1P10M sample GDS file for using Mr as top metal: TSMC_N45_SRDRM_BIB_Mr_AP_4um_PBO1_4D3.gds
1P10M sample GDS file for using Mu as top metal: TSMC_N45_SRDRM_BIB_Mu_AP_4um_PBO1_4D3.gds
 Sealring structures can be used in WLCSP/Flip chip/Wire bond packages.
 Mask combination CB (mask ID:107)/ AP (mask ID: 307)/ CB (mask ID:107) is not allowed for WLCSP
process.
Warning: A seal ring different from the TSMC standard one requires a special approval
from TSMC to mitigate risk during die saw and packaging. Please contact TSMC to get
assistance if an approval process is needed.
The following CAD layers are required for seal ring structure and SLDB in addition to
Via and Metal layers. Please keep these layers in the your chip GDS:
Layer Name CAD Layer #/Datatype Flip Chip required Wire Bond required
OD 6;0 V V
PP 25;0 V V
CO 30;0 V V
CBD#a 169;0 V X
CB 76;0 X V
CB2_FC 86;0 V X
CB2_WB 86;20 X V
PM 5;0 V Optional
LMARK 109;0 V V
SEALRING 162;0 V V
SEALRING_DB 162;1 V V
SEALRING_ALL#b 162;2 V V
CSRDMY 166;0 V V
CSRBIB1DMY 166;1 V V
CSRBIB2DMY 166;2 V V
a. CBD is a required layer in the seal ring region for CB-VD mask (passivation-1) generated from (RV or CBD).
b. Layer SEALRING_ALL (162;2) is used to waive logic rule violations in the seal ring, SLDB, CSR, and assembly
isolation regions.
Metallization Options
The general 45 nm logic process is offered up to 1P10M. Please refer to the following tables to assemble the
metallization option that fits your design.
For any metal combination, a marker “(1+X+Y+Z+R)M_XxYyZzRr” can be used to represent the metal
combination of Mx, My, Mz and Mr.
The marker is interpreted as one layer of M1, X layers of Mx, Y layers of My, Z layers of Mz, and R
layers of Mr. The total metal layer number is (1+X+Y+Z+R).
Naming for different metal types
Code Data Type
M1 0
Mx 0
My 20
Mz 40
Mr 80
Naming for different Via types
Code Data Type
Vx 0
Vy 20
Vz 40
Vr 80
Metallization CAD layers
Layer CAD Layer ID
Metal-1 31
Via-1 51
Metal-2 32
Via-2 52
Metal-3 33
Via-3 53
Metal-4 34
Via-4 54
Metal-5 35
Via-5 55
Metal-6 36
Via-6 56
Metal-7 37
Via-7 57
Metal-8 38
Via-8 58
Metal-9 39
Via-9 59
Metal-10 40
For example, in a 10M_5x2y2z scheme, the Via-6, Metal-7, Via-7, and Metal-8 should use layer (56;20),
(37;20), (57;20), and (38;20), respectively, for My and Vy layers. The Via-8, Metal-9, Via-9, and Metal-10
should use layer (58;40), (39;40), (59;40), and (40;40), respectively, for Mz and Vz layers. The Metal-1 through
Metal-6 should follow their respective CAD layer ID with data type 0.
If customers want to add the seal ring and SLDB before tape out (option 2), please use the TSMC sample
GDS file for seal ring and SLDB as a starting file, and follow the descriptions below to select the related metal
and via layers for your design.
4.5.54.1.1 For Metallization Options Using Mz as the Top Metal

1. Start with “N45_TSMC_SRDMB_BIB_Mz.gds” sample gds file. Select the metallization layers from
the table below based on the target metallization scheme. Delete from the sample GDS any metal
and via layers that are not listed in the column.
Metallization Options using Mz as Top Metal
Metal
1P3M 1P4M 1P5M 1P6M 1P7M
scheme
1x1z 2x1z 3x1z 2x2z 4x1z 3x2z 3x1y1z 5x1z 4x1y1z 3x2y1z 4x2z 3x1y2z
M1 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0
VIA1 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0
M2 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0
VIA2 52;40* 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0
M3 33;40* 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0
VIA3 53;40* 53;0 53;40* 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0
M4 34;40* 34;0 34;40* 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0
VIA4 54;40* 54;40* 54;0 54;40* 54;20* 54;0 54;0 54;20* 54;0 54;20*
M5 35;40* 35;40* 35;0 35;40* 35;20* 35;0 35;0 35;20* 35;0 35;20*
VIA5 55;40* 55;40* 55;40* 55;0 55;20* 55;20* 55;40* 55;40*
M6 36;40* 36;40* 36;40* 36;0 36;20* 36;20* 36;40* 36;40*
VIA6 56;40* 56;40* 56;40* 56;40* 56;40*
M7 37;40* 37;40* 37;40* 37;40* 37;40*
VIA7
M8
VIA8
M9
VIA9
M10
Metallization Options using Mz as Top Metal

Metal 1P8M 1P9M 1P10M
scheme
6x1z 5x1y1z 4x2y1z 5x2z 4x1y2z 3x2y2z 7x1z 6x1y1z 5x2y1z 6x2z 5x1y2z 4x2y2z 7x2z 6x1y2z 5x2y2z
M1 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0
VIA1 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0
M2 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0
VIA2 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0
M3 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0
VIA3 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0
M4 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0
VIA4 54;0 54;0 54;0 54;0 54;0 54;20* 54;0 54;0 54;0 54;0 54;0 54;0 54;0 54;0 54;0
M5 35;0 35;0 35;0 35;0 35;0 35;20* 35;0 35;0 35;0 35;0 35;0 35;0 35;0 35;0 35;0
VIA5 55;0 55;0 55;20* 55;0 55;20* 55;20* 55;0 55;0 55;0 55;0 55;0 55;20* 55;0 55;0 55;0
M6 36;0 36;0 36;20* 36;0 36;20* 36;20* 36;0 36;0 36;0 36;0 36;0 36;20* 36;0 36;0 36;0
VIA6 56;0 56;20* 56;20* 56;40* 56;40* 56;40* 56;0 56;0 56;20* 56;0 56;20* 56;20* 56;0 56;0 56;20*
M7 37;0 37;20* 37;20* 37;40* 37;40* 37;40* 37;0 37;0 37;20* 37;0 37;20* 37;20* 37;0 37;0 37;20*
VIA7 57;40* 57;40* 57;40* 57;40* 57;40* 57;40* 57;0 57;20* 57;20* 57;40* 57;40* 57;40* 57;0 57;20* 57;20*
M8 38;40* 38;40* 38;40* 38;40* 38;40* 38;40* 38;0 38;20* 38;20* 38;40* 38;40* 38;40* 38;0 38;20* 38;20*
VIA8 58;40* 58;40* 58;40* 58;40* 58;40* 58;40* 58;40* 58;40* 58;40*
M9 39;40* 39;40* 39;40* 39;40* 39;40* 39;40* 39;40* 39;40* 39;40*
VIA9 59;40* 59;40* 59;40*
M10 40;40* 40;40* 40;40*
2. Re-assign the layers marked with “*” by the appropriate CAD layers to match with the CAD ID for
that layer.
Example: For a design with 6M_3x1y1z.

Step 1: Locate the “3x1y1z” column under “1P6M” in the metallization options table above. Delete unused
metal and via layers: (54;0), (35;0), (55;0), (36;0), (56;0), (37;0), (57;0), (38;0), (56;20), (37;20),
(58;40) and (39;40) .
Step 2: Re-assign CAD ID for the layers denoted with “*”, from (57;20), (38;20), (59;40) and (40;40),
respectively, to (54;20), (35:20), (55:40) and (36:40) to match with your metallization scheme.
4.5.54.1.2 Metallization Options Using My as the Top Metal

1. Start with “N45_TSMC_SRDMB_BIB_My.gds” sample GDS file. Select the metallization layers from
Metallization Options using My as Top Metal

Metal 1P3M 1P4M 1P5M 1P6M 1P7M 1P8M 1P9M 1P10M
scheme
1x1y 2x1y 3x1y 2x2y 4x1y 3x2y 5x1y 4x2y 6x1y 5x2y 6x2y 7x2y
M1 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0
VIA1 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0
M2 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0
VIA2 52;20* 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0
M3 33;20* 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0
VIA3 53;20* 53;0 53;20* 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0
M4 34;20* 34;0 34;20* 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0
VIA4 54;20* 54;20* 54;0 54;20* 54;0 54;0 54;0 54;0 54;0 54;0
M5 35;20* 35;20* 35;0 35;20* 35;0 35;0 35;0 35;0 35;0 35;0
VIA5 55;20* 55;20* 55;0 55;20* 55;0 55;0 55;0 55;0
M6 36;20* 36;20* 36;0 36;20* 36;0 36;0 36;0 36;0
VIA6 56;20* 56;20* 56;0 56;20* 56;0 56;0
M7 37;20* 37;20* 37;0 37;20* 37;0 37;0
VIA7 57;20* 57;20* 57;20* 57;0
M8 38;20* 38;20* 38;20* 38;0
VIA8 58;20* 58;20*
M9 39;20* 39;20*
VIA9 59;20*
M10 40;20*
that layer.
Example: For a design with 6M_3x2y.

Step 1: Locate the “3x2y” column under “1P6M” in the metallization options table above. Delete unused
metal and via layers: (54;0), (35;0), (55;0), (36;0), (56;0), (37;0), (57;0) and (38;0).
Step 2: Re-assign CAD ID for the layers denoted with “*”, from (58;20), (39;20), (59;20) and (40;20),
respectively, to (54;20), (35;20), (55;20) and (36;20) to match with your metallization scheme.
4.5.54.1.3 Metallization Options Using Mr as the Top Metal

1. Start with “N45_TSMC_SRDMB_BIB_Mr.gds” sample GDS file. Select the metallization layers from
Metallization Options using Mr as Top Metal

Metal scheme 1P7M 1P8M 1P9M 1P10M
5x1r 4x2r 6x1r 5x2r 7x1r 6x2r 7x2r
M1 31;0 31;0 31;0 31;0 31;0 31;0 31;0
VIA1 51;0 51;0 51;0 51;0 51;0 51;0 51;0
M2 32;0 32;0 32;0 32;0 32;0 32;0 32;0
VIA2 52;0 52;0 52;0 52;0 52;0 52;0 52;0
M3 33;0 33;0 33;0 33;0 33;0 33;0 33;0
VIA3 53;0 53;0 53;0 53;0 53;0 53;0 53;0
M4 34;0 34;0 34;0 34;0 34;0 34;0 34;0
VIA4 54;0 54;0 54;0 54;0 54;0 54;0 54;0
M5 35;0 35;0 35;0 35;0 35;0 35;0 35;0
VIA5 55;0 55;80* 55;0 55;0 55;0 55;0 55;0
M6 36;0 36;80* 36;0 36;0 36;0 36;0 36;0
VIA6 56;80* 56;80* 56;0 56;80* 56;0 56;0 56;0
M7 37;80* 37;80* 37;0 37;80* 37;0 37;0 37;0
VIA7 57;80* 57;80* 57;0 57;80* 57;0
M8 38;80* 38;80* 38;0 38;80* 38;0
VIA8 58;80* 58;80* 58;80*
M9 39;80* 39;80* 39;80*
VIA9 59;80*
M10 40;80*
that layer.
Example: For a design with 7M_5x1r.

Step 1: Locate the “5x1r” column under “1P7M” in the metallization options table above. Delete unused
metal and via layers: (56;0), (37;0), (57;0), (38;0), (58;80), (39;80)
Step 2: Re-assign CAD ID for the layers denoted with “*”, from (59;80) and (40;80), respectively, to (56;80)
and (37;80) to match with your metallization scheme.
4.5.54.1.4 Metallization Options Using Mu as the Top Metal

The possible metal option in Mu scheme is different from Section 4.5.54 in the seal ring. No Mr option is
allowed when Mu structure is introduced.
The general 45 nm logic process with Mu scheme is offered up to 1P10M. Please refer to the following
tables to assemble the metallization option that fit your design.
Naming for Different Metal Types

Code Data Type
M1 0
Mx 0
My 20
Mz 40
Mu 60
Naming for Different Via Types

Code Data Type
Vx 0
Vy 20
Vz 40
Vu 40
Metallization CAD Layers

Layer CAD Layer ID
Metal-1 31
Via-1 51
Metal-2 32
Via-2 52
Metal-3 33
Via-3 53
Metal-4 34
Via-4 54
Metal-5 35
Via-5 55
Metal-6 36
Via-6 56
Metal-7 37
Via-7 57
Metal-8 38
Via-8 58
Metal-9 39
Via-9 59
Metal-10 40
For example, in a 10M_6x1y1z1u scheme, the Via-7, and Metal-8 should use layer, (57;20), and (38;20),
respectively, for My and Vy layers. The Via-8, Metal-9, should use layer (58;40), (39;40), respectively, for Mz
and Vz layers. The Via-9, and Metal-10 should use layer (59;40), and (40;60), respectively, for Mu and Vu
layers. The Metal-1 through Metal-7 should follow their respective CAD layer ID with data type 0.
If customers want to add the CSR patterns and the seal ring before tape out (option 2), please use the TSMC
sample GDS file for seal ring and CSR as a starting file, and follow the descriptions below to select the related
metal and via layers for your design.
For Metallization Options Using Mu as the Top Metal
Start with “N45_TSMC_SRDMB_BIB_Mu.gds” sample GDS file. Select the metallization layers from the
table below based on the target metallization scheme. Delete from the sample GDS any metal and via
layers that are not listed in the column.
Example: For a design with 7M_5x1u.

Step 1: Locate the first column under “1P7M” in the metallization options table above. Delete unused
metal and via layers: (56;0), (37;0), (57;0), (38;0), (58;40), (39;40)
Step 2: Re-assign CAD ID for the layers Via9 and M10, from (59;40) and (40;60), respectively, to (56;40)
and (37;60) to match with your metallization scheme.
Metallization Options (Mu with second inter-layer metal/via (My/Vy) are used, where the dielectric film
material for inter-layer My/Vy is “Low-K”.)
Total Number of Metal Layers
Metal/ 1P10M
1P4M 1P5M 1P6M 1P7M 1P8M 1P9M
Via
2x1u 3x1u 2x1z1u 4x1u 3x1z1u 3x1y1u 5x1u 4x1y1u 4x1z1u 3x1y1z1u 6x1u 5x1y1u 5x1z1u 4x1y1z1u 7x1u 6x1y1u 6x1z1u 5x1y1z1u 7x1z1u 6x1y1z1u
M1 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0 31;0
VIA1 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0 51;0
M2 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0 32;0
VIA2 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0 52;0
M3 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0 33;0
VIA3 53;40 53;0 53;40 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0 53;0
M4 34;60 34;0 34;40 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0 34;0
VIA4 54;40 54;40 54;0 54;40 54;20 54;0 54;0 54;0 54;20 54;0 54;0 54;0 54;0 54;0 54;0 54;0 54;0 54;0 54;0
M5 35;60 35;60 35;0 35;40 35;20 35;0 35;0 35;0 35;20 35;0 35;0 35;0 35;0 35;0 35;0 35;0 35;0 35;0 35;0
VIA5 55;40 55;40 55;40 55;0 55;20 55;40 55;40 55;0 55;0 55;0 55;20 55;0 55;0 55;0 55;0 55;0 55;0
M6 36;60 36;60 36;60 36;0 36;20 36;40 36;40 36;0 36;0 36;0 36;20 36;0 36;0 36;0 36;0 36;0 36;0
VIA6 56;40 56;40 56;40 56;40 56;0 56;20 56;40 56;40 56;0 56;0 56;0 56;20 56;0 56;0
M7 37;60 37;60 37;60 37;60 37;0 37;20 37;40 37;40 37;0 37;0 37;0 37;20 37;0 37;0
VIA7 57;40 57;40 57;40 57;40 57;0 57;20 57;40 57;40 57;0 57;20
M8 38;60 38;60 38;60 38;60 38;0 38;20 38;40 38;40 38;0 38;20
VIA8 58;40 58;40 58;40 58;40 58;40 58;40
M9 39;60 39;60 39;60 39;60 39;40 39.40
VIA9 59;40 59;40
M10 40;60 40;60
Metallization Options (Mu with top metal/via (My/Vy, 2XTM) are used, where the dielectric film material for top
My/Vy is “USG”.)
Total Number of Metal Layers

Metal/
1P5M 1P6M 1P7M 1P8M 1P9M 1P10M
Via
2x1y1u 3x1y1u 4x1y1u 5x1y1u 6x1y1u 7x1y1u
M1 31;0 31;0 31;0 31;0 31;0 31;0
VIA1 51;0 51;0 51;0 51;0 51;0 51;0
M2 32;0 32;0 32;0 32;0 32;0 32;0
VIA2 52;0 52;0 52;0 52;0 52;0 52;0
M3 33;0 33;0 33;0 33;0 33;0 33;0
VIA3 53;20 53;0 53;0 53;0 53;0 53;0
M4 34;20 34;0 34;0 34;0 34;0 34;0
VIA4 54;40 54;20 54;0 54;0 54;0 54;0
M5 35;60 35;20 35;0 35;0 35;0 35;0
VIA5 55;40 55;20 55;0 55;0 55;0
M6 36;60 36;20 36;0 36;0 36;0
VIA6 56;40 56;20 56;0 56;0
M7 37;60 37;20 37;0 37;0
VIA7 57;40 57;20 57;0
M8 38;60 38;20 38;0
VIA8 58;40 58;20
M9 39;60 39;20
VIA9 59;40
M10 40;60
4.5.54.2 Chip Corner Stress Relief (CSR) Pattern

Triangle empty areas (74 μm) at four chip corners must be
reserved and no layout is allowed inside, as shown in Fig.
4.5.54.2.1.
CSR.R.1 Warning: Violation of this rule may result in a serious layout = 74
mistake thus the corrections of many masks may be
required! Please jobview the mask data after adding CSR
and seal-ring by tsmc.
74 um
e m p ty a re a C h ip c o r n e r
C S R in 4
74 um
c h ip c o r n e r s
e m p ty a re a
F i g . Fig.
4 . 5 4.5.54.2.1
. 5 0 . 2 . 1 . TTriangle
r i a n g l e empty
e m p tareas
y a r e at
a s4achip
t 4 ccorners.
h ip c o r n e r s .
The CSR structure must include PM, CB2_FC or CB2_WB, AP,
{{CB OR CBD} OR RV}, Mtop/Mtop-1 (top metal),
CSR.R.2 VIAtop/VIAtop-1, M8, VIA7…VIA1, M1, CO, PP, OD layers.
The CSR pattern includes an additional 2/6 μm width seal-ring
and reinforced metal structure, as shown in Fig. 4.5.53.2.2.
CSRDMY layer (CAD layer: 166;0), CSRBIB1DMY (166;1) and
CSRBIB2DMY (166;2) are musts if customers add a seal-ring by
CSR.R.4
themselves. DRC does not check CSR and BiB related rules w/o
those dummy layers.
CSR.W.1 Width of reinforced metal structure a = 9~10
CSR.L.1 Length of reinforced metal structure b = 24~25
CSR.R.3 Distance between 45-degree outer seal-ring and seal-ring corner d = 18~20

DMV pattern in CSR must include Mtop/VIAtop/Mtop-1/VIAtop-
CSR.R.5 1/Mtop-2/VIAtop-2/…/V1/M1, except for Mr and Mu design (DMV
pattern: metal/via dummy pattern)
For Mu design, DMV pattern in CSR must include Mtop-1/Mtop-
CSR.R.6 2/VIAtop-2/…/V1/M1, not including Mtop (Mu), VIAtop, and VIAtop-
1. (DMV pattern: metal/via dummy pattern)
CSR_DM.W.1 Metal width of DMV in CSR region S = Table. 4.5.54.2.1.
CSR_DM.S.1 Metal space of DMV in CSR region T  Table. 4.5.54.2.1.
CSR_DM.S.2 Metal space of DMV to CSR metal bar R  Table. 4.5.54.2.1.
CSR_DM.O.1 Overlay of two adjacent DMV metal layers, except Mr and Mu. U = Table. 4.5.54.2.1.
CSR_DV.W.1 Via width of DMV in CSR region P = Table. 4.5.54.2.1.
CSR_DV.S.1 Via space of DMV in CSR region Q  Table. 4.5.54.2.1.
DMV via enclosure by DMV metal in CSR region.
CSR_DV.EN.1 V  Table. 4.5.54.2.1.
DMV via must be inside DMV metal.
Remark:
Chip corner stress relief pattern and seal ring structures are based on the 1P10M process:
*CSRDMY is a dummy layer aligned to the boundary of stress relief pattern in regionΙ for DRC. Please refer
to Fig. 4.5.54.2.3 in the following.
*Please be careful with the non-generic logical operation or non-TSMC standard seal ring on the drawn
dimensions of stress relief pattern and seal ring. It needs to be reviewed by TSMC.
* Dummy metal/via is implemented in no pattern area to strengthen CSR structure. Please follow the sample
gds file and use correct CAD layers with correct datatypes for DMV on the CSR area.
* Seal ring is surrounded by 8 um (7.2um for N40 on-silicon dimension) scribe line dummy bar to enhance die
saw quality against laser and mechanical die saw alike for a wider package reliability margin. Please refer to
the scribe line dummy bar layout rule in Section 4.5.54.5.
* The seal ring wall structure includes the outer and inner seal ring walls with 2um and 6um width, respectively.
The outer seal ring is 2 um wide (for N45; 1.8um for N40 on-silicon dimension) and adjacent to the scribe line;
the inner seal ring is 6 um wide (for N45; 5.4um for N40 on-silicon dimension) and far away from the scribe
line. Please refer to Fig. 4.5.54.4.1. for an example.
For wire bond product,

* PM (mask code 009, CAD layer: 5;0).
* Polyimide is an optional layer and only covers inner seal_ring; no polyimide coverage over the outer
seal_ring. Please refer to Fig. 4.5.54.4.1.1 for the details. If PM mask is generated by LOP, tsmc will remove
polyimide on sealring to avoid peeling risk from the specific layouts.
For flip-chip product,

* Polyimide only covers inner seal_ring; no polyimide coverage over the outer seal_ring. Please refer to Fig.
4.5.54.4.1.1 for the details.
* CBD (mask code 306) layout is the same as CB.
* Do not draw UBM (mask code 020) layout on the seal ring (chip corner stress relief pattern, seal ring
wall, and assembly isolation) and SLDB. No UBM metal is left in these regions.
* AP (mask 309) must be drawn on seal ring according to the rules.
Chip Corner Stress Relief Pattern (Fig. 4.5.54.2.2)

The scribe line dummy bar is not drawn in this figure.
Top View Fig. 4.5.54.2.2.a
CSR Layout Fig. 4.5.54.2.2.b
CSR additional seal ring
a a
Reinforced
a Metal
b a
structure
Chip Corner Stress Relief pattern (Fig. 4.5.54.2.3)

Chip corner stress relief pattern can reduce the impact of damage induced by thermal stress during packaging and field
application. Please refer to regionΙas an example.
CSR
74um
T r ia n g le e m p t y a r e a
d u m m y m e ta l/v ia
C h ip
c o rn e r
6um
74um
6um
C h ip e d g e
6um 10um 8um
A s s e m b ly S e a l S c r ib e lin e
is o la tio n r in g dum m y bar
Dummy metal/via (DMV) in the CSR region (Fig. 4.5.54.2.4.)

CSR
d u m m y m e ta l/v ia
Table. 4.5.54.2.1. Rule summary of DMV in CSR for items P~V.
Label P Q R S T U V
M1 - - 0.5 0.8 0.4 0.7 -
VIAx/Mx 0.07 0.11 0.5 0.8 0.4 0.7 0.135
VIAy/My 0.14 0.14 0.5 0.8 0.4 0.7 0.14
VIAz/Mz 0.36 0.84 0.5 0.8 0.4 0.7 0.17
VIAr/Mr 0.46 0.74 0.5 1 0.5 - 0.12
VIAu/Mu 0.36 3 3 3 3 - 0.33
C S R Layout
: 3um X3um M u dum m y
C S R Layout
4.5.54.3 Box in Box (BiB) Pattern inside CSR

1. To meet extremely tight requirement of overlay control for critical layers (OD, PO, CO), the box-in-box
patterns are put into the CSR region for overlay monitoring.
2. CSRBIB1DMY(166;1) and CSRBIB2DMY(166;2) are dummy layers aligned to the boundary of the stress
relief pattern in region-Ι for DRC.
CSRBIB1DMY(166;1) -- DRC recognition layer for location at left-top and right-bottom CSR region
CSRBIB2DMY(166;2) -- DRC recognition layer for location at right-top and left-bottom CSR region
PO_OD, CO_OD and CO_PO BiB patterns must inside CSR
 PO_OD BiB pattern is formed by [OD ring + PO ring inside OD ring]
 CO_PO {CO_OD} BiB pattern is formed by [PO {OD} ring + CO ring
inside PO {OD} ring (inner and outer)]
BiB.R.1
Left-top & right-bottom CSR region must has CO_OD and CO_PO BIB
pattern
Right-top & left-bottom CSR region must has PO_OD, and CO_PO BIB
pattern
BiB.W.1 Width of OD ring and PO ring A = 1.1
BiB.W.2 Width of CO (maximum = minimum) B = 0.17
BiB.W.3 Width of ((CO SIZE 0.05) SIZE -0.05) of CO ring L = 0.965
Space of {OD ring or PO ring} to sealring OD
BiB.S.1 C = 4
DRC only select one side of OD ring or PO ring for space check
BiB.S.2 Space of {OD ring OR PO ring} corner to 45-degree seal-ring OD edge D  1.5
BiB.S.3 Space of CO to CO [in the same ring] E = 0.095
BiB.L.1 Length of OD ring inner edge F = 16.5
BiB.L.2 Length of PO ring inner edge [in PO_OD BiB pattern] G = 7.7
BiB.L.3 Length of PO ring inner edge [in CO_PO BiB pattern] H = 16.5
BiB.L.4 Length of ((CO SIZE 0.05) SIZE -0.05) of CO ring M/N = 6.265, 6.53
BiB.EN.1 Enclosure of PO to OD [opposite edge in PO_OD BiB pattern] I = 3.3
BiB.EN.2 Enclosure of outer CO ring to OD [opposite edge in CO_OD BiB pattern] J = 4.0
BiB.EN.3 Enclosure of outer CO ring to PO [opposite edge in CO_PO BiB pattern] K = 4.0
BiB.R.4 Overlap of OD ring, PO ring, CO patterns are not allowed - - -
4.5.54.4 Seal Ring Layout Rules

The seal ring wall rules, DMV (dummy metal/via) in assembly isolation rules, and CDU (critical dimension
uniformity) placement rules are decribed in this section.
Please follow exactly the schematic diagram below (as in the GDS example) for seal ring layout. DRC cannot
fully check these dimensions. Any seal ring design different from the TSMC standard offer cannot be accepted
in product tape out due to unknown risk for die saw and packaging. Please contact TSMC for a special
approval of a non-TSMC standard seal ring.
If the seal ring is added by TSMC, TSMC will add assembly isolation and seal-ring structure at the same time.
Only DMV and CDU are allowed in the assembly isolation region. Please use the sample gds file for DMV and
follow the DMV rules in this region.
AlCu pad (AP)/Polyimide (PM) can be generated by logic operation for wire-bond non-RDL products.
4.5.54.4.1 Seal Ring Wall Layout Rules

The seal ring wall structure includes the outer and inner seal ring walls with 2um and 6um width, respectively.
The outer seal ring is 2 um wide for N45 (1.8um for N40) and adjacent to the scribe line; the inner seal ring is 6
um wide for N45 (5.4um for N40) and far away from the scribe line. Please refer to Fig. 4.5.54.4.1. for an
example.
 If a customer wants to connect a circuit to the seal ring through M1~Mtop, only allow connecting to the
two most inner seal rings. Besides, the DMV pattern must be removed from the connection path in the
assembly isolation region.
 If a customer wants to connect a circuit to the seal ring through AP, only allow connecting to the inner
most seal ring.
SEALRING layer (CAD layer: 162;0) and SEALRING_DB layer (CAD layer: 162;1) are musts if customers
add a seal-ring by themselves. 162;0 is used to cover the outer seal-ring (2um) and inner seal-ring
(6um);162;1 is used to cover SLDB (3.5um duplicate).
SEALRING layer (162;0) and SEALRING_DB layer (162;1) must exist.
SR.R.1
All the drawings of seal-ring and SLDB structures must be inside of SEALRING (162;0) and
SEALRING_DB (162;1). (except Mu)
Please follow the CAD layers usage of 162;0 and 162;1.
DRC does not check seal-ring related rules w/o those layers.
SR.R.7 CO bar and VIA (x,y,z,r,u), CB/CBD/RV bar must be continuous as a ring.
SR.R.8U Only tsmc standard seal-ring is allowed.
Width of assembly isolation = 6 um (layout forbidden area.)
Only M1~AP, DMV pattern, and CDU are allowed in the assembly isolation region.
(DMV pattern: metal/via dummy pattern)
SR.R.9  6
Each M1~AP patterns in the assembly isolation region must follow the following conditions:
1. Each M1~Mtop must be connected to seal ring wall
2. Each AP can only connect to the inner seal ring wall
3. Each M1~AP overlap SLDB is not allowed
CO.W.2 Width of CO bar in seal-ring. P = 0.06
M1.W.4 Width of M1 metal line in outer seal-ring. Q = 2
M1.W.5 Width of M1 metal line in inner seal-ring. R = 6
VIAx.W.2 Width of VIAx bar in seal-ring. B = 0.5
VIAx.W.3 Width of VIAx hole in seal-ring. D = 0.07
VIAx.EN.5 Enclosure of VIAx bar by Mx in seal-ring. A  0.21
VIAx.EN.6 Enclosure of VIAx hole by Mx in seal-ring. I  0.22
VIAx.S.4 Space of VIAx hole in seal-ring. G  0.35
VIAx.S.5 Space of VIAx hole to VIAx bar in seal-ring. C, H  0.365
Maximum space of VIAx hole [INSIDE SEALRING]
VIAx.S.9 G  12
DRC flags: {SEALRING AND Mx} must be fully covered by {{SEALRING AND VIAx holes} SIZING 6um}
Mx.W.4 Width of Mx metal line in outer seal-ring. Q = 2
Mx.W.5 Width of Mx metal line in inner seal-ring. R = 6
VIAy.W.2 Width of VIAy bar in seal-ring. B = 0.5
VIAy.W.3 Width of VIAy hole in seal-ring. D = 0.14
VIAy.EN.5 Enclosure of VIAy bar by My in seal-ring. A  0.21
VIAy.EN.6 Enclosure of VIAy hole by My in seal-ring. I  0.15
VIAy.S.4 Space of VIAy hole in seal-ring. G  0.34
VIAy.S.5 Space of VIAy hole to VIAy bar in seal-ring. C, H  0.3
Maximum space of VIAy hole [INSIDE SEALRING]
VIAy.S.8 G  12
DRC flags: {SEALRING AND My} must be fully covered by {{SEALRING AND VIAy holes} SIZING 6um}
My.W.4 Width of My metal line in outer seal-ring. Q = 2
My.W.5 Width of My metal line in inner seal-ring. R = 6
VIAz.W.2 Width of VIAz bar in seal-ring. B = 0.5
VIAz.W.3 Width of VIAz hole in seal-ring. D = 0.36
VIAz.EN.5 Enclosure of VIAz bar by Mz in seal-ring, except Mu design A  0.21
VIAz.EN.5.1 Enclosure of VIAz bar by Mz in seal-ring in Mu design A  0.30
VIAz.EN.6 Enclosure of VIAz hole by Mz in seal-ring. I  0.21
VIAz.S.4 Space of VIAz hole in seal-ring. G  0.54
VIAz.S.5 Space of VIAz hole to VIAz bar in seal-ring. C, H  0.34
Maximum space of VIAz hole [INSIDE SEALRING]
VIAz.S.8 G  12
DRC flags: {SEALRING AND Mz} must be fully covered by {{SEALRING AND VIAz holes} SIZING 6um}
Mz.W.4 Width of Mz metal line in outer seal-ring. Q = 2
Mz.W.5 Width of Mz metal line in inner seal-ring. R = 6
VIAr.W.2 Width of VIAr bar in seal-ring. B = 0.5
VIAr.W.3 Width of VIAr hole in seal-ring. D = 0.46
VIAr.EN.5 Enclosure of VIAr bar by Mr in seal-ring. A  0.08
VIAr.EN.6 Enclosure of VIAr hole by Mr in seal-ring. I  0.08
VIAr.S.4 Space of VIAr hole in seal-ring. G  0.44
VIAr.S.5 Space of VIAr hole to VIAr bar in seal-ring. C, H  0.44
Maximum space of VIAr hole [INSIDE SEALRING]
VIAr.S.8 G  12
DRC flags: {SEALRING AND Mr} must be fully covered by {{SEALRING AND VIAr holes} SIZING 6um}
Mr.W.4 Width of Mr metal line in outer seal-ring. Q = 2
Mr.W.5 Width of Mr metal line in inner seal-ring. R = 6
VIAu.W.2 Width of VIAu bar in seal-ring. B = 0.5
VIAu.W.3 Width of VIAu hole in seal-ring. D = 0.36
VIAu.EN.5 Enclosure of VIAu bar by Mu in seal-ring. A  0.30
VIAu.EN.6 Enclosure of VIAu hole by Mu in seal-ring. I  0.30
VIAu.S.4 Space of VIAu hole in seal-ring. G  0.54
VIAu.S.5 Space of VIAu hole to VIAu bar in seal-ring. C, H  0.34
Maximum space of VIAu hole [INSIDE SEALRING]
VIAu.S.8 G  12
DRC flags: {SEALRING AND Mu} must be fully covered by {{SEALRING AND VIAu holes} SIZING 6um}
Mu.W.4 Width of Mu metal line in outer seal-ring. Q = 2
Mu.W.5 Width of Mu metal line in inner seal-ring. R = 6
CB.W.3 Width of CB/CBD/RV line opening in inner seal-ring. (Tolerance 0.01 μm) U = 2
CB.EN.2 Enclosure of CB/CBD/RV by AP in inner seal-ring. (Tolerance 0.01 μm) X  1
Width of AP bar [overlaps with inner seal-ring and SREZ]
SR.AP.W.3 (Except AP connect to inner seal-ring from Prime Chip) V = 8
(DRC tolerance at 45-degree turning: ±0.02 μm)
Enclosure of AP bar [overlaps with inner seal-ring and SREZ] by inner seal-ring
AP.EN.2 EN = 1
(DRC tolerance at 45-degree turning: ±0.02 μm)
CB2.W.5 Width of CB2_WB/CB2_FC line opening in outer seal-ring. W = 2
Polyimide is prohibited over outer seal-ring and SLDB regions. It only covers inner seal-ring area
PM.R.3 (6um/5.4um for N45/N40). Please see Fig. 4.5.54.4.1.1. (PM drawn pattern must cover outer seal-ring and
SLDB regions.)
Please add as many VIA holes as possible in metal lines of inner and outer seal-rings.
SR.R.4
DRC flags: {SEALRING NOT INTERACT VIAx, VIAy, VIAz, VIAu, and VIAr holes, respectively}
SR.R.5 LMARK must be inside SEALRING_ALL
Fig. 4.5.54.4.1.1. Cross-sectional view of seal ring

Before LOP:
 TSMC will use LOP to remove {CB2_WB OR CB2_FC} at SLDB and outer seal ring regions.
Post LOP:
Top view of seal ring

Before LOP: Post LOP:

(Adjacent via array) A
A H H
A I G
B D
B D B
C
Assembly
F isolation
VIAx G
Cad Layer 162

(Seal Ring)
Cad Layer 162;0
F
(Seal Ring)
2um 2um 6um

(Outer seal ring wall) (Inner seal ring wall)
(Adjacent via array) A

A H H
A I
G
B D
B D B
F Assembly
isolation
VIAy G
Cad Layer 162

(Seal Ring) Cad Layer 162;0
(Seal Ring)
F
* Recommended value, DRC only checks min. value.

Layer A B C D F G H I
VIAx 0.21 0.5 1* 0.07 0.175 0.35 0.365 0.22
VIAy 0.21 0.5 1* 0.14 0.17 0.34 0.3 0.15

A I A H (Adjacent via array) A
G H
B D
B B
C D
Assembly
F
isolation
VIAz G
Cad Layer 162

(Seal Ring)
F

G H
B D
B B
C D
Assembly
F
isolation
VIAr G
Cad Layer 162

(Seal Ring)
F
VIAz 0.21 0.5 0.72* 0.36 0.38 0.6* 0.67* 0.21
VIAr 0.21* 0.5 0.62* 0.46 0.4 0.8* 0.8* 0.21*
Top view of seal ring (VIAz and VIAu)

When using Mu design

G H
B D
B B
C D
Assembly
F
isolation
Cad Layer 162

(Seal Ring) Cad Layer 162
(Seal Ring)
F

VIAz / VIAu 0.33 0.5 0.48* 0.36 0.38 0.68* 0.43 0.33
4.5.54.4.2 DMV in Assembly Isolation Layout Rules

All DMV rules bypass CDUDMY (165;0) region.
Table.
SR_DM.W.1 Metal width of DMV in assembly isolation S =
4.5.53.4.2.1
Table.
SR_DM.S.1 Metal space of DMV in assembly isolation T 
4.5.53.4.2.1
Table.
SR_DM.S.2 Metal space of DMV to seal-ring metal bar R 
4.5.53.4.2.1
Table.
SR_DM.O.1 Overlay of two adjacent DMV metal layers, except Mr and Mu. U =
4.5.53.4.2.1
Table.
SR_DV.W.1 Via width of DMV in assembly isolation P =
4.5.53.4.2.1
Table.
SR_DV.S.1 Via space of DMV in assembly isolation Q 
4.5.53.4.2.1
Enclosure of DMV via by DMV metal in assembly isolation Table.
SR_DV.EN.1 V 
DMV via must be inside DMV metal. 4.5.53.4.2.1
DMV pattern in assembly isolation region must include Mtop/VIAtop/
SR.R.2 Mtop-1/VIAtop-1/Mtop-2/VIAtop-2/…/V1/M1, except Mr and Mu design.
(DMV pattern: metal/via dummy pattern)
For Mu design, DMV pattern in assembly isolation region must include
SR.R.3 Mtop-1/Mtop-2/VIAtop-2/…/V1/M1, not including Mtop(Mu), VIAtop, and
VIAtop-1. (DMV pattern: metal/via dummy pattern)
Top view of DMV in assembly isolation

(Mz, My, Mr as top metal)
Table. 4.5.54.4.2.1. Rule summary of DMV in assembly isolation for items P~V.
Label P Q R S T U V
M1 - - 0.4 0.8 0.4 0.7 -
VIAx/Mx 0.07 0.11 0.4 0.8 0.4 0.7 0.135
VIAy/My 0.14 0.14 0.4 0.8 0.4 0.7 0.14
VIAz/Mz 0.36 0.84 0.4 0.8 0.4 0.7 0.17
VIAr/Mr 0.46 0.74 0.4 1 0.5 - 0.12
Top view of DMV in assembly isolation

When using Mu design
For Mu design, DMV pattern in assembly isolation is without Mu_(Mtop)/VIAu/VIAz.
Table. 4.5.54.4.2.2. Rule summary of DMV in assembly isolation.

Label R S T U
Mz 0.5 0.8 0.4 0.7
4.5.54.4.3 CDU (Critical Dimension Uniformity) pattern in Assembly Isolation

Rules
CDU pattern is unnecessary. If you want to add a CDU pattern, please place in a 6 μm assembly isolation
beside a seal ring.

CDU.R.1 CDUDMY must be inside the assembly isolation, beside the seal-ring.
CDU.R.2 OD/Poly/NP/CO/M1/Vx/Mx must be inside the CDUDMY.
4.5.54.5 Scribe Line Dummy Bar Layout Rules

Scribe line dummy bar (SLDB) is a structure surrounding the seal ring to enhance die protection against the
die saw damage. Laser grooving or mechanical saw during dicing is not allowed to damage SLDB. 8um
(7.2um for N40) extra space outside the original seal ring structure is needed for SLDB. Please follow exactly
the schematic diagram below (as in GDS example) for SLDB. DRC cannot fully check these dimensions. If you
do not use these dimensions as below, please consult with TSMC. Scribe line dummy bar includes two
duplicates of 3.5 um wide structures. Please refer to Fig. 4.5.54.5.1 for details.
CO.W.3 Width of CO bar in SLDB. P = 0.06
M1.W.6 Width of M1 metal line in SLDB. Q = 0.5
VIAx.W.4 Width of VIAx bar in SLDB. B = 0.5
VIAx.W.5 Width of VIAx hole in SLDB. D = 0.07
VIAx.EN.7 Enclosure of VIAx hole by Mx in SLDB. J  0.015
VIAx.S.6 Space of VIAx hole in SLDB. G  0.35
Mx.W.6 Width of Mx metal line in SLDB. Q = 0.5
VIAy.W.4 Width of VIAy bar in SLDB. B = 0.5
VIAy.W.5 Width of VIAy hole in SLDB. D = 0.14
VIAy.S.6 Space of VIAy hole in SLDB. G  0.34
VIAy.S.7 Space of VIAy hole to VIAy bar in SLDB E  0.68
Width of My metal line in SLDB.
My.W.6 R = 3.5
(DRC tolerance at 45-degree turning: ±0.02)
VIAz.W.4 Width of VIAz bar in SLDB. B = 0.5
VIAz.W.5 Width of VIAz hole in SLDB. D = 0.36
VIAz.S.6 Space of VIAz hole in SLDB. G  0.54
VIAz.S.7 Space of VIAz hole to VIAz bar in SLDB E  0.54
Width of Mz metal line in SLDB.
Mz.W.6 R = 3.5
VIAr.W.4 Width of VIAr bar in SLDB. B = 0.5
VIAr.W.5 Width of VIAr hole in SLDB. D = 0.46
VIAr.S.6 Space of VIAr hole in SLDB. G  0.44
VIAr.S.7 Space of VIAr hole to VIAr bar in SLDB E  0.44
Width of Mr metal line in SLDB.
Mr.W.6 S = 3
Width of Mu metal line in SLDB
Mu.W.6 T = 6
VIAu.W.4 Width of VIAu bar in SLDB. B = 0.5
VIAu.W.5 Width of VIAu hole in SLDB. D = 0.36
VIAu.EN.7 Enclosure of VIAu hole by Mu in SLDB. I, H  0.3
VIAu.S.6 Space of VIAu hole in SLDB. G  0.54
VIAu.S.7 Space of VIAu hole to VIAu bar in SLDB E  0.54
CB.W.4 Width of CB/CBD/RV line opening in SLDB. (Tolerance 0.01 μm) U = 2
CB.EN.3 Enclosure of CB/CBD/RV by AP in SLDB. (Tolerance 0.01 μm) X  1
AP.W.4 Width of AP bar in SLDB. V = 4
CB2.W.6 Width of CB2_WB/CB2_FC line opening in SLDB. W = 2
SR.R.5U Please add VIA holes in metal lines of SLDB as many as possible.
Fig. 4.5.54.5.1. Cross-sectional view of scribe line dummy bar

(Mz, My as top metal)
Before LOP:
Post LOP:
Cross-sectional view of scribe line dummy bar

(Mr as top metal)
Before LOP:
Post LOP:

When using Mu design (Mu as top metal, Mz as top-1 metal)
For Mu design, the structure of scribe line dummy bar (SLDB) is different from the general one in
Mtop/VIAtop/VIAtop-1 when using Mu/Mz as Mtop/Mtop-1. Please see the following figure highlighted in the
green circle.
Before LOP:
Post LOP:

When using Mu design (Mu as top metal, My as top-1 metal)
For Mu design, the structure of scribe line dummy bar (SLDB) is different from the general one in Mtop/VIAtop
when using Mu/My as Mtop/Mtop-1. Please see the following figure highlighted in the green circle.
Before LOP:
Post LOP:
Top view of scribe line dummy bar

Before LOP: Post LOP:
Scribe line Chip
Assembly
Scribe line dummy bar Seal ring
isolation
Outer Inner
SR SR
Wall Wall
Grid: 0.005um AP
AP
8 um
Metal 4 um
CB/CBD CB/CBD
CB/CBD CB2 CB2
2 um 2 um
CB2_FC/CB2_WB
2 um 2 um
AP X X’(X-section)
Contact
0.29 um
0.06
0.06 um
um 2.62 um
0.97 um
0.5um 0.5um
3.5 um 3.5 um 2 um 2 um 6 um 6 um
Top view of scribe line dummy bar (Mx/Vx)

Layer B C D G J K L M N
VIAx 0.5 0.5 0.07 0.35 0.215* 0.5 2.86 0.17 0.5
Top view of scribe line dummy bar (My/Vy and Mz/Vz)

Layer B C D E F G M
VIAy 0.5 0.5 0.14 0.68 0.86 0.34 0.17
VIAz 0.5 0.5 0.36 0.57* 0.64 0.76* 0.56
Top view of scribe line dummy bar (Mr/Vr)
Layer B C D E F G M
VIAr 0.5 1 0.46 0.52* 0.54 0.8* 0.63
Top view of scribe line dummy bar (Mu/Vu)

Layer B C D E F G H I M
VIAu / VIAz 0.5 0.5 0.36 0.57* 0.64 0.76* 1.07* 0.57* 0.56
4.5.55 Resistor Warning Rules
RMDMYn (CAD layer 116;x , x = 1~10) and RMDMYAP (116;16) are dummy layers for DRC/LVS to recognize
the metal resistor. RMDMY breaks the connection in LVS, but DRC does not break the connection.
RM.WARN.1 CO overlap {NWDMY AND NW} is not allowed
RM.WARN.2 CO overlap silicided PO/OD resistor is not allowed
RM.WARN.3 CO overlap {RMDMY1 AND M1} is not allowed
RM.WARN.4 {VIAn OR VIAn-1} overlap {RMDMYn AND Mn} is not allowed. (n = 1~top)
RM.WARN.5 RV overlap {{RMDMYAP AND AP} OR {RMDMYn AND Mn}} is not allowed. (n = top)
Mn RMDMY Mn RMDMY
VIAn-1
VIAn-1
X
Mn RMDMY Mn RMDMY
VIAn-1
VIAn-1
X
Mn RMDMY
VIAn-1
X RM.WARN.4
4.5.56 DRM and DRC Completeness
Rule No. Description Label Value

DRM.R.1 is a rule created to remind you that the following DRM and DRC must be
checked before tape-out.
1. T-N45-CL-DR-003 & T-N45-CL-DR-017 is pad and assembly related design rule that
is not included into this design rule. Please make sure the DRC of T-N45-CL-DR-003 &
DRM.R.1 T-N45-CL-DR-017 has been executed before tape-out. V
2. Antenna deck is seperated from the main. Please make sure the Antenna deck has
been executed before tape-out.
If the above items have been checked, this violation can be ignored. (please refer to the
following Figure)
Figure 4.5.56.1 DRM.R.1 handing flow
5 Layout Guidelines for the Device

Geometry Effect
5.1 Layout Rules for the WPE (Well Proximity Effect)
5.2 Layout Guidelines for LOD (Length of the OD region) Effect
5.3 Layout Guidelines for OSE (OD Space Effect)
5.4 Layout Guidelines for PSE (Poly Space Effect)
5.5 Layout Guidelines for d-CESL Effect
5.1 Layout Rules for the WPE (Well Proximity

Effect)
NMOS or PMOS very close to well edge will exhibit a difference in threshold voltage (Vt) and drive current (Id)
from that of the device located remotely from the well edge. As well edge and gate spacing gets smaller, the Vt
of MOS device is raised and the Id is degraded.
This WPE phenomenon occurs to every MOS: standard Vt, high Vt, low Vt , thin oxide MOS, and thick oxide
MOS.
SPICE model has included the WPE effect. Users need to input SCA, SCB, and SCC in the netlist to activate
these new features. (SCA, SCB, and SCC can be treated as geometry factors derived from device geometry
and its well environment –distances from Well edge(s) to gate.)
For the sensitive circuit, e.g. constant current source or differential input pair, which needs precise device
parameter control (e.g. ΔVt <5mV and ΔId<2%,) please use SPICE model to calculate the required controls
then design accordingly.
Rule No. Device Label Op. Rule

PO.S.14.GSm® Gate space to (OD2 OR (NW OR NT_N)) in Core NMOS  0.8
PO.S.14.LPm® Gate space to (OD2 OR (NW OR NT_N)) in Core NMOS  1.4
PO.EN.1.GSm® Gate enclosure by ((NW NOT OD2) NOT NT_N ) in Core PMOS  1.0
PO.EN.1.LPm® Gate enclosure by (NW NOT NT_N ) in Core PMOS  1.4
PO.EN.2.GSm® Gate enclosure by (OD2 NOT (NW OR NT_N)) in IO NMOS.  3.7
PO.EN.2.LPm® Gate enclosure by (OD2 NOT (NW OR NT_N)) in IO NMOS.  2.0
PO.EN.3.GSm® Gate enclosure by ((NW AND OD2) NOT NT_N) in IO PMOS  2.3
PO.EN.3.LPm® Gate enclosure by (NW NOT NT_N) in IO PMOS  1.8
1. The OD2 layout will change the Well pattern on mask due to logic operation. Therefore, not only NW layout
but also OD2 layout will impact WPE effect. Please refer to the figure 5.1.1 and logic operation of the
above four recommendations.
2. For the dimension smaller than the above rules, the Vt of MOS device is raised as well as the Id is
degraded. This effect increases with the reduction of the space or enclosure dimension.
3. The WPE phenomenon occurs to every MOS: standard Vt, high Vt, low Vt , thin oxide MOS, and thick oxide
MOS.
4. If the above dimension is impossible to comply with in the critical circuit requiring tight matching in
threshold voltage or Id, identical layouts with identical well enclosure dimension should be kept. (Figure
5.1.1)
5. If the distance between gate and well is the same, the WPE impact from the poly end cap direction is
smaller than that from the source/drain direction.
6. SPICE model has included the WPE effect. Users need to input SC in the netlist to activate these new
features. During post-simulation, LPE will automatically extract the SC from layout, and add the extracted
SC to the netlist, then activate the model properly. (SC is the distance between gate to Well edge, please
refer to the Appendix in the SPICE document). Not only NW layout but also OD2 layout will impact WPE
calculation. Please refer to the 4 WPE recommendations in this section and the Figure 5.1.1.
NW
SC1 SC1
SC2 SC4 SC2 SC4
OD2
SC3 SC3
SC1 SC1
SC2 SC4 SC2
SC3
Figure 5.1.1 Both NW layout and OD2 layout are related to WPE. (For LP process, only NW layout will
impact both core and IO PMOS WPE calculation)
7. The detailed information regarding the device parameter impact by one side neighboring Well, or two sides
or four sides is as follows.
Core N/PMOS IO N/PMOS
(N45GS=N40G) (N45GS=N40G)
ΔVt < 5mV ΔId < 2% ΔVt < 5mV ΔId < 2%
1 side 0.5/0.4 0.6/0.7 2.0/ 1.2 0.7/0.4
2 sides 0.6/0.8 0.7/0.8 2.8/1.8 1.6/1.1
4 sides 0.7/0.9 0.8 /1.0 3.7/2.3 2.1/1.5
Core N/PMOS IO N/PMOS

(N45LP/LPG, N40LP/LPG) (N45LP/LPG, N40LP/LPG)
ΔVt < 5mV ΔId < 2% ΔVt < 5mV ΔId < 2%
1 side 0.8/0.6 0.8 1.0/0.8 0.6/0.4
2 sides 1.2/1.0 1 1.4 0.8
4 sides 1.4 1.2/1.4 2.0/1.8 1.2
Well edge Well edge
Well edge Well edge

One side Two sides Four sides
gate space to well edge gate space to well edge
in other three sides ≥ 10um in other two sides ≥ 10um
Figure 5.1.2 One/two/four side for WPE
F o r e x a m p le , t o m e e t Δ V t < 5 m V in c o r e N / P M O S ,
poor p le a s e k e e p g a t e s p a c e t o w e ll e d g e  2 . 0 u m in 4
s id e s .
 2 .0 u m
W e ll e d g e
OK
 2 .0 u m
 2 .0 u m
 2 .0 u m  2 .0 u m
W e ll e d g e
OK
 2 .0 u m
W e ll e d g e
W e ll e d g e
Figure 5.1.3 Device Placement for Matching Pairs
5.2 Layout Guidelines for LOD (Length of the

OD region) Effect
5.2.1 What is LOD?
1. The device performance (Vt or Id) will be impacted by LOD effect. It is due to the different levels of
mechanical stress induced by the different OD length.
2. SPICE model has included the LOD effect. Users need to input SA and SB in the netlist to activate
these new features. (SA and SB are the distance between gate to OD edge). (Figure 5.2.1.1)
SA SB
SA SB
1 SA 1 SB
2 SA 2 SB
3 3
Figure 5.2.1.1 Example of SA and SB
5.2.2 How to have a precise LOD Simulation

1. For pre-sim cases
- PDK: Every MOS device in PDK has a layout view. So, when you use TSMC PDK to do design, the
corresponding pcell layouts are also ready. TSMC PDK includes Skill code which can estimate the SA
and SB values from the corresponding pcell before real layouts. The pre-sim netlist will include the
accurate SA and SB parameters.
- If you do not use PDK cell, you need to estimate the SA and SB first, and put them into the netlists as
transistor instance parameters.
SA and SB are 0.29μm for core devices and 0.48μm for IO devices in the layout of test structure for
TSMC SPICE model generation. If you use the above dimensions precisely during layout design, the
LPE will not do any LOD correction.
2. For post-sim cases (layouts are ready), designers need to use TSMC LPE deck to extract the SA and SB
directly from layouts. The LPE will automatically add the extracted SA and SB to the netlists and thus the
simulators will then activate the models properly.
3. Avoid irregular OD layout due to model accuracy concerns. (Figure 5.2.2.1)
Figure 5.2.2.1 Irregular OD
5.3 Layout Guidelines for OSE (OD Space Effect)

5.3.1 What is OSE?
1. The MOS characteristics will be impacted by OSE. This is due to the varying levels of STI mechanical
stress induced by differences in OD space.
2. The MOS characteristics depend on the surrounding OD space in both the “L-direction” (OD-SL) and the
“W-direction” (OD-SW). (Figure 5.3.1.1)
O D -S W
O D -S L
L -d ir e c tio n
W -d ir e c tio n
Figure 5.3.1.1 Example of OD-SL and OD-SW

5.3.2 Id change on device due to OSE
1. The drain current of MOS core or IO device shows complex OD-SL (or OD-SW) dependence. (Figure
5.3.2.1)
2. The closer the actual OD space of your layout to the SPICE structure (reference point in Figure 5.3.2.1),
the less impact.
I/ O O D - S L ( N 4 0 G ) I/ O O D - S W ( N 4 0 G )
 Id s a t( % )
 Id s a t ( % )
r e fe r e n c e r e fe r e n c e
P MO S
PM O S
+%
+%
0
0
NMO S NM O S
-% -%
0.1 1 10 0.1 1 10
L D ir O D S p a c e (u m ) W D ir O D S p a c e ( u m )
Figure 5.3.2.1 Id shift (%) due to different OSE in core and I/O NMOS/PMOS
5.3.3 How to reduce the differences between pre-

simulation and post-simulation
1. Standard cell:
 OD space to standard cell boundary: 0.05~0.07um in the L-direction
 OD inside the FILLER cell is highly recommended. (Figure 5.3.3.1)
 FILLER cell with fixed 0.07um OD space to standard cell boundary is recommended. (Figure 5.3.3.1)
 Accurate cell characterization with OD on all four sides. (Figure 5.3.3.2)
i. Complete the cell layout
ii. Add 2nd PO outside the cell (refer to PSE)
iii. Add dummy pattern outside the cell
1. Left/right: add FILLER cell
2. Top/down: add OD
iv. LPE netlist extraction with OSE
v. Post-simulation with OSE
 Standard cell array
i. No empty area inside the cell array. FILLER cell is must.
ii. Add OD/PO FILLER cells and {OD OR Dummy OD} on all four sides of the block boundary
(Figure 5.3.3.2)
Filler 1 Filler 2 Filler 3

OD
PO
0.14 0.09
OD OD OD OD OD
0.24 um~ 0.12 um~ 0.12 um ~

0.28 um 0.14 um 0.14 um
Figure 5.3.3.1 TSMC FILLER cell example with fixed 0.07um OD space to standard cell boundary.
Consecutive Filler 1 is not recommended.
Dum m y O D
O D /P O F IL L E R c e lls
Dum m y O D
Dum m y O D
Dum m y O D
Figure 5.3.3.2 Add OD/PO FILLER cells and Dummy OD on four sides
2. Large IP:
 Recommend to insert SR_DOD by TSMC utility within IP to reduce the pre-/post-simulation difference.
 If no SR_DOD, recommend to insert a guard ring with ≥ 0.5um OD, to define the IP boundary.
 DOD/DPO is still needed, at > 2um distance to main OD, to meet the OD and PO density rule.
 LPE netlist extraction with OSE.
 Post-simulation with OSE.
3. DOD/DPO utility:
 N45 utility, with SR_ DOD and SR_DPO (Figure 5.3.3.3), is provided to match the SPICE test key with
0.1um L-direction OD space and 0.88um W-direction OD space.
SR_DO D/
SR_DPO
D O D /D P O
Figure 5.3.3.3 example of SR_ DOD and SR_DPO
4. To optimize model simulation accuracy, avoid irregular OD layout in either the L-direction or the W-
direction. (Figure 5.3.3.4)
Figure 5.3.3.4 Irregular OD
5.4 Layout Guidelines for PSE (Poly Space

Effect)
5.4.1 What is PSE?
Poly space will impact the MOS characteristics. Besides the 1st poly space, the 2nd poly space also impacts the
MOS characteristics. But the PSE by the 2nd poly space is smaller than that by the 1st poly space. (Figure
5.4.1.1)
st st st st
1 p o ly 1 p o ly 1 p o ly 1 p o ly
nd nd nd nd
2 p o ly Ta rg e t g a te 2 p o ly 2 p o ly Ta rg e t g a te 2 p o ly
Figure 5.4.1.1 Example of the 1st poly and the 2nd poly
5.4.2 Id change on device due to PSE

1. PSE affects the drain current of core devices. (Figure 5.4.2.1)
2. The closer the actual PO space of your layout to the SPICE structure, the less impact.
NM OS (N 4 0 G ) P M O S (N 4 0 G )
 Id s a t ( % )
 Id s a t ( % )
+% +%
0 .0 0 .0
0 .1 0 0 .1 5 0 .2 0 0 .2 5 0 .1 0 0 .2 0 0 .3 0
P o ly S p a c e ( u m ) P o ly S p a c e ( u m )
Figure 5.4.2.1 Id shift (%) due to PSE in NMOS/PMOS

simulation and post-simulation on N40G circuit?
1. Make sure to insert the 1st poly to meet the poly space rule (PO.S.2). And follow PO.S.18.GS® carefully.
2. During the characterization, add a 2nd SR_DPO (you can use TSMC’s DOD/DPO utility) next to the 1st
SR_DPO on both sides of the cell boundary, to reduce the difference between pre-simulation and post-
simulation.
3. Add a 2nd SR_DPO on both sides of the IP boundary before characterization as well.
5.5 Layout Guidelines for d-CESL Effect

5.5.1 What is d-CESL effect?
N40G uses d-CESL to enhance the device performance. However, additional differences between pre-
simulation and post- simulation have been observed on the core devices near the stress liner boundary.
(Figure 5.5.1.1)
Figure 5.5.1.1 Example of d-CESL stress liner boundary
5.5.2 Id change on the N40G device due to d-CESL

1. d-CESL effect affects the drain current of N40G core devices. (Figure 5.5.2.1)
2. The closer the actual d-CESL of your layout to the SPICE structure, the less impact.
N M O S EN X N M O S EN Y
0 0
－ % － %
 Id s a t ( % )
 Id s a t ( % )
0 .1 0 1 .0 0 1 0 .0 0
0 .0 1 0 .1 0 1 .0 0 1 0 .0 0
E N X (u m ) E N Y (u m )
PM O S EN X PM O S EN Y
0
＋ %
－ %
0
 Id s a t ( % )
 Id s a t ( % )
－ %
0 .1 0 1 .0 0 1 0 .0 0
0 .0 1 0 .1 0 1 .0 0 1 0 .0 0
E N X (u m ) E N Y (u m )
Figure 5.5.2.1 Id shift (%) due to d-CESL in NMOS/PMOS

simulation and post-simulation on N40G circuit?
1. Standard cell:
 X direction: keep continuous, aligned NW and PW structure, like a standard cell row. Avoid N/P well
interleaving. (Figure 5.5.3.1)
 Y direction: keep regular N-N-P-P well structure, like a standard cell row. (Figure 5.5.3.1)
 Keep the same distance from gate to well boundary for the matching devices, no matter source/drain
or endcap direction (same approach as WPE).
2. IP:
 With N+/NW guard ring (OD width ≥ 0.1um) surrounded.
 P+ ACTIVE in this IP space to OD of the N+/NW guardring ≥ 0.86um.
 IP boundary keeps 1.2um space with other IP boundary.
 Recommend: without empty area
i. Move the white space to be between the different types of MOS in both the X and Y directions,
not between the same types of MOS.
ii. The well boundary should be in the middle, for the X direction.
3. Chip implementation:
 Expected <3% performance difference (worse case) between pre-simulation and post-simulation for
all IPs and standard cells with the above guidelines.
Good Not Good
Y - d ir e c t io n NW
X - d ir e c t io n
NW
PW
NW
PW
PW
NW
Not Good
PW NW PW NW
NW PW NW PW
Figure 5.5.3.1 Example of NW/PW placements
6 N40LP/LPG Design Information

This chapter contains the following N40LP/LPG design information:
6.1 Non-shrinkable Layout Rules
6.2 Design Flow For Tape-Out
In the following, “Drawn dimension” is used for describing dimension of schematics and layout before
shrinking, which are usually seen in customers’ design environment.
“Post-shrink dimension” is used for describing dimension of schematics and layout after shrinking, which are
used in TSMC mask database processing after tape-out.
6.1 Non-shrinkable Layout Rules

6.1.1 Purpose:
A set of non-shrinkable rules are defined to meet the below requirements:
1. The limitation of the silicon process step, testing probing, and assembly.
2. Prevent DRC false errors from 110% (or any other finer scale up ratio like 111%) size up steps.
These rules are mainly for migrating existing 45LP IP to 40LP technology by layout re-use approach.
6.1.2 Non-shrinkable Rules
The poly gate space range to neighboring poly [for channel length <
0.06μm], and allow the violation with length ratio < 30% on one side
and one segment. 0.13 ~ 0.22
PO.S.2.LP.S G =
or 0.32
The length ratio = violation length / device width.
This rule is for poly gate CDU control
OD25_33.W.1.LP.S A  0.55
OD25_33).
OD25_33.W.2.LP.S B  0.44
OD25_33).
HVD_N25.W.2.S Channel width of {Gate INTERACT HVD_N} for SPICE accuracy. N  1.115
HVD_N25.S.11.S W  0.60
[INSIDE HVD_N].
HVD_N25.O.1.S Overlap of {I/O NMOS GATE}. J = 0.33
HVD_N25.L.1.S Channel length of {GATE INTERACT HVD_N}. M  0.88
HVD_P25.W.2.S Channel width of {Gate INTERACT HVD_P} for SPICE accuracy. N  1.115
HVD_P25.S.11.S W  0.60
[INSIDE HVD_P].
HVD_P25.O.1.S Overlap of {I/O PMOS GATE} J = 0.28
HVD_P25.L.1.S Channel length of {GATE INTERACT HVD_P} M  0.66
6.1.3 Stress Migration and Wide Metal Spacing Rules

Adjustment (Rule Relaxing)
 The rules listed in the below table are adjusted to avoid DRC false alarm on 110% size-up circuits.
 Except 110% size-up circuits, other circuits have to follow the stress migration and wide metal
spacing rules in CLN45 logic DRM. However, the following rules will be met automatically as
long as CLN45 rules are met.
OD.L.1.S Maximum length of {ACTIVE (source) [width < 0.12 µm] interacts with butted_STRAP} if no CO in M region.  0.44
Maximum OD length [OD width < 0.12µm] between two contacts as well as between one contact and the OD line-
OD.L.2.S  66
end. (except {RFDMY AND RFIP_DMY} and {MOMDMY(155;21) SIZING 1.2um})
Maximum PO length between two contacts, as well as the length from any point inside PO gate to nearest CO
PO.L.1.S  19.8
when the PO width is < 0.08μm. (This check doesn’t include ESD protection devices.)
Maximum width
M1.W.3.S  4.95
Space [at least one metal line width > 0.19μm (W1) and the parallel metal run length > 0.3μm (L1)] (union
M1.S.2.S  0.08
projection)
M1.S.2.1.S  0.12
projection)
M1.S.2.2.S  0.14
projection)
M1.S.2.3.S  0.21
projection)
Space [at least one metal line width > 0.17 μm (W1) and the parallel metal run length > 0.3μm (L1)] (union
M1.S.2.4.S  0.075
projection)
M1.S.2.5.S  0.085
projection)
M1.S.2.6.S  0.13
projection)
M1.S.2.7.S  0.15
projection)
M1.S.3.S  0.5
projection)
At least two VIAx with space  0.16μm (S1), or at least four VIAx with space  0.7μm (S1’) are required to connect
VIAx.R.2.S
Mx and Mx+1 when one of these two metals has width and length (W1) > 0.235μm.
At least four VIAx with space  0.16μm (S2), or at least nine VIAx with space  0.92μm (S2’) are required to
VIAx.R.3.S
connect Mx and Mx+1 when one of these two metals has width and length (W2) > 0.605μm.
At least two VIAx must be used for a connection that is  1.14μm (D) away from a metal plate (either Mx or Mx+1)
VIAx.R.4.S with >
1.26μm (D) away from a metal plate)
 2.8μm (D) away from a metal plate (either Mx or
VIAx.R.5.S Mx+1) with length > 1.54μm (L) and width > 1.54μm (W). (It is allowed to use one VIAx for a connection that is >
3.08μm (D) away from a metal plate (either Mx or Mx+1) with length > 1.54μm (L) and width > 1.54μm (W).)
At least two VIAx must be used for a connection that is  7.1μm (D) away from a metal plate (either Mx or Mx+1)
VIAx.R.6.S with length > 7.7μm (L) and width > 2.31μm (W). (It is allowed to use one VIAx for a connection that is > 7.81μm
(D) away from a metal plate (either Mx or Mx+1) with length > 7.7μm (L) and width > 2.31μm (W)).
Single VIAx is not allowed in “H-shape" Mx+1 when all of the following conditions come into existence:
(1) The Mx+1 has “H-shape" interact with two metal holes: both two metal hole length  (L2) and two metal
VIAx.R.11.S hole area  5um²
(2) The VIAx overlaps on the center metal bar of this “H-shape” Mx+1
(3) The center metal bar length  1um (L) and the metal bar width  0.235 um.
Maximum width
Mx.W.3.S  4.95
Mx.S.2.S  0.1
projection)
Mx.S.2.1.S  0.12
projection)
Mx.S.2.2.S  0.15
projection)
Mx.S.2.3.S  0.21
projection)
Space [at least one metal line width > 0.17 μm (W1) and the parallel metal run length > 0.3μm (L1)] (union
Mx.S.2.4.S  0.075
projection)
Mx.S.2.5.S  0.11
projection)
Mx.S.2.6.S  0.13
projection)
Mx.S.2.7.S  0.165
projection)
Mx.S.3.S  0.5
projection)
At least two VIAy with space   0.63μm (S1’) are required to
VIAy.R.2.S
connect My and My+1 when one of these two metals has width and length (W1) > 0.465μm.
At least four VIAy with space  0.32μm (S2), or at least nine VIAy with space  0.85μm (S2’) are required to
VIAy.R.3.S
connect My and My+1 when one of these two metals has width and length (W2) > 1.255μm.
At least two VIAy must be used for a connection that distance  1.4μm (D) away from a metal plate (either My
VIAy.R.4.S or My+1) with length > 0.77μm (L) and width > 0.77μm (W). (It is allowed to use one VIAy for a connection that is
> 1.54μm (D) away from a metal plate (either My or My+1) with length > 0.77μm (L) and width > 0.77μm (W).)
At least two VIAy must be used for a connection that distance  2.8μm (D) away from a metal plate (either My
VIAy.R.5.S or My+1) with length > 2.2μm (L) and width > 2.2μm (W). (It is allowed to use one VIAy for a connection that is >
3.08μm (D) away from a metal plate (either My or My+1) with length > 2.2μm (L) and width > 2.2μm (W).)
At least two VIAy must be used for a connection that distance  7.1μm (D) away from a metal plate (either My or
VIAy.R.6.S My+1) with length > 11μm (L) and width > 3.3μm (W). (It is allowed to use one VIAy for a connection that is >
7.81μm (D) away from a metal plate (either My or My+1) with length > 11μm (L) and width > 3.3μm (W)).
Single VIAy is not allowed in “H-shape" My+1 when all of the following conditions come into existence:
(1) The My+1 has “H-shape" interact with two metal holes: both two metal hole length  5um (L2) and two metal
VIAy.R.11.S hole area  5um²
(2) The VIAy overlaps on the center metal bar of this “H-shape” My+1
(3) The center metal bar length  1um (L) and the metal bar width  0.465um.
My.W.3.S Maximum width  13.2
My.S.2.S  0.19
projection)
My.S.2.1.S  0.15
projection)
My.S.3.S  0.5
projection)
My.S.4.S  1.5
projection)
At least two VIAz with spacing  1.87μm are required to connect Mz and Mz+1 when one of these metals has a
VIAz.R.2.S
width and length > 1.98μm.
At least two VIAz must be used for a connection that is  5μm (D) away from a metal plate (either Mz or Mz+1)
VIAz.R.3.S with length > 11μm (L) and width > 3.3μm (W). (It is allowed to use one VIAz for a connection that is > 5.5μm (D)
away from a metal plate (either Mz or Mz+1) with length > 11μm (L) and width > 3.3μm (W)).
Mz.W.2.S Maximum width [except bond pad]  13.2
Mz.S.2.S Space [at least one metal line width > 1.65μm (W1) and the parallel metal run length > 1.65μm (L1)]  0.5
Mz.S.3.S Space [at least one metal line width > 4.95μm (W2) and the parallel metal run length > 4.95μm (L2)]  1.5
At least two VIAr with spacing  1.87 μm are required to connect Mr and Mr+1 when one of these metals has a
VIAr.R.2.S
width and length > 1.98 μm.
At least two VIAr must be used for a connection that is  5 μm (D) away from a metal plate (either Mr or Mr+1)
VIAr.R.3.S with length > 11 μm (L) and width > 3.3 μm (W). (It is allowed to use one VIAr for a connection that is > 5.5 μm
(D) away from a metal plate (either Mr or Mr+1) with length > 11 μm (L) and width > 3.3 μm (W)).
Mr.W.2.S Maximum width [except bond pad]  13.2
Mr.S.2.S Space [at least one metal line width > 1.65 μm (W1) and the parallel metal run length > 1.65 μm (L1)]  0.65
Mr.S.3.S Space [at least one metal line width > 4.95 μm (W2) and the parallel metal run length > 4.95 μm (L2)]  1.5
6.1.4 Pad Rule for Wire Bond

 Please refer to T-N45-CL-DR-003 “TSMC 45NM/ 40NM WIRE BOND, EUTECTIC FLIP CHIP AND
INTERCONNECTION DESIGN RULE” for the detailed rules and guidelines.
 Since the pad rule is limited by testing and assembly capability, customer has to check the drawn
layout dimension, i.e. dimesnion before 90% shrink.
6.1.4.1 Non-shrinkable Rules:

Rule
Rule No. Description Single In-line Staggered
40 ≤ Pitch 50 ≤ Pitch < 60
#CB2.P.1 Pad pitch that allows 90% shrink  45 50
Length of CB/CB2 (the edge perpendicular to nearby 55 ≤ Pitch < 60
#CB2.W.2 
prime chip edge) 88
Table notes:
All numbers are drawing dimensions before 90% shrink.
Minimum pad pitch that allows 90% shrink: 45um (single inline); 55um (staggered).
Items denoted by “#” depend on the capability of each individual probing/ assembly house.
6.1.5 Flip Chip Bump Rules

 Please refer to the following flip chip design rule manuals for the detailed rules and guidelines.
DRM No. DRM title
TSMC 45 NM/ 40 NM WIRE BOND, EUTECTIC FLIP CHIP AND INTERCONNECTION
T-N45-CL-DR-003
DESIGN RULE
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH BUILD UP SUBSTRATE
T-N45-CL-DR-017
(FCBGA, FLIP CHIP BALL GRID ARRAY) AND INTERCONNECTION DESIGN RULE
TSMC 45/40 NM LEAD FREE (LF) BUMP FLIP CHIP WITH LAMINATE SUBSTRATE
T-N45-CL-DR-022
(FCCSP, FLIP CHIP CHIP SCALE PACKAGE) AND INTERCONNECTION DESIGN RULE
 The bumping rules for flip-chip design are critical on the bumping ball formation. Customers must meet
the non-shrinkable rules before 90% linear shrink.
 The bump height and diameter would decrease due to UBM shrinking. Customers must evaluate this
bump height change by themselves.
6.1.5.1 Non-shrinkable Rules:

Rule No. Description Rule
#UBM.P.1 Bump pitch  167
UBM.EN.1t UBM enclosure by prime chip edge  55.6
#UBM.EN.2 Enclosure by AP  2.2
BP.W.4t Width of CBD/CB2_FC under UBM area  55.6
#BP.W.6t Width of UBM  88.9
BP.EN.5t CBD/CB2_FC enclosure by UBM  11.1
BP.EN.7t CBD enclosure by Mtop  2.2
Table notes:
Items denoted by “#” depend on the capability of each individual probing/ assembly house.
Items denoted by “t” applied for tsmc bumping only.
6.2 Design Flow For Tape-Out

6.2.1 How to design for CLN40LP/LPG shrink
technology
 Designers must consider the following items since CLN40LP/LPG are required 90% scaling on the
drawn layout:
 IP libraries and chip are required to run timing and power characterization by
1. CLN40LP/LPG spice models with an embedded scaling factor, 0.9
2. CLN40LP/LPG BEOL RC extraction technology files with as embedded scaling factor,
0.9
 Perform full-chip timing analysis and power simulation to ensure chip functionality and
robustness.
 Since scaling factors are all set in process design kits, shrink technology CLN40LP/LPG
and its corresponding design flow is transparent to designers. Check if versions of EDA
tools – P&R, RC extractor, circuit simulator are able to support transparent shrink
design flow.
 The layout for CLN40LP/LPG must follow the related non-shrinkable rules. (Please refer
to section 6.1 “Non-shrinkable Layout Rules”.)
6.2.2 How to prepare a new design of CLN40LP/LPG

To start a whole new CLN40LP/LPG design (that is, there is no existing CLN45LP/LPG product to
shrink from), please follow the design flow in Figure 6.2.2.1.
 TSMC provides SPICE models, standard cell libraries, I/Os, and SRAM models in CLN40LP/LPG.
 Circuit designers should simulate their IP as described in section 6.2.4, paying attention on critical
circuits. Chip designers should follow the same physical design and timing sign-off flow as
CLN45LP/LPG.
Figure 6.2.2.1 Start a CLN40 new tape-out.
6.2.3 CLN45LP/LPG Design Migration to

CLN40LP/LPG Technology
 SRAM replacement: Designers must replace the CLN45LP/LPG SRAM cell by CLN40LP/LPG
one. The following SRAM cells are proven by TSMC.
Process Type CLN40LP/LPG

SRAM HD HC DP HCDP
Cell Size (Before shrunk)
0.299um^2 0.374um^2 0.589um^2 0.741um^2
(N45 drawn dimension)
Also, designers must replace the dummy, strapping, boundary and twist cells with
CLN40LP/LPG unit-cells.
 When legacy CLN45LP/LPG IP re-usage is preferred for CLN40LP/LPG design, in order to
maintain CLN45LP/LPG IP design performance in CLN40LP/LPG technology, besides layout
size-up procedures (introduced as follows), it’s nice to add a marker layer (LP_IP_MIG:
63;45) on CLN45LP/LPG layout area for differentiating them from most CLN40LP/LPG circuit
layout area.
 110% size-up: Silicon validated N45LP analog circuits (for example: matching circuits,
current-driving at I/O circuits) layout might be preferred to be re-used. Designers may
consider 110% layout size-up relatively to other CLN40LP/LPG shrinkable circuit layout in
order to keep post-shrink dimension as close as possible to original size.
 It’s recommended to re-run simulation on legacy CLN45LP/LPG IP by CLN40LP/LPG spice
model for confirming performance acceptable. Although re-use layout approach could keep
silicon dimension quite close, due to N40LP/45LP process technology differences, there
could be some performance differences.
 For a reference layout size-up utility, please consult TSMC Design and Technology Platform
in details.
 Traditional layout 110% size-up approach would require snapping polygon grids and flattening
design hierarchies. Even with finer design grid 1nm, there could still be device layout mismatch risk.
 IP preparation phantom size-up approach:
I. Pre-requisite: Given CLN45LP/LPG layout GDSII, which is clean on CLN45LP/LPG DRC/LVS check.
II. Layout size-up: Size up CLN45LP/LPG IP GDS 110% (or 111%) and perform snapping to 1nm.
III. Size down GDSII CO/VIA layers back to their original dimension (100%) to meet N40LP drawn rules.
Modify size-up layout by swapping BJT with original BJT. Layout fixing will be necessary due to BJT
routing reconnect and size-up induced DRC violation. Add a marker CAD layer (LP_IP_MIG: 63;45) on
top of IP layout for later mask processing.
IV. Re-characterization: Run LPE/RC extraction and simulation on size-up GDSII.
6.2.4 Layout check and post simulation

When the layout is ready, the designer should run DRC/LVS check first. Figure 6.2.4.1 shows the
sequence.
 Once it passes DRC and LVS, perform RC extraction by scaling commands given in Figure 6.2.4.1.
Perform full-chip simulation and timing analysis on the extracted net-list (with parasitic).
 If timing closure is achieved, it is ready for tape-out. Otherwise, re-design, re-layout or make other
adjustments as needed to meet the timing goals.
By embedded scale factor (0.9) in RC extractor technology, the output of the CLN40LP/LPG RC
extractor will be CLN40LP/LPG parasitics. Please refer to section “RC extraction guideline” setting of
IP-level and chip-level extraction.
Figure 6.2.4.1 Layout check and post simulation.
Retune Chip Layout Dummy Tape-out

N45 Library
Layout checking
Handling Timing Utility Timing N40 GDS
design Interconnect & post-sim
& closure closure
achieved achieved
No
Layout checking & post-simulation

N40
Layout checking
(N40
deckDRC with
(DRC, LVS)
non -shrinkable
rules + N40 LVS)
RC extraction commands:
Fire&Ice: setvar layout_scale 0.9
Star-RCXT: magnification_factor: 0.9 N40 SPICE
N40 SRAM
Full chip N40 Libraries
SPF, netlist Timing
with parasitic Analysis
Timing closure achieved
No
6.2.4.1 SPICE Guidelines for Library IP Development

 TSMC provides N40LP/LPG logic and SRAM models, which could be used for circuit
pre-sim and post-sim.
 Outline for CLN40LP/LPG design
1. If using spice model with embedded scale factor =0.9, thus, at pre-sim stage, spice
net-list device size is in N45 dimension (drawn layout dimension). Otherwise,
designers need to set .option scale=0.9 in spice net-list by themselves.
2. At post-sim stage, LPE will extract device size based on drawn layout dimension and
RC extractor will take care of parasitic extraction scaling. The device size is in drawn
dimension but parasitics is extracted based on 90% shrunk layout. As a result, spice
model with embedded scale=0.9 will be used for CLN40LP/LPG simulation since it
only impacts on MOS, DIO geometric parameters but not on parasitics and electrical
parameters. With this extraction flow, both pre-sim and post-sim scale settings are
the same. Thus, it’s easier for design integration and LVS back-annotation for
debugging.
 Simulation Syntax for scaling (HSPICE only):
1. The Following is an example of embedded scaling for MOS and DIODE lib.
.option geoshrink=0.9
2. For macro model devices resistors and varactors, scale factors are put in spice model
usage file header. It’s suitable for both pre-layout and post-layout simulation. Please
refer to the example below.
***** Macro Model Resistor and Capacitor (or Varactor) *****

.LIB scale_option_res
.param scale_res= 0.9
.ENDL scale_option_res
.LIB scale_option_cap
.param scale_cap=0.9
.ENDL scale_option_cap
.LIB scale_option_cap25
.param scale_cap25=0.9
.ENDL scale_option_cap25
3. There are also flags in SPICE model header for parasitic estimation in pre-layout
simulation stage.
***** Contact-to-poly parasitics *****
.LIB CCO_pre_simu
.param ccoflag=1
.ENDL CCO_pre_simu
.LIB CCO_pre_simu_hvt
.param ccoflag_hvt=1
.ENDL CCO_pre_simu_hvt
.LIB CCO_pre_simu_25
.param ccoflag_25=1
.ENDL CCO_pre_simu_25
.LIB CCO_pre_simu_na
.param ccoflag_na=1
.ENDL CCO_pre_simu_na
.LIB CCO_pre_simu_na25
.param ccoflag_na25=1
.ENDL CCO_pre_simu_na25
4. BJT model is not a scalable model, so users can’t specify “area” in the net-list. The
model is not affected by value of scale and has already been extracted from a shrunk
size.
6.2.4.2 RC Extraction Guidelines

 For IP libraries extraction, there are WPE , DFM switches on transistors parameters for more
accurate circuit simulation. Default RC extraction technology file will scales down layout for
parasitics extraction but NOT scale on device geometric parameters.
 Full-chip timing and power simulation/characterization are required to ensure chip functionality and
robust yields.
 Layout extraction procedure (Figure 6.2.4.2.1):
Figure 6.2.4.2.1 Layout Extraction Flow
CLN40LP/LPG TSMC Online

LPE/RCX Techfile
CLN40LP/LPG
SPICE Model
IP level Device & RC Characterize Delay, IP Library

GDSII Extraction Power Timing
by SPICE simulation
Full-chip RC Full-chip
DEF or Extraction Timing, Power,
Milkyway IR-drop, SI analysis
7 Layout Rules and Recommendations for

Analog Circuits
This chapter provides information about the following topics:
7.1 User guides
7.2 Layout rules, recommendations and guidelines for the analog design
7.3 Layout rules and guidelines for device placement
7.4 Burn-in Guidelines for Analog Circuits
7.1 User Guides

1. Use these rules, recommendations, and guidelines to achieve better analog device performance and
matching. In analog circuits, good device matching provides good performance margin and production
yield.
2. The examples of analog circuits:
o Operational Amplifier: includes differential input pair, bias circuit and current mirror.
o DAC: includes constant current source, amplifier using external Rset to adjust full range current
and bias circuit.
o ADC: includes comparator, amplifier, sample/hold switches, switching capacitor, and reference
voltage resistor ladder.
o PLL: includes VCO (delay stage) and charge pump (current mirror, buffer/opamp)
o Bandgap: BJT, current mirror, bias circuit, differential amplifier and ratioed resistor.
o LNA and mixer
o Sense amplifiers in memories.
o Matching pair includes active and passive devices.
3. If your circuit has concern about the rules, recommendations, and guidelines, TSMC DRC deck can
help you to flag the violations. Analog DRC deck is bundled in the TSMC logic DRC deck. The following
two methods can specify the region to run analog part. Please also refer to the user guide in the DRC
deck.
o Dummy layer:
 RRuleAnalog (CAD layer: 182;3): for the layout rules, recommendations, and guidelines of the
analog designs.
o Cell selection based on the following variable:
 CellsForRRuleAnalog: only check the cells in the variable
 ExclCellsForRRuleAnalog: don’t check the cells in the variable
4. A registered symbol “U“ is marked after the rule number as the rule is not checked by DRC.
7.2 Layout Rules, Recommendations and

Guidelines for the Analog Designs
7.2.1 General Guidelines
If possible, use devices with large widths. Do not use minimum widths and
lengths for performance-critical device.
AN.R.1mgU Using current source device as an example, designer should refer to the device
I-V curve to check at which W/L range, the drain saturation current reaches
constant.
Use larger areas for transistors, resistors, and capacitor devices for better
AN.R.2mgU
mismatch.
It is recommended to adopt all the advisory number of the DFM Action-
AN.R.44mgU Required Rules, and also adopt all the parametric/systematic related DFM
Recommendations/Guidelines.
It is recommended not to use a very long channel device in the design. In order
to ensure the channel relaxation time of the MOS device is enough to build up
charge to the steady state, it is recommended to use <10 times of minimum
AN.R.45mgU
channel length at the high operation frequency range. The operating frequency
shall be below 0.2 * gm / Cgate, where gm is the transconductance of the
transistor and Cgate is the gate-oxide capacitance.
Draw the dummy pattern manually and uniformly, surrounding the matching
pair for both the source/drain direction and the poly end-cap direction. (Figure
7.3.2.6)
 The dummy patterns should be identical in the shape, the dimension, the
AN.R.46mgU
space to the main circuit, and from the source/drain direction and the poly
end-cap direction, respectively.
 The dummy OD and dummy PO should be 100% cover the projection
edge of the matching devices.
Avoid using irregular OD for the matching pair. Use simple rectangle to have
AN.R.47mgU
precisely SPICE simulation accuracy. Refer to figure 7.2.1.1.
AN.R.34mgU Prefer simple shapes (rectangles) of OD and Poly.
Avoid OD routing (Prefer using metals and CO) to limit the number of corner
AN.R.35mgU OD (risk of OD rounding), and to limit the number of narrow OD connections
(risk of OD Rs variation)
Figure 7.2.1.1 Example of irregular ODs
7.2.2 MOS Recommendations

PO.S.5m® Recommended PO space to L-shape OD when PO and OD are in the same MOS for model accuracy J  0.2
PO.S.6m® Recommended L-shape PO space to OD when PO and OD are in the same MOS E  0.1
Recommended L-shape PO space to OD when PO and OD are in the same MOS [channel width < 0.3 um
PO.S.6.1m® E  0.18
and L-shape PO length > 0.1 um (L)] (Figure 7.2.2.2)
PO.EX.1m® Recommended PO extension on OD (end-cap) G  0.11
For current mirror devices using common OD, please pay attention to LOD effect (please refer to LOD effect
section), eg. when using common OD, please follow the following items: (Figure 7.2.2.1)
PO.EX.2mgU (1) Keep the same SA/SB
(2) Enlarge extension (F1) to put dummy gate at both source/drain sides with the same channel width,
length, pitch and count, as possible.
AN.R.71mgU Recommend putting dummy gate in the STI edge on the same OD. (Figure 7.2.2.3)
F1 F1
G
E
OD
OD
PO
J p p p
pD u m m y P O g a tpe w i t h s a m e p it c h p
Figure 7.2.2.1 Analog Circuit Layout

L
W id th
Figure 7.2.2.2 PO.S.6.1m®
Figure 7.2.2.3 Dummy GATE placement of analog circuit
7.2.3 Bipolar Transistor (BJT) Rules and

Recommendations
1. Two kinds of vertical bipolar are provided, PNP bipolar (P+/NW/PSUB) and NPN bipolar (N+/PW/DNW).
2. SPICE and PDK offer 3 kinds of emitter size and base size:
PNP10 and NPN10 PNP5 and NPN5 PNP2 and NPN2
Emitter size 10x10 5x5 2x2
3. In order to have precise SPICE model prediction, it is strongly recommended that users should apply the standard
TSMC bipolar layouts (PDK cells) in their designs.
4. The entire device needs to be covered with an BJTDMY (CAD layer: 110) which is used for DRC and LVS check.
RPO needs to cover 0.3μm on the Emitter OD edge for both OD and STI
BJT.R.1 sides, i.e. RPO= ((Emitter OD SIZING 0.3 µm) NOT (Emitter OD SIZING F = 0.6
-0.3 µm))
BJT.R.8 BJTDMY enclosure of Emitter OD G  0.13
OD (Emitter size) is small 2 μm x 2 μm, middle 5 μm x 5 μm, big 10 μm x
BJT.R.2®
10 μm,
BJTDMY overlap of NT_N, PO, VTH_N, VTH_P, VTLN, VTL_P, VAR,
BJT.R.7®
and SRM is not recommended.
Figure 7.2.3.1 Layout of bipolar device
B JTD M Y
G
E m itte r
OD
R P O (F ) OD
7.2.4 Resistor Rules

R P O  1.8 μm (W’), length  20 μm (L’), and square number  5 (L’/W’)
Width
NWROD.R.1m
for NW resistor within OD.
C LWidth  1.8 μm (W”), length  20 μm (L”), and square number  5 (L”/W”)
NWRSTI.R.1m W
R E S .2 m
for NW resistor under STI.
O P O /O D
R PO
O D
OD OD
W ’ W ”
L’
L”
N W
NW
N P N P
NP NP
N W D M Y NW DMY
N W r e s is t o r w it h in O D N W r e s is t o r u n d e r S T I
N W R O D .R .1 N W R S T I.R .1 m
m
Figure 7.2.4.1 Resistors layout
7.2.5 Capacitor Guidelines

It is recommended not to use a very long channel device in the design. In order to
ensure the channel relaxation time of the MOS capacitor (excluding varactor) is
enough to build up charge to the steady state, it is recommended to use proper
AN.R.36mgU
channel length at the high operation frequency range. The operating frequency
shall be below 0.2 * gm / Cgate, where gm is the transconductance of the
transistor and Cgate is the gate-oxide capacitance.
Varactor (NMOS capacitor in NW) is the best choice as MOS capacitor. And the
AN.R.37mgU
NW should have a P-type guard ring tied to ground.
7.2.5.1 Design Guidelines for Capacitor Connections --

for the Estimation of Minimum Metal Width and
Minimum Via Number
Id e a l c u rre n t c u rv e
R e a l c u rre n t c u rv e
Figure 7.2.5.1 Transient peak current

For the estimation of minimum metal line width and minimum number of via connecting to capacitor terminals,
we assume that the charging up or discharge time is a quarter of clock period T.
In calculation:
△t=T/4 to charge up to VDD or discharge from VDD to ground.
T=1/f, f is the clock frequency.
The current to charge or discharge capacitor is
Imax=Cdv/dt=C* VDD/(1/4f)=4f*VDD*C
C is the capacitance extracted from layout
f (is the clock frequency) and VDD are provided by designer.
The minimum metal line width is

W(metal width in μm)= Imax/Jmax, where Jmax= EM current density for metal line per μm.
The minimum number of via is

N(Via number)= Imax/Jvia, Jvia= EM current density for each Via.
Both Jmax and Jvia are provided by process specifications to avoid EM (electro migration)
7.3 Layout Rules and Guidelines for Device

Placement
7.3.1 General Rules and Guidelines
You need to insert the dummy patterns in the empty area, even if the OD, PO, metal
density has already met the density rules.
Insert the dummy patterns properly.
The recommendation steps for this AN.R.3m:

1st Insert same geometric dummy cells manually to minimize the proximity effect
(Figure 7.3.1.1)
AN.R.3mU 2nd Using TSMC’s utility to fill dummy patterns on the rest of the empty space, and
leave 4um white space to insert SR_DOD & SR_DPO.
3rd In TSMC’s utility, Analog (CAD layer: 182;3) layer can’t avoid DOD, SR_DOD
DPO, SR_DPO, or DM1/DMx/DM1_O/DMx_O insertion in the region. Please
use ODBLK, POBLK, or DM1EXCL/DMxEXCL layer to cover your analog
circuit, which will exclude DOD, SR_DOD, DPO, SR_DPO, or
DM1/DMx/DM1_O/DMx_O insertion during chip level.
4th Do electrical or silicon characterization
Avoid having sparse poly gate. Please refer to the item 3 in the section of
AN.R.4mgU
Improvement of poly CD uniformity
D u m m y p a tte r n s
(b lu e )
A c ti v e c i r c u i t
Figure 7.3.1.1 Example of manual DOD, DPO, or unit cell
7.3.2 Matching Rules and Guidelines

Make certain that the areas and shapes of matching pairs are identical.
AN.R.5mU Do not use matching pairs with different proximities (iso/dense), nor with different widths and areas, and
different shape of equal area.
AN.R.6mU Elements of the matching pair should have the same orientation (Figure 7.3.2.1).
Avoid routing metal over a matching pair. M1 is the most critical. If it is unavoidable, then use identical routing
AN.R.7mU
metal with same potential over the matching pair. (Figure 7.3.2.2).
Place the matching devices close together and, if possible, use “common-centroid” or “inter-digitated”
placement for better matching.
AN.R.8mgU
“Common-centroid” architecture is recommended for those devices that cannot be placed close together
(Figure 7.3.2.3).
Regardless of any device dimensions of matching pairs with consistent resistance concerns, use the
AN.R.9mgU symmetrical number of contacts (please refer to the CO.R.5g) and the same CO to PO gate space.
The layout of interconnection routing should be symmetrical with respect to each branch.
Pay attention on the associated routing layout, as well as the associated pattern density, of the matching pair,
AN.R.10mgU
to minimize the Rs difference. (Figure 7.3.2.4) All the routing should be symmetrical to avoid mismatch.
AN.R.11mgU Pay attention on the matching topology of the resistor layout (Figure 7.3.2.5)
AN.R.12mgU PO gate must connect to a protection diode by M1 to reduce the antenna effects in matching pairs.
Make certain that the local pattern density of, and nearby, the matching pair should be identical. Use enough
AN.R.38mU
dummy cells surrounding the matching pair is highly recommended.
In order to avoid the drift of electrical parameter matching, it is important to maintain identical DC bias on the
AN.R.39.mgU each matching-transistor (NMOS or PMOS) at all operation conditions (eg, standby conditions). If the DC bias
is not identical, please evaluate the impact of matching performance.
It is recommended not to use a very long channel device in the design. In order to ensure the channel
relaxation time of the MOS device is enough to build up charge to the steady state, it is recommended to use
AN.R.45mgU <10 times of minimum channel length at the high operation frequency range. The operating frequency shall be
below 0.2 * gm / Cgate, where gm is the transconductance of the transistor and Cgate is the gate-oxide
capacitance.
Draw the dummy pattern manually and uniformly, surrounding the matching pair for both the source/drain
direction and the poly end-cap direction. (Figure 7.3.2.6)
AN.R.46mgU  The dummy patterns should be identical in the shape, the dimension, the space to the main circuit, and
from the source/drain direction and the poly end-cap direction, respectively.
 The dummy OD and dummy PO should be 100% cover the projection edge of the matching devices.
Avoid using irregular OD for the matching pair. Use simple rectangle to have precisely SPICE simulation
AN.R.47mgU
accuracy. Refer to figure 7.2.1.1.
AN.R.60mgU Recommend to put at least two dummy gate with the same channel length in the same OD. (Figure 7.3.2.7)
AN.R.67mgU Recommend to match antenna diode and their metal routing. (Figure 7.3.2.8)
For analog matching pair, recommend to use the same poly endcap size, even for the dummy poly (Figure
AN.R.61mgU
7.3.2.9)
Recommend to equivalent drain and source orientation. Total numbers of D/S and S/D orientations need to
AN.R.65mgU
match. (Figure 7.3.2.10)
Recommend to equalize interconnect and gate loading for matched transistors and tap the gate connection
AN.R.66mgU
from both ends. (Figure 7.3.2.11)
Recommend the following items for MOS capacitor matching (Figure 7.3.2.12)
- Small identical geometry
- Common centroid layout
AN.R.52mgU
- Dummy capacitor
- No on-top metal routing
- Away from power source
Recommend the following items for resistor matching (Figure 7.3.2.13)
- Interdigital configuration
- Equal structure
- Suitable dimension
AN.R.53mgU
- No corner turning (connection with M1. Not to use OD/PO)
- Dummy pattern
- Away from different power source
- Put more contacts
Recommend the following items for MOM matching (Figure 7.3.2.14)
- Uniform metal density
AN.R.54mgU
- Dummy MOM
- Away from different power domain
- Need to take care RC extraction carefully during IP placement
Recommend the following items for varactor matching (Figure 7.3.2.15)
- Use I/O varactor
- Interdigital unit cell layout
AN.R.74mgU
- Dummy varactor cell
- Away from different power domain
In a multiplier ( 1: N, N>2) function design (MOS,PO/OD resistor,MOS CAP), the metal coverage
AN.R.86mgU above target devices (single or multiple) should keep clean as possible, the non-uniform metal V
coverage would induces unexpected mismatch performance
Better matching layout : the same orientation

PO gates are all along x-direction (or y-direction) Poor matching layout : different orientation
Figure 7.3.2.1 Example of same or different orientation for matching pairs
Poor G ood Poor G ood
OD M 1 OD
R e s is t o r R e s is t o r
P PO
M 1 o v e r M O S a ff e c t in g V t M 1 o v e r r e s is t o r a ff e c t in g r e s is ta n c e
Figure 7.3.2.2 Example of avoiding routing metal over a matching pair
b e tte r m a t c h in g la y o u t n o t s u ita b le f o r c r it ic a l
m a tc h in g p a ir s
c o m m o n - c e n tr o id in te r d ig it a te d
d is c r e te O D ( A B B A ) c o m m o n O D (A B A B )
A
A A A
A B A
A or
B B
B
B A B B
B A B
B
A
D u m m y a r r a y ( b lu e )
 C e n tr o i d M O S l a y o u t i s u se d fo r d e v i c e m a tc h i n g i n
3 D d i r e c ti o n w i th r o u ti n g / c o m p l e x i ty tr a d e -o ff :
 C e n t r o id in d i v id u a l M O S c o n f i g u r a t io n is u s e d f o r t y p ic a l
la y o u t
 C e n t r o id a b u t t e d M O S s t y le e n h a n c e s d e v ic e p e r f o r m a n c e
w it h s m a lle r a r e a ( p r e f e rr e d )
Figure 7.3.2.3 Example of common-centroid or inter-digitated layout for matching pairs
Poor G ood
M a t c h in g p a ir s M a t c h in g p a ir s
Figure 7.3.2.4 Example of the associated routing layout of the matching pair
Poor G ood G ood B e tte
R R R
2R R R R R R R R R
Figure 7.3.2.5 Example of matching topology of resistor layout for matching pairs
  A c t i v e d e v i c e s a r e s u r r o u n d e d b y d u m m y o n e i n a ll d i r e c t i o n s w i t h i n s h o r t d i s t a n c e
  A l l d u m m y d e v i c e s a r e i n c l u d e d i n c i r c u i t c h a r a c te r i z a ti o n
  D u m m y u ti l i ty i s n o t r e c o m m e n d e d fo r d e v i c e c h a r a c te r i z a ti o n
A c t iv e d e v ic e
D u m m y d e v ic e
Figure 7.3.2.6 Dummy pattern for matching pairs
nxx
m 1 m 2
A B
Figure 7.3.2.7 Example of dummy poly beside matching parirs
Figure 7.3.2.8 Example to match antenna diode and their metal routing
Figure 7.3.2.9 Example of the same poly endcap size in the same OD
Figure 7.3.2.10 Example to equivalent drain and source orientation
Figure 7.3.2.11 Example to tap the gate connection from both ends of the gate
Capacitor matching
 Small identical geometry
 Large unit y capacitance

Main capacitor
 Common centroid la yout
 Dummy capacitor
 Capacitor shielding
 No on-top metal routing
 Aw ay from pow er source
Dummy capacitor
Figure 7.3.2.12 Example of capacitor matching
 R e s is t o r m a t c h i n g
M1
 In t e r d ig it a l c o n f ig u r a t io n
 E q u a l s tru c t u re
M a i n r e s i s to r  S u it a b le d im e n s i o n
 N o c o r n e r t u r n in g
 D u m m y p a tte rn
 A w a y fro m p o w e r s o u rc e
D u m m y p a t te r n
Figure 7.3.2.13 Example of resistor matching
Figure 7.3.2.14 Example of MOM matching
Figure 7.3.2.15 Example of Varactor matching
Figure Example of a multiplier ( 1: N, N>2) function design
7.3.3 Electrical Performance Rules and Guidelines

Avoid placing the matching pairs or performance-critical devices at the
AN.R.13mU
prime chip corner and prime chip edge. (Figure 7.3.3.1)
Avoid using silicided-OD connected between well strap and the MOS
AN.R.14mgU source node (butted junction) in analog, matching and performance-
critical devices. (Figure 7.3.3.2)
Optimize the CO number at both source and drain sides of performance-
AN.R.15mgU
critical devices. (Figure 7.3.3.3)
Do not use maximum latch-up rule near narrow ravine between wells.
AN.R.16mgU
(Figure 7.3.3.4)
Place unsilicided PO resistor or MOM (without ground shielding) on an N-
AN.R.17mg well for better noise immunity.
A P+ PO resistor is recommended for overall performance.
Do not use single via for high current or resistance sensitive wire. (Figure
AN.R.18mgU
7.3.3.5)
Use thick oxide (OD2) MOS varactor and capacitor to reduce gate oxide
AN.R.20mg
leakage. DRC can not check capacitor.
CB and CBD are not recommended to put on the top of matching pairs or
AN.R.21mgU
performance-critical devices.
For the matching sensitive circuits with DC bias at low Vgs regions; the
AN.R.40mgU layout style effects (such as LOD, WPE and device orientation) should
be carefully reviewed.
For less device offset and variation of Id_analog (Ids at Vds = Vgs =
AN.R.72mgU 0.5*Vdd) of core device, recommend to use merged-OD than separate-
Ods or use common centroid layout style. (Figure 7.3.3.6)
For less mean offset of Id_analog (Ids at Vds = Vgs = 0.5*Vdd) of core
AN.R.73mgU device, recommend to surround MOSFETs with same type of MOSFETs,
or use TSMC dummy insertion utility to fill the blank area. (Figure 7.3.3.7)
The environment of the critical metal routing should have similar metal
AN.R.55mgU
density (Figure 7.3.3.8)
Recommend to consider interconnect routing in device performance
analysis. Symmetrical routing is critical for device matching. Distributed
RC network is constructed differently dependent on interconnect routing.
AN.R.56mgU
Asymmetrical interconnect routing results in device mismatch. For timing
concern circuit, recommend to run RCC (resistor/capacitor/coupling)
extraction. (Figure 7.3.3.9)
Nwells at different potentials should be separated by Pwell strap to
AN.R.68mgU enhance the separation. Surrounding PW guard-ring will be the best.
(Figure 7.3.3.10)
Recommend to use common central layout for BJT diodes (Figure
AN.R.69mgU
7.3.3.11)
In order to reduce the Id_analog (Ids at Vds = Vgs = 0.5*Vdd) gap
between Si and simulation for the MOS in core region, it is not
AN.R.76mgU
recommend to use opposite-type MOS with area ≥ 5um * 5um size
abutted the target MOS.
A = d ie w id t h
B = d ie le n g th
C = d ie d i a g o n a l l e n g t h
L e n g t h a n d w id t h o f d i e i n c l u d e s s e a l r in g
a n d p a r t o f s c r ib e l in e a f t e r d ie s a w
A
C
a *B
*C
b
B
P ro p o s e d z o n e
a *B
a *A a *A
F o r t h e b o t t o m d ie in a s t a c k e d - d ie w ir e b o n d P B G A p a c k a g e
1) a : a w a y f r o m d ie e d g e  1 0 % o f t h e c h i p e d g e le n g t h
2) b : a w a y f r o m d ie c o r n e r  1 5 % o f t h e c h ip d i a g o n a l d i m e n s io n
F o r a s in g le - d ie w ir e b o n d P B G A p a c k a g e
1) a : a w a y f r o m d ie e d g e  3 % o f t h e c h i p e d g e le n g t h
2) b : a w a y f r o m d ie c o r n e r  5 % o f t h e c h i p d ia g o n a l d im e n s io n
F o r a s in g le - d ie f lip c h ip P B G A p a c k a g e
1) a : a w a y f r o m d ie e d g e  1 % o f t h e c h i p e d g e le n g t h
2) b : a w a y f r o m d ie c o r n e r  3 % o f t h e c h i p d ia g o n a l d im e n s io n
T h e a b o v e n u m b e r s m a y b e c h a n g e d b y s e v e r a l f a c t o r s , e . g . d ie s i z e , d ie t h ic k n e s s , p a c k a g e t y p e ,
p a c k a g e m a t e r ia l , p a c k a g e s i z e , a n d c ir c u it d e s i g n m a r g in , p l e a s e c o n t a c t T S M C f o r m o r e d e t a ils .
Figure 7.3.3.1 The proposed zone for matching pairs or performance-critical devices
Poor Poor G ood
S o u rc e W e ll S t r a p
W e ll S t r a p
W e ll S t r a p
S o u rc e S o u rc e
Figure 7.3.3.2 Example of avoiding using silicided-OD connected between well strap and the MOS
source node
Poor G ood
Figure 7.3.3.3 adequate CO number to enlarge the space of CO-to-gate and CO-to-CO extension
NM O S D o n o t u s e m a x im u m la t c h - u p PM O S
r u le ( r e d u c e t h e s p a c e )
NW NW PW PW
N a r r o w w e ll s p a c e
W e ll S t r a p W e ll S t r a p
( n a r r o w r a v in e )
Figure 7.3.3.4 Example of maximum latch-up rule near narrow ravine between wells
Poor G ood
V ia x V ia x
M x+1 M x M x+1 M x
Figure 7.3.3.5 Example of not using single via for high current or resistance sensitive wire
Figure 7.3.3.6 Example for common centroid, merged OD and separate OD.
S u rro u n d M O S F E T s w ith s a m e ty p e o f
M O S F E Ts,
o r u s e T S M C d u m m y in s e rtio n u tility to fill
th e b la n k a re a
Figure 7.3.3.7 Example to Surround MOSFETs with same type of MOSFETs, or use TSMC dummy
insertion utility to fill the blank area.
Figure 7.3.3.8 The environment of the critical metal routing should have similar metal density
Figure 7.3.3.9 Example of metal routing
N W a t s a m e p o t e n t ia l
S u r r o u n d in g P W g u a r d r in g
N W a t s a m e p o t e n t ia l
N W a t d if f e r e n t p o t e n t ia l
Figure 7.3.3.10 Example of NWs at different potentials should be separated.
Figure 7.3.3.11 Example of common central layout for BJT diodes.
7.3.4 Noise
7.3.4.1 Power and Ground
For the low noise circuit, a P-Well ring, which is tied to VSS, is
AN.R.22mgU
recommended to surround all PMOS devices in each analog circuit block.
For the low noise circuit, a N-Well ring, which is tied to VDD, is
AN.R.23mgU
recommended to surround all NMOS devices in each analog circuit block.
Put NMOS in RW (PW in DNW) is a good practice of isolating critical circuit
AN.R.24mgU from substrate noise (Figure 7.3.4.1.1). Make sure every NW connected to
DNW must be same potential (refer to DNW.R.4).
Use NT_N layer (width ≥ 1μm), as a high resistance region, to isolate two
high frequency circuit, to reduce the noise or signal coupling from substrate
(Figure 7.3.4.1.2).
AN.R.25mgU
- minimize the signal lines crossing the high resistance NT_N region
- maximize the distance between metal lines from the substrate above
the NT_N region (use upper level metal).
Use separate power supplies and ground buses for the noisy and sensitive
AN.R.26mgU
circuit and also for the analog and digital circuits. (Figure 7.3.4.1.4).
AN.R.27mgU Keep enough distance between the noisy and sensitive area.
AN.R.28mgU Use wide guard ring to stabilize substrate and well potential.
Poor G ood
S e n s it iv e c ir c u it N o is y c ir c u it S e n s it iv e c ir c u it N o is y c ir c u it
NM OS NM OS NM OS NM OS
NW NW
DNW
N o is e N o is e is is o la t e d .
Figure7.3.4.1.1 Example of NMOS in RW
G u a r d r in g Poor
NT_N
S e n s it iv e c ir c u it N o is y c ir c u it
G u a r d r in g
PW PW
S e n s it iv e c ir c u it
R _PW
G u a r d r in g
N o is e
Good
S e n s it iv e c ir c u it N o is y c ir c u it
S e n s it iv e c ir c u it N o s iy c ir c u it
NT_N
PW (P s u b ) PW
R _P sub
R _P sub
G u a r d r in g
N o is e
G u a r d r in g
B e c a u s e R _ P s u b i s la r g e r t h a n R _ P W , N T _ N i s b e t t e r
t h a n P W in t h e n o i s e i s o l a t i o n .
Figure 7.3.4.1.2 Example of NT_N layeras a high resistance region
best b e tte r poor

(if p a d lim ite d )
Vdd
Vdd1 N o is y N o is y Vdd N o is y
Vss c ir c u it
c ir c u it c ir c u it
Vss1 Vss
Vdd Vss
N o is y N o is y N o is y
Vdd2 s e n s it iv e s e n s it iv e s e n s it iv e
c ir c u it c ir c u it c ir c u it
Vss2
I/O p a d I/O p a d
I/O p a d
Figure 7.3.4.1.4 Example of separated power supplies and ground buses for the noisy and sensitive
circuit
7.3.4.2 Signal
AN.R.30mgU Keep high frequency signal in high level metal layer.
AN.R.31mgU Use metal shield for victim line that is noise sensitive.
Use metal and poly shield for attacker line that travels through long
AN.R.32mgU
distance.
Prevent from feedback path through chip seal-ring between critical input
AN.R.33mgU and output. Use additional guard ring to isolate the coupling. (Figure
7.3.4.2.1)
F e e d b a c k P a th
S e a l r in g
U s e a d d it io n a l g u a r d Vdd or
Vss
r in g t o is o la t e t h e
In p u t
c o u p lin g .
O u tp u t
O u tp u t
G u a r d r in g
Vdd or
Vss
S e a l r in g
Figure 7.3.4.2.1 Example of prevention from feedback path through chip seal ring
7.4 Burn-in Guidelines for Analog Circuits

For the sensitive circuit, e.g. differential input pair, which needs precise device
mismatching parameter control such as △ Vt and △ Isat, it must avoid
unbalanced DC bias stress during burn-in period.
AN.R.41mgU For example, VA=Vdd or GND and VB=1/2Vdd, which causes current supplied
from current source flowing differently on the differential input pair (IAIB). This
will make differential pair matching become worse after burn-in stress. (Figure
7.4.1)
Be sure that the analog circuit operates at normal operational condition during
burn-in.
AN.R.42mgU
For example, avoid P1 floating (when R is external) and make it be biased at the
normal condition during burn-in. (Figure 7.4.2)
With the protection diode connection in the sensitive circuit to reduce plasma
AN.R.43mgU
induced damage during wafer processing.
Circuit design with state-dependent floating-node must be taken care carefully.
Concern: Accidental over-stress of device may occur and damage or degrade
U the device.
AN.R.50mg For example: DNW/NW indirectly connects to power, and the substrate is biased
negatively. Please simulate to check for potential issues caused by inadvertent
floating wells, and revise design if necessary.
Recommended Floating PAD is not recommended; please add protection diode
to ground.
Floating PAD in the DRC:
FPAD.R.1m (1) {{Mtop OR UTM} INTERACT CB} don’t connect to OD for wire bond.
®U (2) {{Mtop OR UTM} INTERACT CBD} don’t connect to OD for flip chip without
RDL and flip chip with Cu-RDL.
(3) {{Mtop OR UTM} INTERACT RV} don’t connect to OD for flip chip with AP-
RDL.
V A
V B
IA IB
Figure 7.4.1 Example of differential input pair
-
P 1
P 2
P 3
Figure 7.4.2 Example of analog circuit
Figure Example of Floating PAD
8 Dummy Pattern rule and Filling Guideline

This chapter contains the following topics:
8.1 Dummy OD (DOD/SR_DOD) Rules and Guidelines
8.2 Dummy Poly (DPO/SR_DPO) Rules and Guidelines
8.3 Dummy TCD Rule and Filling Guideline
8.4 Dummy TCD Design Information
8.5 In Chip Overlay (ICOVL) Rule And Filling Guideline
8.6 Dummy Metal (DM) Rules
8.7 Dummy VIA (DVIAx) Rules
8.8 Dummy Pattern Fill Usage Summary
8.1 Dummy OD (DOD/SR_DOD) Rules and

Guidelines
1. In order to meet the extremely tight requirement in terms of process control for STI etch, polish,
OSE as well as channel length definition (inter-level dielectric (ILD) planarization), you must fill the
DOD/SR_DOD globally and uniformly even if the originally drawn OD already satisfies the required OD
density rules.
2. It is very important to use TSMC’s auto-fill utilities (documents: T-N45-CL-DR-001-C2 and T-N45-CL-
DR-001-H2).
． It is important to use the TSMC DOD/DPO utility, which will fill the SR_DOD/SR_DPO/DOD/DPO
correctly, to carefully control the OSE and PSE.
．It is important to perform the utility on the IP level, and the whole chip GDS level.
3. It is recommended to use filler cells with OD/PO to fill a large empty area in the standard-cell-based
block during the P&R stage. It is difficult for the current TSMC DOD/DPO utility to insert DOD shapes into
a standard-cell placed area. For higher PO and OD CD control requirements, it is suggested to layout both
OD and PO into a filler cell (treat OD/PO as a dummy filling, need to follow OD/PO and related rules, and
use the GDS layer of OD/PO).
4. Evaluate the impact on OD masks carefully when any one of the following layouts is revised:
 PO/ DPO/ SR_DPO
 NW/ ODBLK/ NWDMY/ LOGO/ INDDMY
5. Use the dummy layer ODBLK properly. This layer (CAD layer no. 150;20) tells the TSMC utility that the
area covered should be blocked from DOD/SR_DOD fill operations. ODBLK is for excluding DOD and
SR_DOD, not for excluding dummy Poly (DPO/SR_DPO).
6. It is suggested to make sure that the ODBLK layer covers sensitive circuits, such as:
 Pad areas for high frequency signals
 SRAM sensitive functional blocks and bit cell arrays
 Analog/RF circuits (DAC/ADC, PLL, Inductor) and so on
7. It is recommended to manually add DOD/SR_DOD uniformly inside regions covered by the ODBLK
layer, to gain better process window and electrical performance.
8. Don’t put DOD/SR_DOD in areas covered by the following marker layers:

 Well resistor under STI (NWDMY)
 Regions of chip corner stress relief pattern, seal ring, and CDU pattern
TSMC’s fill generation utility will not add DOD/SR_DOD into these regions, as these layers are well defined.
The ODBLK covered areas should not cover or overlap the above areas for DRC reasons.
9. Please refer to the “Dummy Pattern Fill Usage Summary” section in this chapter for additional
information.
8.1.1 DOD Layout Rules

DOD.W.1 Width A  0.5
DOD.S.1 Space B  0.4
DOD.S.2 Space to OD (Overlap is not allowed) C  0.34
DOD.S.3 Space to PO (Overlap is not allowed) D  0.3
DOD.S.5 Space to NW F  0.3
DOD.S.8 Space to NWDMY (Overlap is not allowed) I  0.6
DOD.EN.1 Enclosure by NW (Cut is not allowed) L  0.3
1. OD.DN.2/OD.DN.2.1/OD.DN.2.2 and OD.DN.3/OD.DN.3.1/OD.DN.3.2 are checked over any
window 150 μm x 150 μm, stepping 75 μm .
2. (outside OD2) means the overlapped width between the checking window and OD2 layer is
smaller than 37.5 μm.
3. For OD.DN.2/OD.DN.2.1/OD.DN.2.2/OD.DN.3/OD.DN.3.1/OD.DN.3.2, the following regions
can be excluded:
OD.DN.0
- NWDMY/LOGO/INDDMY/INDDMY_MD
- Chip corner stress relief and seal-ring
4. OD.DN.2/OD.DN.2.1/OD.DN.2.2 are applied when the width of (checking window NOT the item
3) is  37.5 μm.
5. OD.DN.3/OD.DN.3.1/OD.DN.3.2 must be followed for every defined ODBLK region. This rule is
only applied when the width of ((checking window AND ODBLK) NOT item 3) is  37.5 μm.
OD.DN.1 Minimum {OD OR DOD OR SR_DOD} density across full chip  25%
OD.DN.1.1 Maximum {OD OR DOD OR SR_DOD} density across full chip  75%
OD.DN.2 Minimum {OD OR DOD OR SR_DOD} local density (window 150μm x 150 μm, stepping 75 μm)  20%
Maximum {OD OR DOD OR SR_DOD} local density [OUTSIDE OD2] (window 150 μm x 150 μm,
OD.DN.2.1  80%
stepping 75 μm)
OD.DN.2.2 Maximum {OD OR DOD OR SR_DOD} local density (window 150 μm x 150 μm, stepping 75 μm)  90%
Minimum {OD OR DOD OR SR_DOD} local density inside ODBLK (window 150 μm x 150 μm,
OD.DN.3  20%
stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density inside ODBLK [OUTSIDE OD2] (window 150
OD.DN.3.1  80%
μm x 150 μm, stepping 75 μm)
Maximum {OD OR DOD OR SR_DOD} local density inside ODBLK (window 150 μm x 150 μm,
OD.DN.3.2  90%
stepping 75 μm)
IND.DN.8® Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY  20%
IND_MD.DN.8® Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY_MD  20%
DOD is a must. DOD CAD layer (TSMC default, 6;1) must be different from OD’s. Please refer to
DOD.R.1
section 8.1.
DOD inside chip corner stress relief area is not allowed [except seal-ring and stress relief patterns
DOD.R.2
drawn by customers].
DOD.R.3 Only square (or rectangular) and solid shapes are allowed. A 45-degree shape is not allowed.
DOD.S.2gU Recommended space to OD (C = 0.6)
DOD
NW DM Y
I NW
P F
D
O DO D L DO D
A
O D B
DO D DO D
8.1.2 SR_DOD Layout Rules

SR_DOD (CAD layer: 6;7) is used for dummy OD. It is a tape-out required layer and will be OPC treatment.
It is very important to use TSMC dummy utility to insert SR_DOD and SR_DPO around your IP, to close your
silicon performance with simulation result.
SR_DOD (CAD layer: 6;7) is not allowed to form device (MOS, RF, VAR, BJT, resistor, diode…).
SR_DOD.W.1 Width A  0.1
SR_DOD.W.2 Maximum width A 0.5
SR_DOD.S.1 Space B  0.12
SR_DOD.S.1.1 Space to OD, DOD (Overlap is not allowed) C  0.12
SR_DOD.S.2 Space to PO (Overlap is not allowed) D  0.05
SR_DOD.S.3 Space to DPO, SR_DPO (Overlap is not allowed) E  0.03
SR_DOD.S.3® Recommended space to DPO, SR_DPO E  0.05
SR_DOD.S.4 Space to 45-degree bent OD F  0.17
SR_DOD.S.7 Space to NW (for both core and I/O) G  0.08
SR_DOD.S.8 Space to NWDMY (Overlap is not allowed) H  0.6
SR_DOD.S.9 Space to LOGO (Overlap is not allowed) I  0
SR_DOD.S.11 Space to NT_N (Overlap is not allowed) K  0.14
SR_DOD.EN.1 NW enclosure of SR_DOD (for both core and I/O) L  0.08
SR_DOD.A.1 Area N  0.05
SR_DOD.L.1 Length O  0.5
SR_DOD.L.2 Maximum length O 10
SR_DOD.R.1 45-degree bent SR_DOD is not allowed
SR_DOD.R.2 Overlap of CO is not allowed.
SR_DOD.R.3 Only rectangle is allowed
It is important to use the TSMC DOD/DPO utility to insert SR_DOD
SR_DOD.R.4gU surrounding and close to the target device before characterization. The
range of the SR_DOD  4um.
Recommended minimum SR_DOD density inside {((((((OD OR PO)
INTERACT GATE) SIZING 2.5um) NOT ((OD OR PO) SIZING 0.4um))
SR_DOD.DN.1®  8%
NOT SRAMDMY;0) NOT OD2)} (The GATE doesn't include the regions
covered by layer TCDDMY, CSRDMY, CDUDMY)
SR_DOD
SR _D PO SR _D PO SR _D PO PO PO PO SR _D PO SR _D PO SR _D PO PO
(1 7 ;7 ) (1 7 ;7 ) (1 7 ;7 ) (1 7 ;7 ) (1 7 ;7 ) (1 7 ;7 ) (1 7 ;0 )
(1 7 ;0 ) (1 7 ;0 ) (1 7 ;0 )
A C
SR _D O D
SR_D O D SR _D O D SR _D O D
B
SR_D O D
OD
(6 ;0 )
E
C
E
D
DPO
DOD
(1 7 ;1 )
(6 ;1 )
SR_D O D
NW DM Y LO G O
H
F O
SR_DO D
OD SR_D O D
SR _D O D NT_N
NW
SR_DO D G L SR _D O D
SR_D O D
SR_DO D
OD2
NW DM Y LOGO
SR_DO D G L SR _D O D
SR _D O D
SR_D O D
IN D D M Y NT_N
CO
SR _D O D
S R _ D O D .R .1
O D, DO D, PO , SR_DPO
SR_DO D
SR_DO D
S R _ D O D .R .2
S R _ D O D .R .3
8.2 Dummy Poly (DPO/SR_DPO) Rules and

Guidelines
1. Good Poly uniformity is the key to meet the PO CD as well as circuit performance requirement. You
must fill the DPO/SR_DPO globally and uniformly even if the original drawn poly already satisfies the
required poly density rules. The designer may wish to add dummy poly to improve the stability of the poly
line dimension on silicon.
2. It is very important to use TSMC’s auto-fill utilities (documents T-N45-CL-DR-001-C2 and T-N45-CL-
DR-001-H2).
． It is important to use the TSMC DOD/DPO utility, which will fill the SR_DOD/SR_DPO/DOD/DPO
correctly, to carefully control the OSE and PSE.
．It is important to perform the utility on the IP level, and the whole chip GDS level.
3. It is recommended to use filler cells with OD/PO to fill a large empty area in the standard-cell-based
block during the P&R stage. It is difficult for the current TSMC DOD/DPO utility to insert DOD shapes into
a standard-cell placed area. For higher PO and OD CD control requirements, it is suggested to layout both
OD and PO into a filler cell (treat OD/PO as a dummy filling, need to follow OD/PO and related rules, and
use the GDS layer of OD/PO).
4. Evaluate the impact on the poly mask carefully when any one of the following layouts is revised:
 OD/DOD/SR_DOD
 POBLK/LOGO/INDDMY
5. Use the dummy layer POBLK properly. This layer (CAD layer no. 150;21) tells the TSMC utility that the
area covered should be blocked from DPO/SR_DPO fill operations. POBLK is for excluding DPO and
SR_DPO, not for excluding dummy OD (DOD/SR_DOD).
6. It is suggested to make sure that the POBLK layer covers sensitive circuits, such as:
a. Pad areas for high frequency signals
b. SRAM sensitive functional blocks and bit cell arrays
c. Analog/RF circuits (DAC/ADC, PLL, Inductor) and so on
7. It is recommended to manually add DPO/SR_DPO uniformly inside regions covered by the dummy
fill blocking layer POBLK, to gain better process window and electrical performance.
8. Don’t put DPO/SR_DPO in areas covered by the following marker layers to avoid DRC problems.
 Regions of chip corner stress relief pattern, seal ring, and CDU pattern
TSMC’s fill generation utility will not add DPO/SR_DPO into these regions because these layers are well
defined.
The POBLK covered areas should not cover or overlap the above areas for DRC reasons.
information.
8.2.1 DPO Layout Rules

DPO.W.1 Width A  0.4
DPO.S.1 Space B  0.3
DPO.S.2 Space to OD (Overlap is not allowed) C  0.2
DPO.S.3 Space to (PO OR SR_DPO) (Overlap is not allowed) D  0.5
PO.DN.1 Minimum {(PO OR DPO) OR SR_DPO} density across full chip  14%
PO.DN.1.1 Maximum {(PO OR DPO) OR SR_DPO} density across full chip  40%
{OD OR DOD OR SR_DOD OR PO OR DPO OR SR_DPO} local density
1. PO.DN.2 is checked by window 20 μm x 20 μm, stepping 10 μm.
2. For PO.DN.2 rules, the following regions can be excluded:
(1) ODBLK/POBLK/NWDMY/LOGO/INDDMY/INDDMY_MD as default
(2) Chip corner stress relief area if seal-ring and stress relief pattern added
PO.DN.2  0.1%
by TSMC.
3. Even in areas covered by {ODBLK OR POBLK}, this pattern density that
follows the PO.DN.2 rules is recommended.
4. The rule is applied when the width of (checking window NOT item 2) is  5
μm.
IND.DN.9® Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY  15%
IND_MD.DN.9
Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY_MD  15%
®
DPO is a must. DPO CAD layer (TSMC default, 17;1) must be a different layer
DPO.R.1
from the PO CAD layer. Please refer to section 8.2.
DPO inside chip corner stress relief area is not allowed [except seal-ring and
DPO.R.2
stress relief patterns drawn by customers].
Only square (or rectangular) and solid shapes are allowed. A 45-degree shape
DPO.R.3
is not allowed.
DPO.S.3g U Recommended space to PO (D = 0.5).
DPO.R.4gU DPO cut DOD is not recommended
DPO
DPO
D A DPO
PO B
OD
8.2.2 SR_DPO Layout Rules

SR_DPO (CAD layer: 17;7) is used for dummy poly. It is a tape-out required layer and will be OPC treatment.
It is very important to use TSMC dummy utility to insert SR_DOD and SR_DPO around your IP, to close your
silicon performance with simulation result.
SR_DPO.W.1 Width A  0.04
SR_DPO.W.2 Width in OD2 B  0.1
Width of 45-degree dummy PO. (Please make sure the vertex of 45-degree pattern is on 0.005 μm grid (refer
SR_DPO.W.6 C  0.17
to the rule, G.6U, in section 3.7))
SR_DPO.S.1 Space to {PO OR SR_DPO} (SR_DPO overlap with PO is not allowed) D  0.1
SR_DPO.S.1® Recommended space to {PO OR SR_DPO} (SR_DPO overlap with PO is not allowed) D  0.12
The SR_DPO (17;7) gate space to other gate (17;0 OR 17;7), SR_DPO (17;7) only can be used for dummy
SR_DPO.S.2 E  0.14
patterns.
SR_DPO.S.3 {((PO OR SR_DPO) AND OD) inside OD2} space in the same OD F  0.22
SR_DPO.S.4 Space to OD G  0.03
SR_DPO.S.9 Space of {(PO OR SR_DPO) AND RPO} H  0.18
SR_DPO.S.16 Space to 45-degree bent {PO OR SR_DPO} I  0.17
SR_DPO.S.17 {CO inside SR_DPO} space to OD J  0.05
SR_DPO.S.18 {SR_DPO AND OD} space to RPO (overlap is not allowed.) K  0.38
SR_DPO.S.19 {SR_DPO AND OD} space to CO (overlap is not allowed.) L  0.04
SR_DPO.S.20 {CO inside OD} space to 1.8V, 2.5V, 3.3V {SR_DPO AND OD} M  0.08
SR_DPO.EN.1 Enclosure of CO N  0.01
SR_DPO.EN.2 Enclosure of CO [at least two opposite sides] O  0.02
SR_DPO.EX.1 Extension on OD (end-cap) P  0.09
SR_DPO.EX.2 OD extension on SR_DPO Q  0.03
SR_DPO.L.1® Recommended length R  0.5
SR_DPO.L.2 Length of 45-degree bent SR_DPO (minimum edge length) S  0.26
SR_DPO.L.3® Recommended maximum Length R  10
SR_DPO.A.1 Area (This check doesn’t include rectangle area with length  0.3 μm) T  0.022
SR_DPO.A.2 Area [with all of edge length < 0.21 μm] T  0.055
SR_DPO.A.3 Enclosed area U  0.04
SR_DPO.A.4 Enclosed area [with all of inner edge length < 0.21 μm] U  0.077
{SR_DPO AND OD} must be a rectangle orthogonal to grid. (Both bent GATE and GATE with jogs are not
SR_DPO.R.1
allowed).
SR_DPO.R.2U SR_DPO line-end must be rectangular. Other shapes are not allowed.
SR_DPO.R.4 SR_DPO intersecting OD must form two or more diffusions. (except MOMDMY (155;21) region)
SR_DPO.R.5 Overlap of SRAM is not allowed
SR_DPO(17;7) can not form device, SR_DPO must be placed beside OD edge. (except MOMDMY (155;21)
SR_DPO.R.6
region).
Recommended minimum SR_DPO density inside {((((((OD OR PO) INTERACT GATE) SIZING 2.5um) NOT
SR_DPO.DN.1® ((OD OR PO) SIZING 0.4um)) NOT SRAMDMY;0) NOT OD2)} (The GATE doesn't include the regions  4%
covered by layer TCDDMY, CSRDMY, CDUDMY)
SR_DPO
OD2
SR_DPO SR_DPO PO SR_DPO SR_DPO
(17;7) (17;7) (17;0) (17;7) (17;7) SR_DPO SR_DPO SR_DPO PO
SR_DPO SR_DPO PO SR_DPO SR_DPO (17;7) (17;7) (17;7) (17;0)
OD (17;7) (17;7) (17;0) (17;7) (17;7)
(6;0)
E E
G OD D
A D
F F (6;0) A
B
SR_DPO.S.19
SR_DPO
SR_DPO SR_DPO SR_DPO PO
(17;7) (17;7) (17;7)
(17;0)
I C
H
SR_DPO OR PO
SR_DPO SR_DPO
H H
OD
L
RPO
Q
N P
O OD2
SR_DPO
SR_DPO
U OD
T
PO M
SR_DPO
SR_DPO
SR_DPO
OD SR_DPO
RPO
K RPO
SR_DPO
J OD
SR_DPO
OD
SR_DPO.R.6
Case-1 Case-2
PO PO
SR_DPO SR_DPO SR_DPO GATE SR_DPO
GATE
OD OD
Allowed Not Allowed
8.3 Dummy TCD Rule and Filling Guideline

8.3.1 Dummy TCD Rules
1. In order to meet the extremely tight requirement in terms of process control for Poly CD, the Dummy
TCD is required within a 2mmX2mm area. If there is not enough space to insert one Dummy TCD for
each 2mmx2mm due to pattern layout, please must ensure the density of Dummy TCD should reach
50%(DTCD.DN.2) in whole chip level.
2. There are two methods to generate dummy TCD. One is the P&R, and another is TSMC’s auto-fill utilities
(documents: T-N45-CL-DR-001-X2): It is important to perform the utility on the whole chip GDS. It is not
recommended to perform the utility only on a single IP.
3. For cyber shuttle case, the gate direction in dummy TCD(TCDDMY_H/ TCDDMY_V) must align to gate
direction in SRAM (DTCD.R.5). For non-cyber-shuttle case, it is no need to align to gate direction in SRAM,
but if possible, recommend to follow gate direction in SRAM.
 For P&R: Please refer to section 8.4.
 For auto-fill dummy utility: There is an utility option, VERTICAL_TCD_PATTERN, to control gate
direction is vertical or horizontal in dummy TCD. The option is default on, and the gate direction of
dummy TCD will be vertical. If this option is turned off, the horizontal gate direction will be generated.
4. Do not rotate or mirror the dummy TCD cell (TCDDMY_H/ TCDDMY_V) except you would like to align gate
direction to SRAM and you can rotate it with clockwise 90 degree and no mirror(DTCD.R.4).
5. Evaluate the impact on OD/NW/PW/NPO/PO/VTL_N/VTL_P/NSSD/NLDD/ PLDD/P+/N+/NILD/PILD/
SSMT masks carefully when any one of the following layouts is revised:
 PO/OD/NP/PP/NW
6. Use the dummy layer POBLK/ODBLK properly. These layers (CAD layer no. 150;20/150;21) tell the
TSMC utility that the area covered should be blocked from Dummy TCD fill operations.
If you do not use TSMC’s dummy utility, please ask for the dummy TCD layout and insert it in your
design flow:
 It is suggested to make sure that the POBLK/ODBLK layer covers sensitive circuits.
 TCDDMY overlaps DOD, SR_DOD, DPO, SR_DPO, OD2, DCO, NT_N, POFUSE, RPO, RH, VAR,
VTH_P, VTH_N, VTL_P, VTL_N, SRM, SRAMDMY, INDDMY, LOGO, BJTDMY, or MOMDMY which is
not allowed.
TCDDMY (CAD layer no: 165;1) relative rules

DTCD.W.1 Width of {(TCDDMY NOT TCDDMY_H) NOT TCDDMY_V} A = 12, 24, 9.245
Channel width of gate inside {(TCDDMY NOT TCDDMY_H) NOT
DTCD.W.2 = 5, 4, 0.43
TCDDMY_V}
DTCD.W.3 Channel length of gate inside TCDDMY = 0.04
Space of poly gate in the same OD inside {(TCDDMY NOT
DTCD.S.1 = 0.14
TCDDMY_H) NOT TCDDMY_V}
Density of DummyTCD (window 2000 μm X 2000 μm is one unit, see
DTCD.DN.1® B  70%
next page for more information)
Density of DummyTCD (window 2000 μm X 2000 μm is one unit, see
DTCD.DN.2 B  50%
next page for more information)
DTCD.R.1 TCDDMY should contain OD/PO/PP/NP/POBLK/ODBLK layer
TCDDMY overlap of DOD, SR_DOD, DPO, SR_DPO, OD2, DCO,
OD_12, NT_N, POFUSE, RPO, RH, VAR, VTH_P, VTH_N, VTL_P,
DTCD.R.2
VTL_N, HVD_N, HVD_P, SRM, SRAMDMY, INDDMY, BJTDMY, or
MOMDMY is not allowed.
TCDDMY (165;1) is a must for any DummyTCD cell.
1. It can waive PO.DN.3, OD.W.2.1GS, OD.W.2.2GS, OD.W.1® , ,
DTCD.R.3 DNW.S.2, PO.EX.2® , OD.S.1® , PO.S.1® , PO.S.6® , PO.EX.1® ,
PO.S.18.GS® , DOD.R.4® , SR_DOD.DN.1® , SR_DPO.DN.1® and
NW.R.1g.
TCDDMY_H/ TCDDMY_V (CAD layer no: 165;4/165;5) relative rules

DTCD.W.1.1 Dimension of TCDDMY_H A’ = 5.71X3.57
DTCD.W.1.2 Dimension of TCDDMY_V A” = 3.6X6.33
DTCD.W.2.1 Channel width of gate inside TCDDMY_H or TCDDMY_V C’ = 2.4, 0.41, 0.31
Gate space to neighboring poly inside TCDDMY_H or TCDDMY_V
DTCD.S.1.1 D’ = 0.14 or 0.2
[channel width <2.0um]
Gate space to neighboring poly inside TCDDMY_H or TCDDMY_V
DTCD.S.1.2 D = 0.14
[channel width ≥ 2.0um]
TCDDMY_H/ TCDDMY_V must keep block orientation as the
following one of two conditions:
a. No rotation, and no mirror in X, Y direction (DRC option:
VERTICAL_TCD_PATTERN is on by default.)
b. Rotated clockwise 90 degree, and no mirror in X, Y direction. (must
DTCD.R.4
turn off DRC option: VERTICAL_TCD_PATTERN)
Rotated clockwise 90 degree, need to align to SRAM gate direction.
Please refer to DTCD.R.5.
DRC will check relative coordinates of three alignment marks with
squre PO (0.5um x 0.5um) in the TCDDMY_H/ TCDDMY_V.
Poly gates in TCDDMY_H/ TCDDMY_V are uni-directional with gates
in SRAM (50;0 OR 186;0) in a chip for cyber shuttle. (must turn on
DTCD.R.5 DRC option: CYBER_SHUTTLE)
(This check does not include the regions covered by layer
RODMY(49;0) and RAM1TDMY (160;0))
Poly gates in TCDDMY_H/ TCDDMY_V are uni-directional in a whole
DTCD.R.6
chip level.
A”
D’
( C A D la y e r : 1 6 5 ; 5 )
TCDDM Y_V
A’ D D’
C’
TCDDM Y_H 6 .3 3 D
3 .5 7 C /C ’
( C A D la y e r : 1 6 5 ; 4 )
C’
5 .7 1 D’
3 .6 D’
SR D O D / D O D / N T_N / O D 2/ D C O / O D _12/ D PO / SR D PO /
TCDDMY V T H _ N / V T H _ P / V T L_N / V T L _ P / R P O / VA R / R H / B JT D M Y /
PO FUSE/ SRM / SRAM DM Y / HVD_N/ HVD_P / M O M DM Y/
IN D D M Y / L O G O
D T C D .R .4
A’ A”
( C A D la y e r : 1 6 5 ; 5 )
TCDDM Y_V
TCDDM Y_H
( C A D la y e r : 1 6 5 ; 4 )
3 .5 7
6 .3 3
5 .7 1
o
o 90
90
3 .6
o
90
o 90
3 .5 7
( C A D la y e r : 1 6 5 ; 4 )
TCDDM Y_H
( C A D la y e r : 1 6 5 ; 4 )
6 .3 3
( C A D la y e r : 1 6 5 ; 5 )
TCDDM Y_H
5 .7 1
A’ TC D D M Y_V
5 .7 1 A” TCDDM Y_V 3 .6
A’ 3 .6 A”
( C A D la y e r : 1 6 5 ; 5 )
6 .3 3
3 .5 7
O O
Dummy TCD
Example for B value calculation
Chip size = 16.5 X 14 mm (8 units X 7 units)
8.3.2 Dummy TCD layout Summary

1. The Dummy TCD cell should include layers as below.
Square Horizontal Vertical
Layer CAD layer
dummy TCD dummy TCD dummy TCD
Cell size (um) 12X12 5.71X3.57 3.6X6.33
OD 6;0 V V V
NW 3;0 V V V
Poly (PO) 17;0 V V V
PP 25;0 V V V
NP 26;0 V V V
* Cell boundarya 108;0 V V V
*IPb 63;63 - V V
* OD block (ODBLK) 150;20 V V V
* PO block (POBLK) 150;21 V V V
* TCDDMY 165;1 V V V
* TCDDMY_H 165;4 - V -
* TCDDMY_V 165;5 - - V
* : To follow cell size for cell boundary/OD block /PO block/TCDDMY/ TCDDMY_H/ TCDDMY_V
a: Cell boundary is used during the P&R stage that do not generate by dummy utility.
b : It is for IP tagging layer that do not generate by dummy utility.
2. The Dummy TCD cell can abut on the main circuit.
8.4 Dummy TCD Design Information

8.4.1 Overview
This chapter provides the dummy TCD macro insertion methodology.
Dummy TCD insertion is an implementation approach to improve IDU (Intra-Die uniformity) for designs.
Inserting dummy TCD in the chip design planning stage to meet design guidelines, like even distribution, is
recommended. Post-route dummy TCD insertion is only supplemental for uniform distribution improvement.
 Two types of dummy TCD macros are given:
 Horizontal type macro -> 5.71um x 3.57um
 Vertical type macro -> 3.6um x 6.33um
 Both dummy macros are with vertical poly direction
 Choosing either V type or H type would be fine within a window:
For example, one possible scenario could be
 Select H type for insertion first for all windows
 Adjust dummy macro placement incrementally and swap H type to V type when floorplan environment is
more suitable for V type in some window
8.4.2 Design Consideration of Dummy TCD Insertion

 In order to reduce area and timing penalty, dummy TCD macros could be placed in the following areas
first
1. Channel between core, IO, analog IPs
2. Channel between blocks
3. Digital block corner area
4. Channel between core, SRAMs
 It is recommended considering dummy TCD insertion at top level during chip floorplan.
 If dummy TCD inserted in large blocks or circuit IP (~2000umX2000um), please be aware of the
followings.
1. Consistent TCD orientation in whole chip.
2. It’s not allowed to have individual TCD rotation and mirror in X, Y.
3. Placing TCD at least 75um away from block boundary could meet 150um spacing recommendation.
8.4.3 Dummy TCD Macro Placement

 Minimize dummy macro electrical impact to main pattern circuits like std cell, SRAM, analog IP by
either one of the approaches as below.
 Reserve 2μm space around dummy TCD by placement blockage as Fig 1., to let DPO/DOD utility
insert dummy OD/dummy PO.
 If you do not generate the dummy TCD by tsmc’s dummy OD/PO utility, use std cell fillers size ≥
0.4μm to surround dummy macros as Fig 2
 Dummy TCD contain 2 different types, V and H, your can select one type to insert into window.
 Dummy TCD V and H cannot overlap but it can use V or H simultaneously when insert to different
window.
 Dummy TCD could not overlap with any standard cell, macro, or IPs.
 Dummy TCD is physical only cell, and it doesn’t need to connect power supply.
Placement blockage
Dummy TCD macro

Std cell filler Dummy TCD macro
FILL3
2um
Fig.1 Fig.2
8.4.4 P&R Dummy TCD Rule Check

 Dummy TCD P&R reference utility provided by TSMC could have a summary report for percentage
of window with dummy TCD.
 P&R reference utility could highlight windows without dummy TCD macros in GUI.
 For dummy TCD P&R rule reference utility, please refer to N40 DFM Implementation Flow package.
8.4.5 Dummy TCD Macros Insertion Flow

IO/analog/SRAM
Macro placement
Power Plan
Consider dummy
ICOVL Insertion insertion
in a chip globally
before hierarchical chip
Floorplan Dummy TCD insertion block partition.
stages
conventional Block partition
Dummy pattern
Insertion related Place and Route
Tape-out GDS Dummy TCD could be inserted

by DM utility on GDS.
8.4.6 TCD Library Kits

 Dummy TCD GDSII files
 DMY_TCD_H_20100305.gds
 DMY_TCD_V_20100305.gds
 P&R implementation kits
 LEF macro for dummy TCD
 lef/DMY_TCD_H_20100305.lef
 lef/DMY_TCD_V_20100305.lef
 Milkyway library for dummy TCD
 milkway/DMY_TCD_H_20100305/
 milkway/DMY_TCD_V_20100305/
 Volcano library for dummy TCD
 volcano/DMY_TCD_H_20100305/
 volcano/DMY_TCD_V_20100305/
8.5 In Chip Overlay (ICOVL) Rule And Filling

Guideline
8.5.1 In Chip Overlay (ICOVL) Rules
 2 kinds of 36.7um x36.7um square in chip overlays are offered: OVL_PO_OD and OVL_CO_PO.
 OVL_PO_OD = ICOVL NOT INTERACT CO
 OVL_CO_PO = ICOVL INTERACT CO
 ICOVL (CAD layer no.: 165;3) is must for in chip overlay.
 Two folders are including in tarball (file name: N40_OVL_library_kits.tar.gz): (1) P&R physical library for
ICOVL and (2) gds.
 Total 4 gds files are provided: two single ICOVLs (OVL_PO_OD and OVL_CO_PO) and 2 Combo ICOVLs
(OVL_PO_OD_CO_PO_H and OVL_PO_OD_CO_PO_V).
 OVL_PO_OD: OVL_PO_OD_N40_20101210.gds
 OVL_CO_PO: OVL_CO_PO_N40_20101210.gds
 OVL_PO_OD_CO_PO_H: OVL_PO_OD_CO_PO_H_N40_20101210.gds
 OVL_PO_OD_CO_PO_V: OVL_PO_OD_CO_PO_V_N40_20101210.gds
S in g le IC O V L C o m b o IC O V L
O VL_PO _O D O VL_CO _PO O VL_PO _O D_C O _PO _V O VL_PO _O D_C O _PO _H
3 6 .7 u m
40um
3 6 .7 u m
1 1 3 .4 u m
40um 1 1 3 .4 u m
 OVL_PO_OD and OVL_CO_PO ICOVL can be used individually or combined with 40um spacing as 36.7um
X113.4um or 113.4umX36.7um rectangular in chip overlays.
 There are two ICOVL guidelines in chip rotation: Floorplan A and Floorplan B.
 Terminologies for 1X1die, 1X2die, 2X1 die and 2X2 die (The following dimensions are before shrink):
 Floorplan A for N45GS(=N40G)/N40LP/N40LPG:
1. 1X1 die size: 14.31mm < X and 18.24mm < Y
2. 1X2 die size: 14.31mm < X and 12.13mm < Y  18.24mm
3. 2X1 die size: 9.51mm < X  14.31mm and 18.24mm < Y
4. 2X2 die size: 9.51mm < X  14.31mm and 12.13mm < Y  18.24mm
 Floorplan B for N45GS(=N40G)/N40LP/N40LPG:
 Floorplan A for N45LP/N45LPG:

3. 2X1 die size: 8.56mm < X  12.88mm and 16.42mm< Y
4. 2X2 die size: 8.56mm < X  12.88mm and 10.92mm< Y  16.42mm
 Floorplan B for N45LP/N45LPG:
 In general, you need to follow ICOVL floorplan A.
 If you know your tapeout will be rotated in tsmc, need to follow ICOVL floorplan B.
 Because when you request to rotate your chip, tsmc EBO will do anti-clockwise 90 degree for mask making.
 Please refer to ICOVL.R.3® U ~ ICOVL.R.6® U for floorplan A and B.
ICOVL.S.1® Recommend OVL_PO_OD space to OVL_CO_PO A  40
ICOVL.S.2® Recommend space between two OVL_PO_ODs or two OVL_CO_POs A’  2000
ICOVL.S.3® Recommend ICOVL (CAD layer no.: 165;3) space to {(OD OR PO) OR CO} B  2
ICOVL.S.4® Recommend enclosed OD space inside OVL_PO_OD (maximum = minimum) D = 1.1
ICOVL.S.5® Recommend space between two COs for OVL_CO_PO [in the same ring] E = 0.10
ICOVL.W.1® Recommend width of PO ring inside ICOVL (maximum = minimum) F = 1.1
ICOVL.W.2® Recommend width of M1 ring inside OVL_CO_PO (maximum = minimum) G = 1.1
ICOVL.W.3® Recommend width of CO inside OVL_CO_PO (maximum = minimum) H = 0.17
ICOVL.W.4® Recommend width of {OD INTERACT PO} inside OVL_PO_OD (maximum = minimum) I = 16.5
ICOVL.W.5® Recommend PO hole width inside OVL_CO_PO (maximum = minimum) J = 16.5
ICOVL.EN.1® Recommend {OD INTERACT PO} enclosure by PO inside OVL_PO_OD (maximum = minimum) K = 3.3
ICOVL.EN.2® Recommend M1 ring enclosure by PO ring inside OVL_CO_PO (maximum = minimum) L = 3.92
ICOVL is must for any ICOVL cell. It can waive:
ICOVL.R.1
OD.W.2.2GS, PO.DN.3, PO.R.1, RPO.S.3, RPO.S.4, CO.W.1.
ICOVL.R.2® U Recommend the ICOVL patterns should be as uniform as possible over the chip
Recommend at least 2 OVL_PO_ODs on top row (Floorplan A)/ right row (Floorplan B) by
ICOVL.R.3® U (1) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 8 segments for 1X1 die
(2) Dividing chip Y (Floorplan A) / X (Floorplan B) direction into 4 segments for 1X2 die
Recommend at least 2 OVL_CO_POs on top row (Floorplan A)/ right row (Floorplan B) by
Recommend at least 1 OVL_PO_ODs on top row (Floorplan A)/ right row (Floorplan B) by dividing chip Y
ICOVL.R.5® U
(Floorplan A) / X (Floorplan B) direction into 8 segments for 2X1 die
Recommend at least 1 OVL_CO_POs on top row (Floorplan A)/ right row (Floorplan B) by dividing chip Y
ICOVL.R.6® U
(Floorplan A) / X (Floorplan B) direction into 8 segments for chip size for 2X1 die
ICOVL.R.7® Recommend at least 8 OVL_PO_ODs and 8 OVL_CO_POs for 1X1 die
ICOVL.R.8® Recommend at least 4 OVL_PO_ODs and 4 OVL_CO_POs for 1X2 die or 2X1 die
ICOVL.R.9® Recommend only one polygon is allowed in one chip for 1X1 die by {OVL_PO_OD SIZING +6500um}
ICOVL.R.10® Recommend only one polygon is allowed in one chip for 1X1 die by {OVL_CO_PO SIZING +6500um}
ICOVL.R.11® Recommend only one polygon is allowed in one chip 1X2 die or 2X1 die by {OVL_PO_OD SIZING +8000um}
ICOVL.R.12® Recommend only one polygon is allowed in one chip 1X2 die or 2X1 die by {OVL_CO_PO SIZING +8000um}
Recommend empty space between two OVL_PO_ODs for 1X1 die. DRC flags:
ICOVL.R.13®  16000
{((Chip NOT OVL_PO_OD) SIZING -8000μm) SIZING +8000μm}
Recommend empty space between two OVL_CO_POs for 1X1 die. DRC flags:
ICOVL.R.14®  16000
{((Chip NOT OVL_CO_PO) SIZING -8000μm) SIZING +8000μm}
Recommend empty space between two OVL_PO_ODs for 1X2 die or 2X1 die.
ICOVL.R.15®  13000
DRC flags: {((Chip NOT OVL_PO_OD) SIZING -6500μm) SIZING +6500μm}
Recommend empty space between two OVL_CO_POs for 1X2 die or 2X1 die.
ICOVL.R.16®  13000
DRC flags: {((Chip NOT OVL_CO_PO) SIZING -6500μm) SIZING +6500μm}
ICOVL.R.17® Recommend density of {(OVL_PO_OD SIZING +16500um) SIZING -15500um} for 1X1 die  25%
ICOVL.R.18® Recommend density of {(OVL_CO_PO SIZING +16500um) SIZING -15500um} for 1X1 die  25%
ICOVL.R.19® Recommend density of {(OVL_PO_OD SIZING +13000um) SIZING -10000um} for 1X2 die or 2X1 die  25%
ICOVL.R.20® Recommend density of {(OVL_CO_PO SIZING +13000um) SIZING -10000um} for 1X2 die or 2X1 die  25%
ICOVL.R.21® Recommend at least 1 OVL_PO_OD fully inside {Chip SIZING -2380um} for 2X2 die
ICOVL.R.22® Recommend at least 1 OVL_CO_PO fully inside {Chip SIZING -2380um} for 2X2 die
S in g le IC O V L
B
CO
A
B
B
OD
PO
M 1 r in g
M e ta l r o u tin g c o u ld b e a c r o s s O V L _ C O _ P O a n d O V L _ P O _ O D
b u t M 1 n e e d s to d e to u r a r o u n d M 1 r in g (O V L _ C O _ P O )
C o m b o IC O V L s C o m b o IC O V L to S in g le IC O V L s
A’
A
A A’ A
A’ A
O VL_PO _O D
K
PO
K D
F
O VL_C O _PO
E
H
M1 PO
G J
U U
IC O V L .R .3 ® a n d IC O V L .R .4 ®
1 X 1 d ie in a r e tic le : A t le a s t 8 O V L _ P O _ O D s 1 X 2 d ie in a r e tic le : A t le a s t 4 O V L _ P O _ O D s
a n d 8 O V L _ C O _ P O s in 1 d ie a n d 4 O V L _ C O _ P O s in 1 d ie
(1 ) A t le a s t 2 O V L _ P O _ O D s a n d a t le a s t 2 (1 ) A t le a s t 2 O V L _ P O _ O D s a n d a t le a s t 2
O V L _ C O _ P O s o n to p r o w b y d iv id in g c h ip O V L _ C O _ P O s o n to p r o w b y d iv id in g c h ip Y
Y d ir e c tio n in to 8 s e g m e n ts d ir e c tio n in to 4 s e g m e n ts
(2 ) P u t r e m a in in g 6 O V L _ P O _ O D s a n d 6 (2 ) P u t r e m a in in g 2 O V L _ P O _ O D s a n d 2
O V L _ C O _ P O s a s u n ifo r m a s p o s s ib le O V L _ C O _ P O s a s u n ifo r m a s p o s s ib le
F lo o r p la n A F lo o r p la n A
o o
R o ta te d c lo c k w is e 9 0 R o ta te d c lo c k w is e 9 0
F lo o r p la n B
F lo o r p la n B
ICOVL.R.5® U and ICOVL.R.6® U ICOVL.R.21® and ICOVL.R.22®

2X1 die in a reticle: At least 4 OVL_PO_ODs 2X2 die in a reticle: Select 1 of center 2X2
and 4 OVL_CO_POs in 1 die windows for ICOVL insertion
(1) At least 1 OVL_PO_ODs and at least 1 • At least 1 OVL_PO_ODs and 1 OVL_CO_POs
OVL_CO_POs on top row by dividing chip inside {Chip SIZING -2380um} for 2X2 Die
Y direction into 8 segments
(2) Put remaining 3 OVL_PO_ODs and 3
OVL_CO_POs as uniform as possible
Floorplan A
Floorplan A
2380 2380
2380 2380 2380 2380
2380 2380
2380 2380
2380 2380 2380 2380
2380 2380
Rotated clockwise 90o Rotated clockwise 90o

Floorplan B
Floorplan B
2380 2380
2380 2380
2380 2380
2380 2380
2380 2380
2380 2380
2380 2380
2380 2380
8.5.2 ICOVL layout Summary

1. The ICOVL cell should include layers as below.
OVL_PO_OD OVL_CO_PO OVL_PO_OD_CO_PO_H OVL_PO_OD_CO_PO_V
Layer CAD Layer
(single) (single) (combo) (combo)
Size (um) 36.7X36.7 36.7X36.7 113.4X36.7 36.7X113.4
IPb 63;63 V V V V
OD 6;0 V V V V
PO 17;0 V V V V
CO 30;0 - V V V
M1 31;0 - V V V
PP 25;0 V V V V
RPO 29;0 V V V V
*Cell boundarya 108;0 V V V V
DOD 6;1 V V V V
DPO 17;1 V V V V
DM1 31;1 - V V V
*DM1EXCL 150;1 - V V V
*OD block (ODBLK) 150;20 V V V V
*PO block (POBLK) 150;21 V V V V
*ICOVL 165;3 V V V V
* : To follow cell size for cell boundary/OD block /PO block/ DM1EXCL/ ICOVL
a
: Cell boundary is used during the P&R stage.
b: It is for IP tagging layer.
2. The in-chip OVL cell can neighbor on the main circuit.
8.5.3 N40 In-Chip OVL Marker Design Insertion

Methodology
8.5.3.1 Overview
Overlay (OVL) marker insertion is to reduce mask alignment errors by in-chip OVL marker pattern. In N40 technology, it is
very important to insert in-chip OVL (ICOVL) inside your chip for the big chip design (e.g. 1x1, 2x1, 1x2 and 2X2 in a
retile).
8.5.3.2 Combo ICOVL LEF, Placement and Routing

 To generate combo ICOVL LEF, create 2 OBS OVERLAP rectangles on top of OD/PO/CO markers on both sides (as
shown below)
 Cell could be placed inside combo ICOVL, in which area there is no OBS OVERLAP.
 Routing is legal to be across ICOVL when there is no M1 blockage.
 There are two ICOVL guidelines in chip rotation: Floorplan A and Floorplan B.
 In general, you need to follow ICOVL floorplan A.
 If you know your tapeout will be rotated in tsmc, need to follow ICOVL floorplan B.
 Because when you request to rotate your chip, tsmc EBO will do anti-clockwise 90 degree for mask making.
 Please refer to ICOVL.R.3® U ~ ICOVL.R.6® U for floorplan A and B.
8.5.3.3 Dummy Patterns Priority

 ICOVL marker priority is higher than TCD dummy for the big chip
 Combo ICOVL priority higher than single ICOVL, if room of a specific window in floorplan is enough. Combo ICOVL
could reduce insertion effort.
 Combo H or V types are of equal priority. Choose either one orientation, which is suitable for floorplan and with less
layout impact.
 Need to consider ICOVL insertion in chip level point of view, because insertion in block or IP might not be able to meet
uniformity requirement (please refer ICOVL.R.2® U ~ ICOVL.R.6® U, ICOVL.R.7® ~ ICOVL.R.8® , ICOVL.R.9® U ~
ICOVL.R.22® U).
8.5.3.4 Single ICOVL vs. Combo ICOVL
8.5.3.5 ICOVL Insertion Guidelines

Die size for mask 1X1 reticle 2X1 reticle 1X2 reticle 2X2 reticle
Window partition 8X8 4X8 8X4 -
Number of ICOVL
8® * 4® 4® 1®
required
Number of ICOVL on
2® 1® 2® 0
top row
*: 8 means 8 for PO_OD and another 8 for OD_CO.

 Select windows for ICOVL to achieve maximum ICOVL placement evenness. For die size for mask definitions, please
refer 1X1 die, 1X2 die, 2X1 die and 2X2 die terminologies in sec.8.5.1.
 In each window partition, choose either a set of single ICOVL (both OD/PO and OD/CO), or a combo ICOVL H or V.
 For 1X1 die, please refer ICOVL.R.2® U~4® U, ICOVL.R.7® , ICOVL.R.9® U, ICOVL.R.10® U, ICOVL.R.13® U,
ICOVL.R.14® U, ICOVL.R.17® U and ICOVL.R.18® U for details.
 For 1X2 die, please refer ICOVL.R.2® U~4® U, ICOVL.R.8® , ICOVL.R.11® U, ICOVL.R.12® U, ICOVL.R.15® U,
ICOVL.R.16® U, ICOVL.R.19® U and ICOVL.R.20® U for details.
 For 2X1 die, please refer ICOVL.R.2® U, ICOVL.R.5® U, ICOVL.R.6® U, ICOVL.R.8® , ICOVL.R.11® U,
ICOVL.R.12® U, ICOVL.R.15® U, ICOVL.R.16® U, ICOVL.R.19® U and ICOVL.R.20® U for details.
 Both combo and single ICOVL placement rotation and mirror in X,Y are legal.
8.5.3.6 Dummy Pattern Insertion in Design Phase
IO/analog/SRAM
Macro placement
Power Plan
ICOVL Insertion Consider dummy insertion in

a chip globally before
hierarchical chip block
partition.
Floorplan Dummy TCD insertion
stages Consider dummy TCD in
floorplan first.
Conventional Block partition
Dummy pattern
Insertion related Place and Route
Tape-out GDS
8.6 Dummy Metal (DM) Rules

(DMx, x = 1,2,3,4,5,6,7,8,9,10)
1. To improve the metal CMP process window, you must fill the dummy metal globally and uniformly
even if the originally drawn Mx has already met the density rules.
2. Use either the P&R dummy fill or the utility dummy fill as a method for inserting dummy metal. Two
methods are available for automated dummy metal insertion: commercial P&R tools and a utility from
TSMC:
 The P&R dummy fill is better for dummy metal insertion at the chip level.
 The utility dummy fill is better for IP blocks, library cells, and full custom cells.
 Commercial P&R software inserts rectangular DMx geometry.
 The TSMC utility can insert square DMx uniformly within the original layout. (documents T-N45-CL-DR-
001-C3 and T-N45-CL-DR-001-H3)
 If you use TSMC’s auto-fill utility to fill the dummy metal on the whole chip GDS, TSMC will waive the
local density violation. If you do not use TSMC’s utility to perform the dummy metal generation, you
must meet the local density rules.
3. In the TSMC utility, two kinds of dummy metal are generated, DMx and DMx_O.
DMx: dummy metal
 No OPC on DMx
 DMx for Mx, My, Mz, Mr, and Mu.
DMx_O: OPC dummy of inter-metal.
 The rule of DMx_O is the same as real metal, Mx. So, there is no related rule in this section.
 There is no DMx_O for My, Mz, Mr, and Mu.
 DMx_O receives OPC.
The distinction between Mx, DMx and DMx_O
Mx DMx DMx_O
GDS datatype 0(x), 20(y), 40(z), 60(u), 80(r) 1(x), 21(y), 41(z), 61(u), 81(r) 7(Mx)
Do OPC modification on it Yes No Yes
Refer to it during OPC Yes Yes Yes
Follow Mx rule Yes No Yes
4. Use the dummy layer DMxEXCL properly. This layer tells TSMC’s utility that the area covered should be
blocked from DM fill operations.
5. It is suggested to make sure that DMxEXCL is drawn over the following:
Sensitive circuits (such as SRAM sensitive function blocks and bit cell array) and analog circuits (such
as DAV/ADC, and PLL)
RF application circuits
Pad areas for high frequency signals
For sensitive areas with auto-fill operations blocked by the DMxEXCL layer, it is recommended filling
dummy pattern evenly by manual operations to gain a better process window and electrical performance.
6. For DMxEXCL, use the GDS layer numbers 150;n (n = 1,2,3,4,5,6,7,8,9,10).

7. Revision of the following layers may necessitate re-filling of dummy metal. Because of this, evaluate the
impact on the metal layer mask carefully when any one of the following layouts is revised:
Mx and DMxEXCL layers. This layout revision impacts the Mx mask only.
LOGO/INDDMY. This revision impacts all the metal layer masks.
8. In order to have an accurate interconnect RC for timing and power analysis, it is important to extract RC
after dummy metal insertion, and extract RC with density based metal thickness variation feature enabled.
9. Don’t put dummy metal in areas covered by the following marker layers:
Inductor region (INDDMY)
LOGO
Regions of chip corner stress relief pattern, seal ring, and CDU pattern
TSMC’s fill generation utility will not add dummy metal into these regions because these layers are well
defined.
The DMxEXCL covered areas should not cover or overlap the above areas for DRC reasons.
information.
11. Please consult with TSMC first before you use your own dummy metal rules.

DMx.W.1 Width (minimum) A 
DMx.W.2 Width (maximum) (checked by sizing down 1.5 μm) B  3.0
DMx.S.1 Space C 
DMx.S.2 Space to Mx (Overlap is not allowed) D 
Space to Mx (Overlap is not allowed) [Mx width > 4.5 μm and the parallel
DMx.S.3 E  1.5
metal run length > 4.5 μm]
DMx.EN.2 Enclosure of DVIAx-1  0.01
DMx.A.1 Area (minimum) M 
DMx.A.2 Area (maximum) N 
DMx_O.R.1 DMx_O INTERACT Mx is not allowed.
Dimension
Layer
A C D M N
M1 0.14 0.14 0.6 / 1.5 * 0.16 80
Mx (thin metal) 0.14 0.14 0.6 / 1.5 * 0.16 80
My 0.4 0.4 0.6 0.565 160
Mz (thick metal) 0.4 0.4 0.6 0.565 160
Mr 0.8 0.8 0.8 1.44 160
Mu (ultra thick metal) 3.0 3.0 3.0 9.00 600
Table Notes:
0.6μm: space to main patterns for DMx smaller than 1μm x 1μm
1.5μm: space to main patterns for DMx larger than 1μm x 1μm

Mx.DN.1 Minimum metal density in window 125 um x 125 um, stepping 62.5 um  10%
Mx.DN.1.1 Maximum metal density in window 125 μm x 125 μm, stepping 62.5 μm  85%
1. Mx.DN.1/Mx.DN.1.1 would exclude the following regions:
LOGO/INDDMY for 10% rule
Chip corner stress relief area and seal-ring
2. Mx.DN.1  10% rule is applied when the width of (checking window NOT item 3) is  31.25 μm.
3. Mx.DN.1.1  85% rule is applied when the width of (checking window NOT item 3) is  31.25 μm.
4. Bond pad (Mtop/Mtop-1) is excluded from 85% density check.
The metal density difference between any two neighboring checking windows including DMxEXCL [window 200
μm x 200 μm, stepping 200 μm].
Mx.DN.4  50%
Anticipate metal density gradient from layout of small cell by targeting density ~40% (this way, it will limit the risk
of low density and of high gradient.)
Mx.DN.5 It is not allowed to have local density > 85% of all 3 consecutive metal (Mx, Mx+1, and Mx+2) over any window
62.5 μm x 62.5 μm (stepping 31.25 μm), i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local
density  85%.
2. The check does not include chip corner stress relief pattern, SEALRING_ALL (162;2) and top two metals at
the CUP area.
Metal density  1% must be followed for items (A) to (C).
(A) Metal density [window 80 μm x 80 μm, stepping 40 μm]  1%.
(B) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density < 1%]
≤ 6400um2, except the merged low density windows width ≤ 30um.
(C) Maximum area of merged low density windows [checking window 10umx10um, stepping 5um, density < 1%]
Mx.DN.6 ≤ 18000um2.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is  40um for (A) and 
5um for both (B)/(C).
stepping 5um, density < 1%] ≤ 1600um2, except the merged low density windows width ≤ 30um. This item is
applied for {IP NOT (IP SIZING -10um)} region when the width of IP is  10um.
Mx.DN.6®
stepping 5um, density < 1%] ≤ 4500um2. This item is applied for {IP NOT (IP SIZING -10um)} region when
the width of IP is  10um.
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is  20um for (A) and 
5um for both (B)/(C).
It is not allowed to have local density < 5% of all 3 consecutive metal (Mx, Mx+1 and Mx+2) over any 30um x
30um (stepping 15um), i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local density ≥ 5%.
Mx.DN.7 2. The following special regions are excluded while the density checking:
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding region) is  15 μm.
It is not recommended to have local density < 5% of all 3 consecutive metal (Mx, Mx+1 and Mx+2) over any
15um x 15um (stepping 15um) for IP level, i.e. it is allowed for either one of Mx, Mx+1, or Mx+2 to have a local
density ≥ 5%.
Mx.DN.7® 2. The following special regions are excluded while the density checking:
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding region) is ≥ 7.5μm and for
Mx.DN.8® 1. Mx width == 0.07um
3. Mx has two segments with space == 0.07um with the parallel run length (0.209  parallel run length < 0.52)
DMx.R.1 DMx is a must. The DMx CAD layer must be different from the Mx CAD layer.
DMx inside chip corner stress relief area is not allowed [except seal-ring and stress relief patterns drawn by
DMx.R.2
customers].
DMx.R.3 DMx must be rectangular
U It is important to insert the DMx & DVIAx uniformly to avoid white space. You should use tsmc standard backend
DMx.R.4®
utility to insert the backend dummy pattern. The usage of DMxEXCL needs to be minimized.
Recommended DMx size (width x length) and space
Square
(Utility Fill)
Width x Length
M1 0.5x0.5~2x2
DMx.W.1gU Mx 0.5x0.5~2x2
My 1x1~2x2
Mz 1x1~2x2
Mr 1.2x1.2~3x3
Mu 3x3
DMx
D M x
D /E
M x
A /B
C D M xE X C L
D M x D M x
M /N
M in im u m /M a x im u m a re a
D M x M x
O
8.7 Dummy VIA (DVIAx) Rules

(DVIAx, x = 1,2,3,4,5,6,7)
1. To improve the Flip Chip reliability window, you must fill the dummy VIA globally and uniformly.
2. Dummy VIA is only allowed to be inserted between dummy metals (DVIAx.R.2).
3. Use either the P&R dummy fill or the utility dummy fill as a method for inserting dummy VIA. Two
methods are available for automated dummy VIA insertion: commercial P&R tools and a utility from TSMC:
The P&R dummy fill can only insert dummy VIA at the chip level but the filling rate is not good.
The TSMC DMx utility can insert DVIAx with good filling rate. It can support IP blocks, library cells, and
full custom cells. (documents T-N45-CL-DR-001-C3 and T-N45-CL-DR-001-H3).
4. In the TSMC utility, one kind of dummy VIA is generated, DVIAx.
DVIAx: dummy VIA
 No OPC on DVIAx
 DVIAx for VIAx only, not for VIAy, VIAz, VIAr, VIAu
The distinction between VIAx, DVIAx
VIAx DVIAx
GDS datatype 0 1
Do OPC modification on it Yes No
Refer to it during OPC Yes Yes
Follow VIAx rule Yes No
5. Use the dummy layer DVIAxEXCL properly. This layer directs TSMC’s utility that the area covered should
be blocked from DVIAx fill operations.
6. It is suggested to make sure that DVIAxEXCL is drawn over the following:
Sensitive circuits (such as SRAM sensitive function blocks and bit cell array) and analog circuits (such
as DAV/ADC, and PLL)
RF application circuits
Pad areas for high frequency signals
For sensitive areas with auto-fill operations blocked by the DVIAxEXCL layer, it is recommended filling
dummy pattern evenly by manual operations to gain a better process window and electrical performance.
7. For DVIAxEXCL, use the GDS layer numbers 150;n (n = 51,52,53,54,55,56,57).
8. Revision of the following layers may necessitate re-filling of dummy VIA. Because of this, evaluate the
impact on the metal/VIA layer mask carefully when any one of the following layouts is revised:
Mx/DMx/VIAx/DVIAx/DMxEXCL and DVIAxEXCL layers. This layout revision impacts the Mx/VIAx/
Mx+1 masks.
LOGO/INDDMY. This revision impacts all the metal/VIA layer masks.
information.
10. Please consult with TSMC first before you use your own dummy VIA rules.

DVIAx.W.1 Width (maximum = minimum) A = 0.12
DVIAx.S.1 Space B  0.20
DVIAx.S.2 Space to VIAx D  0.20
DVIAx.EN.1 Enclosure by DMx C  0.01
DVIAx.R.1 DVIAx must be fully inside DMx and DMx+1.
DVIAx.R.2 DVIAx interact Mx, Mx+1, DMx_O, DMx+1_O is not allowed.
DVIAx is a must for Flip Chip.
DVIAx.R.3 To comply tsmc dummy utility, DRC will flag as violation when the area
ratio of (DVIAx to DMx) & (DVIAx to DMx+1) are < 1% at the same time.
DVIAx
C B D
A
D V IA x V IA x
D M x M x
8.8 Dummy Pattern Fill Usage Summary

This section is divided into the following sections:
 Dummy pattern filling requirements
 Recommended flow for dummy pattern filling
 Blockage layer (ODBLK/POBLK/DMxEXCL/DVIAxEXCL) requirements and recommendations
 Dummy pattern filling guidelines
 Mask revision guidelines
 Dummy pattern re-fill evaluation flow chart
8.8.1 Dummy Pattern Filling Requirements
1. OD/PO/Metal pattern density requirements
Local Density Range Window check size Whole Chip Density Range
20%~80% for Core region
OD 150 μm * 150 μm 25%~75%
20%~90% for I/O region
Poly NA NA 14%~40%
125 μm * 125 μm for
Metal 10%~85% for M1/Mx/My/Mz/Mu NA
M1/Mx/My/Mz/Mr/Mu
2. DOD/DPO/DMx requirement: The DOD/DPO/DMx must be filled, even if the local or chip density has
already met the density rules
(OD.DN.1/OD.DN.1.1/OD.DN.2/OD.DN.2.1/OD.DN.2.2/OD.DN.3/OD.DN.3.1/OD.DN.3.2/PO.DN.1/PO.DN.1
.1/PO.DN.2/PO.DN.3/Mx.DN.1/Mx.DN.1.1/Mx.DN.4/Mx.DN.5) (x=1~10).
3. Density requirement: It is recommended that you use the TSMC auto-fill utility to generate dummy fill
patterns.
If you use TSMC’s auto-fill utility to fill DOD and DMx, TSMC will waive the low density rule violations
(OD.DN.2, OD.DN.3, Mx.DN.1, and Mx.DN.4) (x=1~10). Both the local density rules and chip density rules
must be met if TSMC’s auto-fill utility is not used to generate the DOD/DPO/DMx fill.
4. Tool recommendation: It is recommended filling dummy patterns using P&R dummy fill (for DMx only)
with TSMC provided settings or using the TSMC’s auto-fill utility.
The TSMC auto-fill utility can fill patterns uniformly. It is structurally and hierarchically optimized to provide
maximum yield and manufacturability improvement with minimum perturbation to the circuit.
5. DVIAx requirement: It is important to add as many DVIAx as possible (DVIAx.R.3) to enhance the Flip
Chip assembly reliability window.
8.8.2 Recommended Flow for Dummy Pattern Filling
IP le v e l u tility
F ill D M x /D V IA x
(G D S ) b y ro u te r o r u tility ?
ro u te r
F ill D O D /D P O /D M x /
F ill D M x /D V IA x b y ro u te r
D V IA x b y T S M C u tility
(re fe r th e to o l/s e ttin g fro m F ill D M x /D V IA x
a n d c o n firm D R C c le a n
T S M C R e fe re n c e F lo w ) b y T S M C u tility
N e w IP Yes
D R C c le a n ?
(G D S )
N o
In c re m e n ta lly fill D M x /D V IA x w ith

P & R a t c h ip le v e l
d iffe r e n t D M x -M x o r D M x -D M x s p a c e
(tim in g , p o w e r… .)
to m e e t lo c a l d e n s ity *
N e tlis t F ill D O D /D P O b y
T S M C u tility
E v a lu a tio n
(tim in g , p o w e r… .)
N o
D R C c le a n e x c e p t
S o lv e D R C v io la tio n
lo c a l d e n s ity ?
Yes
Yes
D R C c le a n fo r F ill D M x /D V IA x
lo c a l d e n s ity ?
b y T S M C u tility
N o N o
u tility ro u te r
T S M C w a iv e lo c a l U s in g T S M C W a iv e d b y
u tility o r ro u te r? TSM C?
d e n s ity v io la tio n
Yes
F in is h D u m m y fillin g
* If in c r e m e n ta ll y f ill D M x is d o n e m a n y tim e s , i t s till c a n ’t m e e t in g lo c a l d e n s it y, p l e a s e f ill D M x b y T S M C

u t i l i t y o r a s k T S M C ’s c o m m e n t t o w a i v e i t o r n o t .
8.8.3 Blockage Layer (ODBLK/POBLK/DMxEXCL/

DVIAxEXCL) Requirements and
Recommendations
1. Density requirement: For any area covered by a blockage layer, it is especially critical to meet the local
density rules.
Blockage layers specify sensitive regions (by recommendation or requirement), and P&R dummy fill(for
DMx only) or the TSMC auto-fill utility does not fill dummy patterns for these regions. For details, please
refer to the following sections in this chapter: “Dummy OD Rules,” Dummy Poly Rules,” and “Dummy
Metal Rules.”
Blockage Layer
Circuit
ODBLK POBLK DMxEXCL DVIAxEXCL
RF application circuit Must Must Must Must
Pad metal area for high Must Must Must Must
frequency signals
Analog block (ADC/DAC/PLL, Must Must Recommended Not necessary
and so on)
 RF circuits: Draw a blockage layer that covers the entire RF circuit. Designers should consider the
signal coupling impact and keep a suitable distance between the RF circuits and the blockage layer
edge.
 High frequency signal pads: Draw blockage layers that are coincident with the outer edge of the
metal pads.
 Other sensitive regions: Draw a blockage layer that covers the other sensitive regions, including the
SRAM function block and bit cell array, analog circuits (DAC/ADC/PLL), and so on.
2. Areas excluded from certain dummy fill: Don’t put any dummy patterns into the following regions:
Well resistor under STI region (NWDMY): DOD/SR_DOD
INDDMY region: DOD/DPO/DMx
LOGO region: DMx
Seal ring /CDU /chip corner stress relief pattern region: DOD/SR_DOD/DPO/SR_DPO/DMx
The TSMC utility will not add dummy patterns into these regions unless the correct dummy layer is
specified, or the correct option is turned on (for chip corner).
The ODBLK/POBLK/DMxEXCL covered areas should not cover or overlap the above areas for DRC
reasons.
8.8.4 Dummy Pattern Filling Guidelines

1. Dummy pattern filled by P&R dummy fill (for DMx only) or TSMC’s dummy fill utility.
Put all relevant layers (MUST and OPTION listed in the following table) into one GDS file. If the OPTION
layers are not ready to tape out, draw the blockage layer to avoid dummy pattern fill.
Dummy Pattern
Layer ID Description DMx DVIAx
DOD DPO
(x=1,2,3,4,5,6,7,8,9,10) (x=1,2,3,4,5,6,7)
OD Diffusion MUST MUST
PO Poly MUST MUST
NW N-well MUST
NP N+ S/D implant MUST MUST
PP P+ S/D implant MUST MUST
Mx x=1,2,3,4,5,6,7,8,9,10 MUST
VIAx x=1,2,3,4,5,6,7 MUST
NWDMY N-Well resistor OPTION
INDDMY Inductor dummy layer OPTION OPTION OPTION OPTION
ODBLK DOD blockage layer OPTION
POBLK DPO blockage layer OPTION
DMxEXCL DMx blockage layer OPTION
DVIAxEXCL DVIAx blockage layer OPTION
LOGO Product labels OPTION
2. Dummy pattern geometry (DOD/DPO/DMx) generated by P&R tool or TSMC utility: You must place
this fill geometry in a reserved layer (data type 1 as default).
3. Dummy pattern generated by a non-TSMC utility: If the auto-fill utility is not provided by TSMC, it must
meet the DOD/DPO/DMx rule. Also, keep this fill geometry in a reserved layer (data type 1 as default).
4. CAD layer usage: If dummy patterns and active patterns have different GDS layers and data types (such
as data type 0 and 1), the dummy patterns should follow the DOD/DPO/DMx rules.
If dummy geometry and active circuit geometry are placed on the same GDS layers and data types (such
as data type 0), the dummy patterns should follow the appropriate OD/PO/Mx rules. Please note that
placement of dummy geometry on the same CAD layer as circuit geometry will result in longer mask
making cycle times.
8.8.5 Mask Revision Guidelines

When masks or layouts are revised, re-evaluate to modify the filled dummy patterns.
Dummy Pattern
Layer ID DMx DVIAx
DOD DPO
(x=1,2,3,4,5,6,7,8,9,10) (x=1,2,3,4,5,6,7)
1 OD    
2 PO    
3 NW    
4 Mx (x=1,2,3,4,5,6,7,8,9,10)    
5 VIAx (x=1,2,3,4,5,6,7)    
6 NWDMY    
7 INDDMY    
8 ODBLK    
9 POBLK    
10 DMxEXCL (x=1,2,3,4,5,6,7,8,9,10)    
11 DVIAxEXCL (x=1,2,3,4,5,6,7)    
12 LOGO    
13 DOD    
14 DPO    
 : Needs GDS/mask revision
 : Evaluate GDS/mask revision
: Doesn’t need GDS/mask revision
8.8.6 Dummy Pattern Re-fill Evaluation Flow Chart
OD Mask Revision Decision Flow
If NW/PO/NWDRY/INDDMY/ODBLK/
DPO is revised
(Example: PO revised)
Check DOD and DPO rules on the old

DOD layout and newly revised layer.
(Example: Run rule check of DOD.S.3)
NO There is no need to revise the OD

Design rule violations?
mask.
(EX: Violated DOD.S.3) (Example: There is no impact
on the OD mask.)
YES
Must revise OD mask.

(Example: The OD is impacted)
PO Mask Revision Decision Flow
If OD/INDDMY/POBLK/DOD
revised
(Example: OD revised)
Check DOD and DPO rules on the old

DPO layout and newly revised layer.
(Example: Run the rule check of DPO.S.2)
There is no need to revise the PO

Design rule violations? mask.
NO
(Example: Violated DPO.S.2) (Example: There is no impact on the
PO mask.)
YES
Must revise PO mask.
(Example: The PO is impacted)
Mx Mask Revision Flow
If INDDMY/DMxEXCL/LOGO is
revised
(Example: INDDMY revised)
Check dummy metal rules on the old DMx

layout and newly revised layer.
(Example: Check DMx.S.4)
There is no need to revise the

MX mask.
Design rule violations? NO
(Example: There is no impact on
(Example: Violate DMx.S.4?)
the Mx mask.)
YES
Must revise the Mx mask.
(Example: The Mx is impacted.)
VIAx Mask Revision Flow
If Mx/INDDMY/DMxEXCL/
DVIAxEXCL/LOGO is revised
(Example: INDDMY revised)
Check dummy VIA rules on the old DVIAx

layout and newly revised layer.
(Example: Check DVIAx.S.1)
There is no need to revise the

Design rule violations? VIAx mask.
NO
(Example: Violate DVIAx.S.1?) (Example: There is no impact on
the VIAx mask.)
YES
Must revise the VIAx mask.
(Example: The VIAx is impacted.)
9 Design For Manufacturing (DFM)

This chapter provides information about the following topics:
9.1 Layout guidelines for yield enhancement
9.2 DFM Recommendations and Guidelines Summary
9.3 Mechanical and Thermal Guidelines for FCBGA
9.4 GDA die size optimization kit
9.1 Layout Guidelines for Yield Enhancement

This section provides guidelines for layout optimization to minimize certain potential and unnecessary yield or
timing loss under the condition that they introduce no area penalty.
For a given chip design, first and foremost, efforts should be made to achieve as small a die size as possible.
The guidelines should not be used indiscriminately, which could result in unnecessarily large chip sizes.
This section is divided into the following topics:

 Layout tips for minimizing critical areas
 Guidelines for optimal electrical model and silicon correlation
 Guidelines for mask making efficiency
9.1.1 Layout Tips for Minimizing Critical Areas
Defects are variable in size and therefore follow a size distribution. A critical area of a given layout is an
accumulative area that is susceptible to certain failures (shorts or opens) caused by defects of a certain size.
For example, although the total occupied areas are the same in panels A and B of Figure 9.1.1, the wires in
layout A are more vulnerable to defect-induced shorts because they have a larger critical area.
A B
Figure 9.1.1 Layout Examples of Critical Areas
1. Space out the wiring.

Spacing out the wiring, either using Wire Spreading at P&R stage or manually layout modification at cell
level, to take advantage of an empty space can reduce the critical area. This practice has additional
benefits:
It can reduce wire cross coupling.
It can reduce the possibility of pattern short.
It can evenly distribute the local pattern density, thereby creating less variation in wire Rs.
2. Reduce the probability of wiring shorts.
The critical area plays a role in the yield of a given design, but so does the rate of failure that corresponds
to the critical area. Manufacturing experience indicates that a wiring short circuit is a more frequent
problem than an open circuit.
Give priority to increasing wiring space for conductors of non-minimum wiring pitch, second only to wire
resistance or EM considerations. Refer to Figure 9.1.2.
Figure 9.1.2 Reduced Probability of Wiring Shorts

For long and parallel metal or poly lines, use a larger space.
Avoid the use of redundant wiring, except for reliability or performance considerations.
Draw wires in an orthogonal fashion.
Avoid leaving small jogs, especially in the corner areas where metal spacing is at a minimum.
Avoid using 45-degree turns, except for very wide metal buses, where the length of the 45-degree
portion should be sufficiently large. X-metal uses more advanced E-beam writer to generate mask and
no need to consider this recommendation
3. Reduce the risk of open silicided wire or high resistance silicided wire.
To avoid a potential silicide break related to an open circuit or high resistance in narrow lines of poly or OD:
Do not use a long narrow width poly conductor, if possible, as a means of local interconnection. The
length of non-contacted narrow width poly should be kept to a minimum.
If possible, do not use a narrow width OD conductor as a means of interconnection.
Avoid a butted N+OD/P+OD interface in a narrow OD/PO.
Use a sufficient number of contacts when a narrow OD strip is used for substrate tapping.
4. Reduce the probability of a contact or via open circuit.

Open and soft open (excessively high Rc) of a single contact or via are usually a yield bottleneck, given
their sheer number in a chip. While the manufacturer strives to bring down the failure rate as low as
possible, a designer can contribute to further reduction of the probability.
Whenever possible, include redundant vias and contacts for the following benefits:
Reduces the probability of an open circuit
Reduces via and contact resistance and potential variation.
Potentially increases via stress migration immunity
5. Reduce the probability of open vias in a single-via stack.
Whenever possible, use a larger than minimum sized island metal for stacking a single via. This reduces
the risk of via resistance variation or open vias.
9.1.2 Guidelines for Optimal Electrical Model and

Silicon Correlation
The following sections offer recommended practices to minimize the deviation of processed hardware from
electrical models.
9.1.2.1 Transistors
1. Avoid layout styles that may contribute to silicon-to-model deviation.
 Avoid using narrow-width devices and short channel device if they require high precision, such as
current source device.
 Due to critical dimension variations in channel length and channel width, the electrical
properties of narrow-width devices and short channel devices vary more than those of larger
devices.
 Poly or OD corner rounding may impact the device length or width critical dimension.
Source or drain contacts should be placed symmetrically wherever possible. Avoid using single source
or drain contacts on large width devices, especially for the multi-finger device with large Isat, place use
full contacts or  1/2 full contacts uniformly for channel width  1um (refer to CO.S.7® )
 Use the recommendation from DFM rule CO.EN.1® regarding sufficient OD-to-contact enclosure.
 The benefits of sufficient OD-to-contact enclosure are less variation of contact resistance and the
avoidance of potentially excessive drain or source leakage.
 Use uniform poly and OD densities across a design.
 The poly and OD densities in the neighboring area could affect the gate critical dimension. Although
the post-layout insertion of dummy OD, or dummy poly, or both, may patch some empty spaces, it is
best to avoid the problem with careful planning and space filling at the macro levels of layout design
initially. Please refer to these rules in the chapter of Dummy Pattern rule and Filling Guideline: “DOD
Rule“, “SR_DOD Rule”, “DPO Rule”, “SR_DPO Rule” and “Dummy Pattern Fill Usage Summary.” The
poly and OD densities in the neighboring areas could also affect device perfomance, not only gate
critical dimension. So, please avoid putting sensitive circuits near the region of too low/high poly/OD
density (refer to OD.DN.4® ~7® and PO.DN.4® ~7® ).
2. Be aware that thin oxide gate leakage of the 45 nm process is higher than that of previous
generations. Its impact on the functionality of a circuit, which uses thin oxide transistors and/or capacitors
and/or MOS varactors, must be taken into account by using a proper SPICE model that contains the
leakage components.
3. Pay attention to the leakage current for narrow-width devices with a low-Vt option.
Please consult the SPICE model for detailed information.
4. Device behavior is influenced by layout style possibly due to stress distribution induced by STI/OD
edge. Designers should take this length of OD (LOD) effect into consideration during device or cell level
design.
5. Avoid using asymmetrical or single source/drain CO placement on large devices (CO.R.5g).
6. For a PMOS device, if the NWELL is tied to the source used as an internal AC node, the NWELL
total area junction capacitance should be included in the circuit simulation by adding the Well
capacitance at the source node.
7. Take NWELL sheet resistance into consideration during simulation, to reflect the transient bias
variation by adding the Well resistance between source node and substrate node.
9.1.2.1.1 Improvement of poly CD uniformity

Further recommendation for improvement of poly CD uniformity (3-sigma) at small channel length:
 Insert dummy PO surrounding existing PO gate if this PO gate is the nearest one to the cell
edge and follow the 1st poly space rule (PO.S.2). (S1, S3 in Figure 9.1.3)
 For IP design
 Add dummy PO/OD manually around sensitive circuits to avoid mismatch caused by layout
effect
 Add dummy PO/OD by utility on whole IP to fill the remaining sparse area
 Add a dummy PO/OD blockage the same size as the IP cell boundary.
 Have dummy patterns in the blockage area as a default and verify with a library
characterization process.
 Avoid any open area  1.8 um x 1.8um without any OD/PO patterns inside in the macro cell
area.
 During chip integration, a placement blockage could be added on top of IP to avoid std cells
abutment with this IP, thus, there could be white space around IP without PO/OD.
 To keep PO/OD pattern density uniformity, please use the dummy PO/OD utility again to insert
dummy PO/OD on the whole chip.
Core device PO gate
OD
S1 S2 S3
Have same parallel run length to
surrounded PO gate
Figure 9.1.3 Reduce sparse poly count
 It is recommended placing the gate with uni-direction in a chip.

 1nm CD gap is observed between horizontal and vertical poly lines.
 An empty area in the standard cell array is not allowed. Customers need to use a patterned
filler cell to insert the empty area of the standard cell array by P&R.
 It is requested to have OD and PO patterns in the filler cell, which provides better gate CD
uniformity.
 Need to put dummy PO firstly on sides of both cell edges with < 0.5μm space to nearby cell
edge. A space ( 0.1μm) to nearby cell edge is recommended.
 Need to follow the layout rules of DRM.
 Put OD and PO uniformly across the whole filler cell. Maximize the length of the OD and PO as
much as you can (to match the cell height). If the space is not enough, put PO first.
 A rectangular PO pattern is recommended in the filler cell.
 Dummy fillers of floating and fixed voltage are both acceptable from the process point of view.
However, the associated implant layers are a must if the filler cell is connected to a fixed
voltage.
 It is also recommended to put a filler cell at the edges of standard cell arrays during P&R.
Figure 9.1.4 Example of filler cell
 Guidelines for P&R during filler cell insertion at P&R:

o Flow:
F lo o r p la n – p o w e r p la n a n d
h a r d m a c r o p la c e m e n t
B o u n d a r y f ille r c e lls
in s e r t io n
S ta n d a r d c e ll p la c e m e n t a n d
o p t im iz a t io n
I n t e r n a l f ille r c e lls
in s e r t io n
o Layout with filler cells

 Boundary filler cells
 Before standard cell placement, inserting fillers on block boundary and macro
boundary for occupying the placement locations.
 Internal filler cells
 After standard cell placement, using original filler insertion command.
Figure 9.1.5 Layout with filler cells
9.1.2.1.2 Device impact by CO placement

 Asymmetric partial CO design will degrade Isat seriously on a large device (W>1um). LPE cannot
reflect every kind of CO placement layout style due to tool limitation, and will cause silicon slower than
simulation. It is recommended to use fully-CO or uniform-CO design.
 For the fully-CO design, it is recommended to add additional 1ohm R_probe_tip in the simulation
while certifying your IP.
 For the asymmetry partial CO design, it is recommended to follow CO.S.7® , or add more design
margin.
S S S S S
G G G G G G G
D D D D D D D
F u lly -C O U n ifo r m -C O P a r tia l-C O P a r tia l-C O P a r tia l-C O P a r tia l-C O
9.1.2.1.3 Device impact by local OD/PO density

Isat will increase as the local OD density decreases.
Isat will increase as the local PO density increases.
 It is important to follow the layout guidelines for sensitive circuits to reduce the gap between
simulation and silicon. (OD.DN.4® ~7® and PO.DN.4® ~7® )
In the region of (sensitive IP sizing 20um):
OD density: 10~70%, PO density: 5~35%
Avoid abutting your IP to PO resistor, varactor, capacitor, large BJT, and SRAM, which easily leads
to OD density violation
Separate the MOM, capacitor and PO resistor in the IP properly, and insert DOD/DPO between
them
Avoid abutting your IP to MOM, varactor, capacitor, PO resistor, and large diode, which easily to PO
density violations
 Wide OD guard rings need to have DPO in between.
It is important not to have a large DCAP surrounding the IP, or not to insert too many DCAPs in the
std cell array
 Remove some DCAPs as the IP violates the PO density 35%
 Only insert DCAP on the IR sensitive area. Use other filler cells if possible.
Avoid to place the IP close to IO and chip corner if possible

 Increase the design margin, if it is unavoidable
In the region of (sensitive IP sizing 100um):
OD density: 20~70%, PO density: 15~35%
Keep your IP away from the Inductor, which easily leads to OD and PO density violations
It is recommended to keep enough space from the sensitive IP to varactor, PO resistor, large diode,
IO, and prime chip edge (hi OD%, low PO%)
9.1.2.1.4 Device impact by OSE/PSE

The DOD/DPO layout style also impacts the Isat
 For the sensitive circuit, it is recommended to leave 4um space, and use the TSMCutility to insert
SR_DOD and SR_DPO uniformly surrounding the target device.
 For the matching pair, it is recommended to insert with dummy devices with identical
shape/dimension/space surrounding the target device, and then insert the SR_DOD/SR_DPO and
DOD/DPO uniformly.
 Keep dummy device OD space close to 0.88um in W-direction and 0.1um in L-direction
 If you can’t manually implement the recommendations (2nd PO space, OD space) for OSE/PSE,
please use TSMC dummy OD/PO insertion utility.
 It is very important to use the TSMC utility to make your circuit design more robust.
Chip design flow IP design flow
S c h e m a t ic s d e s ig n C h ip H D L d e s i g n
P r e - la y o u t s im u la t i o n R T L s y n t h e s is / P r e - la y o u t s im u la t io n
F in a l l a y o u t d e s i g n P la c e & R o u t e l a y o u t
D M d u m m y u t i lit y D P O / D O D D u m m y u t i li t y D P O / D O D / D M D u m m y u t i lit y
D R C /LV S /L P E D R C /LV S
R C E x tr a c tio n R C E x tr a c tio n
P o s t - la y o u t s im u la t io n S T A / P o s t - la y o u t s im u la t i o n
Ta p e -o u t Ta p e -o u t
A n a lo g D e v ic e o r IP
D O D /D P O
s u r r o u n d e d w ith
d u m m y d e v ic e s
A n a lo g D e v ic e o r IP S R _ D O D /S R _ D P O
N o t r e c o m m e n d (S i to s im u la tio n g a p :) Recom m end Recom m end

(> 1 0 % ) (> 1 0 % ) (> 1 0 % ) (< 5 % ) (< 5 % )
1. W ith o u t d u m m y d e v ic e s & D O D /D P O IP s u r r o u n d e d IP s u r r o u n d e d
2. O n ly s u rro u n d e d by dum m y d e v ic e s , but no D O D /D P O w ith D O D /D P O w ith d u m m y d e v ic e s
p ro te c t b y u p d a te d u tility fir s t, th e n in s e r t
3. O n ly s u r r o u n d e d b y D O D /D P O , b u t n o S R _ D O D /S R _ D P O
D O D /D P O
9.1.2.2 Resistors
1. For SPICE accuracy it is strongly recommended to put each OD/poly resistor in a dense area.
2. Avoid using small poly and OD width resistor that is critical in performance.
3. In order to have accurate interconnect RC for timing and power analysis, it is important to extract RC
after dummy metal insertion and extract RC with density based metal thickness variation feature enabled.
9.1.2.2.1 Unsilicided PO Resistor impact by local OD/PO density
It is important to follow the layout guidelines for unsilicided PO resistor to reduce the gap between simulation
and silicon.
PO resistor: OD.DN.8® , OD.DN.9® , PO.DN.8® , PO.DN.9® ,
9.1.3 Electrical Wiring

1. Avoid using minimum-width poly or OD where resistance is critical to the circuit performance.
2. Maintain uniform metal density to minimize wire sheet resistance variation.
3. Wherever possible, use two or more narrower metal buses to replace a single bus that uses the
maximum width.
4. Maintain metal density in the mid range of the specification, avoiding the two extreme ends.
5. During IP/macro design, it is important to put certain density margin to avoid the possibility of high density
violations (Mx.DN.1, Mx.DN.4, and Mx.DN.5) during placement. It may have unexpected violations during
the IP/macro placement due to the environment, even if the IP/macro already pass the high density rule
check. Therefore, you need to carefully design the dimensions of the width/space for wide metal (e.g.,
power/ground bus), under the proper high density limit.
6. Need dummy insertion in the library/IP/Macro blockage area:
Either extend hard macro boundary to align with blockage area or minimize the distance (recommended
 3 m) from the blockage edge to the macro cell boundary. Also embed this blockage region in
macro cell.
Have dummy patterns in the blockage area as a default and verify with the library characterization
process.
Need to re-define I/O pin for P&R at new macro cell boundary if you push out hard macro boundary to
align with blockage area.
Avoid any open area  3 m x 3 m without any metal patterns inside in the macro cell area .
9.1.4 Guidelines for Mask Making Efficiency

Please refer to the Chapter 3 sections:
 “Design Geometry Restrictions”
 “Design Hierarchy Guidelines”
9.2 DFM Recommendations and Guidelines

Summary
o Please use the following advisory/recommended dimensions and guidelines whenever possible, unless
doing so impacts chip size or performance.
o DFM does not have to comply to the advisory/recommendation value completely. Any change even by one
grid helps.
o By using DFM recommendations and guidelines, higher precision of models, better reliability, lower timing,
process or yield variation may be expected.
o If your circuit has concern about the DFM Action-Required rules (refer to the section of Action-Required
Rules) and Recommendations (refer to the section of Recommendations) TSMC DRC deck can help you
to flag the violations. DFM DRC deck is bundled in the TSMC logic DRC deck. The following 2 methods
can specify the region to run DFM recommendations in DFM DRC deck. Please also refer to the “User
Guide” in the DFM deck
1. Dummy layer:
 RRuleRequire(CAD layer: 182;1): for the DFM Action Required recommendations.
 RRuleRecommend(CAD layer: 182;2): for the DFM Recommended recommendations
2. Cell selection based on the following variables:
 CellsForRRuleRequired
 CellsForRRuleRecommended
9.2.1 Action-Required Rules

Using minimum dimension of the following rules may have influence on the electrical characteristics (e.g. Idsat)
of a related device. It is required that either the concerned influence be taken into account in a circuit electrical
design if a dimension is less than the advisory point, or the advisory value be used. In order to have precisely
CKT simulation, user needs to turn on the DFM-LPE (RC extraction tool, built in TSMC LVS released package
under the directory “DFM”) option for PO.EX.2® , PO.S.5® , PO.S.6® , to get the optimized device parameter.
Rule No. Description Op. Advisory Min. Rule
Recommended OD extension on PO (full and symmetrical contact
placement are recommended at both source and drain side) to
PO.EX.2® avoid Isat degradation, especially for channel width > 1.5 μm.  0.13 0.09
When you use poly space = 0.16 um (PO.S.2), please use = 0.13
um for this recommendation.
Recommended space to L-shape OD when PO and OD are in the
PO.S.5.LP®  0.1 0.03 (PO.S.4)
same MOS (avoid corner rounding effect) for LP/LPG
Recommended space to L-shape OD when PO and OD are in the
PO.S.5.GS®  0.06 0.03 (PO.S.4)
same MOS (avoid corner rounding effect) for GS
Recommended L-shape PO space to OD when PO and OD are in
PO.S.6.LP®  0.1 0.04 (PO.S.6)
the same MOS (avoid corner rounding effect) for LP/LPG
Recommended L-shape PO space to OD when PO and OD are in
PO.S.6.GS®  0.07 0.04 (PO.S.6)
the same MOS (avoid corner rounding effect) for GS
9.2.2 Recommendations
Using minimum dimension of the following rules is okay. If a non-minimum recommendation is used, however,
the variation of the related electrical parameter (e.g. contact or via Rc) can be minimized and yield benefit may
be expected. It is recommended that the Recommendations be used wherever possible.
OD.DN.4® ~OD.DN.7® and PO.DN.4® ~7® are only checked within a dummy layer SENDMY for sensitive
circuit. SENDMY (255;8): DRC recognition layer for sensitive circuit
Rule No. Description Recommended Min Rule
Recommended minimum interconnect OD width (except MOMDMY (155;21) region and
OD.W.1®  0.08 0.06
TCDDMY)
OD.S.1® Recommended minimum OD space to reduce the short possibility caused by particle  0.1 0.08
It is not recommended the gate interact with the region of {(OD local density < 10%)
SIZING 20um}.
OD.DN.4® {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND  10% -
RODMY)}
It is not recommended the gate interact with the region of {(OD local density > 70%)
SIZING 20um}.
OD.DN.5® {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND  70% -
RODMY)}
It is not recommended the gate interact with the region of {(OD local density < 20%)
SIZING 100um}.
OD.DN.6® {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND  20% -
RODMY)}
It is not recommended the gate interact with the region of {(OD local density > 70%)
SIZING 100um}.
OD.DN.7® {(((Gate INTERACT SENDMY*) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND  70% -
RODMY)}
It is not recommended the unsalicided poly resistor interact with the region of {(OD local
density < 20%) SIZING 100um}.
OD.DN.8®  20% -
It is not recommended the unsalicided poly resistor interact with the region of {(OD local
density > 60%) SIZING 100um}.
OD.DN.9®  60% -
It is important to use TSMC DOD/DPO utility to insert the SR_DOD and SR_DPO properly
surrounding your IP and circuit, and then do post-simulation carefully before chip
implementation.
DOD.R.4®  1.8x1.8um2 -
DRC will flag the empty rectangle area larger than 1.8x1.8um2 inside
{(GATE SIZE 2.8) NOT (((OD OR DOD) OR SR_DOD) SIZE 0.12) NOT ((PO SIZE 0.05)
OR ((DPO OR SR_DPO) SIZE 0.03)) NOT ((NW SIZE 0.08) NOT (NW SIZE -0.08))}
(Except TCDDMY and SEALRING_ALL (162;2))
SR_DOD.S.3® Recommended space to DPO, SR_DPO  0.05 0.03
Recommended minimum SR_DOD density inside {((((((OD OR PO) INTERACT GATE)
SR_DOD.DN.1® SIZING 2.5um) NOT ((OD OR PO) SIZING 0.4um)) NOT SRAMDMY;0) NOT OD2)} (The  8% -
GATE doesn't include the regions covered by layer TCDDMY, CSRDMY, CDUDMY)
DNW.EN.1® Recommended enclosure by NW for better noise isolation  1.0 -
NWROD.S.3® Recommended RPO space to CO in NW resistor within OD for SPICE simulation accuracy = 0.3 -
Recommended OD enclosure of CO in NW resistor under STI for SPICE simulation
NWRSTI.EN.2® = 0.3 -
accuracy
PO.W.1® U
Recommended minimum interconnect PO width  0.06 0.04
Recommended minimum interconnect PO space to reduce the short possibility caused by
PO.S.1®  0.12 0.1
particle
0.12 ~ 0.22 or
PO.S.2.LP® Recommended GATE space in the same OD to avoid Isat degradation for LP/LPG  0.14
0.32
Recommended gate space [L-shape OD and L-shape PO enclosed area < 0.0196 μm2] for
PO.S.4.1®  0.14 0.11
PO/OD rounding effect
Recommended Gate edge [channel length = 0.04um, channel width ≤ 0.2um] space to
{(PO OR SR_DPO) OR DPO } [width ≥ 0.12um] [projection in S/D direction], and Gate
PO.S.17®  0.16 -
edge parallel run length (individual projection) in the same gate ≥ 0.1um, for poly gate
CDU control
Recommend to add 2nd poly away from 1st poly [for channel length < 0.08μm] (DRC only
PO.S.18.GS® = 0.14~0.2 -
check 1st poly space to gate ≤ 0.2um and width < 0.08um)
PO.EX.1® Recommended extension on OD (end-cap) to avoid line-end shortening.  0.11 0.09
It is not recommended the gate interact with the region of {(PO local density < 5%) SIZING
20um}.
PO.DN.4®  5% -
2. {(((Gate INTERACT SENDMY) NOT LOGO) NOT CSRDMY) NOT (SRAMDMY AND
RODMY)}
It is not recommended the gate interact with the region of {(PO local density > 35%)
SIZING 20um}.
PO.DN.5®  35% -
RODMY)}
It is not recommended the gate interact with the region of {(PO local density < 15%)
SIZING 100um}.
PO.DN.6®  15% -
RODMY)}
It is not recommended the gate interact with the region of {(PO local density > 35%)
SIZING 100um}.
PO.DN.7®  35% -
RODMY)}
It is not recommended the unsalicided poly resistor interact with the region of {(PO local
density < 15%) SIZING 100um}.
PO.DN.8®  15% -
{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY)}
It is not recommended the unsalicided poly resistor interact with the region of {(PO local
density > 40%) SIZING 100um}.
PO.DN.9®  40% -
{(((RH AND (RPO AND PO)) AND RPDMY) AND SENDMY)}
SR_DPO.S.1® Recommended space to {PO OR SR_DPO} (SR_DPO overlap with PO is not allowed)  0.12 0.11
SR_DPO.L.1® Recommended length  0.5 -
SR_DPO.L.3® Recommended maximum Length  10 -
Recommended minimum SR_DPO density inside {((((((OD OR PO) INTERACT GATE)
SR_DPO.DN.1® SIZING 2.5um) NOT ((OD OR PO) SIZING 0.4um)) NOT SRAMDMY;0) NOT OD2)} (The  4% -
GATE doesn't include the regions covered by layer TCDDMY, CSRDMY, CDUDMY)
ESDIMP.EN.1® Recommended (OD NOT PO) enclosure of ESDIMP. = 0.4 0.4
U For better Idsat uniformity with single finger gate, HVD_N is recommended to be located
HVD_N25.R.5®
at the same side of the gate.
For better Idsat uniformity with single gate, HVD_P is recommended to be located at the
HVD_P25.R.5® U
same side of the gate.
For better Idsat uniformity with single finger gate, HVD_N is recommended to be located
HVD_N18.R.5® U
at the same side of the gate.
For better Idsat uniformity with single gate, HVD_P is recommended to be located at the
HVD_P18.R.5® U
same side of the gate.
Recommend reducing the breach region of M1 on guard-ring if using M1 to connect HV
HVD_GR.R.7® U
N/PMOS to outside circuits.
CO.S.3® Recommended space to gate to reduce the short possibility caused by particle.  0.05 0.04
CO.EN.0® Recommended enclosure by OD is defined by {CO.EN.1® and CO.EN.1.1® }.
CO.EN.1® Recommended enclosure by OD to avoid high Rc.  0.03 0.01
CO.EN.1.1® Recommended enclosure by OD [at least two opposite sides]  0.04 0.03
CO.EN.3® Recommended enclosure by PO [at least two opposite sides] to avoid high Rc.  0.04 0.02
Maximum effective CO space in Source/Drain of device [channel width1 μm] (This
check doesn't include the regions covered by SR_ESD and SDI.)
Definition of effective CO: (1) CO projection space to GATE0.22 μm (D2). (2) {COs
INSIDE {HVD_N OR HVD_P}} which projection space to GATE 1 μm.
Definition of maximum effective CO space (B3): Channel width – effective CO projection
CO.S.7®  0.29 -
length to GATE.
Besides, if there is no CO in Source/Drain or no CO connected to Source/Drain by OD, it
is allowed. {CO OUTSIDE {HVD_N OR HVD_P}} projection space to PO (without CO
shielding) > 0.22 μm or {COs INSIDE {HVD_N OR HVD_P}} projection space to PO
(without CO shielding) > 1 μm for HVMOS drain side will be flagged on gate.
M1.S.1® Recommended space to reduce the short possibility caused by particle  0.09 0.07
M1.A.1® Recommended area to avoid high Rc (except DMx_O)  0.0351 0.0215
M1.EN.0® Recommended enclosure of CO is defined by either M1.EN.1® or M1.EN.2® .
M1.EN.1® Recommended enclosure of CO to avoid high Rc  0.03 0.00
M1.EN.2® Recommended enclosure of CO [at least two opposite sides] to avoid high Rc  0.05 0.03
0.015 [parallel
Recommended Enclosure of CO [metal width  0.11μm, space < 0.08μm] to avoid high Rc
M1.EN.5®  0.015 run length >
0.27 μm]
(A) For IP level, recommend metal density [window 40 μm x 40 μm, stepping 40 μm]  1%.
This item is applied for {IP NOT (IP SIZING -40um)} region when the width of IP is 
40um.
(B) For IP level, recommend maximum area of merged low density windows [checking
window 10umx10um, stepping 5um, density < 1%] ≤ 1600um2, except the merged low
density windows width ≤ 30um. This item is applied for {IP NOT (IP SIZING -10um)}
region when the width of IP is  10um.
M1.DN.6® (C) For IP level, recommend maximum area of merged low density windows [checking
window 10umx10um, stepping 5um, density < 1%] ≤ 4500um2. This item is applied for
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is
 20um for (A) and  5um for both (B)/(C).
VIAx.EN.0® Recommended enclosure by Mx or M1 is defined by either VIAx.EN.1® or VIAx.EN.2® .
VIAx.EN.1® Recommended enclosure by Mx or M1 to avoid high Rc.  0.03 0.00
VIAx.EN.2® Recommended enclosure by Mx or M1 [at least two opposite sides] to avoid high Rc.  0.05 0.03
Recommended maximum consecutive stacked VIAx layer, which has only one via for each
VIAx layer to avoid high Rc. (Except {LOWMEDN NOT (LOWMEDN SIZING -4 um)})
(Example: VIA1~VIA4, VIA2~VIA5, VIA3~VIA6, VIA4~VIA7. This rule does not apply to
VIAx.R.8®  4 -
top via. It is allowed to stack from VIA4 to VIA9 because VIA8 and VIA9 are top via. It is
allowed to stack more than four VIAx layers if two or more vias in each VIAx layer are on
the same metal.)
Mx.S.1® Recommended space to reduce the short possibility caused by particle  0.09 0.07
Mx.A.1® Recommended area to avoid high Rc (except DMx_O)  0.0351 0.027
Mx.EN.0® Recommended enclosure of VIAx-1 is defined by either Mx.EN.1® or Mx.EN.2® .
Mx.EN.1® Recommended enclosure of VIAx-1 to avoid high Rc.  0.03 0.00
Mx.EN.2® Recommended enclosure of VIAx-1 [at least two opposite sides] to avoid high Rc.  0.05 0.03
(A) For IP level, recommend metal density [window 40 μm x 40 μm, stepping 40 μm] 
1%. This item is applied for {IP NOT (IP SIZING -40um)} region when the width of IP is
 40um.
(B) For IP level, recommend maximum area of merged low density windows [checking
window 10umx10um, stepping 5um, density < 1%] ≤ 1600um2, except the merged low
density windows width ≤ 30um. This item is applied for {IP NOT (IP SIZING -10um)}
region when the width of IP is  10um.
Mx.DN.6®
(C) For IP level, recommend maximum area of merged low density windows [checking
window 10umx10um, stepping 5um, density < 1%] ≤ 4500um2. This item is applied for
- LOWMEDN
2. This rule is applied when the width of (checking window NOT above excluding region) is
 20um for (A) and  5um for both (B)/(C).
It is not recommended to have local density < 5% of all 3 consecutive metal (Mx, Mx+1
and Mx+2) over any 15um x 15um (stepping 15um) for IP level, i.e. it is allowed for either
one of Mx, Mx+1, or Mx+2 to have a local density ≥ 5%.
Mx.DN.7®
- LOWMEDN
3.These rules are applied when the width of (checking window NOT above excluding
region) is  7.5μm and for {IP NOT (IP SIZING -15um)} region when the width of IP is 
15um.
1. Mx width == 0.07um
Mx.DN.8®
3. Mx has two segments with space == 0.07um with the parallel run length (0.209 
parallel run length < 0.52)
It is important to insert the DMx & DVIAx uniformly to avoid white space. You should use
DMx.R.4® U tsmc standard backend utility to insert the backend dummy pattern. The usage of
DMxEXCL needs to be minimized.
Recommend dummy metal is not inserted between protection rings or in the breach of
LOWMEDN.R.8® U
protection ring. Please use DMxEXCL to aviod dummy metal insertion.
VIAy.EN.1® Recommended enclosure by Mx or My to avoid high Rc.  0.045 0
VIAy.EN.2® Recommended enclosure by Mx or My [at least two opposite sides] to avoid high Rc.  0.075 0.045
My.EN.0® Recommended enclosure of VIAy-1 is defined by either My.EN.1® or My.EN.2® .
My.EN.1® Recommended enclosure of VIAy-1 to avoid high Rc.  0.045 0
My.EN.2® Recommended enclosure of VIAy-1 [at least two opposite sides] to avoid high Rc.  0.075 0.045
Recommended Mz width [Mz on (((Mz-1 OR DMz-1) with space  5 um x 5 μm) SIZING 1
Mz.W.3®  0.42 0.40
μm)] for CMP dishing concern.
Recommended Mr width [Mr on (((Mr-1 OR DMr-1) with space  5 um x 5 μm) SIZING 1
Mr.W.3®  0.55 0.50
um)]
AP.W.2® U Recommended total width of BUS line [Connect with bump pad]  16 -
MOM.DN.1® Recommend metal density inside {MOMDMY_n SIZING 10um}. (For M1/Mx layers)  30% -
IND.DN.8® Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY  20% -
IND.DN.9® Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY  15% -
IND_MD.DN.8® Recommend {(OD OR DOD) OR SR_DOD} density inside INDDMY_MD  20% -
IND_MD.DN.9® Recommend {(PO OR DPO) OR SR_DPO} density inside INDDMY_MD  15% -
ROM.R.2® U Recommend to insert dummy PO between two ROM bits on different OD.
Each ROM cell must be covered by ROM(50;6).
ROM.R.3® DRC only flags no ROM(50;6) in the chip. But if there is no ROM cell in the chip, the
violation can be waived.
Density of DummyTCD (window 2000 μm X 2000 μm is one unit, see next page for more
DTCD.DN.1®  70% -
information)
ICOVL.S.1® Recommend OVL_PO_OD space to OVL_CO_PO  40
ICOVL.S.2® Recommend space between two OVL_PO_ODs or two OVL_CO_POs  2000
ICOVL.S.3® Recommend ICOVL (CAD layer no.: 165;3) space to {(OD OR PO) OR CO}  2
ICOVL.S.4® Recommend enclosed OD space inside OVL_PO_OD (maximum = minimum) = 1.1
ICOVL.S.5® Recommend space between two COs for OVL_CO_PO [in the same ring] = 0.10
ICOVL.W.1® Recommend width of PO ring inside ICOVL (maximum = minimum) = 1.1
ICOVL.W.2® Recommend width of M1 ring inside OVL_CO_PO (maximum = minimum) = 1.1
ICOVL.W.3® Recommend width of CO inside OVL_CO_PO (maximum = minimum) = 0.17
ICOVL.W.4® Recommend width of {OD INTERACT PO} inside OVL_PO_OD (maximum = minimum) = 16.5
ICOVL.W.5® Recommend PO hole width inside OVL_CO_PO (maximum = minimum) = 16.5
Recommend {OD INTERACT PO} enclosure by PO inside OVL_PO_OD (maximum =
ICOVL.EN.1® = 3.3
minimum)
ICOVL.EN.2® Recommend M1 ring enclosure by PO ring inside OVL_CO_PO (maximum = minimum) = 3.92
ICOVL.R.2® U Recommend the ICOVL patterns should be as uniform as possible over the chip
ICOVL.R.5® U
dividing chip Y (Floorplan A) / X (Floorplan B) direction into 8 segments for 2X1 die
ICOVL.R.6® U dividing chip Y (Floorplan A) / X (Floorplan B) direction into 8 segments for chip size for
2X1 die
ICOVL.R.7® Recommend at least 8 OVL_PO_ODs and 8 OVL_CO_POs for 1X1 die
ICOVL.R.8® Recommend at least 4 OVL_PO_ODs and 4 OVL_CO_POs for 1X2 die or 2X1 die
Recommend only one polygon is allowed in one chip for 1X1 die by {OVL_PO_OD SIZING
ICOVL.R.9®
+6500um}
Recommend only one polygon is allowed in one chip for 1X1 die by {OVL_CO_PO SIZING
ICOVL.R.10®
+6500um}
Recommend only one polygon is allowed in one chip 1X2 die or 2X1 die by {OVL_PO_OD
ICOVL.R.11®
SIZING +8000um}
Recommend only one polygon is allowed in one chip 1X2 die or 2X1 die by {OVL_CO_PO
ICOVL.R.12®
SIZING +8000um}
Recommend empty space between two OVL_PO_ODs for 1X1 die. DRC flags:
ICOVL.R.13®  16000
Recommend empty space between two OVL_CO_POs for 1X1 die. DRC flags:
ICOVL.R.14®  16000
Recommend empty space between two OVL_PO_ODs for 1X2 die or 2X1 die.
ICOVL.R.15® DRC flags:  13000
Recommend empty space between two OVL_CO_POs for 1X2 die or 2X1 die.
ICOVL.R.16® DRC flags:  13000
Recommend density of {(OVL_PO_OD SIZING +16500um) SIZING -15500um} for 1X1
ICOVL.R.17®  25%
die
Recommend density of {(OVL_CO_PO SIZING +16500um) SIZING -15500um} for 1X1
ICOVL.R.18®  25%
die
Recommend density of {(OVL_PO_OD SIZING +13000um) SIZING -10000um} for 1X2
ICOVL.R.19®  25%
die or 2X1 die
Recommend density of {(OVL_CO_PO SIZING +13000um) SIZING -10000um} for 1X2
ICOVL.R.20®  25%
die or 2X1 die
ICOVL.R.21® Recommend at least 1 OVL_PO_OD fully inside {Chip SIZING -2380um} for 2X2 die
ICOVL.R.22® Recommend at least 1 OVL_CO_PO fully inside {Chip SIZING -2380um} for 2X2 die
* CAD layer SENDMY (255;8) is used to check OD.DN.4® ~ OD.DN.9® for sensitive circuits. If your IP is sensitive to
the Isat variation due to low/high OD density, you can cover the SENDMY to perform this check.
9.2.3 Guidelines
The followings are guidelines regarding layout design practice, although they cannot be quantified. These
guidelines should be observed to their maximum in any circuit designs.
For OD, PO, VTL_N, VTL_P, VTH_N, VTH_P, ULVT_N, ULVT_P, DCO_LPP, NP, PP, M1, Mx, My, all vertices
G.6gU and intersections of 45-degree polygon must be on an integer multiple of 0.005 um except PO inside the layer
186;5 for GS/GL and 186;4 for LP/LPG.
Avoid small jogs (Figure 3.7.4).
OPC.R.2gU It is recommended to use greater than, or equal to, half of the minimum width of each layer for each segment of
a jog.
It is strongly suggested to limit the max interconnect length (M) to be as short as possible to avoid high Rs
OD.L.2gU
variation.
It is important to use the TSMC DOD/DPO utility to insert SR_DOD surrounding and close to the target device
SR_DOD.R.4gU
before characterization. The range of the SR_DOD  4um.
Recommend not using unintentional floating well to avoid unstable device performance. DRC flags {NW
NW.R.1g
OUTSIDE {N+OD INTERACT CO}}.
DNW.R.6gU Recommended not using floating RW unless necessary to avoid unstable device performance.
Recommended to use rectangle shape resistor for the SPICE simulation accuracy. DRC can flag {NWDMY
NWROD.R.3g
AND NW} is not a rectangle.
NWROD.R.8g Recommend: NWDMY intersecting NWROD forms two or more NWs.
NWRSTI.R.3g
DRC can flag {NWDMY AND NW} is not a rectangle.
NWRSTI.R.4g Recommend: NWDMY intersecting NWRSTI forms two or more NWs.
PO.L.1gU Recommend to limit the max interconnect PO length (R) as short as possible to avoid high Rs variation.
RES.R.15g DRC can flag {((RH AND OD) AND RPO) AND RPDMY} or {((RH AND PO) AND RPO) AND RPDMY} which is
not a rectangle.
{RPDMY AND {{OD INTERACT CO} AND RPO}} is recommended being identical to {RH AND {{OD
RES.R.16g
INTERACT CO} AND RPO}}, except BJTDMY.
{RPDMY AND {{PO INTERACT CO} AND RPO}} is recommended being identical to {RH AND {{PO INTERACT
RES.R.17g
CO} AND RPO}}
RES.R.18g Recommend: RPDMY intersecting {(OD AND RH) NOT INTERACT RPO} forms two or more ODs.
RES.R.19g Recommend: RPDMY intersecting {(PO AND RH) NOT INTERACT RPO} forms two or more POs.
RES.R.20g {CO BUTTED ((RPDMY AND RH) NOT INTERACT RPO)} is recommended.
Recommended to put contacts at both source side and butted well pickup side to avoid high Rs. DRC can flag
CO.S.6g
if the STRAP is butted on source, one of STRAP and source is without CO.
Recommended to put {CO inside PO} space to GATE as close as possible to avoid unexpected resistance
CO.R.1gU
variation.
Recommend using redundant CO to avoid high Rc wherever layout allows
1. Recommended to use double CO or more on the resistor connection.
2. Double CO on Poly gate to reduce the probability of high Rc
CO.R.5g 3. For large transistor, if it is impossible to increase the CO to gate spacing (CO.S.3® ), limit the number of
source/drain CO: have the number of CO necessary for the current, and then spread them uniformly all over
the Source/Drain area.
4. DRC can flag single CO.
Recommend using redundant vias to avoid high Rc wherever layout allows. (Except {LOWMEDN NOT
VIAx.R.9gU
(LOWMEDN SIZING -4 um)}) Please refer to section “Via Layout Recommendations”
Recommend using redundant vias to avoid high Rc wherever layout allows. Please refer to section “Via Layout
VIAy.R.9gU
Recommendations”
Recommend using redundant vias to avoid high Rc wherever layout allows.. Please refer to section “Via Layout
VIAz.R.5gU
Recommendations”
VIAr.R.5gU Recommend using redundant vias wherever layout allows.
Mx.R.2gU to reduce the wire capacitance and the possibility of metal short. Please refer to section 9.1.1 and TSMC
Reference Flow.
My.R.2gU
to reduce the wire capacitance. Please refer to section 9.1.1 and TSMC Reference Flow.
IND.R.15gU Recommend putting NT_N to fully cover the inductor (metal) region to achieve high quality factor.
9.2.4 Grouping Table of Recommendations

No. 1st priority to implement for yield and Systematic Defect Simulation
performance enhancement CMP Litho/OPC Others Accuracy
PO.EX.1® v v
PO.EX.2® v v
DNW.EN.1® v
OD.W.1® v
OD.S.1® v
OD.DN.4® v
OD.DN.5® v
OD.DN.6® v
OD.DN.7® v
OD.DN.8® v
OD.DN.9® v
DOD.R.4® v
NWROD.S.3® v
SR_DOD.S.3® v
SR_DOD.DN.1® v*
SR_DPO.S.1® v
SR_DPO.L.1® v
SR_DPO.L.3® v
SR_DPO.DN.1® v*
NWRSTI.EN.2® v
PO.W.1® U v v
PO.S.1® v
PO.S.2.LP® v v
PO.S.4.1® v v
PO.S.5.LP® v v
PO.S.5.GS® v v
PO.S.6.LP® v v
PO.S.6.GS® v v
PO.S.17® v v
PO.S.18.GS® v
PO.DN.4® v
PO.DN.5® v
PO.DN.6® v
PO.DN.7® v
PO.DN.8® v
PO.DN.9® v
ESDIMP.EN.1® v
HVD_N25.R.5® U v
HVD_P25.R.5® U v
HVD_N18.R.5® U v
HVD_P18.R.5® U v
HVD_GR.R.7® U v
CO.S.3® v v
CO.S.7® v
CO.EN.0® v v
CO.EN.1® v v
CO.EN.1.1® v v
CO.EN.3® v v
M1.S.1® v
M1.A.1® v v
M1.EN.0® v v v
M1.EN.1® v v v
M1.EN.2® v v v
M1.EN.5® v
M1.DN.6® v
VIAx.EN.0® v v v
VIAx.EN.1® v v v
VIAx.EN.2® v v v
VIAx.R.8® v
Mx.S.1® v
Mx.A.1® v v
Mx.EN.0® v v v
Mx.EN.1® v v v
Mx.EN.2® v v v
Mx.DN.6® v
Mx.DN.7® v
Mx.DN.8® v*
DMx.R.4® U v v
LOWMEDN.R.8® U v v
VIAy.EN.1® v v v
VIAy.EN.2® v v v
My.EN.0® v v v
My.EN.1® v v v
My.EN.2® v v v
Mz.W.3® v
Mr.W.3® v
AP.W.2® U v v
MOM.DN.1® v v
IND.DN.8® v v
IND.DN.9® v v
IND_MD.DN.8® v v
IND_MD.DN.9® v v
PO.S.14.GSm® v v v
PO.S.14.LPm® v v v
PO.EN.1.GSm® v v v
PO.EN.1.LPm® v v v
PO.EN.2.GSm® v v v
PO.EN.2.LPm® v v v
PO.EN.3.GSm® v v v
PO.EN.3.LPm® v v v
PO.S.5m® v v
PO.S.6m® v v
PO.S.6.1m® v v
PO.EX.1m® v v
BJT.R.2® v
BJT.R.7® v v
DTCD.DN.1® v v
ICOVL.S.1® v v
ICOVL.S.2® v v
ICOVL.S.3® v v
ICOVL.S.4® v v
ICOVL.S.5® v v
ICOVL.W.1® v v
ICOVL.W.2® v v
ICOVL.W.3® v v
ICOVL.W.4® v v
ICOVL.W.5® v v
ICOVL.EN.1® v v
ICOVL.EN.2® v v
ICOVL.R.2® U v v
ICOVL.R.3® U v v
ICOVL.R.4® U v v
ICOVL.R.5® U v v
ICOVL.R.6® U v v
ICOVL.R.7® v v
ICOVL.R.8® v v
ICOVL.R.9® v v
ICOVL.R.10® v v
ICOVL.R.11® v v
ICOVL.R.12® v v
ICOVL.R.13® v v
ICOVL.R.14® v v
ICOVL.R.15® v v
ICOVL.R.16® v v
ICOVL.R.17® v v
ICOVL.R.18® v v
ICOVL.R.19® v v
ICOVL.R.20® v v
ICOVL.R.21® v v
ICOVL.R.22® v v
G.6gU v
OPC.R.2gU v
OD.L.2gU v
SR_DOD.R.4gU v
NW.R.1g v v
DNW.R.6gU v v
NWROD.R.3g v
NWROD.R.8g v
NWRSTI.R.3g v
NWRSTI.R.4g v
PO.L.1gU v v
RES.R.15g v
RES.R.16g v
RES.R.17g v
RES.R.18g v
RES.R.19g v
RES.R.20g v
CO.S.6g v v
CO.R.1gU v
CO.R.5g v v v
VIAx.R.9gU v v v
VIAy.R.9gU v v v
VIAz.R.5gU v v v
VIAr.R.5gU v v v
Mx.R.2gU v v
My.R.2gU v v
IND.R.15gU v v
ROM.R.2® U v v
ROM.R.3® v*
M1.EN.0® : Recommended enclosure of CO is defined by either M1.EN.1® or M1.EN.2® .
VIAx.EN.0® : Recommended enclosure by Mx or M1 is defined by either VIAx.EN.1® or VIAx.EN.2® .
Mx.EN.0® : Recommended enclosure of VIAx-1 is defined by either Mx.EN.1® or Mx.EN.2® .
VIAy.EN.0® : Recommended enclosure by Mx or My is defined by either VIAy.EN.1® or VIAy.EN.2® .
My.EN.0® : Recommended enclosure of VIAy-1 is defined by either My.EN.1® or My.EN.2® .
*: For chip level.
9.3 GDA Die Size Optimization Kit

 Gross Die Advisor (GDA) is to optimize die size x-y for higher mask field utilization (MFU) and gross die
(GD) while keep chip area as constant.
 The function of GDA is based on user input die size, scribe line width and TSMC generic fabrication
conditions to recommend a list of other die size combinations (X / Y) with higher gross die and MFU.
Based on GDA result, user can survey the advised numbers to adjust your die size in the early design
phase.
 Use GDA function from TSMC on-line
 TSMC On-line Directory: Home/Design Portal 2.0/Technology Selection (GDA)/Gross Die Advisor
(MFU calculator)
9.3.1 What is MFU?

 Mask Field Utilization (MFU) is a ratio of mask utilized region which is calculated by (multiple die area+
scribe_line area) / (scanner maximum field area). (Fig. 9.3.1.1)
 Low MFU implies low scanner productivity at whole lithography layers. It is important to improve MFU as
possible as you can. MFU > 80% is strong recommended.
Figure 9.3.1.1 Example of MFU
9.3.2 Design Guidelines for Higher MFU

 Before design:
 Square shape digital block and IP is preferable.
 For rectangle shape IP, provide 2 orientation types of the same IP with keeping core PO gate in
vertical direction. For example, left/right type IO and top/bottom type IO or horizontal and vertical
type IP shapes.
 Use “Quick MFU Calc” (download from reference flow package) in floorplan design phase.
 Avoid chip size at the borderline with low MFU, and it is strongly recommended to adjust the chip
dimension for higher MFU.
 Design is at floorplan stage or floorplan is done:
 Core limited design: IP and blocks size and floorplan adjustment may be needed
 I/O limited design: I/O and interface IP adjustment may be needed
9.3.3 Recommended GDA criteria MFU > 80%

 The benefits from GDA:
 Based on the advised die sizes to adjust your chip dimension to gain high MFU and more gross die.
9.3.4 MFU Reference Table for N45
9.3.5 MFU Reference Table for N40
10 Layout Guidelines for Latch-Up and I/O

ESD
This chapter consists of the following two sections:
10.1 Layout rules and guidelines for latch-up prevention
10.2 I/O ESD protection circuit design and layout guideline
Uses and Limitations of latch-up rules:

The Latch-up rules/guidelines are for design reference to achieve the target proposed by TSMC (JESD 78D).
There are no specification or guaranteed levels for final chip/product qualifications, since Latch-up immunity is
absolutely layout and circuit design dependent, including over-driven and substrate bias conditions, floating
body circuits, SCR ESD IPs, and so on. Therefore, product latch-up validation is must before mass production.
Also, note that these rules/guidelines do not cover the conditions such as power surge test, electrical fast
transient test, high-level current injection by inductance load, cable discharge event, transient Latch-up by
special function request or by system-level ESD test, etc.
Uses and Limitations of ESD guideline:

These ESD design guidelines are for reference only, and do not provide specification or guaranteed levels
of product performance and system level ESD. It is believed that ESD devices, which passed device-level ESD
testing, do not guarantee a particular circuit using that device will survive ESD qualifications. Product ESD
validation is must before mass production.
In addition to the dedicated ESD protection device, the final chip/product ESD levels depend on the follows:
1. The normal functional devices in parallel (whose immunity and gate bias during ESD rely on the specific
circuit design),
2. The power clamp protection cell/network, interface, the separation of high (Vdd, Vcc) and low (Vss, GND)
power supply pads/groups,
3. The floor plan/metal bus routing and current density (endurance) of the backend interconnection's design.
Note that TSMC won't review the customer's chip design, so TSMC can not guarantee the customer's success.
Also, product ESD validation is must before mass production.
10.1 Layout Rules and Guidelines for Latch-up

Prevention
10.1.1 Latch-up Introduction
In explaining the Latch-up, the equivalent circuit of the parasitic components of CMOS inverter is shown in
Figure 10.1.1.1. When the signal at the output node is 0.7V higher than the Vdd (overshooting), the bipolar
VT2 may be turned on first and, similarly, the bipolar LT2 will be turned on while the output signal is lower
than –0.7V (undershooting). For the fact that the collector of each BJT (i. e. Vt2) plays the role as base of the
other transistor (i. e. LT2) and the collected carriers will reduce the potential difference between emitter and
base of the transistor (LT2). Under this situation, the LT2 may be turned on and the collect current of the LT2
will feedback to VT2 at the same time. The positive feedback loop will make the concentration of minority
carrier increased to higher than the doping concentrations of both the NW and PW (Figure 10.1.1.2).
Subsequently, the potential barrier between NW and PW will be disappeared and then obtains a highly
conductivity path between Vdd and Vss. This may result in the circuit malfunction, and destroy the device in
the worst case.
Vin
Vout Vdd Overshoot
Vss Vdd
0V
undershoot
P+ N+ N+ P+ P+ N+
NW
RNW
PW
RpW
LT1 LT2 VT2 VT1
P-sub
Fig. 10.1.1.1 Lump element model for an inverter before latch-up
N+
P+
N+ zzzzz
P+ b.
a. N+
zzzzz
ity
zzzzz
N+zzzzz P+ zzzzz
on ctiv
P+ zzzzz
zzzzz
zzzzz
re n d u
zzzzz zzzzz zzzzz .
zzzzz zzzzz zzzzz
o
gi
zzzzz.
yc
zzzzz . . NW
av
zzzzz . zzzzz
He
PW .
. .
.
Fig. 10.1.1.2 Hole concentration (a) before latch-up, (b) after latch-up
The latch-up trigger sources often come from the IO Pad, but both IO circuits and internal circuits might cause
a latch-up if the layout does not follow the latch-up design rules. The following lists the latch-up failure cases
caused by layout rule violations.
Fig. 10.1.1.3 LUP.1 rule violation: (IO without guard-ring)
Fig. 10.1.1.4 LUP.2 rule violation:

(Within 15um from IO, N/PMOS in the internal circuit without the guard-ring)
Fig. 10.1.1.5 LUP.3 rule violation: (IO N/PMOS spacing is too small)
10.1.2 Layout Rules and Guidelines for Latch-up

Prevention
10.1.2.1 Special Definition in Latch-up Prevention
Term Definition
I/O pads Do not include Vdd pad and Vss pad.
Internal circuit Include NMOS, PMOS, de-coupling capacitors and varactor that do not connect to an IO pad.
Complete un-broken ring-type OD and M1 with CO as many as possible, connected to Vdd or
Guard-ring
Vss.
Complete un-broken ring-type (NP AND OD) and M1 with CO as many as possible,
N+ guard-ring
connected to Vdd.
Complete un-broken ring-type (PP AND OD) and M1 with CO as many as possible, connected
P+ guard-ring
to Vss.
Guard-band Band-type OD and M1 with CO as many as possible, connected to Vdd or Vss.
N+ guard-band Band-type (NP AND OD) and M1 with CO as many as possible, connected to Vdd.
P+ guard-band Band-type (PP AND OD) and M1 with CO as many as possible, connected to Vss.
NMOS cluster A group of NMOSs
PMOS cluster A group of PMOSs
Any OD directly connected to I/O pad. Ex. MOS, HIA diode, diode string (DRC uncheckable),
OD resistor, and well resistor directly connected to I/O PAD.
OD injector
N+ OD directly connected to I/O pad is N+ OD injector.
P+ OD directly connected to I/O pad is P+ OD injector.
Core MOS/OD injector MOS/OD injector NOT INTERACT OD2
1.5V/1.8V MOS/OD
(MOS/OD injector INTERACT (OD_18 OR OD25_18) NOT INTERACT (HVD_N OR HVD_P))
injector
((MOS/OD injector INTERACT OD_25) NOT INTERACT (OD25_18 OR OD25_33) NOT
2.5V MOS/OD injector
INTERACT (HVD_N OR HVD_P))
3.3V MOS/OD injector MOS/OD injector INTERACT (OD_33 OR OD25_33)
5V MOS/OD injector MOS/OD injector INTERACT ((HVD_N OR HVD_P) OR DEHVD_N)
P+ guard-ring N+ guard-ring
NMOS NMOS PMOS PMOS
NMOS NMOS PMOS PMOS
NMOS cluster: A group of NMOSs PMOS cluster: A group of PMOSs
Fig. 10.1.2.1 Example of an NMOS cluster and a PMOS cluster
10.1.2.2 Latch-up Dummy Layers Summary

10.1.2.2.1 LUPWDMY Dummy Layer (CAD layer: 255;1)
LUPWDMY is a dummy layer to waive these rules, LUP.1, LUP.2, LUP.3.1.1~2, LUP.3.2.1~2, LUP.3.3.1~2,
LUP.3.4.1~2, LUP.3.5.1~2, LUP.4, LUP.5.1.1~2, LUP.5.2.1~2, LUP.5.3.1~2, LUP.5.4.1~2 and LUP.5.5.1~2.
Condition:
It is not recommended to use this layer before silicon is proven at the package.
Please consult TSMC if you would like to follow it as rules and have DRC violations before tapeout.
Usage:
Draw LUPWDMY to fully cover OD injector, including the source, gate, drain, and diode, but not
necessarily to cover Well STRAP, guard-ring.
It is for DRC usage but not a tapeout required CAD layer.
NP/PP
OD
LUPWDMY
Source Drain
PO Guard ring
Fig. 10.1.2.2.1 Example of LUPWDMY
10.1.2.2.2 LUPWDMY_2 Dummy Layer (CAD layer: 255;18)

“LUPWDMY_2 (255;18)” is a DRC dummy layer to trigger the area I/O latch-up rules check.
Please refer to 10.1.2.5 for detailed AAIO I/O latch-up rule introduction.
Usage:
Draw a LUPWDMY_2 pattern to fully cover the OD injector of the area IO cells, including the source, gate,
drain, and diode. However it is not necessary to cover the Well STRAP, or guard-ring.
P+ pick-up ring
OD
PO
N+ active
NP
PP
LUPWDMY_2 (255; 18) needs to cover AAIO OD injector

Figure 10.1.2.2.2 Example of LUPWDMY_2 Usage
10.1.2.2.3 RES200 Dummy Layer (CAD layer: 255;9)

RES200 is a DRC dummy layer and is used to recognize a resistor with resistance larger than 200 ohm. If the
resistance of used resistors between PAD and the OD injector is larger than 200 ohm, the dummy layer
RES200 (255;9) should be covered on the resistor.
 Latch-up rules’ checking connection will be broken by resistors with RES200 layers.
RES200 RES200
Poly RES. Poly RES.
RPDMY RPDMY
Figure 10.1.2.2.3
10.1.2.3 DRC methodology for Latch-up Rules

10.1.2.3.1 Overview
The critical point in correctly checking lathcup design rules is to accurately recognize OD injector (OD directly
connected to I/O PAD) and VDD/VSS PADs (for potential parasitic SCR [silicon-controlled rectifier] path). With
additional designer input, the accuracy may be improved with the use of optional DRC switches, dummy
layerers, and/or pin texts.
Section 10.1.2.3 covers different aspect of DRC methodology in its sub-sections. They are:
(1) 10.1.2.3.2 General DRC methodology for PAD type
This covers how DRC deck is able to recognize different PAD types (VDD/VSS/IO).
(2) 10.1.2.3.3 General DRC methodology for I/O pad connectivity
This covers how OD injector is recognized with the use of resistor connecting to I/O PAD. RES200
usage and LUP DRC switch for resistor is covered.
(3) 10.1.2.3.5~10.1.2.3.8 DRC methodology for LUP.x
These sub-sections cover DRC methodology for selected LUP design rules.
10.1.2.3.2 General DRC methodology for PAD type

DRC use the following features to distinguish Power and I/O PAD:
1. By default, DRC will recognize power PAD according to the connectivity of AP, CB, CB2, and UBM to
STRAP (except VAR, NW resistor).
2. DRC will also recognize PAD with “power dummy layer” as power PAD.
I. VDDDMY(255;4): Dummy Layer for Power(Vdd) PAD
II. VSSDMY(255;5): Dummy Layer for Ground(Vss) PAD
3. Alternatively, with corresponding DRC switch turned-on manually, DRC will recognize PAD with
“power text” as power PAD.
I. Control by the switch of #DEFINE_PAD_BY_TEXT. The switch is off by default.
II. Default power text name is “VDD?” “VSS?”
4. All other unrecognized PADs through step 1~3 are I/O PAD.
OD OD
PO VDDDMY PO
IO Metal
Metal VDD Metal
Metal
PAD PAD
OD OD
PO PO
VDD Metal
Metal
Metal NW strap
VSS Metal
VSS
Metal
PAD PAD
“VSS” is a top level text attached on metal, and

DEFINE_PAD_BY_TEXT option is turned on in DRC
OD
PO
PAD Check LUP.1~5 in Cell level without PAD

Metal
Metal 1. Attach top-level text on metal. E.g. “PAD”
2. Turn on DEFINE_PAD_BY_TEXT option.
Figure 10.1.2.3.2
10.1.2.3.3 General DRC methodology for I/O pad connectivity

 DRC use the following features to check the device connectivity to I/O pad (OD injector recognition):
1. Build-up the connection by Metal, Via, RV, AP, CB, CB2, and UBM
2. Latch-up risk of the junction/OD connects to pad through a resistor:
a. If R >= 200 ohm.  low latch-up risk (as internal circuit)
b. If R <= 50 ohm. High latch-up risk (as OD injector)
c. If 50ohm <R<200ohm design dependent..
RES200 CAD layer is required for recognizing the resistance. If R>200 ohm, the dummy layer
RES200 (255:9) should cover the resistor to disable LU check (because latch-up risk is low).
3. There are two DRC switches and one required CAD layer (RES200 layer) related to the resistor in
series: "DISCONNECT_ALL_RESISTOR" (1st DRC switch; default OFF),
"CONNECT_ALL_RESISTOR" (2nd DRC switch; default OFF), and RES200 CAD layer (manually
placed).
Only one of the "DISCONNECT_ALL_RESISTOR" and "CONNECT_ALL_RESISTOR" can be
turned ON when in actual use or both DRC switches should be OFF (default). If both DRC switch are
turned ON, "DISCONNECT_ALL_RESISTOR" will now be the override setting (LUP.WARN.1).
Below are possible scenarios for their interactions in between:
1. Consider resistance (default) to recognize circuits behind resistor:
(R<200ohm) => Set both switches to OFF and W/O RES200, circuits after resistor will be
recognized as OD injector.
(R>=200ohm) => Set both switches to OFF and the R>=200ohm resistor is covered by RES200
layer, circuits after resistor will NOT be checked
2. Neglect circuits behind resistor
 Set "DISCONNECT_ALL_RESISTOR" to ON, all circuits after resistor will NOT be recognized
as OD injector (RES200 layer is irrelevant this scenario.)
3. Check circuits behind resistor
 Set "CONNECT_ALL_RESISTOR" to ON, all circuits after resistor will be recognized as OD
injector (RES200 layer is irrelevant this scenario.)
A OD
RES200
B OD
PO
RES.
PO
RPDMY
IO Metal
PAD C OD
PO
RES.
RPDMY
Figure 10.1.2.3.3
Table 10.1.2.3.3
DRC deck setup

A/B/C in Fig. 10.1.2.3.3
Default
Turn ON Turn ON
OD injector or Internal (DISCONNECT_ALL_RESISTOR: OFF)
DISCONNECT_ALL_RESISTOR CONNECT_ALL_RESISTOR
circuit (CONNECT_ALL_RESISTOR: OFF)
A OD injector OD injector OD injector

B Internal circuit Internal circuit OD injector
C OD injector Internal circuit OD injector
10.1.2.3.4 DRC methodology for LUP.1

DRC use the following features to find out the devices for LUP.1:
OD injector means that any OD is directly connected to I/O pad.
Ex. MOS, STI diode (STI bonded), OD resistor, and well resistor directly connected I/O PAD.
1. The following cases is excluded :
I. The OD injector is covered by LUPWDMY (255;1).
2. The guard ring can not be shared by different type devices.

DRC use the following features to find out the devices for LUP.2:
1. The MOS OD within 15um space from OD injector for LUP.1 check
2. The following cases are excluded:
I. The MOS OD is floating without any contact over gate and S/D.
II. The OD injector is covered by LUPWDMY (255;1)
III. The NMOS is inside DNW, and the NW over DNW is not the same as the NW of relative PMOS,
but these two NWs are connected.
M1
III.
NW
DNW
NMOS PMOS
Fig. 10.1.9 example of LUP.2 III
10.1.2.3.6 DRC methodology for LUP.3 group

DRC use the following features to find out the devices for LUP.3 group:
1. Find out the OD injector for LUP.1 check
2. The following cases are excluded:
I. The excluded case in LUP.1.
II. The NMOS is inside DNW, and the NW over DNW is not the same as the NW of relative PMOS,
but these two NWs are connected.

DRC use the following features to check the guard-ring width.
1. Find out the OD injector for LUP.1 and LUP.2 check.
2. The devices should be placed inside a complete guard-ring with width ≥ 0.12um.
Fail ≥ 0.12um
Fail ! ≥ 0.12um
! OD
NW
OD PMOS NW
PMOS
< 0.12um
Pass
Pass ≥ 0.12um ≥ 0.12um
!
! OD < 0.12um
OD ≥ 0.12um
PMOS PMOS
PMOS PMOS
NW NW
Fig. 10.1.10 example of LUP.4
10.1.2.3.8 DRC methodology for LUP.5 group

DRC use the following features to find out the devices for LUP.5 group:
1. Find out the OD injector for LUP.1 and LUP.2 check.
2. The excluded cases are “I”, “II”, and “III” in LUP.2.
10.1.2.4 Layout Rules and Guidelines for Latch-up

Prevention
The LUP rules are for design reference to achieve the specifications proposed by TSMC. They are
extracted by the standard digital I/O and Area I/O test structures. Note that Latch-up free can not be
guaranteed for all applications such as substrate bias condition, floating body circuits, SCR ESD IPs, and etc.
You can refer to section 10.1.2.3 to understand DRC methodology for Latch-up Rules in detail.
For 5V application, the DRC only check the related latch-up for 5V HVMOS device. Please see section
10.1.2.1 for details.
All pickup ring, gurad ring, and straps described in TSMC LUP rules are required to have appropriate
direct connection to corresponding VDD/VSS with minmum resistance. If any pickup ring, gurad ring, and
straps does not have proper connection and with minimum connection resistance, LUP risk may rise
significantly.
DRC LUP switch setting conflict detected (refer to section 10.1.2.3.3 for details):
Please follow one of the following LUP switch settings:

1. [Default setting: RES200 usage] Turns off both "DISCONNECT_ALL_RESISTOR", and
"CONNECT_ALL_RESISTOR": circuits after RES200 will NOT be recognized as OD injector, or
2. Turns on "DISCONNECT_ALL_RESISTOR" only: circuits after any resistor will NOT recognized as OD
LUP.WARN.1
injector, or
3. Turns on "CONNECT_ALL_RESISTOR" only: circuits after any resistor will always be recognized as OD
injector
Please DO NOT turn on both "DISCONNECT_ALL_RESISTOR", and "CONNECT_ALL_RESISTOR" at the same

time, otherwise “DISCONNECT_ALL_RESISTOR” will have higher priority
Any N+ OD injector or an N+ OD injector cluster must be surrounded by a P+ guard-ring. (Figure 10.1.2.4.1)
Any P+ OD injector or a P+ OD injector cluster connected to an I/O pad must be surrounded by a N+ guard-ring.
LUP.1
(Figure 10.1.2.4.1)
Please also refer to LUP.9g for further information.
Within 15um (≤15um) space from the OD injector, a P+ guard-ring is required to surround an NMOS or an NMOS
cluster. And an N+ guard-ring is required to surround a PMOS or a PMOS cluster. (Figure 10.1.2.4.3 and 10.
1.2.4.5)
LUP.2 Rule exclusion: LUP.2 does not apply to NMOS in DNW if both of the following conditions are true (Fig.
10.1.2.4.2):
1. NMOS is inside DNW with voltage (Va) ≥ PMOS NW voltage (Vb).
2. NMOS DNW doesn’t physically interact with PMOS NW.
However, DRC can only flag the different connection.
Within 15um (≤15um) space from the OD injector, a NW in proximity to another NW with different potential and one
LUP.2.1U P+OD was enclosed by the relative higher potential NW, a P+ STRAP is required to be inserted between these
NWs. (Figure 10.1.2.4.5)
LUP.3.x can be exempted from the following conditions (Figure 10.1.2.4.2):
1. NMOS is inside DNW with voltage (Va) ≥ PMOS NW voltage (Vb)
LUP.3.0
In LUP.3.1.1 and LUP.3.1.2 for the N/PMOS which connects to an I/O pad, space between the core PMOS and the
LUP.3.1.0
NMOS. (Figure 10.1.2.4.1),
LUP.3.1.1 if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1) A ≥ 2
LUP.3.1.2 if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1) A ≥ 3
In LUP.3.2.1 and LUP.3.2.2, for the N/PMOS which connects to an I/O pad directly, space between the 1.8V/1.5V
LUP.3.2.0
PMOS and the NMOS. (Figure 10.1.2.4.1)
LUP.3.2.1 if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1) A ≥ 2.3
In LUP.3.3.1 and LUP.3.3.2, for the N/PMOS which connects to an I/O pad directly, space between the 2.5V
LUP.3.3.0
PMOS and the NMOS. (Figure 10.1.2.4.1)
LUP.3.3.1 if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1) A ≥ 2.6
In LUP.3.4.1 and LUP.3.4.2, for the N/PMOS which connects to an I/O pad directly, space between the 3.3V
LUP.3.4.0
PMOS and the NMOS (Figure 10.1.2.4.1)
In LUP.3.5.1 and LUP.3.5.2, for the N/PMOS which connects to an I/O pad directly, space between the 5V PMOS
LUP.3.5.0
and the NMOS. (Figure 10.1.2.4.1)
Width of the N+ guard-ring and P+ guard-ring for the OD injector, and also MOS within 15um space from the OD
LUP.4 B ≥ 0.12
injector. (e. g. width of guard-ring of LUP.1 and LUP.2) (Figure 10.1.2.4.1)
LUP.5.x (except LUP.5.6.x) can be exempted from the following conditions (Figure 10.1.2.4.2):
1. NMOS is inside DNW with voltage (Va) ≥ PMOS NW voltage (Vb)
LUP.5.0
In LUP.5.1.1 and LUP.5.1.2 for the internal circuits within 15um space from OD injector,
LUP.5.1.0 (1) space between the N+OD injector and the core PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the core P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
LUP.5.1.1 if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2) C ≥ 2
LUP.5.1.2 if one of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2) C ≥ 3
LUP.5.2.0 (1) space between the N+OD injector and the 1.8V/1.5V PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the 1.8V/1.5V P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
LUP.5.2.1 if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2) C ≥ 2.3
LUP.5.3.0 (1) space between the N+OD injector and the 2.5V PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the 2.5V P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
LUP.5.3.1 if all of guard-ring width ≥ 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2) C ≥ 2.6
LUP.5.4.0 (1) space between the N+OD injector and the 3.3V PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the 3.3V P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
LUP.5.5.0 (1) space between the N+OD injector and the 5V PMOS in the internal circuit (Figure 10.1.2.4.3)
(2) space between the 5V P+OD injector and the NMOS in the internal circuit (Figure 10.1.2.4.3)
LUP.5.5.2 if all of guard-ring width < 0.2um (e. g. width of guard-ring of LUP.1 and LUP.2) C ≥ 15
Space between the P+ OD injector and NW if the P+ OD injector in proximity to another NW are in different
potential, (low potential related to P+ OD injector) need to follow LUP.5.6.1U ~4U:
LUP.5.6.0U
The guard ring and STRAP width between P+ OD injector and NW should be as larger as possible. (Figure
10.1.2.4.3)
LUP.5.6.1U If the voltage potential difference is > 0V, and ≤ 1.8V C1 ≥ 6
LUP.5.6.2U If the voltage potential difference is > 1.8V, and ≤ 2.5V C1 ≥ 10
LUP.5.6.3U If the voltage potential difference is > 2.5V, and ≤ 3.3V C1 ≥ 15
If the voltage potential difference is > 3.3V, and ≤ 5V
LUP.5.6.4U C1 ≥ 20
Please consult TSMC if the voltage potential difference is > 5V.
1. Any point inside NMOS source/drain {(N+ ACTIVE INTERACT PO) NOT PO} space to the nearest PW
STRAP in the same PW. (Figure 10.1.2.4.4)
2. Any point inside PMOS source/drain {(P+ ACTIVE INTERACT PO) NOT PO} space to the nearest NW
LUP.6 D ≤ 30/40
STRAP in the same NW. (Figure 10.1.2.4.4)
In SRAM bit cell region, the rule is relaxed from 30um to 40um.
[In logic region/ In SRAM bit cell region]
For the NW and PMOS within 15 μm space from OD injector,
LUP.7.6.0U space between the P+ OD of PMOS and NW if the P+ OD in proximity to another NW are in different potential,
(low potential related to P+ OD) need to follow LUP.7.6.1U ~4U.(Figure 10.1.2.4.5)
LUP.7.6.1U If the voltage potential difference is > 0V, and ≤ 1.8V E1 ≥ 6
LUP.7.6.2U If the voltage potential difference is > 1.8V, and ≤ 2.5V E1 ≥ 10
LUP.7.6.3U If the voltage potential difference is > 2.5V, and ≤ 3.3V E1 ≥ 15
If the voltage potential difference is > 3.3V, and ≤ 5V
LUP.7.6.4U E1 ≥ 20
Please consult TSMC if the voltage potential difference is > 5V.
Additional one N+ STRAP and one P+ STRAP are required to be inserted between the P+ guard-ring and N+
guard-ring for LUP.1 (Figure 10.1.2.4.1).
LUP.9gU
1. NW STRAP should isolate the PW STRAP and the P+ guard-ring (P+ pick-up ring).
2. PW STRAP should isolate the NW STRAP and the N+ guard-ring (N+ pick-up ring).
Vss Vdd
A
P+ N+ N+ P+ N+ P+ N+ P+ P+ N+
STRAP STRAP
NMOS PMOS
PW NW PW NW
P+ guard-ring N+ guard-ring
P+ guard-ring (Vss) N+ guard-ring (Vdd)

B B
B B
N+ P+
STRAP STRAP
(Vdd) (Vss)
NMOS
PW NW
To exchange N+ STRAP and P+ STRAP not recommended (LUP.9g U)
Figure 10.1.2.4.1
If the NW of the checked

NW PMOS interacts with the
DNW DNW, the space needs to
follow A or C.
NMOS
A A
C C
PMOS PW PMOS
If voltage Va ≥ Vb,
the space can be < A or < C
Vb Va
NW NW
DNW
PW
P+
STRAP
NMOS
PMOS
N+STRAP (N+ guard ring) N+STRAP
Guard ring is not necessary Va ≥ Vb,

Vb Vb Va but P+ STRAP is still required.
Vd
P+ N+ P+ P+ N+ N+ N+ N+ P+ N+
PW d
NW
PW NW NW
PW
Guard ring Guard ring and P+ STRAP

follow A or C. DNW
Guard ring and P+ STRAP are
For LUP.2, LUP.3.1.1~2, LUP.3.2.1~2,not necessary ifLUP.3.4.1~2,
LUP.3.3.1~2, Va >= Vb. LUP.3.5.1~2, LUP.5.1.1~2,
LUP.5.2.1~2, LUP.5.3.1~2, LUP.5.4.1~2, LUP.5.5.1~2, if voltage Va ≥ Vb, the above rules allow that
the NMOS is enclosed by a DNW and the NW of the checked PMOS does not interact with the DNW.
Figure 10.1.2.4.2
P+ guard-ring Vss
NW Voltage potential is lower than P+ OD injector

B
C1
C ≤15um
B B B B B B B B
N+guard-ring(Vdd)
P+ guard-ringVss)
P+ guard-ringVss)
N+guard-ring(Vdd)
P+ guard-ringVss)
N+guard-ring(Vdd)
N+ strap(Vdd)
P+ strap(Vss)
A C
Active connects to IO pads directly Internal circuit
Figure 10.1.2.4.3 Latch-up prevention design for LUP.3.x, LUP.4, LUP.5.x
D D
N+ S TRAP
N+ S TRAP
Nwell
P+ STRAP
P + S TRAP
D D
Pwell
N+ S TRAP
N+ S TRAP
Nwell
P + S TRAP
P+ STRAP
P+ OD
Pwell
Figure 10.1.2.4.4 Latch-up prevention design for LUP.6
15um
PMOS NW PW
N+ guard ring P+ guard ring
PMOS NW PW NMOS
N+ guard ring P+ guard ring
E1
NW
15um
OD 15um
Injector
Figure 10.1.2.4.5 Latch-up prevention design for LUP.2, LUP.2.1, and LUP.7.6.x
10.1.2.5 Layout Rules and Guidelines for Area I/O(AAIO)

Latch-up Prevention
To increase the number or density of I/Os in VLSI designs, the area-I/O(AAIO) is adopted to achieve a smaller package
size (such as flip-chip), shorter wire length, better signal and power integrity. However, an external injection of minority
carriers from an Area IO cell can trigger a latchup event easily in the parasitic pnpn path of the surrounding CMOS circuits
in the chip’s core area. The Area I/O cell is different from the peripheral type I/O ring (example Fig.10.1.20), it does not
have pre-driver structure between the post driver (carrier injector) and the core CMOS circuits, which can help absorb the
substrate currents or carriers from an external injection. The AAIO latch-up rules need to be applied to the IO cells put in
chip center and next to internal circuit as shown in Fig. 10.1.2.5.1 and Fig 10.1.2.5.2, Fig 10.1.2.5.1~10.1.2.5.4 show the
schematic diagram of the Area I/O structure.
AAIO latchup DRC enablement:

1) Marker CAD layer based (Regard specific IO which covered by LUPWDMY_2 as AAIO only):
“LUPWDMY_2 (255;18)” is a DRC dummy layer to trigger the AAIO latch-up rules check.
Usage:
Draw a LUPWDMY_2 pattern to fully cover the OD injector. However it is not necessary to cover the Well
STRAP, or guard-ring. (Fig 10.1.2.5.3)

For Area I/O, within 75 μm(≤75um, label “A” in Fig. 10.1.2.5.1) sizing of the OD injector A
(covered by LUPWDMY_2), specific guard rings/guard bands rules and N/P wells
STRAP rules (LUP.11~LUP.14) should be followed to enhance latch up immunity. (Fig
10.1.2.5.1)
LUP.10
Exclusive conditions:
If the spacing between the N+ OD and P+ OD of the core CMOS circuits ≥ 3 μm (Label
“F” in Fig 10.1.2.5.1).
LUP.11U For Area I/O, the minimum total width of the P+ guard band (Fig 10.1.2.5.1) B ≥ 2
LUP.12U For Area I/O, the minimum total width of the N+ guard band (Fig 10.1.2.5.1) C ≥ 2
LUP.13 For Area I/O, D ≤ 15
1. Any point inside NMOS source/drain {(N+ ACTIVE INTERACT PO) NOT PO} space
to the nearest PW STRAP in the same PW. (Figure 10.1.2.5.2)
2. Any point inside PMOS source/drain {(P+ ACTIVE INTERACT PO) NOT PO} space
to the nearest NW STRAP in the same NW. (Figure 10.1.2.5.2)
3. The height of pick-up OD is recommended to be equal to that of source/drain ODs.
LUP.14 For Area I/O, E ≥ 0.2
N+OD injector must be surrounded by P+ guard-ring (P+ pick-up ring).
P+OD injector must be surrounded by N+ guard-ring (N+ pick-up ring).
The PW of N+OD injector must be surrounded by N+ guard-ring.
The NW of P+OD injector must be surrounded by P+ guard-ring.
And all of the guard ring widths >= 0.2
Figure 10.1.2.5.1 Area I/O latchup prevention
D D
N+ S TRAP
N+ S TRAP
Nwell
P+ STRAP
P + S TRAP
D D
Pwell
N+ S TRAP
N+ S TRAP
Nwell
P + S TRAP
P+ STRAP
P+ OD
Pwell
Figure 10.1.2.5.2
OD
LU PW D M Y_2
Figure 10.1.2.5.3 Example of LUPWDMY_2 Usage
PAD PAD PAD PAD PAD PAD PAD PAD PAD PAD
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PAD PAD PAD PAD
Peripheral
IO
PAD PAD PAD PAD PAD PAD PAD

Peripheral Peripheral
IO IO
IO IO
PAD PAD
AA IO Peripheral
AA IO IO
AA IO Peripheral
IO
Peripheral
IO
Core Circuit Peripheral
IO
Peripheral
IO
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
AA IO
IO
IO
IO
IO
IO
IO
LUPWDMY_2(255;18)
PAD PAD PAD PAD PAD PAD PAD
Figure 10.1.2.5.4 IO cells put in the chip center and next to internal circuit need to follow AAIO latch-up.
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PAD PAD PAD PAD PAD PAD

PAD PAD PAD PAD PAD PAD
IO IO
IO IO
IO IO
IO IO
IO
Peripheral Core Circuit IO
Peripheral
IO IO
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Figure 10.1.2.5.5 The AAIO latch-up rules are not required for this scenario.
10.1.3 Test Specification and Requirements

TSMC Latch-Up testing is performed at room temperature and 125C by complying the Latch-up test
methodology defined by JEDEC 78. The test items include Input/Output over-voltage/ over-current test (Fig.
10.1.3.1) and supply over-voltage test (Fig. 10.1.3.2). It applies a stepped voltage/current to one pin per device
with all other pins open except Vdd and Vss. Testing was started from Vdd/50mA (positive) or 0V/-50mA
(negative), and the DUT was biased for 0.5 seconds. If the Icc current does not reach the predefined limit
(Idd=200mA), then the voltage was increased by +/-0.1V or +/-50mA and the pin was tested again until +/-
1.5Vdd or +/-100mA for Input/Output over-voltage/ over-current.
Notes:
1. DUT: Device under test.
T rig g e r Id d
s o u rc e
Vdd
O v e r -v o lt a g e
Vss
O v e r -c u r r e n t
Fig. 10.1.3.1 Input/Output Over-Voltage/Current Test
Id d
Vdd
O v e r -v o lt a g e
Vss
Fig. 10.1.3.2 Supply Over-voltage Test
10.2 I/O ESD Protection Circuit Design, Layout

Rules and Guidelines
10.2.1 ESD introduction
During manufacturing, it is inevitable the IC will suffer various kinds of Electrostatic-Discharge (ESD) damage.
Different environments, wafer during CMOS process, package, testing and human handling, will generate
different kinds of ESD’s. Currently, the charge device model (CDM), Human-Body mode (HBM) and Machine
model (MM) are the most common models used to simulate the ESD events generated from various
environments. The main difference between CDM and HBM is that CDM charges come from the substrate
through the internal circuit to the pad, while the ESD’s for HBM and MM come from the external environment
to the pad. So, most ESD protection devices only can be used to protect HBM and MM, but cannot be used to
protect the CDM since the ESD protection device is at the pad and there is no direct current path between the
internal circuit and the ESD protection device.
The discharging behaviors for the three ESD models all can be simplified by the equivalent circuit in Figure
10.2.1 and expressed by the equation:
(   )t  (   ) t
e  e
(1). where =Ro/(2Lo),  
2
I ESD
 V ESD
(RoC o
)  4 LoC o
/( 2 L o C o
) For HBM, the Ro , Co
2Lo
and Lo is 1.5K, 100pF and 7.4H, respectively. For MM, the Ro , Co and Lo is 10, 200pF and 7.4H,
respectively. Substituting the above values into eq. (1), the measured and theoretical current waveforms for
HBM and MM are shown in Figure 10.2.2. For HBM, the rise time is <10nsec, the decay time is 150nsec
(RoCo=1.5K100pF) and the peak current is equal to VESD/Ro. The period for MM is nearly 90nsec and the
peak current for 100V MM is nearly 1.7A.
Figure 10.2.3 shows the CDM discharging current waveforms vs. Lo and Ro based on eq. (1) for 500V CDM.
The CDM period and peak current are varied with Lo, Co, and Ro. Compared with HBM and MM, the CDM has
a shorter period and a larger peak current.
Lo
IESD
VESD CESD
Ro
Vss
Fig. 10.2.1.1 The simplified equivalent circuit for ESD
0.035
a. 0.030 b.
0.8 Mea. current
M ea. current Cal. current
C al. current 0.6
)
0.025
0.4
A
Current ( A )
(
0.020 0.2
C u rre n t
0.015 0.0
0.010 -0.2
0.005 -0.4
0.000
-0.6
0 50 100 150 200 250
0 50 100 150 200
Tim e ( nsec )
Time ( nsec )
Fig. 10.2.1.2 The discharging current waveform for (a) HBM and (b) MM
L=25nH, C=4pF, R=10ohm

8 L=25nH, C=4pF, R=50ohm
6 L=25nH, C=2pF, R=10ohm
Current ( A )
-2
-4
-6
0 1 2 3 4 5
Tims ( nsec )
Fig. 10.2.1.3 The CDM discharging current waveforms vs. Lo, Ro, and Co
Besides the above three models, another kind of ESD, which occurs during wire bonding, has been found. We
call it ball-bonding ESD (BBE). The stress period of the BBE (~20nsec) is shorter than HBM and MM, but
longer than CDM. The stress voltage (~13V) of BBE is much smaller than HBM, MM and CDM. The BBE came
from the charged wire through the pad and device which connect the pad to the substrate. It might induce the
reliability issue and degrade the device ESD performance if the ESD protection device is not robust enough or
the pad is without the ESD protection device. (please refer to JH Lee et. al, “The impact of ball-bonding
induced voltage transient on sub-90nm CMOS technology,” in IRPS, p. 97, 2007.)
Because the pad is the median used to interact with externals for an IC, all pads need ESD protection devices
to protect the ESD coming from various environments to prevent internal circuit damage.
10.2.2 TSMC IO ESD layout style introduction

TSMC IO ESD protection scheme is the self-protection scheme that IO is the ESD protection device. No
matter NMOS or PMOS, they all have the snapback phenomena. The snapback mechanism can be described
as the following: As the applied voltage is higher than the device trigger voltage (Vt1 in Fig. 10.2.2.1), a lot of
holes are generated due to a drain junction occurrence Avalanche-breakdown. The hole current (Isub in Fig.
10.2.2.1) flows through the substrate (Rsub in Fig. 10.2.2.1) and raises up the substrate potential (Vsub in Fig.
10.2.2.1), and eventually forward bias the p-n junction (D1 in Fig. 10.2.2.1) between the P-substrate and the
source when the potential becomes higher than 0.7V. Subsequently, a lot of electrons are injected from the
source and flow to the p-n junction between the P-substrate and the drain, which generates more electron-hole
pairs due to impact-ionizations at the high electrical field of the drain junction. The resulting carrier transport
mechanism causes a positive feedback effect to turn on the parasitic n-p-n bipolar transistor (npn in Fig.
10.2.2.1). As the parasitic n-p-n is turned on, it can sink a much higher current level than the initial Avalanche-
breakdown current and goes into a stable snapback region as shown in Fig. 10.2.2.1.
(a) Vss ESD (b) 6 0.12

Vt1
Current
5 0.10
n- n- N+
N+
0.08
P+ 4
Voltage ( V )
Current ( A )
snapback
0.06
3
Base Voltage
D1 2
0.04
npn
0.02
Vsub= ISubRSub 1
ISub(x) 0.00
Rsub(x)
0
P-substrate 0 20 40 60 80 100 120 140
Time ( nsec )
Fig. 10.2.2.1 (a) the parasitic components of a Grounded-gate NMOS (GGNMOS), (b). real time IV
characteristics of a GGNMOS under 100 nsec TLP pulse
The RPO is the silicide blocking layer which is commonly used for an ESD protection device to forbid the
silicide formation on the drain region. The RPO scheme might be not a good solution for IO design due to
larger series resistance, but it can provide a stable ESD performance for an ESD protection device. So, the
device ESD performance does not vary between technology generations or manufacturing fabs. Fig. 10.2.2.2
shows the high current IV characteristics of a RPO N+ OD resistor. The RPO N+ OD resistor has a saturation
region. In the saturation region, the resistor becomes a high impedance resistor, so the increase in the applied
voltage does not increase the stress current. From this characteristic, we can deduce that RPO can be used to
clamp the current to prevent the current being localized in a given region. As a region enters the saturation
point, it becomes a high impedance resistor. Then, the current of this region cannot be increased anymore.
Subsequently, the current will be pushed to flow to other non-saturated regions and the current can distribute
along the junction uniformly.
20
15 Saturation
Current ( mA )
region
10
RPO N+ OD (W/L 1.4/2)
0
0 2 4 6 8
Voltage ( V )
Fig. 10.2.2.2 High current IV charactertistics of a RPO N+ OD resistor
The ESD implant is a process scheme to enhance the device ESD performance without changing the device
layout since it only covers the drain region and needs to have 0.4um space from the poly gate. The current
ESD implant recipe is P-type ESD implant. It can reduce the device breakdown voltage and create the higher
electrical field during the snapback region, resulting in better ESD performance. At TSMC, only one dosage
exits for P-type ESD implants. The dosage for ESD implants is higher than the channel implant dosage for
3.3V and 2.5V devices, but lower than the channel implant dosage for below 1.8V devices. So, the ESD
implant is recommended for 3.3V and 2.5V devices, but is no use for devices below 1.8V. For 5V, 3.3V and
2.5V high voltage tolerant I/O, an ESD implant should be used.
10.2.3 ESD Implant (ESDIMP) Layout Rules (MASK ID:

111)
ESDIMP (CAD layer: 189;0) is a drawn layer for ESD implant.
The following width, space, area, and enclosed area are based on process concern. Please use larger
dimension for ESD implant.
Recommended ESDIMP in the following NMOS drain side,

2.5V tolerant I/O circuits using a 1.8V I/O device. A 2.5V tolerant I/O is defined by the VIN criterion: VIN >
VDD but VIN ≤ (2.5V +10%)
3.3V tolerant I/O circuits using a 2.5V I/O device. A 3.3V tolerant I/O is defined by the VIN criterion: VIN >
VDD but VIN ≤ (3.3V +10%)
5V tolerant I/O circuits using a 3.3V I/O device. A 5V tolerant I/O is defined by the VIN criterion: VIN > VDD
but VIN ≤ (5V +10%)
ESDIMP.W.1 Width A  0.5
ESDIMP.S.1 Space B  0.5
(OD NOT PO) enclosure of ESDIMP. C  0.4
ESDIMP.EN.1
ESDIMP must be fully inside (OD NOT PO).
ESDIMP.EN.1® Recommended (OD NOT PO) enclosure of ESDIMP. C = 0.4
ESDIMP.A.1 Area D  1.0
ESDIMP.A.2 Enclosed area E  1.0
ESDIMP.R.1 ESDIMP must be fully inside N+ ACTIVE
C C
ESDIMP ESDIMP
C C C C
C C
Drain
Drain
C
ESDIMP ESDIMP ESDIMP ESDIMP
E A C C
D
A B
B
10.2.4 SR_ESD device Layout Rules (N40G only)

The SR_ESD layer (CAD layer: 121;0) is ONLY used for N40G core voltage ESD related device, which
features with:
 Core devices with SR_ESD layer will waive following OD/PO rules: OD.W.2.1GS, OD.W.2.2GS,
PO.S.2.1.1GS, PO.EX.2.1GS, and CO.S.7® .
 Additional rules are wavied by SDI layer coverage itself: PO.W.6.GS, RPO.EX.1, RPO.EX.1.1, RPO.EX.1.2
and CO.S.7® .,
 For speed-sensitive circuit design, standard MOS layout with dual-diode protection is the recommended
approach.
 For core voltage MOS, SR_ESD layer can’t cover core PMOS where SiGe is used. Only core NMOS (active
power clamp; Ncs) is allowed to be covered by SR_ESD.

SR_ESD.W.1 width A  0.18
SR_ESD.W.2 Channel length in SR_ESD regions B  0.1
SR_ESD.W.3 Channel width of core device in SR_ESD regions C = 15 ~ 60
SR_ESD.S.1 Space D  0.18
SR_ESD.EX.1 Extension on ACTIVE E  0.02
SR_ESD.L.1 Maximum ACTIVE length of core device in SR_ESD regions F  60
SR_ESD.R.1 SR_ESD can not cover core PMOS
SR
S ES
R__E SD
D
SR _ESD
E
OD
SR _ESD E
C
A D
E
E
B
10.2.5 ESD Dummy Layers Summary

10.2.5.1 SDI Dummy Layer
 SDI (CAD layer: 122) is a DRC layer, but not for mask making. It is required to cover all ESD MOS OD
regions (Regular IO, high voltage tolerant I/O, Power clamp) that are connected to the pads. SDI is not
necessary to cover the well STRAP or ESD guard-ring.
This includes the source, gate, and drain, but not necessarily the field PO and well strap OD regions. Refer to
Figure 10.2.5.1, shown below.
NP/PP
OD
SDI
Source Drain
PO
Figure 10.2.5.1 The SDI dummy layer layout
10.2.6 ESD circuits Definition

TSMC provides MOS-based (or snapback-based) ESD protection scheme and design guidelines for regular IO
and HV tolerant IO application. Furthermore, the design guidelines for the diode-based protection scheme are
also added.
10.2.6.1 Regular IO
Regular I/O is composed of the NMOS and PMOS and the drains of the NMOS and PMOS connect to the pad
directly (N1/P1 in Figure 10.2.9.1.4).
10.2.6.2 HV tolerant IO
The HV tolerant I/O is composed of the PMOS in floating NW (P2 Figure 10.2.9.3.1) and cascode (stacked
gate) NMOS and the drains of the floating NW PMOS and cascode (stacked gate) NMOS connect to the pad
directly (P2/N2/N3 in Figure 10.2.9.3.1). There are three kinds of HV tolerant IO listed below.
10.2.6.2.1 5V tolerant I/O

5V tolerant I/O circuits using a 3.3V I/O device with VIN criterion: VIN > 3.3V but VIN ≤ (5V +10%).
10.2.6.2.2 3.3V tolerant I/O

3.3V tolerant I/O circuits using a 2.5V I/O device with VIN criterion: VIN > 2.5V but VIN ≤ (3.3V +10%).
10.2.6.2.3 2.5V tolerant I/O

2.5V tolerant I/O circuits using a 1.8V I/O device with VIN criterion: VIN > 1.8V but VIN ≤ (2.5V +10%).
10.2.6.3 IO Buffer
The I/O Buffer includes regular I/O and HV tolerant I/O.
10.2.6.4 Power Clamp Device (Ncs)

The device is used for VDD Pad to VSS Pad protection (Ncs in Figure 10.2.9.1.4 and Figure 10.2.9.3.1). Please
refer to section 10.2.9.4.
10.2.6.5 ESD Device

The ESD Device includes any device (NMOS, PMOS, I/O buffer, power clamp device, diodes, SCR and
resistor) which connects to the pad directly and can be used to discharge the ESD current.
10.2.7 Requirements for ESD Implant Masks

 For HV tolerant (cascode) I/O NMOS, ESD implant mask is required unless TSMC approves a special
exclusion request. The ESDIMP layer is a drawing layer and you have to draw ESDIMP layer for mask
making. The ESDIMP layer is a drawing layer. Please refer to the section 10.2.3 for the detail.
 For customers who use their own ESD design structure, or do not use HV tolerant NMOS, ESD implant is
optional.
Table 10.2.7.1 ESD Implant Masks for HV Tolerant I/O Circuits
I/O Design Style ESDIMP (CAD layer 189;0) ESD mask (no.111)
Requirement Requirement
TSMC-style I/O with HV tolerant IO circuits Drawing Required Yes
TSMC-style I/O without HV tolerant I/O circuits No need No need
Non TSMC-style ESD Depends Depends
10.2.8 DRC methodology for ESD guidelines

10.2.8.1 DRC methodology to identify ESD MOSFET
1. The ESD MOS is defined by MOS covered by SDI (122;0).
2. The Regular ESD N/P MOS is defined in the following:
 ESD N/P MOS with gate partially covered by RPO and without gate fully covered by RPO
3. The HV Tolerance ESD PMOS is defined in the following:
ESD PMOS with gate partially covered by RPO and without gate fully covered by RPO.(same as
Regular ESD PMOS)
4. The HV Tolerance ESD NMOS is defined in the following:
 ESD NMOS with gate partially covered by RPO and with gate fully covered by RPO
5. The Power Clamp ESD NMOS is defined in the following:
 ESD NMOS without RPO overlap
# Note: For other non-TSMC-standard ESD MOSFETs, there is no DRC ESD guidelines check.
Table 10.2.8.1 how to recognize ESD MOSFET

RPO Partially Cover Gate RPO Fully Cover Gate ESD MOS Type
Y Y HV Tolerance ESD NMOS
Y N Regular ESD N/P MOS or
HV Tolerance ESD PMOS
N Y No support
N N Power Clamp ESD NMOS
10.2.8.2 DRC methodology to identify ESD MOS Source

and Drain
1. The S/D region is defined by {MOS_OD NOT POLY}
2. The S/D region which connected to well pick-up is Source.
 The connectivity is broken by resistor for this check.
3. The S/D region outside RPO is Source. (except for Power Clamp)
4. Except for recognized Source, all the others are Drain.
# Note: If the ESD layout structure is not TSMC-standard, this approach will fail.
Figure 10.2.8.2 Example of S/D for ESD device
10.2.8.3 DRC methodology for ESD.1g

1. ESD S/D is covered by OD2, and connected to Core device S/D/G (without OD2).
2. If ESD S/D is connected to P-well pick-up, it is excluded from this rule check.
PAD Fail ! PAD Fail !

1.8V/2.5/3.3V ESD Core Circuit 1.8V/2.5/3.3V ESD Core Circuit
Figure 10.2.8.3 Example of ESD.1g

1. ESD S/D interact one gate only is defined as edge side OD.
2. The edge side OD is not connected relative well pick-up.
 N-well pick-up works for NMOS, P-well pick-up works for PMOS.
 The connectivity is not broken by resistor for this check.
# Note: This check will fail for stacked ESD circuit.
The Source is not connected to power !

PAD
The Source is not connected to ground !

1. Check the space between two ESD MOS in same connection of Drain to PAD.
2. The space < 2um, and there is a well pick-up between these two ESD MOSs

1. Check the space < 1.2um between two same type Non-ESD MOSs connected to different Signal PAD.
(Non-ESD MOS: MOS not covered by SDI).
 The connectivity depends on “DISCONNECT_AFTER_RESISTOR” is turned ON or OFF.
2. Check the space < 1.2um between two same type Non-ESD MOSs in the same well, or these two wells
are connected.
3. Find out the MOSs meet above two criteria at the same time, and there is no different type of OD placed
between these two MOSs.
Signal
Pass Fail ! Pass PAD
! !
Signal >= 1.2um < 1.2um < 1.2um

PAD
10.2.8.7 DRC methodology for finger width

1. This check is for ESD.16g, ESD.17g, ESD.24g, ESD.25g, ESD.37g, ESD.41g, ESD.48g, and ESD.49g.
2. The total finger width is calculated by the ESD MOS (ESD.16g, ESD.17g, ESD.24g, ESD.25g, ESD.37g,
and ESD.41g) in the same Drain connection.
3. The total width is calculated by the ESD Field Device (ESD.48g, ESD.49g) in the same collector
connection.
 The connectivity is broken by resistor for this check.
Figure 10.2.8.7 Example of finger width
10.2.8.8 DRC methodology for ESD.19g and ESD.27g

1. As mentioned in previous, the drain-side is recognized by S/D not outside RPO, so that the check of drain-
side OD without RPO would be meaningless.
2. DRC only highlight the gate without overlap with RPO.
Figure 10.2.8.8 Example of ESD.19g and ESD.27g
10.2.8.9 DRC methodology for ESD.20g, ESD.28g, ESD.29g,

and ESD.42g
1. For Regular ESD N/P MOS and HV Tolerance ESD PMOS :
 The overlap of RPO and Gate should exactly equal to 0.06um.
 The overlap should occur in one-side only
 Without overlap is not allowed
2. For HV Tolerance ESD NMOS :
 The RPO should fully cover the first Gate.
 The overlap of RPO and second Gate should exactly equal to 0.06um.
 The overlap should occur in one-side only.
 Without overlap is not allowed.
second Gate
first Gate
Fail ! Fail ! Fail ! Fail ! Fail !

RPO RPO
Pass Pass
! !
Figure 10.2.8.8.9 Example of ESD.20g, ESD.28g, ESD.29g, and ESD.42g
10.2.9 ESD Guidelines

 TSMC's ESD target is 2KV for Human Body Model (HBM) and 200V for Machine Model (MM)
 These design guidelines are designed to increase ESD protection levels to TSMC specifications.
 These guidelines are developed from our test chip silicon data. The test structures in these test chips
include most of the failure cases we have studied. Yet, there might be other weak paths that are not
captured by these guidelines. Thus, chip level ESD testing should be carried out.
10.2.9.1 General Guideline for ESD Protection

For I/O pin ESD protection scheme, the primary ESD protection (1st ESD) devices are required and it can
be one of following listed devices.
ESD.NET.1gU 1. Regular I/O P/NMOS (refer to ESD.16g~23g) or HV-tolerant I/O P/NMOS (refer to ESD.24g~35g)
2. HIA diode (refer to HIA.1~6g)
3. Diode with DIODMY (total perimeter >=300um)
SDI is not in whole chip.
ESD.WARN.1
If SDI does not exist, the ESD related DRC will not work well.
ESD.WARN.2 SDI enclosure of ACTIVE ≥ 0
Avoid gate of core MOS directly tie to Vdd/Vss except decap, GGNMOS/GDPMOS, and footer/header (see
ESD.WARN.3U section 10.4.4.1 for details).
For CDM application with peak current < 6A, this rule can be waived.
Use thin oxide transistor for thin oxide power clamp and thin oxide I/O buffers; use thick oxide transistor for
the thick oxide Power Clamp and thick oxide I/O buffers (Figure 10.2.8.3 and 10.2.9.1.1).
ESD.1g DRC will flag the following condition:
((MOS INTERACT OD2) INTERACT SDI) connected to (MOS NOT INTERACT OD2)
DRC will exclude Drain/Source/Gate connected to PW STRAP.
Use thin oxide transistor for thin oxide secondary ESD protection (2nd ESD, N4/P4); use thick oxide
transistor for thick oxide secondary ESD protection (2nd ESD, N4). (Figure 10.2.1.5)
For diode based 2nd ESD protection, use thin oxide transistor (Mp/Mn) for thin oxide power clamp (Ncs); use
ESD.1.1gU
thick oxide transistor (Mp/Mn) for thick oxide power clamp (Ncs) (Fig 10.2.1.5)
Thick oxide ESD protection or power clamp connect to thin oxide transistor is not allowed.
Both input pin and cross domain 2nd ESD are required to comply with this rule.
ESD.3g Unit finger width of NMOS and PMOS for I/O buffer and Power Clamp Device (Figure 10.2.9.1.2) G = 15~ 60
The OD area of the edge side of I/O buffer and Power Clamp should be Source or Bulk rather than Drain
(Figure 10.2.8.4 and 10.2.9.1.2), to avoid an unwanted parasitic bipolar effect or an abnormal discharge
ESD.4g path in ESD zapping.
DRC will flag (((OD INTERACT SDI) NOT PO) INTERACT one Gate) does not connect to STRAP. (Please
refer to section 10.2.8.4 in detail)
Same type OD of the I/O buffer and Power Clamp should be surrounded by a guard-ring. All other type ODs
should be placed outside this guard-ring. (Figure 10.2.9.1.2)
ESD.5g DRC will flag the following two conditions,
1. Different type ODs in the most inner guard-ring.
2. OD not inside the most inner guard-ring
Butted STRAP and the STRAP which are between two sources of the N/PMOS in the same I/O buffer and
Power Clamp are strictly prohibited. (Figure 10.2.9.1.3)
ESD.6g
DRC will flag Butted STRAP and the STRAP which is within 2um space of two sources of (MOS INTERACT
SDI) connected to same pad. (Please refer to section 10.2.8.5 in detail)
Except the ESD device, either one of the following two conditions must be followed.
the space of two same type ODs
ESD.7g two same type ODs should be separated by different types of OD. ≥ 1.2
The same type ODs are N+OD and N+OD in the same PW, or P+OD and P+OD in the same NW, which
connect to two different pads. (Please refer to section 10.2.8.6 in detail)
ESD.8gU Value of resistor R (ohm) between the gate oxide and IO PAD (Figure 10.2.9.1.4~10.2.9.1.6) ≥ 200
ESD.9.1gU~9.6gU are used to define N/PMOS (N4/P4) and diode (D3/D4) of ESD secondary protection in
Figure 10.2.9.1.5
The N/PMOS (N4/P4) and diodes (D3/D4) should follow:

U 1. Either MOS based or diode based secondary protection is required at input pin. (N4 in Figure 10.2.9.1.5
ESD.9.0g
and D3/D4 in Figure 10.2.9.1.5)
2. Should be added after the resistor R (on the far side of R from the pad).
3. NOT in SDI
4. ESD implant and RPO are not needed in these secondary protection devices.
For MOS based secondary protection, the secondary PMOS is “Nice to have”
U Channel Length of core voltage MOS for N/PMOS (N4/P4) of MOS based ESD secondary protection in
ESD.9.1g = 0.07
Figure 10.2.9.1.5.
Channel Length of 1.8V MOS for N/PMOS (N4/P4) of MOS based ESD secondary protection in Figure
ESD.9.2gU = 0.15
10.2.9.1.5.
ESD.9.3gU = 0.27
10.2.9.1.5.
ESD.9.4gU = 0.42
10.2.9.1.5.
ESD.9.5g U
Channel width of MOS based (N4/P4) ESD secondary protection (for all voltages) in Figure 10.2.9.1.5 ≥ 20
ESD.9.6gU Total perimeter of diode based ESD secondary protection (D3/D4) in Figure 10.2.9.1.5 ≥ 10
It is not allowed to use OD unsilicided resistors or NW resistors connected to I/O PAD (Figure 10.2.9.1.4
and Figure 10.2.9.1.6).
ESD.12g
DRC will use (((RPDMY OR RH) AND OD) AND RPO) to recognize OD unsilicided resistor.
DRC will use (NWDMY INTERACT NW) to recognize NW resistor.
1. Resistance of the power bus line from IO pad to the closest Power clamp. (R1+R2+R4 in Figure
10.2.9.1.7) ()
ESD.14.3gU ≤ 1
2. Resistance of the ground bus line from IO pad to the closest Power clamp. (R1+R5+R6 in Figure
10.2.9.1.7) ()
Resistance of the bus line from Power pad to the closest GND pad. (R3+R4+R6+R7 in Figure 10.2.9.1.7)
ESD.14.4gU ≤ 1
()
Bypass discharge cells should be inserted between each separate VDD and VSS to avoid ESD damage to
internal circuits.
The suggested bypass discharge cell is back to back diode (Figure 10.2.9.1.8) and it can be either HIA
diode or diode with DIODMY.
ESD.15gU 1. HIA diode (HIA.3g)
2. Diode with DIODMY (total perimeter >=300um).
The connections are illustrated in Figure 10.2.9.1.
(For more details, please see the “section 10.4.3 Tips for Power-Ground ESD Protection” section in this
chapter.)
Vdd (core)
core
dec.
Pad cap.
3.3V/2.5V/1.8V
core circuit
3.3V/2.5V/1.8V
ESD Vss power clamp device
Figure 10.2.9.1.1 Use thin oxide transistor for the ESD protection of thin oxide circuits
I=I1+I2+…=Metal connection to bond pad>=16um
Metal connecting between Drains and pad

>=16um
OD
I1 I2 Guard ring PO
CO
Drain Drain M1
Via1
M2
G
Source
Source
Figure 10.2.9.1.2 NMOS and PMOS Layouts for I/O Buffer
STRAP Butted STRAP

RPO RPO RPO
OD
PO
X X X X X X CO
Z Z Z RPO
≤ 2um ≤ 2um Source

Drain Source Drain
Source Source
To the same Pad

Figure 10.2.9.1.3 Butting or Inserted STRAP between two sources of I/O buffer is prohibited
Vdd
P1 P1
RPO P4 Trigger
X R (>=200 Ω) Ncs Circuits
Pad
RPO N1 N1 N4
Vss secondary protection

Figure 10.2.9.1.4 Regular I/O
VDD1
Primary
ESD Ncs
P4 Mp Active
RESD Trigger
PAD Circuit
Primary N4 Mn
ESD
VSS1
(a) MOS-based secondary ESD protection
VDD1
Primary D4
ESD Ncs
Mp Active
RESD Trigger
PAD Circuit
Primary
D3 Mn
ESD
VSS1
(b) Diode-based secondary ESD protection
Figure 10.2.9.1.5 Diode as ESD secondary protection
S tru c tu re . I S tr u c tu r e . II S tr u c tu r e . III
Vcc
Vcc Vcc
R
R
Pad Pad Pad

R
Vss Vss
Vss
Figure 10.2.9.1.6 A resistor before the output transistor
R2 R3 VDD
PAD
Primary R4
ESD cell
Internal Power
IO PAD Clamp
R1 devices
Primary
ESD cell R6
VSS
PAD
R5 R7
R1+R2+R4 & R1+R5+R6 <=1ohm
R3+R4+R6+R7 <=1ohm
Figure 10.2.9.1.7 Bus-Lines Design
Db1
VSSA VSS
Db2
Figure 10.2.9.1.8 Schematic of a back to back (B2B) diode
Vdd (comm.)
ESD ESD ESD

conduction Vdda conduction Vddb conduction Vddc
circuit circuit circuit
Circuit I ESD Circuit II ESD Circuit III ESD

Clamp Clamp Clamp
ESD ESD ESD

conduction
conduction Vssa conduction Vssb circuit
Vssc
circuit circuit
Vss (comm.)
Figure 10.2.9.1.9 Schematic of a Multiple Power ESD Protection Design
10.2.9.2 Regular I/O (3.3V/2.5V/1.8V/1.1V/0.9V RPO Device)

 Regular I/O ESD MOS layout style on core voltage MOS is only applicable for non-N40G process. In
N40G, Core voltage MOS can not be drawn with this layout style.
 DRC deck uses (N+ ACTIVE AND SDI) AND (some of the related Gate partially overlap RPO but no
related Gate fully inside RPO) to recognize NMOS of Regular I/O.
 DRC deck uses (P+ ACTIVE AND SDI) AND (some of the related Gate partially overlap RPO but no
related Gate fully inside RPO) to recognize PMOS of Regular I/O.
Total finger width for NMOS in same connection of drain. (Please refer to
ESD.16g ≥ 360
section 10.2.8.7 in detail)
Total finger width for PMOS in same connection of drain. (Please refer to
ESD.17g ≥ 480
section 10.2.8.7 in detail)
ESD.18g Channel length: 3.3V Regular I/O (in OD_33) L ≥ 0.42
ESD.18.1g Channel length: 2.5V Regular I/O (in OD_25) L ≥ 0.35
ESD.18.2g Channel length: 1.8V Regular I/O (in OD_18) L ≥ 0.2
ESD.18.3g Channel length: 1.1V/0.9V Regular I/O (not in OD_33, OD_25 and OD_18) L ≥ 0.1
The NMOS and PMOS should have an unsilicided area on the drain side.
That is, the RPO mask should block the drain side of the device (except
ESD.19g the contact region which should remain silicided).
DRC only flags no RPO in this device. (Please refer to section 10.2.8.8 in
detail)
Overlap of RPO on the drain side to the poly gate (N1/P1 in Figure
ESD.20g 10.2.9.1.4 and Figure 10.2.9.2.1) (Please refer to section 10.2.8.9 in Z = 0.06
detail)
ESD.21g Width of the RPO on the drain side for NMOS. (Figure 10.2.9.2.1) X  1.0
ESD.22g Width of the RPO on the drain side for PMOS. (Figure 10.2.9.2.1) X  0.6
ESD.23g Space of poly to CO on the source side (Figure 10.2.9.2.1) Y  0.22
Z Z Z Z
OD
PO
X X X X RPO
CO
SDI
L L L L
To PAD To PAD
Figure 10.2.9.2.1 NMOS and PMOS (N1 and P1 in Figure 10.2.9.1.4) for regular I/O
10.2.9.3 HV Tolerant I/O

 HV tolerant I/O ESD MOS layout style is only applicable for I/O voltage MOS. Core voltage MOS can not
be drawn with this layout style.
 DRC deck uses (N+ ACTIVE AND SDI) AND (some of the related Gate fully inside RPO and some of the
related Gate partial overlap RPO) to recognize the NMOS of HV tolerant I/O.
 DRC deck uses (P+ ACTIVE AND SDI) AND (some of the related Gate fully inside RPO and some of the
related Gate partial overlap RPO) to recognize PMOS of HV tolerant I/O, whose layout is the same as
PMOS of Regular I/O.
 For 5V and 3.3V tolerant I/O, the ESDIMP is must layer. The detail layout for ESDIMP is shown in section
10.2.3.
Total finger width for NMOS in same connection of drain. ESD.24g has been
ESD.24g ≥ 360
checked by ESD.16g. (Please refer to section 10.2.8.7 in detail)
Total finger width for PMOS in same connection of drain.
ESD.25g ESD.25g has been checked by ESD.17g. (Please refer to section 10.2.8.7 in ≥ 480
detail)
Channel length: 5V tolerant I/O (in OD_33). N2,N3, P2 in Figure 10.2.9.3.1,
ESD.26g L ≥ 0.42
Figure 10.2.9.3.2 and Figure 10.2.9.3.3.
Channel length: 3.3V tolerant I/O (in OD_25). N2,N3, P2 in Figure 10.2.9.3.1,
ESD.26.1g L ≥ 0.35
Channel length : 2.5V tolerant I/O (in OD_18). N2,N3, P2 in Figure 10.2.9.3.1,
ESD.26.2g L ≥ 0.2
The NMOS and PMOS should have an unsilicided area on the drain side. That
is, the RPO mask should block the drain side of the device (except the contact
ESD.27g
region which should remain silicided).
DRC only flags no RPO in this device. (Please refer to section 10.2.8.8 in detail)
For NMOS (N2 and N3 in Figure 10.2.9.3.1 and Figure 10.2.9.3.2), the RPO
ESD.28g needs to cover all inactive poly gates and extend to overlap the N3 gate by Z = Z = 0.06
0.06um. (Please refer to section 10.2.8.9 in detail)
For PMOS (P2 in Figure 10.2.9.3.1 and Figure 10.2.9.3.3), overlap of RPO on
ESD.29g Z = 0.06
the drain side to the poly gate. (Please refer to section 10.2.8.9 in detail)
ESD.30g Width of the RPO on the drain side for NMOS. (Figure 10.2.9.3.2) X ≥ 1.0
ESD.31g Width of the RPO on the drain side for PMOS. (Figure 10.2.9.3.3) X ≥ 0.6
Space of poly to CO on the source side (Figure 10.2.9.3.2 and Figure
ESD.32g Y ≥ 0.22
10.2.9.3.3)
For NMOS (N2 and N3 in Figure 10.2.9.3.1), space of the N2 gate to the N3
ESD.33g S = 0.22~0.25
gate. (Figure 10.2.9.3.2)
ESDIMP is a required layer for HV tolerant NMOS. Please refer to section
10.2.3
ESD.34g
DRC only flags (no ESDIMP INTERACT N+ ACTIVE) for the NMOS of HV
tolerant I/O.
Figure 10.2.9.3.1 The schematic of HV Tolerant I/O buffer
Z Z
N3 N2 N2 N3 OD
PO
S X X S RPO
CO
SDI
L L L L
To PAD
Figure 10.2.9.3.2 HV Tolerant NMOS (N2/N3 in Figure 10.2.9.3.1)
Z Z Z Z
OD
PO
X X X X RPO
CO
SDI
L L L L
To PAD To PAD
Figure 10.2.9.3.3 HV Tolerant PMOS (P2 in Figure 10.2.9.3.1)
10.2.9.4 Power Clamp Device (Ncs)

 DRC deck uses ((N+ ACTIVE AND SDI) NOT INTERACT RPO) to recognize 3.3V/2.5V/1.8V/1.1V/0.9V
fully silicided type Power Clamp.
 DRC deck uses ((N+ ACTIVE AND SDI) AND (all of the related gates partially overlap RPO)) to recognize
3.3V/2.5V RPO (unsilicided) type Power Clamp.
 RPO mask can be applied for 3.3V/2.5V Power clamp. The 3.3V/2.5V Power Clamp with RPO mask is
3.3V/2.5V RPO (unsilicided) type Power Clamp. The 3.3V/2.5V RPO (unsilicided) type Power Clamp (Ncs
in Figure 10.2.9.4.3) must have an unsilicided area on the drain side. That is, the RPO mask can block
the drain side silicided of the device (except the contact region which should remain silicided).
 The Active Power Clamp is required to put between power and ground buses. The Active Power Clamp is
consisted of one trigger circuit and one big FET. The trigger circuit is designed to turn on the big FET
during ESD events and keep the big FET in off state at normal operation. (Figure 10.2.9.4.1)
 Care should be taken to prevent potential damage risk to the thin gate oxide. An active power clamp
(VT1~1V) is needed if there are thin-oxide devices whose gates directly connect to power (for example
the NMOS’s and PMOS’s gates connect to VDD and VSS, respectively) like a decoupling capacitor.
 Both fully silicided type and RPO (unsilicided) type power clamp must be Active power clamps. (Figure
10.2.9.4.1).
Total finger width for 3.3V/2.5V/1.8V fully silicided type Power Clamp in
ESD.37g same connection of drain. (Ncs in Figure 10.2.9.4.1) (Please refer to section ≥ 1000
10.2.8.7 in detail)
Total finger width for 1.1V/0.9V fully silicided type Power Clamp in same
ESD.37.1g connection of drain. (Ncs in Figure 10.2.9.4.1) (Please refer to section ≥ 1900
10.2.8.7 in detail)
Channel length: 3.3V Power Clamp (in OD_33) for both RPO (unsilicided)
ESD.38g L ≥ 0.42
and fully silicided types (Figure 10.2.9.4.2 and Figure 10.2.9.4.3)
Channel length: 2.5V Power Clamp (in OD_25) for both RPO (unsilicided)
ESD.38.1g L ≥ 0.35
and fully silicided types (Figure 10.2.9.4.2 and Figure 10.2.9.4.3)
Channel length: 1.8V Power Clamp (in OD_18) for fully silicided types
ESD.38.2g L ≥ 0.2
(Figure 10.2.9.4.2)
Channel length: 1.1V/0.9V Power Clamp (not in OD_33, OD_25 and
ESD.38.3g L ≥ 0.1
OD_18) for fully silicided types (Figure 10.2.9.4.2)
The total finger width for 3.3V/2.5V RPO (unsilicided) type Power Clamp in
ESD.39g the same connection of drain. (Ncs in Figure 10.2.9.4.1 and Figure ≥ 1000
10.2.9.4.3) (Please refer to section 10.2.8.7 in detail)
Overlap of RPO on the drain side to the poly gate (Figure 10.2.9.4.3)
ESD.40g Z = 0.06
(Please refer to section 10.2.8.9 in detail).
Width of the RPO on the drain side for 3.3V/2.5V RPO (unsilicided) type
ESD.41g X ≥ 0.6
Power Clamp (Ncs in Figure 10.2.9.4.3).
Space of poly to CO on the source side for 3.3V/2.5V RPO (unsilicided) type
ESD.42g Y ≥ 0.11
Power Clamp (Ncs in Figure 10.2.9.4.3).
The big FET of RPO (unsilicided) type Power Clamp is strongly
ESD.43g
recommended having ESDIMP. (Figure 10.2.9.4.1).
Each set of Vdd and Vss must have its own power clamp cells and active
ESD.45gU
power clamp is required (Figure 10.2.9.4.1)
The single stage power clamp (between VDD and VSS ) needs to be
ESD.45.1gU
covered by SDI layer (Figure 10.2.9.4.2)
Active Power Clamp Gate-grounded Power Clamp

VDD VDD
Active
Trigger
Circuit
Big FET Big FET
VSS VSS
Figure 10.2.9.4.1 The schematic of the Active Power Clamp
Source Drain Drain Source
L L L L
SDI
Figure 10.2.9.4.2 Ncs Layout in Figure 10.2.9.1.4 and Figure 10.2.9.3.1
RPO OD
PO
Y Y Y CO
RPO
X X
L L L
Z=0.06 To Pad Z=0.06
SDI
Figure 10.2.9.4.3 RPO (unsilicided) type power clamp Layout for 3.3V and 2.5V RPO (unsilicided) type
Power Clamp in Figure 10.2.9.1.4 and Figure 10.2.9.3.1
10.2.9.5 5V HVMOS protection (Field Device)

 Device usage:
A combination of NFD along with PFD is designed to protected 5V HVMOS based I/O signal PAD.
Please refer to Figure 10.2.9.5.4 for the reference ESD network construction. Please also note that
TSMC ESD protection scheme does not cover this 5V power clamp design.
 DRC methodology:
I. NFD (Figure 10.2.9.5.2)
 DRC deck uses ((((N+ ACTIVE NOT INTERACT PO) NOT RPDMY) AND SDI) CUT RPO) to
recognize NFD of 5V HVMOS protection.
 DRC deck uses NFD connect to LV PW STRAP to recognize NFD Emitter
 DRC deck uses NFD NOT (NFD Emitter) to recognize NFD Collector
II. PFD (Figure 10.2.9.5.3)
 DRC deck uses ((((P+ ACTIVE NOT INTERACT PO) NOT RPDMY) AND SDI) CUT RPO) to
recognize PFD of 5V HVMOS protection.
 DRC deck uses PFD connect to LV NW STRAP to recognize PFD Emitter
 DRC deck uses PFD NOT (PFD Emitter) to recognize PFD Collector
ESD.47g The layer of OD2 (OD_25) is required for 5V protection (NFD and PFD)
ESD.48g Total width for NFD in same connection of collector. (Figure 10.2.9.5.1) ≥ 360
ESD.49g Total width for PFD in same connection of collector. (Figure 10.2.9.5.1) ≥ 360
ESD.50g STI spacing of the NFD and PFD DL = 0.35
ESD.51g Unit collector width of NFD and PFD CW = 15-60
Unit emitter width of NFD and PFD should be the same as unit collector width
ESD.52g
(EW=CW)
ESD.53g Unit emitter length of NFD and PFD EL ≥ 0.86
ESD.54g Width of the RPO on the collector side for NFD and PFD DX ≥ 1.95
ESD.55g Width of the RPO on the emitter side for NFD and PFD DZ = 0.1
ESD.56g Space of RPO to CO on the collector and emitter side (Figure 10.2.9.5.1) DY  0.22
ESD.57g Total width of the RPO on the HVMOS protection. (Figure 10.2.9.5.1) A ≥ 2.4
D Y = 0 .2 2 D Y = 0 .2 2 D Y = 0 .2 2
OD
P P /N P
CO
A CW A RPO
EW
SDI
EL DX DX
OD2
DL DL
E m itte r
E m itte r
E m itte r C o lle c to r
D Z = 0 .1 To PAD D Z = 0 .1
Figure 10.2.9.5.1 5V HVMOS protection Layout
VSS PAD VSS

DZ
DY DY
RPO
DX
P+ N+ N+ N+ P+
E m itte r C o lle c to r E m itte r

DL
EL
P -w e ll
P -s u b
Figure 10.2.9.5.2 NFD cross-section diagram
VDD PAD VDD

DZ
D DY
D
DY
Z D
DX
RPO
Y
X
N+
N
P N
P
P+ N+
P
P+ N
P+
P N+
P
Emitter Collector
Collector Emitter
Emitter
Emitter
+ + DL
D + + +
EL L
N-well
wel
l
P-sub
Figure 10.2.9.5.3 PFD cross-section diagram
Figure 10.2.9.5.4 The schematic of 5V HVMOS protection
10.2.9.6 High Current Diode (HIA_DIO)
10.2.9.6.1 Dual-Diode I/O Protection

HIA_DIO stands for the diode, which can be used for logic, low capacitance or high speed/frequency ESD
protection. For diode-base ESD protection scheme, it should work together with low trigger power clamps,
such as RC-gate driven clamp.
Fig. 10.2.9.6.1 shows the common dual-diode protection scheme. One diode is for pull-up path to the VDD
and the other is for pull-down path to the VSS. There are four current discharge paths between the PAD, VDD
and VSS. The brief descriptions are as follows:
1. For a positive pulse from PAD respect to VDD, the current passes through the pull-up diode to VDD.
2. For a negative pulse from PAD respect to VDD, the current enter the VDD pin, through the power clamp,
and then passes through the pull-down diode,
3. For a positive pulse from PAD respect to VSS, the current passes through the pull-up diode, along the
supply metal bus to through the power clamp and out the VSS.
4. For a negative pulse from PAD respect to VSS, the current passes through the pull-down diode and out the
PAD.
Please note that excellent ESD performance is achieved when the discharge paths are confined to the
design paths as mentioned above. It depends on the low turn-on resistance of the diode, wiring and power
clamp devices. The designer should minimize the I-R drop effect as much as possible. The resistance of metal
bus between the PAD and power clamp should be less than 1 ohm (ESD.14.3gU). Also, both the ESD level
and parasitic capacitance are directly proportional to the diode’s perimeter. Hence, the designer should
consider the parasitic capacitance of the diodes on the I/O PAD and has to balance the ESD and circuit’s
performance.
Figure 10.2.9.6.1 The schematic diagram for diode-base protection
10.2.9.6.2 Layout Guidelines for HIA_DIO

 HIA_DIO is the diodes both can use for logic, high speed or low capacitance ESD protection. A layout
example is shown Figure 10.2.9.6.3.2 and Figure 10.2.9.6.3.3.
 The naming of HIA comes from high current application purposes (High Amp). There is no structural
difference between HIA_DIO and regular core voltage junction diode. The only difference is layout style.
 The HBM level is proportion to the diode’s perimeter, however the parasitic capacitance is increasing also.
10.2.9.6.3 HIA_DIO Layout Guidelines

10.2.9.6.3.1 HIA_Dummy Layer (CAD layer: 168;0)
 DRC deck uses (N+ ACTIVE AND HIA_Dummy NOT NW) to recognize N diodes for ESD protection.
 DRC deck uses (P+ ACTIVE AND HIA_Dummy AND NW) to recognize P diodes for ESD protection.
 Draw HIA_Dummy (CAD layer: 168;0) to fully cover diode’s OD regions that are connected to I/O pads,
including the anode, cathode, and guard-ring. Refer to Figure 10.2.9.6.3.1, and shown below.
 It is for DRC usage but not a tapeout required CAD layer.
 Diode’s layout (all dimensions of width/length/spacing/overlap) should be exactly identical to the p_cell, or
the RF model’s accuracy will be impacted.
HIA_Dummy
Cathode Anode
Guard-ring
Fig. 10.2.9.6.3.1 Example of HIA_Dummy
10.2.9.6.3.2 High current diodes protection

U Width of N+ Active (N-HIA diode’s cathode) and P+ Active (P-HIA diode’s anode) inside HIA_DUMMY. (Figure
HIA.1g A = 0.6-1.6
10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
Length of N+ Active (N-HIA diode’s cathode) and P+ Active (P-HIA diode’s anode) inside HIA_DUMMY. (Figure
HIA.2gU B = 5-40
10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
Total perimeter of each N+ or P+ ACTIVE inside HIA_dummy in same connection of IO PAD. (Figure
10.2.9.6.3.2 and Figure 10.2.9.6.3.3).
(A+B)*2
HIA.3gU ≥ 300
*N
The perimeter counts the drawn anode junction parameter region ex. The drawing OD perimeter dimension of
active inside HIA_DUMMY= (A+B)*2*N
The OD spacing between anode and cathode in the width direction (A; longer side of N+/P+ Active) (Figure
HIA.4gU C1 = 0.3-0.4
10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
The OD spacing between anode and cathode in the length direction (B; shorter side of N+/P+ Active) (Figure
HIA.5gU C2 = 0.6-0.8
10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
Cathode width should be larger than anode width for P-diode, and anode width should be larger than cathode
HIA.6gU D
width for N-diode (D≥A). (Figure 10.2.9.6.3.2 and Figure 10.2.9.6.3.3)
D
A C1 D NOD
Cathode B
POD
CO
C2 HIA_Dummy
Anode
Figure 10.2.9.6.3.2 HIA_DIO layout (N-HIA diode)
D NOD
A C1 D POD
Anode B CO
C2 NW
HIA_Dummy
Cathode
Figure 10.2.9.6.3.3 HIA_DIO layout (P-HIA diode)
10.2.9.7 RPO and ESD Implant Summary

NMOS of PMOS of 3.3V/2.5V NMOS 3.3V/2.5V/1.8V/
3.3V/2.5V/1.8V/ 3.3V/2.5V/1.8V/
5V/3.3V/2.5V 5V/3.3V/2.5V for RPO 1.1V/0.9V NMOS
I/O Device 1.1V/0.9V NMOS 1.1V/0.9V PMOS
HV Tolerant HV Tolerant (unsilicided) type for fully silicided
for Regular I/O for Regular I/O
I/O I/O Power Clamp type Power Clamp
Minimum RPO width

1.0 0.6 1.0 0.6 0.6 No
on drain side (X)
Overlap poly by Overlap poly by Completely Overlap poly Overlap poly by

RPO-to-N2 (Z) = No
0.06 0.06 cover N2 by 0.06 0.06
First poly-to-N3
No No 0.25 No No No
space =
RPO coverage in the
Completely
OD region between No No No No No
cover diffusion
poly gates
Overlap N3 by
RPO-to-N3 (Z) = No No No No No
0.06
3.3V/2.5V:
Recommended
ESD implant No Yes No Recommended No
1.8V/1.1V/0.9V:
No need
Dummy layer for

SDI SDI SDI SDI SDI SDI
DRC
Figure Figure
Illustration Figure 10.2.9.2.1 Figure 10.2.9.2.1 Figure 10.2.9.4.3 Figure 10.2.9.4.2
10.2.9.3.2 10.2.9.3.3
10.2.9.8 CDM Protection for Cross Domain Interface

CDM is an increasingly important issue for modern integrated circuits in N45 technology and beyond as
the gate oxide thickness keeps on shrinking and the number of power domains continues increasing. With
respect to the CDM protection, the cross-domain interface is the most crucial situation as compared with the
I/O input gate (defined as ESD.9g in DRM), the gate directly connected to power/ground, and the long signal
path without parasitic junction diode. It is because that the fatal CDM charges are mostly accumulated at the
power/ground metal buses and easily damage the gate oxide at the interface when the discharge current path
crosses the different power domains.
To prevent this kind of CDM damage for the complex power domains, the protection scheme is proposed
as Figure 10.2.9.8.1~3 shown. The protection network consists of a resistor, a pair of gate-ground NMOS and
gate-Vdd PMOS and active power clamp cells. Basically, the CDM protection transistors have to be placed as
close to the receiver gates as possible, and share the same power/ground and well of the receiver cell. A
global active clamp cell should be placed near the cross-domain interface to help conducting the CDM
currents. Additionally, the resistance of power bus between the global active power clamp cells is
recommended to be smaller than 1Ω. The turn-on resistance of “current conducting element” should be as
small as possible to minimize the voltage drop during CDM zapping.
Domain a Domain b
vdda vddb
2nd ESD for CDM

Global Global
Active bus bus Active
clamp active active clamp
clamp N4 clamp
vssa vssb
Current conducting element

Global ESD bus
Resistance between two bus active clamp(current conducting element)<1Ω
Figure 10.2.9.8.1 The MOS-based protection scheme for cross-domain CDM
Domain a Domain b
vdda vddb
2nd ESD for CDM D2

Global Global
Active bus bus Active
clamp active active clamp
clamp clamp
D1
vssa vssb
Current conducting element

Global ESD bus
Resistance between two bus active clamp(current conducting element)<1Ω
Figure 10.2.9.8.2 The diode-based protection scheme for cross-domain CDM
Domain b
Domain a
vdda vddb
Active Active
clamp clamp
vss
Figure 10.2.9.8.3 Common-grounded cross-domain CDM ESD protection scheme

1. For cross domain with separate grounds (Fig. 10.2.9.8.1~2), either MOS
based or diode based secondary protection with interface resistor is
required at interface. (N4 in Figure 10.2.9.8.1 and D1/D2 in Figure
ESD.60.0gU 10.2.9.8.2).
2. If the receiver is the I/O device, the secondary protection is not required.
3. As the cross domain with on-rule power clamp added between vdda to
vssb, the secondary protection is not required.
Total finger width of 3.3V/2.5V/1.8V/1.1V/0.9V cross-domain MOS based
ESD.61gU ≥ 8
secondary protection. (Figure 10.2.9.8.1)
Total perimeter of cross-domain diode based secondary protection. (D1/D2
ESD.61.1gU ≥ 10
in Figure 10.2.9.8.2)
Channel Length of 5V MOS based domain b secondary protection. (Figure
ESD.62.1gU = 0.8
10.2.9.8.1)
Channel Length of 3.3V MOS based domain b secondary protection. (Figure
ESD.62.2gU = 0.42
10.2.9.8.1)
ESD.62.3gU = 0.27
10.2.9.8.1)
ESD.62.4gU = 0.15
10.2.9.8.1)
Channel Length of 1.1V/0.9V MOS based domain b secondary protection.
ESD.62.5gU = 0.07-0.08
(Figure 10.2.9.8.1)
Recommended interface voltage clamping resistor resistance for cross-
ESD.63gU  200 Ω
domain with separated grounds.(resistor in Figure 10.2.9.8.1~2)
10.3 ESD Back-End Reliability Guidelines

Typically the design purpose within a dedicated ESD protection device is that interconnect will no be the
limitation for the ESD robustness. This section provides information to evaluate the max. current density (CD)
of metal line, via, contact, and resistor under ESD stress condition. According to the ESD back-end reliability
guideline, the customer can optimize their layout and get better ESD performance.
10.3.1 Test Methodology

The TLP is used to extract the maximum ESD current density (CD). The pulse width and rise time of TLP
are 100ns and 10ns, respectively, to simulate the HBM waveform.
The It2 can be extracted by TLP. As below figure shown, the It2 of Metal is about 0.18A and that of Resistor
is 0.06A as shown in Fig.10.3.1
Metal
DC leakage (A)
1E-13 1E-11 1E-09 1E-07 1E-05 1E-03
0.2
0.18
It 2
0.16
0.14
I_TLP (A)
TLP 0.12
measurement 0.1
T r=10ns, Td =100ns 0.08
DC leakage
0.06
|V| measurement 0.04
0.02
0
0 2.5 5 7.5 10 12.5 15
V_TLP (V)
Resistor
Time
It 2
Figure.10.3.1
10.3.2 Failure Mechanism

The measurement is performed by TLP (Td=100ns, Tr=10ns) under 25oC using wafer-level probing. The IESD
means the suggested ESD CD value.
1. For resistor, the resistance will degrade after ESD stress if IESD > ISnapback(It2)
2. The resistance of the resistor will degrade if it goes to snapback after ESD stress. The I ESD is defined as
the maximum current before snapback.
3. For contact, via, and metal, the TLP current density (CD) has chance of degradation after ESD stress if
IESD > 0.5 * It2.
The contact/via/metal ESD failure have the form of an open connection, the change of the sheet resistance,
the degradation of electromigration lifetime. The TLP current density (IESD) is defined as the half of maximum
current before open connection.
10.3.3 Maximum ESD Current Density for Resistor

Below table shows the IESD of resistor.
TLP Specification IESD>12mA
(Tr=10ns; Td=100ns) (ESD.CD. 2gU)
Resistor ESD
IESD The suggested metal
Current Density (Normalized by width, width, contact and via
contact and via number ) number.
Silicided N+ PO
N/A N/A
Resistor (rnpoly)
Silicided P+ PO
N/A N/A
Resistor (rppoly)
Silicided N+ OD
N/A N/A
Resistor (rnod)
Silicided P+ OD
N/A N/A
Resistor (rpod)
Unsilicided N+ PO
7.32 mA/um 1.7 um
Resistor (rnpolywo)
Unsilicided P+ PO
3.68 mA/um 3.3 um
Resistor (rppolywo)
Unsilicided N+ OD
8.2 mA/um 1.5 um
Resistor (rnodwo)
Unsilicided P+ OD
24 mA/um 0.5 um
Resistor (rpodwo)
NW Resistor [under
N/A N/A
STI) (rnwsti)
NW Resistor [under
N/A N/A
OD) (rnwod)
10.3.4 Maximum ESD Current Density for Via and Metal

Below table shows the IESD of via, contact and metal width for HBM 2KV specification.
TLP Specification IESD>1.3A Specification IESD>12mA
(Tr=10ns; Td=100ns) (ESD.CD. 1gU) (ESD.CD. 2gU)
Metal, via, and
contact ESD IESD The suggested metal The suggested metal
Backend (Normalized by width, width, contact and via width, contact and via
contact and via number ) number. number.
M1 (130nm) 75 mA/um 17.4 um 0.16 um

Mx (140nm) 85 mA/um 15.3 um 0.14 um
My (310nm) N/A N/A N/A
Mz (900nm) 425 mA/um 3.06 um 0.028 um
Mr (1250nm) N/A N/A N/A
Mu(3400nm) N/A N/A N/A
AP N/A N/A N/A
Contact (N+ OD) 5.5 mA/CO 237 3
Contact (P+ OD) 4.5 mA/CO 289 3
Contact (Poly) 5.5 mA/CO none 3
VIAx
31 mA/via 42 1
(0.07um x 0.07um)
VIAy
N/A N/A N/A
(0.14um x 0.14um)
VIAz
240 mA/via 6 1
(0.36um x 0.36um)
VIAr
N/A N/A N/A
(0.46um x 0.46um)
VIAu
N/A N/A N/A
(0.36um x 0.36um)
RV N/A N/A N/A
10.3.5 Minimum ESD Current for ESD Device

ESD.CD.1gU Suggested minimum ESD current (IESD) for the primary ESD discharge path. ≥ 1.3A
(Fig.10.3.5)
Primary ESD devices include dual-diode, ESD MOS in regular I/O, ESD MOS in
HV-tolerant I/O, power clamp, and back to back (b2b) diode.
Primary ESD discharge current path include:

1. Metal line width connecting the bond pad and the primary ESD device.
2. The contact number in the primary ESD device
3. The Via number in the primary ESD device
ESD.CD.2gU Suggested minimum ESD current (IESD) for the secondary ESD discharge path. ≥ 12mA
(Fig.10.3.5)
Secondary ESD devices include ESD resistor, diode based and MOS based
secondary protections.
Secondary ESD discharge current path include:

1. Metal line width connecting the bond pad and the secondary ESD device.
2. The contact number in the secondary ESD device
3. The Via number in the secondary ESD device
VDD
Pad
1st 2nd
pull-up pull-up
RESD
IO Power
Pad Clamp
1st 2nd
pull-dn pull-dn
b2b
diode
VSS1 VSS2
Pad Pad
Figure 10.3.5 ESD current path
10.4 Tips for the ESD/Latchup design

10.4.1 Tips for General Latchup Design
To enhance Latchup immunity, the following guidelines are recommended.
1) Solid guard ring/STRAP coonection:

 All the guard rings and STRAPs should be connected to VDD/VSS directly with very low parasitic
resistance. Use as many M0_OD and VIAs as possible.
2) Large-size capacitor displacement current induced LUP:
 A P+ guard-ring should separate a large capacitor and MOS to avoid displacement current induce latch-up.
The p+ guard ring width should be enlarger than 0.1 μm.
3) Potential Latchup concern from OD/NW resistor:
If OD/NW resistor is connected to an I/O PAD, this OD/NW resistor may potentially inject substrate current through its
parasitic diode or parasitic BJT during LUP over-current tests. Potential latchup issue may exists if this OD/NW
resistor is nearby parasitic pnpn (SCR).
10.4.2 Tips for General ESD Design

To enhance ESD immunity, the following guidelines are recommended.
1) Complete ESD protection coverage:

 Any Drain/Source/Gate of a transistor connected to a pad should have ESD protection.
2) Solid back-end in the entire ESD discharge path:
 M0_OD and VIAs should be as many as possible in all ESD devices and current paths, including the diode
and metal connection.
3) Robust victim design with use of drain-ballasted NMOS:
 When using drain-ballasted NMOS as I/O ESD protection device, the gate length of post driver should be
larger than the gate length of drain-ballasted NMOS.
4) Pass-gate exists between PAD and internal block:
If a pass-gate (IO device) is added between a PAD and core device, take care if the ESD protection device can
effectively protect the core device. It is not allowed to use IO device to protect the core device (as shown in below
figure). If the pass gate device (I/O device) covered with SDI layer, the DRC will be triggered to check ESD.1g.
VDD
Pass gate device should be covered with SDI layer
to trigger ESD.1g DRC checking.
SDI layer
PAD Pass gate
SDI layer Core

MOS
IO device
VSS
 Figure 10.4.2.1

5) Potential ESD concern from OD/NW resistor:
The OD resistor can potentially trigger its parasitic diode /BJT, leading to ESD failure during ESD stress.
To reduce this ESD vulnerability:.

A. For P+ OD resistor, adopt floating NW design when possible.
B. For N+ OD resistor, enclose hot side (connected to I/O PAD) with NW when possible.
C. Surround OD/NW resistor with double guard rings. Avoid local high field and current crowding during ESD by
layout optimization.
Have robust ESD network design with low turn-on voltage and low clamping voltage. The aim is to avoid parasitic
device turn-on.
10.4.3 Tips for Power-Ground ESD Protection

To avoid ESD damage to internal circuits, it’s critical to arrange robust whole chip ESD protection design. Special
care should be paid to the digital and analog circuits. In the mixed-mode ICs, separate digital and analog powers are used,
and the interface devices between the digital and analog circuits are particularly sensitive to ESD damage. Bellow are
some guidelines for robust power-ground design.
1) Power protection for each Vdd/Vss domain:

Each set of VDD and VSS must have its own power clamp cells to provide direct discharge path between
VDD and VSS. The number of power clamp cells should be as many as allowed.
2) Inter-domain power protection design:
Cross-couple power clamps between each power/ground combination are necessary. This includes
Vdd(x) to Vss(y) and Vdd(x) to Vdd(y). The x and y denote different power supply combination.
3) Recommended power protection design:
The recommended power ESD protection cell is gate-driven NMOS.
4) Receommended power protection design:
Implement largest total channel width allowed for better ESD immunity. TSMC design rule only represent
a bare minimum requirement on size.
5) Evenly distributed power protection design:
Use at least one clamping and/or conduction cell for every 1.0Ω of power line resistance.
6) Power bus design:
Power lines should keep ultra low resistance and avoid disconnection. For different powers or grounds
with the same potential, use bi-directional cell such as back to back diodes to link them together.
7) Latchup avoidance:
Each component of power clamp and back to back diode cells must be surrounded by double guard
rings to avoid latch up events.
8) Active clamp trigger circuit design:
Avoid mis-trigger due to power noise or glitch by carefully designing the certain aspects in turn-on
detector circuit, for example, the RC time constant and the junctions acting as minority collectors.
If the detector circuit is RC-inverter trigger circuit design, the ratio between inverter NMOS and PMOS
should be carefully considered to prevent any burn-out issue during reliability (such as burn-in) test
period.
9) Robust body diode/parasitic diode design:
Guard rings directly connected to VDD or VSS power pad should be as wide as possible, to avoid silicon
burn out on parasitic junction diode during ESD events.
10.4.4 Tips for MOS gate directly connected to

power/ground/IO PAD
10.4.4.1 MOS gate directly connected to Power/Ground PAD
Gate oxide with direct connection to Power/Ground is a potential ESD weak spot - especially for CDM. The
restriction on direct gate connection to Power/Ground PAD depends on Gate oxide type:
1) No restriction for I/O voltage gate oxide.
2) Core voltage gate can NOT directly connect to power/ground with a few exceptions.
ESD vulnerable gate connection design:

1) Core voltage device gate connects to Power directly and either device source or drain connects to Ground
2) Core voltage device gate connects to Ground directly and either device source or drain connects to Power
VDD VDD VDD VDD
Core NMOS Core PMOS

Not allow Not allow Not allow
DNW
Not allow
Core PMOS Core NMOS
VSS VSS VSS VSS

(a) (b) (c) (d)
Figure 10.4.4.1.1
Exceptions (core-voltage gate direct connection to power/ground is allowed):

1) Decoupling capacitor (including varactor type; see Figure 10.4.4.1.2)
2) Header/Footer design (see Figure 10.4.4.1.3)
3) GGNMOS/GDPMOS across power/ground design: (see Figure 10.4.4.1.4)
 GGNMOS: Gate, bulk, and either drain or source connect to ground while the leftover drain or source is
connected to power.
 GDPMOS: Gate, bulk, and either drain or source connect to power while the leftover drain or source is
connected to ground.
N-decap. P-decap.
VDD VDD
Core NMOS
Include varactor
allow
allow
Core PMOS
include varactor
VSS VSS
(a) (b)
Figure 10.4.4.1.2
Footer Design Header Design

VDD VDD
Core NMOS
allow
allow
Core PMOS
(a) VSS (b) VSS

Figure 10.4.4.1.3
GGNMOS Design GDPMOS Design

VDD VDD
allow Core NMOS

allow Core PMOS
(a) VSS (b) VSS

Figure 10.4.4.1.4
Solutions:
1) Core voltage gate is connected to Power/Ground through tie-high/tie-low cells.
VDD VDD VDD VDD

allow Core PMOS
allow Core NMOS
tie high tie high
Core NMOS
allow allow DNW
tie low tie low
Core PMOS
VSS VSS VSS VSS

(a) (b) (d) (d)
Figure 10.4.4.1.5
10.5 ESD testing methodology

10.5.1 Stress condition and Measurement condition
The ESD test items include HBM and MM which need to meet MIL-STD 883 and JEDEC standards. The rise time and
decay time of HBM are within 10ns and 150ns, respectively. The rise time and period of MM are within 10ns and 80ns,
respectively. The specification for HBM is 2KV and for MM is 100V. The peak currents of 2KV HBM is1.2A-1.48A and for
MM 100V is 1.4A-1.9A.
The ESD test is performed at room temperature. The sample size for ESD test is three devices and each device are
stressed three times at each voltage level. The DC parametric and functional testing at room temperature is performed on
all devices before ESD testing. The test devices need to meet device data sheet requirements and the DC parameters.
The pin zapping combinations depend on the number of power pin groups like VDD1, VDD2, VSS1, VSS2, GND, etc.
Please refer to MIL-STD 883 and JEDEC standards.
10.5.2 Failure criteria

The DC parametric and functional testing of the device should be characterized after each voltage level to check the
device ESD failure threshold. The device will be defined as a failure if, after exposure to ESD pulses, it no longer meets
the device data sheet requirements using DC parameter and functional testing.
11 CLN45LP/LPG Reliability Rules

11.1 Terminology
11.2 Front-end process reliability rules and models
11.3 Back-end process reliability rules
The information in this chapter is to help customers meet their product application needs and their design-in
reliability goals. The following sections include descriptions about gate oxide integrity, hot carrier effect
injection (HCI), PMOS negative bias temperature instability (NBTI), EM, and SM specifications.
11.1 Terminology
This section provides definitions for key terms that are included in this chapter.
Table 11.1.1
Term Definition
MTTF The lifetime in which 50% of the population has failed
0.1% cumulative failure The lifetime in which 0.1% of the population has failed
11.2 Front-End Process Reliability Rules and

Models
This section provides information about overdrive voltage, gate oxide integrity, HCI degradation, and negative
bias temperature instability.
11.2.1 I/O Over Drive Voltage
For 2.5V I/O device, it can be overdrived to 3.3V with 10% tolerance. The assumptions are:
1. The device concerns Idsat shift only, not Vt shift. The failure criterion is Idsat shift 10%, and an AC lifetime
of 10 years.
2. Device operated at 3.3V only, and 10% Idsat shift is based on 3.3V Idsat value.
3. And, to meet overdrive requirement, poly channel length must be extended to:
(A) NMOS Lg_minimum extend to 0.5um for 3.3V + 10%.
(B) PMOS Lg_minimum extend to 0.4um for 3.3V + 10%
11.2.2 Gate Oxide Integrity

This section provides information to help customers predict gate oxide reliability and prevent a time dependent
dielectric breakdown (TDDB). TDDB is the breakdown of gate oxide induced by a combination of voltage,
junction temperature, and oxide thickness.
Warning: Following the information in this section ensures a reliability performance of a
0.1% cumulative failure rate for reference conditions as a function of transistor type, oxide
thickness and area, junction temperature, and applied gate voltage. Deviations from the
information could result in a potentially unreliable integrated circuit. For specific memory or
analog capacitor applications, please consult with TSMC to ensure the required product
level reliability specification can be met.
11.2.2.1 Gate Oxide Lifetime Prediction Model

For core thin gate oxide and I/O thick gate oxide:
Time to failure  (Vcc)-n  exp (Ea/KT)  (Aox)-1/
Where:
Aox is the total gate oxide area on silicon (unit: m2)
T is the absolute junction temperature (unit: K)
Vcc is the gate voltage (unit: volt)
n is the power law exponent for core thin gate oxide
Ea is the thermal activation energy
k is the Boltzmann’s constant ((8.617  10-5) cV/K)
 is the Weibull shape factor (distribution spread)
11.2.2.2 Failure Mechanism

When an electron current is passed through gate oxide, defects such as electron traps, interface states,
positively charged donor-like traps, and so on, gradually build up in the gate oxide until a conduction path is
formed, followed by thermal run away.
According to the anode hole injection model, injected electrons generate holes at the anode that can tunnel
back into the oxide. Intrinsic breakdown occurs when a critical hole density is reached.
11.2.2.3 Test Methodology

11.2.2.3.1 Measurement Conditions
1. Ig is the gate current with Vb=Vs=Vd=GND. T=125C.
2. Vg is set to 3.6~ 7.0 volts for N45LP/N45LPG (I/O) gate oxide.
3. Vg is set to 3.4 ~ 3.8 volts for N45LP/N45LPG (LP oxide), or 2.5 ~3.0 volts for N45LPG (G oxide) for thin
(core) gate oxide.
11.2.2.3.2 Stress Conditions
At least 50 samples constitute a sample size for core.
At least 30 samples constitute a sample size for I/O.
1. To determine the voltage acceleration factor (n), 3 stress voltages are used at each fixed stress
temperature.
2. To determine the thermal activation energy (Ea), 3 stress temperatures are used at each fixed stress
voltage.
11.2.2.3.3 Failure Criteria
The failure criterion for thin (core) gate oxide is an onset of the first soft breakdown when there is a gate
current (Ig) progressively increasing in noise or variance, and progressive breakdown model will be applied to
extend core oxide lifetime after soft breakdown for overdrive purpose if needed. The failure criterion for thick
(I/O) gate oxide is a hard breakdown.
11.2.2.3.4 DC Lifetime and Vmax

DC Lifetime and Vmax for 45nm LP/LPG as shown below:
The following tables provide an example of maximum gate voltage (Vccmax) calculations for 45nm LP/LPG core
gate oxide applications. The reference conditions are a gate oxide area of 0.1 cm² for core, 0.01cm² for IO, a
cumulative failure rate of 0.1%, and a duty factor of 100%.
Table 11.2.2.3.4.1 45nm LP 1.1V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
Area (Aox=0.1cm²); Failure Rate (Fref=0.1%) Duty Factor of 100%
NMOS PMOS
LifeTime T= T= T= T= Lifetime T= T= T= T=
(Years) 65C 85C 105C 125C (Years) 65C 85C 105C 125C
10 1.68 1.65 1.62 1.59 10 1.48 1.44 1.4 1.37
7 1.7 1.66 1.63 1.6 7 1.49 1.45 1.41 1.38
5 1.71 1.67 1.64 1.62 5 1.5 1.46 1.43 1.4
NMOS PMOS
10 2.7 2.65 2.6 2.56 10 3.02 2.9 2.8 2.71
7 2.72 2.67 2.62 2.58 7 3.04 2.93 2.82 2.74
5 2.74 2.69 2.64 2.6 5 3.07 2.95 2.85 2.76
NMOS PMOS
10 4.45 4.34 4.24 4.16 10 4.81 4.69 4.58 4.49
7 4.49 4.38 4.28 4.19 7 4.85 4.73 4.62 4.53
5 4.52 4.41 4.31 4.23 5 4.89 4.77 4.66 4.57
Table 11.2.2.3.4.4 45nm LPG 0.9V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
NMOS PMOS
10 1.15 1.13 1.1 1.08 10 1.3 1.22 1.16 1.11
7 1.16 1.14 1.11 1.09 7 1.32 1.25 1.18 1.13
5 1.17 1.15 1.12 1.1 5 1.34 1.27 1.2 1.15
NMOS PMOS
10 1.67 1.64 1.61 1.59 10 1.47 1.43 1.4 1.37
7 1.69 1.65 1.62 1.6 7 1.49 1.44 1.41 1.38
5 1.7 1.67 1.64 1.61 5 1.5 1.46 1.42 1.39
NMOS PMOS
10 2.71 2.66 2.61 2.57 10 3.02 2.91 2.81 2.72
7 2.73 2.68 2.63 2.59 7 3.05 2.93 2.83 2.74
5 2.75 2.7 2.65 2.61 5 3.07 2.95 2.85 2.76
11.2.3 Hot Carrier Injection Effect

Hot carriers are holes or electrons that have been accelerated to a high energy by a local electric field. Hot
carrier degradation can significantly impact circuit performance and functionality. It is important for circuit
designers to carefully check the lifetime degradation of their designs caused by hot carrier injection (HCI).
Cumulative degradation and process variation must be taken into account for burn-in, field operation, and
overdrive applications.
11.2.3.1 Lifetime Prediction Model for Device Degradation

Owing to the importance of hot carrier injection on circuit operation, customers should employ detailed models
to calculate device degradation during circuit operation and to simulate the impact on circuit operation. The
following is a general model for the degradation of device characteristics:
MTTF = A x f (L, W)  (%)1/n  exp [B  (1/Vds)]  exp [Ea/k (1/T)]
Where:
MTTF is the mean time to failure
L is the drawn channel length (unit: μm)
W is the drawn channel width (unit: μm)
% dsat, 10% Gm)
Vds is the drain to source bias (unit: volt)
n is the power law factor of time dependent degradation
Ea is the activation energy
k is the Boltzmann constant ((8.617  10-5) cV/K)
A and B are empirical fitting parameters

A percentage of the energetic hot carriers will impact the lattice and create electron-hole pairs. The created
electron-hole pairs will create even more pairs later on. If the hot carriers have a kinetic energy larger than the
silicon-insulator barrier height, some of the carriers may surmount the barrier and be propelled toward the
insulator that has a moderate or higher gate bias. These carriers can either be trapped in the oxide region or
at the Si-SiO2 interface. The trapped charges from HCI stress have the following effect on the transistors:
1. Shift in the Vt (threshold voltage) of the device
2. Reduced mobility of the conducting carriers
3. Reduced device drain current
4. Increased effective series resistance, from a charge trapped above the S/D extension region
5. Degraded sub-threshold slope
These transistor changes are dependent on the amount of HCI stress that is incurred. The HCI stress in the
transistor is dependent on several factors: Lgate, Vds, Vgs, Vbs, and temperature.

1. Idsat is the forward saturation region drain current with Vd=Vg=Vcc, Vs=Vb=GND.
2. Idlin is the forward linear region drain current with Vd=0.05V Vcc, Vg=Vcc, Vs=Vb=GND.
3. Gm is the maximum transconductance with Vd=0.1V, Vs=Vb=GND.
4. Vt is the threshold voltage extrapolated at maximum transconductance.
1. The core device is stressed at Vd=Vg < 90% device breakdown voltage; Vs=Vb=GND.
2. The IO device is stressed at a given Vd < 90% device breakdown voltage; Vg is at the maximum substrate
current for a given Vd; Vs=Vb=GND.
11.2.3.3.3 Dimension Ranges of Stress Devices
1. Channel Length: 0.04um for core N/PMOS devices,
0.15um for 1.8V I/O N/PMOS devices,
0.27um for 2.5V I/O N/PMOS devices,
2. Channel Width: 10um for core N/PMOS devices,
10um for 1.8/2.5V I/O N/PMOS devices
11.2.3.3.4 Failure Criteria and Spec

The failure criteria for all devices are 10% degradation
1. Spec= AC 10 yrs
2. Spec= DC 0.05 yrs for core device
3. Spec= DC 0.2 yrs for IO device
4. AC/DC factor= 50 for core and IO.
11.2.3.3.5 DC Lifetime and Vmax: Vcc = 1.1V +- 10% and 1.2V +- 5% for N45LP
DC Lifetime definition: 0.1% cum
Criteria: Idsat shift 10%:
N45LP
1.1V Core (STD): NMOS=0.211 [email protected]. Vmax of NMOS=1.25V for W/L=10/0.04, 125℃
[email protected]. Vmax of PMOS=1.28V for W/L=10/0.04, 125℃
1.8V IO: [email protected]. Vmax of NMOS= 2V for W/L=10/0.15, 25℃
[email protected]. Vmax of PMOS= 2.251V for W/L=10/0.15, 25℃
2.5V IO: [email protected]. Vmax of NMOS= 2.9V for W/L=10/0.27, 25℃
2.5V OD 3.3V IO: [email protected]. Vmax of NMOS=3.64V for W/L=10/0.5, 25℃
11.2.3.3.6 DC Lifetime and Vmax: Vcc = 1.1V +- 10% and 1.2V +- 5% for
N45LPG_LP, Vcc = 0.9V+10% and 1.0V +- 5% for N45LPG_G

Criteria: Idsat shift 10%:
N45LPG
PMOS=0.36 [email protected]. Vmax of PMOS=1.057V for W/L=10/0.04, 125℃
1.8V IO: [email protected]. Vmax of NMOS=1.99V for W/L=10/0.15, 25℃
11.2.4 Negative Bias Temperature Instability (NBTI)

Negative Bias Temperature Instability (NBTI) is a key reliability item below 65nm technology that is of newer
aging issue in p-channel MOS devices stressed with negative gate voltages. The high temperature and bias
on Gate terminal will cause significantly NBTI effect, which increase in the threshold voltage and decrease in
drain current. It is significant for circuit designers to consider the lifetime degradation ratio of their designs
caused by negative bias temperature instability (NBTI) and must be taken into account for burn-in, field
operation, and overdrive applications from process variation.
11.2.4.1 Lifetime Prediction Model for Negative Bias

Temperature Instability
The lifetime for the negative bias temperature instability (NBTI) is correlated with voltage, temperature,
parametric failure criteria, device length, and device width.
MTTF = A  f (L, W)  (Idsat%)1/n  exp [- xVg]  exp [Ea/k (1/T)]
Where:
Idsat dsat degradation percentage
Vg is the operation gate bias (unit: volt)
 is the voltage acceleration factor
T is the absolute junction temperature (unit:K)
A is a constant
11.2.4.2 Lifetime Prediction Model for AC

For an acceptable specification, the AC lifetime must be considered. Currently, TSMC’s proposed standard
is an AC-to-DC factor of 2, based on the assumption that the off-state operation occupies half the product’s
operation time. The accepted AC lifetime is 10 years, with a DC lifetime of 5 years at temperature 125C.

The PMOS device has a lower mobility than the NMOS device. Mobility for a PMOS device is decreased
further, and significantly, by negative bias stress on the transistor gate under a high temperature environment.
A hole injected under negative bias into the oxide-substrate interface increases interface states. The
electrochemical reaction induces device instability that is enhanced by boron implanted in the gate poly
engineering process. Logic circuits could suffer from the driving current decrease, and analog circuits could
suffer from the mismatching or shift of threshold voltage.
Negative bias temperature stress under constant voltage (DC) causes the generation of interface trap (N IT)
before the gate oxide and Si substrate, which translate to device Vt shift and Ion loss. The NBTI effect is more
severe for PMOS than NMOS due to the process of holes in the PMOS inversion layer that are known to
interact with oxide state.

11.2.4.4.1 Measurement Condition
Idsat is the saturation region of drain current with Vd=Vg=Vcc, Vs=Vb=GND at a stress temperature.
1. Sample size is at least 5 samples for each stress condition.
2. Voltage range is 6~ 10MV/cm for core devices and 6 ~ 10 MV/cm for I/O devices.
3. Temperature range is 125C ~ 175C.
4. Channel Length: 0.04 μm for core N/PMOS devices,
0.15 mm for 1.8V I/O N/PMOS devices,0.27 μm for 2.5V I/O N/PMOS devices,
5. Channel Width: 10 mm for core N/PMOS devices,
10 mm for 1.8/2.5V I/O N/PMOS devices
The failure criterion for NBTI is Idsat 10% degradation for N45LP/N45LPG SVT/LVT device , and 15% for
N45LP HVT device.
Spec=DC 5 years, AC/DC factor=2
11.2.4.4.4 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +-5% for N45LP
N45LP:
1.1V Core (SVT): [email protected]. Vmax of PMOS=1.234V for W/L=10/0.04, 125℃
1.1V Core (HVT): [email protected]. Vmax of PMOS=1.269V for W/L=10/0.04, 125℃
1.1V Core (LVT): [email protected]. Vmax of PMOS=1.327V for W/L=10/0.04, 125℃
1.8V IO: PMOS=6.36 [email protected]. Vmax of PMOS= 2.0V for W/L=10/0.15, 125℃
2.5V IO: [email protected]. Vmax of PMOS= 3.31V for W/L=10/0.27, 125℃
2.5V OD 3.3V IO: [email protected]. Vmax of PMOS=3.7V for W/L=10/0.4, 125℃
11.2.4.4.5 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +- 5% for
N45LPG:
0.9V Core (SVT): PMOS=9.04 [email protected]. Vmax of PMOS=1.016V for W/L=10/0.04, 125℃
1.1V Core (SVT): [email protected]. Vmax of PMOS=1.228V for W/L=10/0.04, 125℃
1.8V IO: [email protected]. Vmax of PMOS=1.998V for W/L=10/0.15, 125℃
11.2.5 N45 Poly Current Density

The maximum current density for poly resistor (unsilicided) is 0.50 * Wp mA at a junction temperature of 110C.
This density is calculated using 0.1% point of measurement data at a 5% resistance increase after 100K hours
of continuous operation. Wp (in μm) represents the drawn width of poly line.
Use the following table to calculate Imax if the junction temperature differs from 110C. For a junction
temperature below 105C, use the rule at 105C.
Table 11.2.5.1
Junction temperature 105C 110C 125C
Rating factor of Jmax 1.03 1.00 0.927
For example, Imax (at 125C) = 0.927  Imax (at 110C).

This rule is applicable to N+, and P+ unsilicided poly resistors.
For silicided poly, the maximum DC current density is 6 * Wp mA at a junction temperature of 110C. This
density is calculated using 0.1% point of measurement data at a 5% resistance increase after 100K hours of
continuous operation. Wp (in μm) represents the drawn width of poly line.
11.2.6 N45 Poly EM Joule heating

11.2.6.1 Irms Current
The following table (Table 11.2.6.1) provides the maximum allowed current (Irms or DC) for poly. In this table,
Wp (in μm) represents the drawn width of poly line and ∆ T (C) is the temperature rise due to Joule heating
effect.
Table 11.2.6.1, Wp: poly drawn width

poly Irms (mA)
unsilicided Sqrt [0.003614 x △ T x Wp x (Wp + 0.96) ]
silicided Sqrt [0.168 x △ T x Wp x (Wp + 1.604) ]
Table 11.2.6.2 Example for the relationships of Irms (mA), poly width (μm), and joule heating effect (∆T)
Irms for unsilicided poly(mA), Sqrt [0.003614 x △ T x Wp x (Wp + 0.96) ]
Poly width (μm) ΔT=10 ℃ ΔT=20 ℃ ΔT=30 ℃ ΔT=40 ℃ ΔT=50 ℃ ΔT=60 ℃
0.04 0.038 0.054 0.066 0.076 0.085 0.093
0.5 0.162 0.230 0.281 0.325 0.363 0.398
1 0.266 0.376 0.461 0.532 0.595 0.652
3 0.655 0.927 1.135 1.310 1.465 1.605
Irms for silicided poly (mA), Sqrt [0.168 x △ T x Wp x (Wp + 1.604) ]

0.04 0.332 0.470 0.576 0.665 0.743 0.814
0.5 1.329 1.880 2.303 2.659 2.973 3.256
1 2.092 2.958 3.623 4.183 4.677 5.123
3 4.817 6.812 8.343 9.634 10.771 11.799
11.2.6.2 Ipeak
The following table provides the Ipeak allowed for poly, In the table, Wp (in μm) represents the drawn width of
poly line.
Table 11.2.6.3
poly Ipeak (mA)
unsilicided 1.5* Wp
silicided 26* Wp
Ipeak is the current at which a poly line undergoes excessive Joule heating and can begin to melt. This
current should be used infrequently.
11.2.7 N45 OD Current Density

For diffusion (OD) unsilicided resistors and/or silicided interconnect, no Imax rule is given. Since diffusion
(OD) is crystalline silicon with implantation, no electromigration or Joule heating problems occur. If the
design follows contact, metal, and via current density rules, there will be no reliability concern for diffusion
(OD).
11.3 Back-End Process Reliability Rules

11.3.1 Stress Migration (SM)
The Cu vias are frequently subjected to significant stress. The stress frequently causes voids, commonly
referred to stress migration (SM) or stress-induced voids (SIV).

The stress result from the different coefficient of thermal expansion (CTE) between Cu and the surrounding
material will drive micro-vacancy in Cu to diffuse and agglomerate through interfacial surface and grain
boundary. Eventually the stress-induced voids may significantly affect the electrical characteristics and may
cause the semiconductor structure to fail.

The measurement is performed under 25 C using wafer-level probing after oven bake. The baking
temperature ranges between 125C and 250C.
A DUT is considered as failed if 10% resistance increase is reached.
11.3.1.3 SM design rule

Please refer to below rule codes of chapter4.
VIAx.R.2, VIAx.R.3, VIAx.R.4, VIAx.R.5, VIAx.R.6, VIAx.R.8, VIAx.R.11, VIAy.R.2, VIAy.R.3, VIAy.R.4, VIAy.R.5,
VIAy.R.6, VIAy.R.11, VIAz.R.2, VIAz.R.3, VIAr.R.2, VIAr.R.3
11.3.2 Low-k Dielectric Integrity
This section provides information to help customers predict LK dielectric reliability and prevent a time
dependent dielectric breakdown (TDDB). IMD TDDB is the breakdown of LK dielectric induced by a
combination of operation voltage, temperature, and oxide thickness.
11.3.2.1 Low-k Dielectric Lifetime Prediction Model

TTF = A x exp(-r*E0.5) x exp(Ea/kT)
TTF : Time to Failure
A: a constant
r: field acceleration factor
E: electric field
Ea: activation energy
k: Boltzman’s constant
T: temperature

While the current passed through LK dielectric and formed a conduction path, it would result in LK dielectric
breakdown.
The possible failure mechanisms after IMD-TDDB test could be as followings.
1. Dielectric interface breakdown (ie: LK dielectric porosity, ESL integration, Cu ions residue…etc.)
2. Dielectric bulk breakdown (ie: trench barrier formation, LK dielectric porosity…etc.)

1. Ig is the leakage current between metal lines at T=125C under Ed (constant stress field).
2. Ed is set to 2 ~ 4 MV/cm.
A DUT is considered as failed if Ig (Tbd) > 100 * Ig (T0).
11.3.2.3.3 Lifetime
0.1% Cum.Fail > 10 years @1.1Vcc, 125C
11.3.2.4 Low-k dielectric integrity design rule

Please refer to below rule codes of chapter4.
M1.S.1, M1.S.8, M1.S.8.1, Mx.S.1, Mx.S.8, Mx.S.8.1
11.3.3 Cu Metal Current Density (EM) Specifications

This section provides information to evaluate the quality of N45 Cu process and to determine the EM lifetime
of metal line, via, stack via, contact under normal operation condition.
11.3.3.1 Electromigration Lifetime Prediction Model
TTF = A x J^(-n) x exp(Ea/kT)
A: a constant which contains a factor involving the cross-sectional area of the film
n: exponent of current density ( n =1 )
J: current density flowing in metal
Ea: activation energy ( Ea =0.9eV)
T: temperature

When a stress current is applied, Cu ions move from cathode to anode under electromigration, vacancy will
generate at cathode and it will cause resistance increasing.
11.3.3.3 Failure Criteria

A DUT is considered as failed if dR (Tbd) > 10%* R0.
11.3.3.4 Rating factor for Maximum DC Current

Imax is the maximum DC current allowed for metal lines, vias, or contacts. Imax is based on 0.1% point of
measurement data at a 10% resistance increase after 100K hours of continuous operation at 110C. Use the
following table to calculate Imax if the junction temperature differs from 110C.
Table 11.3.3.4.1
Temperature 105C 110C 115C 120C 125C
Rating factor of Imax 1.434 1.000 0.704 0.500 0.358
The rating factor is 2.077 for the case of temperature below 100℃ for joule heating effect consideration.
11.3.3.5 Maximum DC Current for Metal Lines, Contacts

and Vias (Tj = 110C)
11.3.3.5.1 General
The table provides the maximum allowed DC current, Imax for each of the metals, contacts, and vias at junction
temperature of 110C. In the table, w (in m) represents the width of the metal line.
Table 11.3.3.5.1
Metal Wiring Level / Interlevel connection Imax (mA)
M1 1.104  (w-0.010)
Mx 1.196  (w-0.010)
My(2nd inter-layer metal) 2.686  (w-0.02)
My(2XTM) 2.686  (w-0.02)
Mz 8.096  (w-0.02)
Mr 11.316  (w-0.02)
Mu 31.08  (w-0.02)
Contact (size: 0.06x0.06 μm2) 0.208 per contact
VIAx (size : 0.07  0.07 μm2) 0.072 per via
VIAy (2nd inter-layer metal) (size : 0.14  0.14μm2) 0.322 per via
VIAy (2XTM) (size : 0.14  0.14 μm2) 0.322 per via
VIAz (size : 0.36  0.36 μm2) 3.077 per via
VIAr (size : 0.46  0.46 μm2) 5.432 per via
VIAu (size : 0.36  0.36 μm2) 3.077 per via
11.3.3.5.2 Imax dependence on metal length (length ≤ 10m)

For a metal line with a length ≤ 10 m, the Imax current limit can be further increased by a factor of 1.5 for 10 ≥
L > 5 and a factor of 4 for L ≤ 5. The detailed Imax specs for various metal lines and vias are described in Table
11.3.3.5.2. In this table, w represents the width of the metal line in m, while L represents the length of the
metal line in m. The junction temperature for these specs is 110°C.
Table 11.3.3.5.2
Metal Wiring Level / Interlevel connection Metal Length, L (m) Imax (mA)
L > 10 1.104  (w-0.010)
M1 10 ≥ L > 5 1.5  1.104  (w-0.010)
L≤5 4  1.104  (w-0.010)
L > 10 1.196  (w-0.010)
Mx 10 ≥ L > 5 1.5  1.196  (w-0.010)
L≤5 4  1.196  (w-0.010)
L > 10 2.686  (w-0.02)
My (2nd inter-layer metal) 10 ≥ L > 5 1.5  2.686  (w-0.02)
L≤5 4  2.686  (w-0.02)
L > 10 2.686  (w-0.02)
My (2XTM) 10 ≥ L > 5 1.5  2.686  (w-0.02)
L≤5 4  2.686  (w-0.02)
L > 10 8.096  (w-0.02)
Mz 10 ≥ L > 5 1.5  8.096  (w-0.02)
L≤5 4  8.096  (w-0.02)
L > 10 11.316  (w-0.02)
Mr 10 ≥ L > 5 1.5  11.316  (w-0.02)
L≤5 4  11.316  (w-0.02)
L > 10 31.08  (w-0.02)
Mu 10 ≥ L > 5 31.08  (w-0.02)
L≤5 31.08  (w-0.02)
L > 10 0.072 per via
VIA (size : 0.07  0.07 μm2) 10 ≥ L > 5 1.5  0.072 per via
L≤5 4  0.072 per via
L > 10 0.322 per via
VIAy (2nd inter-layer metal) (size : 0.14  0.14 μm2) 10 ≥ L > 5 1.5  0.322 per via
L≤5 4  0.322 per via
L > 10 0.322 per via
VIAy (2XTM) (size : 0.14  0.14 μm2) 10 ≥ L > 5 1.5  0.322 per via
L≤5 4  0.322 per via
L > 10 3.077 per via
VIAz (size : 0.36  0.36 μm2) 10 ≥ L > 5 1.5  3.077 per via
L≤5 4  3.077 per via
L > 10 5.432 per via
VIAr (size : 0.46  0.46 μm2) 10 ≥ L > 5 1.5  5.432 per via
L≤5 4  5.432 per via
L > 10 3.077 per via
VIAu (size : 0.36  0.36 μm2) 10 ≥ L > 5 3.077 per via
L≤5 3.077 per via
Note: The current enhancement factors (the coefficients in the column of “Imax (mA)”) described in Table
11.3.3.5.2 (length dependence) and Table 11.3.3.5.3 (width dependence) should not be multiplied
together because multiplying them together would be too aggressive. Only one enhancement factor from
either Table 11.3.3.5.2 or Table 11.3.3.5.3 can be applied to the enhanced Imax spec, but not both.
(1) Metal Length Definition (L):

The total length of metal wiring level is from one line-end site to another site line-end site of metal.
L M x+ 1 M x+ 1 M x+ 1
Vx Vx Vx
M x
(2) For the Via length rule, use whichever L is larger between upper_metal and lower_metal.
If L1 is larger than L2, Imax of via for short length is based on L1.
L2
M x+ 1
Vx
Mx
L1
For example : Via1 connect to 10um-length M1 and 5um-length M2.

Imax of M1 = 1.5 x1.104 x (w-0.010)
Imax of M2 = 4x 1.196 x (w-0.010)
Imax of Via1= 1.5 x0.072
11.3.3.5.3 Imax dependence on metal width (width ≥ 0.5 µm)

For a metal line with a width ≥ 0.5 m, the Imax current limit is improved by a factor of 2 compared with a
corresponding narrow metal line (w < 0.5). The detailed Imax specs for various metal lines and vias are
described in Table 11.3.3.3.5.3. In this table, w represents the width of the metal line in m. The junction
temperature for these specs is 110°C.
Table 11.3.3.5.3
Metal Wiring Level / Interlevel connection Metal width, w (m) Imax (mA)
w < 0.5 1.104  (w-0.010)
M1
w ≥ 0.5 2 x 1.104  (w-0.010)
w < 0.5 1.196  (w-0.010)
Mx
w ≥ 0.5 2 x 1.196  (w-0.010)
w < 0.5 2.686  (w-0.02)
My (2nd inter-layer metal)
w ≥ 0.5 2 x 2.686  (w-0.02)
w < 0.5 2.686  (w-0.02)
My (2XTM)
w ≥ 0.5 2 x 2.686  (w-0.02)
w < 0.5 8.096  (w-0.02)
Mz
w ≥ 0.5 2 x 8.096  (w-0.02)
Mr w ≥ 0.5 2 x 11.316  (w-0.02)
Mu w ≥ 2.0 1 x 31.08  (w-0.02)
Contact (size: 0.06 x 0.06 μm2) Any metal width 0.208 per contact
w < 0.5 0.072 per via
VIAx (size : 0.07  0.07 μm2)
w ≥ 0.5 2 x 0.072 per via (Array)
w < 0.5 0.322 per via
VIAy (2nd inter-layer metal) (size : 0.14 x 0.14 μm2)
w ≥ 0.5 2 x 0.322 per via (Array)
w < 0.5 0.322 per via
VIAy (2XTM) (size : 0.14 x 0.14 μm2)
w ≥ 0.5 2 x 0.322 per via (Array)
w < 0.5 3.077 per via
VIAz (size : 0.36  0.36 μm2)
w ≥ 0.5 2 x 3.077 per via (Array)
w < 0.5 5.432 per via
VIAr (size : 0.46  0.46 μm2)
w ≥ 0.5 2 x 5.432 per via (Array)
w < 0.5 3.077 per via
VIAu (size : 0.36  0.36 μm2)
w ≥ 0.5 1 x 3.077 per via (Array)
together because multiplying them together would be too aggressive. Only one enhancement factor
from either Table 11.3.3.5.2 or Table 11.3.3.5.3 can be applied to the enhanced Imax spec, but not both.
The maximum allowed current for per via can be raised together with this wide metal EM rule (w ≧ 0.5) but
via-array is needed.
Recommended Rule: The number of contacts and vias placed across a line (perpendicular to direction of
current flow) must be maximized to increase reliability by providing redundancy in the case of blocked or
resistive vias. (increases as much as the line width permits).
Narrow Line SECURITY B – TSMC RESTRICTED SECRET
tsmc Narrow Line
Confidential – Do Not Copy Version : 2.6
Required vias
Wide Line
Recommended
Wide Line
11.3.3.5.4 Stacked Vias

Stacked via can decompose to single via, and follow single via rule.
11.3.3.5.5 DC Operation, Required Number of Vias

(1) If space permits, it is preferable to have more contacts or vias than the EM rules require.
(2) At a minimum rule, the EM current rules require one via.
(a) Example 1, if M1 is 0.07 μm and the current density is 1.104 mA/μm; that is, the current is
1.104*(0.07-0.010) = 0.066 mA, only one VIA1 is necessary to ensure the reliability margin.
(b) Example 2, if M2 is 0.07 μm and the current density is 1.196 mA/μm; that is, the current is
1.196*(0.07-0.010) = 0.072 mA, only one VIA1 and one VIA2 are necessary to ensure the reliability
margin.
(3) To determine the required number of vias, please proceed as follow:
(a) From the DC current given in section 11.3.3.5, determine the necessary line width (W-line);
(b) Calculate the Maximum allowed Idc_line for the given line width (W-line).
(c) Calculate the required number of contacts or vias to carry line current Idc_line : Number of vias =
Idc_line/ Idc_via.
(4) Recommended Rule: The number of contacts and vias placed across a line (perpendicular to direction of
resistive vias. ( increases as much as the line width permits).
N a r r o w L in e N a r r o w L in e
N a r r o w L in e
N a r r o w L in e
R e q u ir e d v ia s
W id e L in e
R e co m m e n d e d
W id e L in e
11.3.4 AP RDL Current Density (EM) Specifications

11.3.4.1 Maximum DC Current
Jmax is maximum DC current allowed per um of AP RDL metal line width or per RV via. The number is based
on 0.1% point of measurement data at 10% resistance increase after 100K hours of continuous operation at
110C. Use the following table to calculate Imax if the junction temperature differs from 110C.
Table 11.3.4.1
Temperature 85C 90C 95C 100C 105C 110C 115C 120C 125C
Rating factor of Imax 1.800 1.623 1.466 1.329 1.151 1.000 0.872 0.764 0.671
For example, Jmax (at 125C) = 0.671  Jmax (at 110C).
If the junction temperature is below 85C, please use the rating factor (1.800) at 85C or contact with TSMC
reliability.
11.3.4.2 Maximum DC Current for AP RDL Metal Lines (Tj =

110C)
The table provides the maximum allowed DC current, Imax for each of the metal wiring levels at junction
temperature of 110C. In the table, w (in μm) represents the width of the metal line.
Table 11.3.4.2
Metal Wiring Level Imax (mA)
AP RDL (14.5KÅ ) 2.7  w
AP RDL (28KÅ ) 5.21  w
11.3.4.3 Maximum DC Current for AP RDL (RV) Vias (Tj =

110C)
The table provides the maximum allowed DC current, Imax for each of the contact and via at junction
temperature of 110C. In the table, the sizes of contact and via are also noted.
Table 11.3.4.3
Interlevel Connection Imax (mA) Size
RV 12.15 per RV 3  3 μm2
RV 5.4 per RV 2  2 μm2
11.3.5 Cu Metal AC Operation

11.3.5.1 Pulsed Signal Terminology
The general terminology for a pulsed DC or AC signal is:
Period ()
Duration (tD)
For your convenience, you could measure the pulse width of Ipeak at half the peak to define the duration (tD).
The definition of Ipeak is:
I peak
 max  I (t ) 
I (t) I (t)
Ipeak  Ipeak
1/2 Ipeak
tD
duration Time, t Time, t
tD
duration
, period , period
11.3.5.2 Average Value of the Current

Iavg is the average value of the current, which is the effective DC current. Therefore, Iavg rules are identical to
Imax rules. Please refer to the DC EM sections. The temperature de-rating table is also applicable to the Iavg
rule for a junction temperature different from 110C.
The definition of Iavg is:

  
 I ( t ) dt  / 
I avg 
   0  
11.3.5.3 Root-Mean-Square Current

Irms is the root-mean-square of the current through a metal line. The definition of Irms is:
1/2

  
I ( t ) dt  / 
2
 
I rms
   0  
The following tables provide the Irms allowed for each of the metal wiring levels at a junction temperature of
110C. In the table, w (in μm) represents the width of the metal line and ∆T (C) is the temperature rise due to
Joule heating.
Note to use IrmsΔT limitation:

The EM lifetime is a function of temperature and current density. The higher temperature will cause EM lifetime
degradation. Table 11.3.5.3 is the degradation factor for EM lifetime. The recommend temperature increase,
ΔT is below < 5 °C. Because a 5 °C temperature increase is sufficient to degrade the EM lifetime by about
30%.
Table 11.3.5.3
ΔT Temp TTF
110C 1
5C 115C 0.704
10C 120C 0.500
15C 125C 0.358
20C 130C 0.258
30C 140C 0.138
For M1MxMz combination, please refer to sections 11.3.5.3.1 and 11.3.5.3.2.

For M1MxMyMz, M1MxMr, and M1MxMy combinations, please refer to sections 11.3.5.3.3, 11.3.5.3.4,
11.3.5.3.5, and 11.3.5.3.6.
11.3.5.3.1 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMz

process, no My)
Table 11.3.5.3.1.1
Metal level Irms (mA)
M1 Sqrt [ 18.04 x ∆ T x (w -0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
M2 Sqrt [ 4.86 x ∆ T x (w - 0.01) x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
2
M3 Sqrt [ 2.73 x ∆ T x(w - 0.01)2 x( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]

M4 Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
M5 Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
M6 Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
M7 Sqrt [ 0.99 x ∆ T x (w - 0.01)2 x( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
M8 Sqrt [ 0.85 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
M9 Sqrt [ 4.73 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.936 ) / ( w - 0.02 + 0.0443 ) ]
M10 Sqrt [ 3.98 x ∆ T x(w - 0.02)2 x ( w - 0.02 + 2.303 ) / ( w - 0.02 + 0.0443 ) ]
Table 11.3.5.3.1.2 Example Root-Mean-Square Current for ∆T = 5C

M1 Sqrt [ 90.20 x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
M2 Sqrt [ 24.30 x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
M3 Sqrt [ 13.65 x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
M4 Sqrt [ 9.50 x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
M5 Sqrt [ 7.25 x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
M6 Sqrt [ 5.90 x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
M7 Sqrt [ 4.95 x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
M8 Sqrt [ 4.25 x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
M9 Sqrt [ 23.65 x (w - 0.02)2 x ( w - 0.02 + 1.936 ) / ( w - 0.02 + 0.0443 ) ]
M10 Sqrt [ 19.90 x (w - 0.02)2 x ( w - 0.02 + 2.303 ) / ( w - 0.02 + 0.0443 ) ]
11.3.5.3.2 Root-Mean-Square Current for LK Dielectrics (other metallization

options, M1MxMz process, no My)
Table 11.3.5.3.2.1 and Table 11.3.5.3.2.2 apply to 1P8M process. For other metallization options, please use
Irms of M9 and M10 as the first and second Mz, respectively.
For example, 1P8M with M2 ~ M7 as Mx, and M8 as Mz, the Irms rules are:
Table 11.3.5.3.2.1
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2
x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
M2 Sqrt [ 4.86 x ∆ T x (w - 0.01) x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 )
2 ]
M3 Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
M4 Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
M5 Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
M6 Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
M7 Sqrt [ 0.99 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
M8 Sqrt [ 4.73 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.936 ) / ( w - 0.02 + 0.0443 ) ]
Another example, 1P8M with M2 ~ M6 as Mx, M7 and M8 as Mz, the Irms rules are:
Table 11.3.5.3.2.2
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2
x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
M2 Sqrt [ 4.86 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
M3 Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
M4 Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
M5 Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
M6 Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
M7 Sqrt [ 4.73 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.936 ) / ( w - 0.02 + 0.0443 ) ]
M8 Sqrt [ 3.98 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.303 ) / ( w - 0.02 + 0.0443 ) ]
11.3.5.3.3 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMz

process)
Table 11.3.5.3.3.1
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 4.86 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 0.99 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 0.85 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
My1 Sqrt [ 2.01 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
My2 Sqrt [ 1.55 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.028 ) / ( w - 0.02 + 0.0443 ) ]
Mz1 Sqrt [ 3.74 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
Mz2 Sqrt [ 3.25 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.815 ) / ( w - 0.02 + 0.0443 ) ]
Table 11.3.5.3.3.2 Example Root-Mean-Square Current for ΔT = 5C

M1 Sqrt [ 90.20 x (w - 0.01)2x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 24.30 2
x (w - 0.01) x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 13.65 x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 9.50 x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 7.25 x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 5.90 x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 4.95 x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 4.25 x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
My1 Sqrt [ 10.05 x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
My2 Sqrt [ 7.75 x (w - 0.02)2 x ( w - 0.02 + 2.028 ) / ( w - 0.02 + 0.0443 ) ]
Mz1 Sqrt [ 18.7 x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
Mz2 Sqrt [ 16.25 x (w - 0.02)2 x ( w - 0.02 + 2.815 ) / ( w - 0.02 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 5x2y2z, then use Mx1 ~ Mx5, My1 ~ My2, and Mz1 ~ Mz2.
If the metal scheme is 1P10M with M1 + 6x1y2z, then use Mx1 ~ Mx6, My1, and Mz1 ~ Mz2
If the metal scheme is 1P9M with M1 + 5x2y1z, then use Mx1 ~ Mx5, My1 ~ My2, and Mz1.

options, M1MxMyMz process)
Table 11.3.5.3.4.1 and Table 11.3.5.3.4.2 apply to 1P10M process. For other metallization options, please
use Irms of M9 and M10 as the first and second Mz, respectively. Please refer to the section 2.5 of
Metallization Options for allowed metal schemes.
For example, 1P10M with M1 + 5x2y2z (M2 ~ M6 as Mx, M7 ~ M8 as My, and M9 ~ M10 as Mz), the Irms
rules are:
Table 11.3.5.3.4.1
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
M2 (Mx1) Sqrt [ 4.86 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
M3 (Mx2) Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
M4 (Mx3) Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
M5 (Mx4) Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
M6 (Mx5) Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
M7 (My1) Sqrt [ 2.01 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
M8 (My2) Sqrt [ 1.55 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.028 ) / ( w - 0.02 + 0.0443 ) ]
M9 (Mz1) Sqrt [ 3.74 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
M10 (Mz2) Sqrt [ 3.25 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.815 ) / ( w - 0.02 + 0.0443 ) ]
Another example, 1P10M with M1 + 6x1y2z (M2 ~ M7 as Mx, M8 as My, and M9 ~ M10 as Mz), the Irms rules
are:
Table 11.3.5.3.4.2
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2
x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
M2 (Mx1) Sqrt [ 4.86 x ∆ T x (w - 0.01) x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 )
2 ]
M3 (Mx2) Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
M4 (Mx3) Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
M5 (Mx4) Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
M6 (Mx5) Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
M7 (Mx6) Sqrt [ 0.99 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
M8 (My1) Sqrt [ 2.01 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
M9 (Mz1) Sqrt [ 3.74 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
M10 (Mz2) Sqrt [ 3.25 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.815 ) / ( w - 0.02 + 0.0443 ) ]
One more example, 1P9M with M1 + 5x2y1z (M2 ~ M6 as Mx, M7 ~ M8 as My, and M9 as Mz), the Irms rules
are:
Table 11.3.5.3.4.3
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
M2 (Mx1) Sqrt [ 4.86 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
M3 (Mx2) Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
M4 (Mx3) Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
M5 (Mx4) Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
M6 (Mx5) Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
M7 (My1) Sqrt [ 2.01 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.566 ) / ( w - 0.02 + 0.0443 ) ]
M8 (My2) Sqrt [ 1.55 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.028 ) / ( w - 0.02 + 0.0443 ) ]
M9 (Mz1) Sqrt [ 3.74 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.448 ) / ( w - 0.02 + 0.0443 ) ]
11.3.5.3.5 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMr

process)
Table 11.3.5.3.5.1
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2
x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 4.86 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 0.99 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 0.85 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
Mr1 Sqrt [ 6.51 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.953 ) / ( w - 0.02 + 0.0443 ) ]
Mr2 Sqrt [ 5.25 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 2.422 ) / ( w - 0.02 + 0.0443 ) ]

M1 Sqrt [ 90.20 x (w - 0.01)2x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 24.30 x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 13.65 x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 9.50 x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 7.25 x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 5.90 x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 4.95 x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 4.25 x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
Mr1 Sqrt [ 32.55 x (w - 0.02)2 x ( w - 0.02 + 1.953 ) / ( w - 0.02 + 0.0443 ) ]
Mr2 Sqrt [ 26.25 x (w - 0.02)2 x ( w - 0.02 + 2.422 ) / ( w - 0.02 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x2r, then use Mx1 ~ Mx7, and Mr1 ~ Mr2.
If the metal scheme is 1P9M with M1 + 6x2r, then use Mx1 ~ Mx6, and Mr1 ~ Mr2
If the metal scheme is 1P9M with M1 + 7x1r, then use Mx1 ~ Mx7, and Mr1.
11.3.5.3.6 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMy

process, My/Vy are used as 2X top Metal/Via)
Table 11.3.5.3.6.1
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2
x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 4.86 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 0.99 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 0.85 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
My1_TM Sqrt [ 1.70 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.853 ) / ( w - 0.02 + 0.0443 ) ]
My2_TM Sqrt [ 1.58 x ∆ T x (w - 0.02)2 x ( w - 0.02 + 1.992 ) / ( w - 0.02 + 0.0443 ) ]

M1 Sqrt [ 90.20 x (w - 0.01)2x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 24.30 2
x (w - 0.01) x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 13.65 x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 9.50 x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 7.25 x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 5.90 x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 4.95 x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 4.25 x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
My1_TM Sqrt [ 8.50 x (w - 0.02)2 x ( w - 0.02 + 1.853 ) / ( w - 0.02 + 0.0443 ) ]
My2_TM Sqrt [ 7.8 x (w - 0.02)2 x ( w - 0.02 + 1.992 ) / ( w - 0.02 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x2y, then use Mx1 ~ Mx7, and My1_TM ~ My2_TM.
If the metal scheme is 1P9M with M1 + 6x2y, then use Mx1 ~ Mx6, and My1_TM ~ My2_TM
If the metal scheme is 1P9M with M1 + 7x1y, then use Mx1 ~ Mx7, and My1_TM.
11.3.5.3.7 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMzMu

process, Mu/Vu are used as top Metal/Via)
Table 11.3.5.3.7.1
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2
x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 4.86 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 0.99 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 0.85 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
My1 Sqrt [ 2.01 x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 1.566 ) / ( w - 0.020 + 0.0443 ) ]
Mz1 Sqrt [ 4.23 x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 2.043 ) / ( w - 0.020 + 0.0443 ) ]
Mu1 Sqrt [ 14.22 x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 2.432 ) / ( w - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x1z1u, then use Mx1 ~ Mx7, Mz1, and Mu1.
If the metal scheme is 1P9M with M1 + 5x1y1z1u, then use Mx1 ~ Mx5, My1, Mz1, and Mu1.
If the metal scheme is 1P9M with M1 + 6x1y1u, then use Mx1 ~ Mx6, My1, and Mu1.
If the metal scheme is 1P6M with M1 + 4x1u, then use Mx1 ~ Mx4, and Mu1.

M1 Sqrt [ 90.20 x (w - 0.01)2x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 24.30 x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 13.65 x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 9.50 x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 7.25 x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 5.90 x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 4.95 x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 4.25 x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
My1 Sqrt [ 10.05 x (w - 0.020 )2 x ( w - 0.020 + 1.566 ) / ( w - 0.020 + 0.0443 ) ]
Mz1 Sqrt [ 21.15 x (w - 0.020 )2 x ( w - 0.020 + 2.043 ) / ( w - 0.020 + 0.0443 ) ]
Mu1 Sqrt [ 71.10 x (w - 0.020 )2 x ( w - 0.020 + 2.432 ) / ( w - 0.020 + 0.0443 ) ]
11.3.5.3.8 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMu

process, My/Vy are 2XTM, Mu/Vu are used as top Metal/Via)
Table 11.3.5.3.8.1
M1 Sqrt [ 18.04 x ∆ T x (w - 0.01)2
x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 4.86 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 2.73 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 1.9 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 1.45 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 1.18 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 0.99 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 0.85 x ∆ T x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
My_TM Sqrt [ 1.70 x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 1.853 ) / ( w - 0.020 + 0.0443 ) ]
Mu1 Sqrt [ 16.40 x ∆ T x (w - 0.020 )2 x ( w - 0.020 + 2.110 ) / ( w - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x1y1u, then use Mx1 ~ Mx7, My_TM, and Mu1.

M1 Sqrt [ 90.20 x (w - 0.01)2x ( w - 0.01 + 0.264 ) / ( w - 0.01 + 0.0443 ) ]
Mx1 Sqrt [ 24.30 x (w - 0.01)2 x ( w - 0.01 + 0.293 ) / ( w - 0.01 + 0.0443 ) ]
Mx2 Sqrt [ 13.65 x (w - 0.01)2 x ( w - 0.01 + 0.522 ) / ( w - 0.01 + 0.0443 ) ]
Mx3 Sqrt [ 9.50 x (w - 0.01)2 x ( w - 0.01 + 0.751 ) / ( w - 0.01 + 0.0443 ) ]
Mx4 Sqrt [ 7.25 x (w - 0.01)2 x ( w - 0.01 + 0.980 ) / ( w - 0.01 + 0.0443 ) ]
Mx5 Sqrt [ 5.90 x (w - 0.01)2 x ( w - 0.01 + 1.209 ) / ( w - 0.01 + 0.0443 ) ]
Mx6 Sqrt [ 4.95 x (w - 0.01)2 x ( w - 0.01 + 1.437 ) / ( w - 0.01 + 0.0443 ) ]
Mx7 Sqrt [ 4.25 x (w - 0.01)2 x ( w - 0.01 + 1.666 ) / ( w - 0.01 + 0.0443 ) ]
My_TM Sqrt [ 8.50 x (w - 0.020 )2 x ( w - 0.020 + 1.868 ) / ( w - 0.020 + 0.0443 ) ]
Mu1 Sqrt [ 82.00 x (w - 0.020 )2 x ( w - 0.020 + 2.110 ) / ( w - 0.020 + 0.0443 ) ]
If the metal scheme is 1P9M with M1 + 6x1y1u, then use Mx1 ~ Mx6, My1_TM, and Mu1.
11.3.5.4 Peak Current

Ipeak = max ( | I(t) | )
Ipeak is the current at which a metal line undergoes excessive Joule heating and can begin to melt. This current
should be used infrequently.
The limit for the peak current, Ipeak, can be calculated by using the following formula:
I peak _ DC
I peak

r
Note: the above equation is only applicable for frequency larger than 1 MHz and r larger than 0.05.
r is the duty ratio, which is equal to the pulse duration divided by the period,
tD
r 

where Ipeak_DC is provided in the following table. In the table, w (in μm) represents the width of the metal line.
Table 11.3.5.4
Metal Level Ipeak_DC (mA)
M1 26.0  (w-0.01)
Mx 14.0  (w-0.01)
My (2nd inter-layer metal) 21.0  (w-0.02)
My (2XTM) 21.0  (w-0.02)
Mz 63.0  (w-0.02)
Mr 87.5  (w-0.02)
Mu 202.8  (w-0.02)
The Ipeak rule applies to the periodic AC or pulsed DC signals.

For a single event high current pulse or signals which cannot be specified by duty ratio, please follow the ESD
guidelines.
The Ipeak rules provided in this section are applicable to signals with a pulse width (tD) of less than 1sec. No
temperature adjustment factor for the Irms and Ipeak is given.
The Irms and Ipeak of contacts and vias do not include because the heating in contacts and vias is negligible and
is usually determined by metal or substrate. If the metal width is increased to some extent and only one via is
used in that metal, then the heating in the via cannot be considered negligible. However, if the design follows
the SM rules, via heating can be negligible. Please follow the VIAx.R.2~VIAx.R.6, VIAy.R2~VIAy.R6,
VIAz.R.2~VIAz.R.3 and VIAr.R.2~VIAr.R.3 rules to make sure that the via heating is not a problem.
11.3.6 AP RDL AC Operation

The general terminology for AP RDL is the same as Cu interconnects.
The following tables provides the maximum Irms allowed for AP RDL at a junction temperature of 110C. In the
table, w (in μm) represents the width of the RDL line and ∆ T (C) is the temperature rise due to Joule heating.
Table 11.3.6
AP RDL (14.5KÅ ) Sqrt [ 2.54  ∆ T  w  ( w + 2.924 ) ]
AP RDL (28KÅ ) Sqrt [ 4.90  ∆ T  w  ( w + 2.924 ) ]
The Ipeak rule for AP RDL (14.5KÅ ) is 58 mA/um.
The Ipeak rule for AP RDL (28KÅ ) is 112 mA/um.
12 CLN40LP/LPG/45GS(=40G) Reliability
Rules
12.1 Terminology
12.2 Front-end process reliability rules and models
12.3 Back-end process reliability rules
The information in this chapter is to help customers meet their product application needs and their design-in
reliability goals. The following sections include descriptions about gate oxide integrity, hot carrier effect
injection (HCI), PMOS negative bias temperature instability (NBTI), EM, and SM specifications.
12.1 Terminology
This section provides definitions for key terms that are included in this chapter.
Table 12.1.1
Term Definition
MTTF The lifetime in which 50% of the population has failed
0.1% cumulative failure The lifetime in which 0.1% of the population has failed
12.2 Front-End Process Reliability Rules and

Models
This section provides information about overdrive voltage, gate oxide integrity, HCI degradation, and negative
bias temperature instability.
12.2.1 I/O Over Drive Voltage
For 2.5V I/O device, it can be operated at 3.3V with 10% tolerance. The assumptions are:
1. The device concerns Idsat shift only, not Vt shift. The failure criterion is Idsat shift 10%, and an AC lifetime
of 10 years.
2. Device operated at 3.3V only, and 10% Idsat shift is based on 3.3V Idsat value.
3. And, to meet overdrive requirement, poly channel length must be extended to:
(A) NMOS Lg_minimum extend to 0.55um (drawn width) for 3.3V + 10%.
(B) PMOS Lg_minimum extend to 0.44um (drawn width) for 3.3V + 10%
12.2.2 Gate Oxide Integrity
This section provides information to help customers predict gate oxide reliability and prevent a time dependent
dielectric breakdown (TDDB). TDDB is the breakdown of gate oxide induced by a combination of voltage,
junction temperature, and oxide thickness.
Warning: Following the information in this section ensures a reliability performance of a
0.1% cumulative failure rate for reference conditions as a function of transistor type, oxide
thickness and area, junction temperature, and applied gate voltage. Deviations from the
information could result in a potentially unreliable integrated circuit. For specific memory or
analog capacitor applications, please consult with TSMC to ensure the required product
level reliability specification can be met.
12.2.2.1 Gate Oxide Lifetime Prediction Model

For core thin gate oxide and I/O thick gate oxide:
Time to failure  (Vcc)-n  exp (Ea/KT)  (Aox)-1/
Time to failure  exp(rVcc)  exp (Ea/KT)  (Aox)-1/ for 3.3V IO only
Where:
Aox is the total gate oxide area on silicon (unit: m2)
Vcc is the gate voltage (unit: volt)
n is the power law exponent for core thin gate oxide
r is the voltage acceleration factor for 3.3V thick gate oxide
Ea is the thermal activation energy
k is the Boltzmann’s constant ((8.617  10-5) cV/K)
 is the Weibull shape factor (distribution spread)

When an electron current is passed through gate oxide, defects such as electron traps, interface states,
positively charged donor-like traps, and so on, gradually build up in the gate oxide until a conduction path is
formed, followed by thermal run away.
According to the anode hole injection model, injected electrons generate holes at the anode that can tunnel
back into the oxide. Intrinsic breakdown occurs when a critical hole density is reached.

1. Ig is the gate current with Vb=Vs=Vd=GND. T=125C.
2. Vg is set to 3.6~ 8.6 volts for N40LP/N40LPG/40G (I/O) gate oxide.
3. Vg is set to 3.4 ~ 3.8 volts for N40LP/N40LPG (LP oxide), or 2.5 ~3.0 volts for N40G/N40LPG (G
oxide) for thin (core) gate oxide.
At least 50 samples constitute a sample size for core.
At least 30 samples constitute a sample size for I/O.
1. To determine the voltage acceleration factor (n), 3 stress voltages are used at each fixed stress
temperature.
2. To determine the thermal activation energy (Ea), 3 stress temperatures are used at each fixed stress
voltage.
The failure criterion for thin (core) gate oxide is an onset of the first soft breakdown when there is a gate
current (Ig) progressively increasing in noise or variance, and progressive breakdown model will be applied to
extend core oxide lifetime after soft breakdown for overdrive purpose if needed. The failure criterion for thick
(I/O) gate oxide is a hard breakdown.
12.2.2.3.4 DC Lifetime and Vmax

DC Lifetime and Vmax for 40nm LP/LPG/G as shown below:
The following table provides an example of maximum gate voltage (Vccmax) calculations for 40nm LP/LPG/G
gate oxide applications. The reference conditions are a gate oxide area of 0.1 cm² for core, 0.01cm² for IO, a
cumulative failure rate of 0.1%, and a duty factor of 100%.
Table 12.2.1 40nm LP 1.1V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
NMOS PMOS
10 1.69 1.66 1.63 1.6 10 1.47 1.43 1.4 1.37
7 1.71 1.67 1.64 1.62 7 1.49 1.45 1.41 1.38
5 1.72 1.69 1.65 1.63 5 1.5 1.46 1.42 1.39
NMOS PMOS
10 2.71 2.66 2.61 2.57 10 3.05 2.93 2.83 2.73
7 2.73 2.68 2.63 2.59 7 3.08 2.96 2.85 2.76
5 2.75 2.7 2.65 2.61 5 3.11 2.98 2.87 2.78
NMOS PMOS
10 4.4 4.29 4.19 4.11 10 4.85 4.72 4.61 4.51
7 4.44 4.33 4.23 4.14 7 4.89 4.76 4.65 4.55
5 4.48 4.37 4.27 4.18 5 4.94 4.81 4.69 4.59
Table 12.2.4 40nm LPG 0.9V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
NMOS PMOS
10 1.18 1.15 1.13 1.1 10 1.34 1.26 1.2 1.15
7 1.19 1.16 1.14 1.11 7 1.36 1.29 1.22 1.17
5 1.2 1.17 1.14 1.12 5 1.39 1.31 1.24 1.19
NMOS PMOS
10 1.69 1.65 1.62 1.6 10 1.48 1.44 1.41 1.38
7 1.7 1.67 1.64 1.61 7 1.5 1.46 1.42 1.39
5 1.71 1.68 1.65 1.62 5 1.51 1.47 1.43 1.4
NMOS PMOS
10 4.93 4.81 4.7 4.6 10 5.61 5.48 5.36 5.26
7 5.01 4.89 4.78 4.68 7 5.69 5.56 5.44 5.34
5 5.08 4.96 4.85 4.75 5 5.77 5.64 5.52 5.42
Table 12.2.7 40nm G 0.9V Maximum Gate Voltage for Reference Condition with 0% Tolerance;
NMOS PMOS
10 1.19 1.17 1.14 1.12 10 1.35 1.27 1.21 1.15
7 1.2 1.18 1.15 1.13 7 1.37 1.3 1.23 1.17
5 1.21 1.19 1.16 1.14 5 1.4 1.32 1.25 1.2
NMOS PMOS
10 2.65 2.6 2.55 2.51 10 2.97 2.85 2.75 2.66
7 2.67 2.62 2.57 2.53 7 3 2.88 2.78 2.69
5 2.69 2.64 2.59 2.55 5 3.02 2.9 2.8 2.71
NMOS PMOS
10 4.43 4.31 4.22 4.13 10 4.71 4.6 4.49 4.4
7 4.47 4.35 4.25 4.17 7 4.76 4.64 4.54 4.44
5 4.5 4.39 4.29 4.2 5 4.8 4.68 4.57 4.48
12.2.3 Hot Carrier Injection Effect

Hot carriers are holes or electrons that have been accelerated to a high energy by a local electric field. Hot
carrier degradation can significantly impact circuit performance and functionality. It is important for circuit
designers to carefully check the lifetime degradation of their designs caused by hot carrier injection (HCI).
Cumulative degradation and process variation must be taken into account for burn-in, field operation, and
overdrive applications.
12.2.3.1 Lifetime Prediction Model for Device Degradation

Owing to the importance of hot carrier injection on circuit operation, customers should employ detailed models
to calculate device degradation during circuit operation and to simulate the impact on circuit operation. The
following is a general model for the degradation of device characteristics:
MTTF = A x f (L, W)  (%)1/n  exp [B  (1/Vds)]  exp [Ea/k (1/T)]
Where:
% egradation of an electrical parameter (for example, 10% Idsat, 10% Gm)
Vds is the drain to source bias (unit: volt)
A and B are empirical fitting parameters

A percentage of the energetic hot carriers will impact the lattice and create electron-hole pairs. The created
electron-hole pairs will create even more pairs later on. If the hot carriers have a kinetic energy larger than the
silicon-insulator barrier height, some of the carriers may surmount the barrier and be propelled toward the
insulator that has a moderate or higher gate bias. These carriers can either be trapped in the oxide region or
at the Si-SiO2 interface. The trapped charges from HCI stress have the following effect on the transistors:
1. Shift in the Vt (threshold voltage) of the device
2. Reduced mobility of the conducting carriers
3. Reduced device drain current
4. Increased effective series resistance, from a charge trapped above the S/D extension region
5. Degraded sub-threshold slope
These transistor changes are dependent on the amount of HCI stress that is incurred. The HCI stress in the
transistor is dependent on several factors: Lgate, Vds, Vgs, Vbs, and temperature.
Negative bias temperature stress under constant voltage (DC) causes the generation of interface trap (N IT)
before the gate oxide and Si substrate, which translate to device Vt shift and Ion loss. The NBTI effect is more
severe for PMOS than NMOS due to the process of holes in the PMOS inversion layer that are known to
interact with oxide state.

1. Idsat is the forward saturation region drain current with Vd=Vg=Vcc, Vs=Vb=GND.
2. Idlin is the forward linear region drain current with Vd=0.05V, Vg=Vcc, Vs=Vb=GND.
3. Gm is the maximum transconductance with Vd=0.1V, Vs=Vb=GND.
4. Vt is the threshold voltage extrapolated at maximum transconductance.
The core device is stressed at Vd=Vg < 90% device breakdown voltage; Vs=Vb=GND.
The IO device is stressed at a given Vd < 90% device breakdown voltage; Vg is at the maximum substrate
current for a given Vd; Vs=Vb=GND.
12.2.3.3.3 Failure Criteria and Spec
The failure criteria for all devices are 10% degradation
Spec= AC 10 yrs
12.2.3.3.4 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +- 5% for N40LP
N40LP
1V Core(STD): NMOS=0.212 [email protected]. Vmax of NMOS=1.258V for W/L=10/0.04, 125℃
1.1V Core(LVT): NMOS=0.182 [email protected]. Vmax of NMOS=1.25V for W/L=10/0.04, 125℃
1.1V Core(HVT): NMOS=0.184 [email protected]. Vmax of NMOS=1.25V for W/L=10/0.04, 125℃
1.8V IO: [email protected]. Vmax of NMOS= 2.04V for W/L=10/0.15, 25℃
2.5V IO: [email protected]. Vmax of NMOS= 3V for W/L=10/0.27, 25℃
N40 LPG
0.9 V Core(STD): NMOS=3.03 [email protected]. Vmax of NMOS=1.11V for W/L=10/0.036, 105℃
0.9 V Core(LVT): NMOS=2.84 [email protected]. Vmax of NMOS=1.1V for W/L=10/0.036, 105℃
1.1V Core(STD): NMOS=0.3 [email protected]. Vmax of NMOS=1.27V for W/L=10/0.036, 105℃
1.1V Core(HVT): [email protected]. Vmax of NMOS=1.28V for W/L=10/0.036, 105℃
3.3V IO: [email protected]. Vmax of NMOS=3.64V for W/L=10/0.36, 25℃
12.2.3.3.6 DC Lifetime and Vmax : Vcc = 0.9V +- 10% and 1.0V+- 5% for N40G
N40G (=N45GS)
0.9 V Core(STD): NMOS=2.29 [email protected]. Vmax of NMOS= 1.1V for W/L=10/0.036, 125℃
PMOS=1.85 [email protected]. Vmax of PMOS= 1.09V for W/L=10/0.036, 125℃
0.9 V Core(HVT): NMOS=1.86 [email protected]. Vmax of NMOS=1.095V for W/L=10/0.036, 125℃
0.9 V Core(LVT): NMOS=3.01 [email protected]. Vmax of NMOS=1.11V for W/L=10/0.036, 125℃
1.8V IO: NMOS=1.053 [email protected]. Vmax of NMOS= 2.08V for W/L=10/0.135, 25℃
2.5V IO: NMOS=5.6191 [email protected]. Vmax of NMOS= 3.09V for W/L=10/0.243, 25℃
12.2.4 Negative Bias Temperature Instability (NBTI)

Negative Bias Temperature Instability (NBTI) is a key reliability item below 65nm technology that is of newer
aging issue in p-channel MOS devices stressed with negative gate voltages. The high temperature and bias
on Gate terminal will cause significantly NBTI effect, which increase in the threshold voltage and decrease in
drain current. It is significant for circuit designers to consider the lifetime degradation ratio of their designs
caused by negative bias temperature instability (NBTI) and must be taken into account for burn-in, field
operation, and overdrive applications from process variation.
12.2.4.1 Lifetime Prediction Model for Negative Bias

Temperature Instability
The lifetime for the negative bias temperature instability (NBTI) is correlated with voltage, temperature,
parametric failure criteria, device length, and device width.
MTTF = A  f (L, W)  (Idsat%)1/n  exp [- xVg]  exp [Ea/k (1/T)]
Where:
Idsat dsat degradation percentage
Vg is the operation gate bias (unit: volt)
 is the voltage acceleration factor
T is the absolute junction temperature (unit:K)
A is a constant
12.2.4.2 Lifetime Prediction Model for AC

For an acceptable specification, the AC lifetime must be considered. Currently, TSMC’s proposed standard
is an AC-to-DC factor of 2, based on the assumption that the off-state operation occupies half the product’s
operation time. The accepted AC lifetime is 10 years, with a DC lifetime of 5 years at temperature 125C.

The PMOS device has a lower mobility than the NMOS device. Mobility for a PMOS device is decreased
further, and significantly, by negative bias stress on the transistor gate under a high temperature environment.
A hole injected under negative bias into the oxide-substrate interface increases interface states. The
electrochemical reaction induces device instability that is enhanced by boron implanted in the gate poly
engineering process. Logic circuits could suffer from the driving current decrease, and analog circuits could
suffer from the mismatching or shift of threshold voltage.

Idsat is the saturation region of drain current with Vd=Vg=Vcc, Vs=Vb=GND at a stress temperature.
1. Sample size is at least 5 samples for each stress condition.
2. Voltage range is 6~ 10MV/cm for core devices and 6 ~ 10 MV/cm for I/O devices.
3. Temperature range is 75°C ~ 125°C.
The failure criterion for NBTI is Idsat 10% degradation for N40LP/N40LPG/N40G SVT/LVT device, and 15%
for N40LP/N40LPG/N40G HVT device.
Spec=DC 5 years, AC/DC factor=2
12.2.4.4.4 DC Lifetime and Vmax : Vcc = 1.1V +- 10% and 1.2V +- 5% for N40LP
N40LP
1.1V Core(SVT): [email protected]. Vmax of PMOS= 1.24V for W/L=10/0.04, 125℃
1.1V Core(HVT): [email protected]. Vmax of PMOS=1.259V for W/L=10/0.04, 125℃
1.1V Core(LVT): [email protected]. Vmax of PMOS= 1.297V for W/L=10/0.04, 125℃
1.8V IO: PMOS=6.82 [email protected]. Vmax of PMOS=2V for W/L=10/0.15, 125℃
2.5V OD 3.3V IO: [email protected]. Vmax of PMOS=3.755V for W/L=10/0.44, 125℃
2.5V IO: [email protected]. Vmax of PMOS= 3.466V for W/L=10/0.27, 125℃
N40LPG
0.9 V Core(SVT): PMOS=9.09 [email protected]. Vmax of PMOS=1.02V for W/L=10/0.036, 105℃
0.9 V Core(LVT): PMOS=64.3 [email protected]. Vmax of PMOS=1.12V for W/L=10/0.036, 105℃
1.1V Core(SVT): [email protected]. Vmax of PMOS=1.257V for W/L=10/0.036, 105℃
1.1V Core(HVT): [email protected]. Vmax of PMOS=1.215V for W/L=10/0.036, 105℃
3.3V IO: PMOS=104 [email protected]. Vmax of PMOS=4.235V for W/L=10/0.36, 105℃
12.2.4.4.6 DC Lifetime and Vmax : Vcc = 0.9V +- 10% and 1.0V+- 5% for N40G
N40G(N45GS)
0.9 V Core(STD): PMOS=17 [email protected]. Vmax of PMOS= 1.048V for W/L=10/0.036, 125℃
0.9 V Core(HVT): PMOS=218 [email protected]. Vmax of PMOS=1.152V for W/L=10/0.036, 125℃
0.9 V Core(LVT): PMOS=68.1 [email protected]. Vmax of PMOS=1.105V for W/L=10/0.036, 125℃
1.8V IO: PMOS=13.8 [email protected]. Vmax of PMOS= 2.078V for W/L=10/0.135, 125℃
2.5V IO: PMOS=256 [email protected]. Vmax of PMOS= 3.425V for W/L=10/0.243, 125℃
2.5V OD 3.3V IO: PMOS=14.2 [email protected]. Vmax of PMOS=3.682V for W/L=10/0.4, 125℃
12.2.5 N40 Poly Current Density

The maximum current density for poly resistor (unsilicided) is 0.50 * (Wp*0.9) mA at a junction temperature of
110C. This density is calculated using 0.1% point of measurement data at a 5% resistance increase after
100K hours of continuous operation. Wp (in μm) represents the drawn width of poly line.
Use the following table to calculate Imax if the junction temperature differs from 110C. For a junction
temperature below 105C, use the rule at 105C.
Table 12.2.5.1
Junction temperature 105C 110C 125C
Rating factor of Jmax 1.03 1.00 0.927

This rule is applicable to N+, and P+ unsilicided poly resistors.
For silicided poly, the maximum DC current density is 6 * (Wp*0.9) mA at a junction temperature of 110C.
This density is calculated using 0.1% point of measurement data at a 5% resistance increase after 100K
hours of continuous operation. Wp (in μm) represents the drawn width of poly line.
12.2.6 N40 Poly EM Joule heating

12.2.6.1 Irms current
The following table (Table 12.2.6.1) provides Irms for poly. In this table, Wp (in μm) represents the drawn width
of poly line and ∆ T (C) is the temperature rise due to Joule heating effect.
Table 12.2.6.1, Wp: poly drawn width

poly Irms (mA)
unsilicided Sqrt [0.003614 x △ T x Wp x (Wp + 0.96) ]
silicided Sqrt [0.168 x △ T x Wp x (Wp + 1.604) ]
Table 12.2.6.2 Example for the relationships of Irms(mA), poly width(μm), and joule heating effect (∆T)
Irms for unsilicided poly(mA), Sqrt [0.003614 x △ T x Wp x (Wp + 0.96) ]
0.04 0.038 0.054 0.066 0.076 0.085 0.093
0.5 0.162 0.230 0.281 0.325 0.363 0.398
1 0.266 0.376 0.461 0.532 0.595 0.652
3 0.655 0.927 1.135 1.310 1.465 1.605
Irms for silicided poly (mA), Sqrt [0.168 x △ T x Wp x (Wp + 1.604) ]

0.04 0.332 0.470 0.576 0.665 0.743 0.814
0.5 1.329 1.880 2.303 2.659 2.973 3.256
1 2.092 2.958 3.623 4.183 4.677 5.123
3 4.817 6.812 8.343 9.634 10.771 11.799
12.2.6.2 Ipeak
The following table provides the Ipeak allowed for poly, In the table, Wp (in μm) represents the drawn width of
poly line.
Table 12.2.6.3
poly Ipeak (mA)
unsilicided 1.5* Wp
silicided 26* Wp
Ipeak is the current at which a poly line undergoes excessive Joule heating and can begin to melt. This
current should be used infrequently.
12.2.7 N40 OD Current Density

For diffusion (OD) unsilicided resistors and/or silicided interconnect, no Imax rule is given. Since diffusion
(OD) is crystalline silicon with implantation, no electromigration or Joule heating problems occur. If the
design follows contact, metal, and via current density rules, there will be no reliability concern for diffusion
(OD).
12.3 Back-End Process Reliability Rules

12.3.1 Stress Migration (SM)
The Cu vias are frequently subjected to significant stress. The stress frequently causes voids, commonly
referred to stress migration (SM) or stress-induced voids (SIV).

The stress result from the different coefficient of thermal expansion (CTE) between Cu and the surrounding
material will drive micro-vacancy in Cu to diffuse and agglomerate through interfacial surface and grain
boundary. Eventually the stress-induced voids may significantly affect the electrical characteristics and may
cause the semiconductor structure to fail.

The measurement is performed under 25 C using wafer-level probing after oven bake. The baking
temperature ranges between 125C and 250C.
12.3.1.3 SM design rule

Please refer to below rule codes of chapter 4.
VIAx.R.2, VIAx.R.3, VIAx.R.4, VIAx.R.5, VIAx.R.6, , VIAxR.8, VIA.x.R.11, VIAy.R.2, VIAy.R.3, VIAy.R.4,
VIAy.R.5, VIAy.R.6, VIAy.R.11, VIAz.R.2, VIAz.R.3, VIAr.R.2, VIAr.R.3
12.3.2 Low-k Dielectric Integrity

This section provides information to help customers predict LK dielectric reliability and prevent a time
dependent dielectric breakdown (TDDB). IMD TDDB is the breakdown of LK dielectric induced by a
combination of operation voltage, temperature, and oxide thickness.
12.3.2.1 Low-k Dielectric Lifetime Prediction Model

TTF = A x exp(-r*E0.5) x exp(Ea/kT)
A: a constant
r: field acceleration factor
E: electric field
Ea: activation energy
T: temperature

While the current passed through LK dielectric and formed a conduction path, it would result in LK dielectric
breakdown.
The possible failure mechanisms after IMD-TDDB test could be as followings.
1. Dielectric interface breakdown (ie: LK dielectric porosity, ESL integration, Cu ions residue…etc.)
2. Dielectric bulk breakdown (ie: trench barrier formation, LK dielectric porosity…etc.)

1. Ig is the leakage current between metal lines at T=125C under Ed (constant stress field).
2. Ed is set to 2 ~ 4 MV/cm.
A DUT is considered as failed if Ig (Tbd) > 100 * Ig (T0).
12.3.3 Cu Metal Current Density (EM) Specifications

This section provides information to evaluate the quality of N40 Cu process and to determine the EM lifetime
of metal line, via, stack via, contact under normal operation condition.
12.3.3.1 Electromigration Lifetime Prediction Model

TTF = A x J^(-n) x exp(Ea/kT)
A: a constant which contains a factor involving the cross-sectional area of the film
n: exponent of current density ( n =1 )
J: current density flowing in metal
Ea: activation energy ( Ea =0.9eV)
T: temperature

When a stress current is applied, Cu ions move from cathode to anode under electromigration, vacancy will
generate at cathode and it will cause resistance increasing.
12.3.3.3 Failure Criteria

12.3.3.4 Rating factor for Maximum DC Current

Imax is the maximum DC current allowed for metal lines, vias, or contacts. Imax is based on 0.1% point of
measurement data at a 10% resistance increase after 100K hours of continuous operation at 110C. Use the
following table to calculate Imax if the junction temperature differs from 110C.
Table 12.3.3.4.1
Temperature 105C 110C 115C 120C 125C
Rating factor of Imax 1.434 1.000 0.704 0.500 0.358
The rating factor is 2.077 for the case of temperature below 100°C for Joule heating effect consideration.
12.3.3.5 Maximum DC Current for Metal Lines, Contacts

and Vias (Tj = 110C)
12.3.3.5.1 General
The table provides the maximum allowed DC current, Imax for each of the metals, contacts, and vias at junction
temperature of 110C. In the table, w (in m) represents the width of the drawn metal line.
Table 12.3.3.5.1
Metal Wiring Level / Interlevel connection Imax (mA)
M1 1.227  (w x0.9-0.008)
Mx 1.329  (w x0.9-0.008)
My (2nd inter-layer metal) 3.040  (w x0.9-0.02)
My (2XTM) 3.040  (w x0.9-0.02)
Mz 9.048  (w x0.9-0.02)
Mr 12.631  (w x0.9-0.02)
Mu 34.59 X (w x0.9-0.02)
Contact (size: 0.054x0.054 μm2) 0.208 per contact
VIAx (size : 0.063  0.063 μm2) 0.072 per via
VIAy (2nd inter-layer metal) (size : 0.126  0.126 μm2) 0.322 per via
VIAy (2XTM) (size : 0.126  0.126 μm2) 0.322 per via
VIAz (size : 0.324  0.324 μm2) 3.077 per via
VIAr (size : 0.414  0.414 μm2) 5.432 per via
VIAu (size : 0.324  0.324 μm2) 3.077 per via
12.3.3.5.2 Imax dependence on metal length (length ≤ 10m)

For a metal line with a length ≤ 10 m, the Imax current limit can be further increased by a factor of 1.5 for 10 ≥
L > 5 and a factor of 4 for L ≤ 5. The detailed Imax specs for various metal lines and vias are described in Table
12.3.3.5.2. In this table, w represents the width of the metal line in m, while L represents the length of the
metal line in m. The junction temperature for these specs is 110°C.
Table 12.3.3.5.2
L > 10 1.227  (w x0.9-0.008)
M1 10 ≥ L > 5 1.5  1.227  (w x0.9-0.008)
L≤5 4  1.227  (w x0.9-0.008)
L > 10 1.329  (w x0.9-0.008)
Mx 10 ≥ L > 5 1.5  1.329  (w x0.9-0.008)
L≤5 4  1.329  (w x0.9-0.008)
L > 10 3.040  (w x0.9-0.02)
My (2nd inter-layer metal) 10 ≥ L > 5 1.5  3.040  (w x0.9-0.02)
L≤5 4  3.040  (w x0.9-0.02)
L > 10 3.040  (w x0.9-0.02)
My (2XTM) 10 ≥ L > 5 1.5  3.040  (w x0.9-0.02)
L≤5 4  3.040  (w x0.9-0.02)
L > 10 9.048  (w x0.9-0.02)
Mz 10 ≥ L > 5 1.5  9.048  (w x0.9-0.02)
L≤5 4  9.048  (w x0.9-0.02)
L > 10 12.631  (w x0.9-0.02)
Mr 10 ≥ L > 5 1.5  12.631  (w x0.9-0.02)
L≤5 4  12.631  (w x0.9-0.02)
L > 10 34.590  (w x0.9-0.02)
Mu 10 ≥ L > 5 34.590  (w x0.9-0.02)
L≤5 34.590  (w x0.9-0.02)
L > 10 0.072 per via
VIAx (size : 0.063  0.063 μm2) 10 ≥ L > 5 1.5  0.072 per via
L≤5 4  0.072 per via
L > 10 0.322 per via
VIAy (2nd inter-layer metal) (size : 0.126 x 0.126 μm2) 10 ≥ L > 5 1.5  0.322 per via
L≤5 4  0.322 per via
L > 10 0.322 per via
VIAy (2XTM) (size : 0.126 x 0.126 μm2) 10 ≥ L > 5 1.5  0.322 per via
L≤5 4  0.322 per via
L > 10 3.077 per via
VIAz (size : 0.324  0.324 μm2) 10 ≥ L > 5 1.5  3.077 per via
L≤5 4  3.077 per via
L > 10 5.432 per via
VIAr (size : 0.414  0.414 μm2) 10 ≥ L > 5 1.5  5.432 per via
L≤5 4  5.432 per via
L > 10 3.077 per via
VIAu (size : 0.324 0.324 μm2) 10 ≥ L > 5 3.077 per via
L≤5 3.077 per via
together because multiplying them together would be too aggressive. Only one enhancement factor from
either Table 12.3.3.5.2 or Table 12.3.3.5.3 can be applied to the enhanced Imax spec, but not both.
(1) Metal Length Definition (L):

The total length of metal wiring level is from one line-end site to another site line-end site of metal.
L M x+ 1 M x+ 1 M x+ 1
Vx Vx Vx
M x
(2) For the Via length rule, use whichever L is larger between upper_metal and lower_metal.
L2
M x+ 1
Vx
Mx
L1
For example : Via1 connect to 10um-length M1 and 5um-length M2.

Imax of M1 = 1.5 x1.227 x (wx0.9-0.008)
Imax of M2 = 4x 1.329 x (wx0.9-0.008)
Imax of Via1= 1.5 x0.072
12.3.3.5.3 Imax dependence on metal width (width ≥ 0.5µm)

For a metal line with a width ≥ 0.5 m, the Imax current limit is improved by a factor of 2 compared with a
corresponding narrow metal line (w < 0.5). The detailed Imax specs for various metal lines and vias are
described in Table 12.3.3.5.3. In this table, w represents the width of the metal line in m. The junction
temperature for these specs is 110°C.
Table 12.3.3.5.3
w < 0.5 1.227  (wx0.9-0.008)
M1
w ≥ 0.5 2 x 1.227  (wx0.9-0.008)
w < 0.5 1.329  (wx0.9-0.008)
Mx
w ≥ 0.5 2 x 1.329  (wx0.9-0.008)
w < 0.5 3.040  (wx0.9-0.02)
My (2nd inter-layer metal)
w ≥ 0.5 2 x 3.040  (wx0.9-0.02)
w < 0.5 3.040  (wx0.9-0.02)
My (2XTM)
w ≥ 0.5 2 x 3.040  (wx0.9-0.02)
w < 0.5 9.048  (wx0.9-0.02)
Mz
w ≥ 0.5 2 x 9.048  (wx0.9-0.02)
Mr w ≥ 0.5 2 x 12.631  (wx0.9-0.02)
Mu w ≥ 2.0 1 x 34.590  (wx0.9-0.02)
Contact (size: 0.054x0.054 μm2) Any metal width 0.208 per contact
w < 0.5 0.072 per via
VIAx (size : 0.063  0.063 μm2)
w ≥ 0.5 2 x 0.072 per via (Array)
w < 0.5 0.322 per via
VIAy (2nd inter-layer metal) (size : 0.126 x 0.126 μm2)
w ≥ 0.5 2 x 0.322 per via (Array)
w < 0.5 0.322 per via
VIAy (2XTM) (size : 0.126 x 0.126 μm2)
w ≥ 0.5 2 x 0.322 per via (Array)
w < 0.5 3.077 per via
VIAz (size : 0.324  0.324 μm2)
w ≥ 0.5 2 x 3.077 per via (Array)
w < 0.5 5.432 per via
VIAr (size : 0.414  0.414 μm2)
w ≥ 0.5 2 x 5.432 per via (Array)
w < 0.5 3.077 per via
VIAu (size : 0.324  0.324 μm2)
w ≥ 0.5 1 x 3.077 per via (Array)
together because multiplying them together would be too aggressive. Only one enhancement factor
from either Table 12.3.3.5.2 or Table 12.3.3.5.3 can be applied to the enhanced Imax spec, but not both.
The maximum allowed current for per via can be raised together with this wide metal EM rule (w ≧ 0.5) but
via-array is needed.
Recommended Rule: The number of contacts and vias placed across a line (perpendicular to direction of
resistive vias. ( increases as much as the line width permits).
Narrow Line SECURITY B – TSMC RESTRICTED SECRET
tsmc Narrow Line
Confidential – Do Not Copy Version : 2.6
Required vias
Wide Line
Recommended
Wide Line
12.3.3.5.4 Stacked Vias

Stacked via can decompose to single via, and follow single via rule.
12.3.3.5.5 DC Operation, Required Number of Vias

(1) If space permits, it is preferable to have more contacts or vias than the EM rules require.
(2) At a minimum rule, the EM current rules require one via.
(a) Example 1, if M1 is 0.07 μm (drawn width) and the current density is 1.227 mA/μm; that is, the current
is 1.227*(0.07*0.9-0.008) = 0.067 mA, only one VIA1 is necessary to ensure the reliability margin.
(b) Example 2, if M2 is 0.07 μm (drawn width) and the current density is 1.329 mA/μm; that is, the current
is 1.329*(0.07*0.9-0.008) = 0.072 mA, only one VIA1 and one VIA2 are necessary to ensure the
reliability margin.
(3) To determine the required number of vias, please proceed as follow:
(a) From the DC current given in section 12.3.3.5, determine the necessary line width (W-line);
(b) Calculate the Maximum allowed Idc_line for the given line width (W-line).
(c) Calculate the required number of contacts or vias to carry line current Idc_line: Number of vias =
Idc_line/ Idc_via.
(4) Recommended Rule: The number of contacts and vias placed across a line (perpendicular to direction of
resistive vias. (increases as much as the line width permits).
Narrow Line Narrow Line
Narrow Line
Narrow Line
Required vias
Wide Line
Recommended
Wide Line
12.3.4 AP RDL Current Density (EM) Specifications

12.3.4.1 Maximum DC Current
Jmax is maximum DC current allowed per um of AP RDL metal line width or per RV via. The number is based
on 0.1% point of measurement data at 10% resistance increase after 100K hours of continuous operation at
110C. Use the following table to calculate Imax if the junction temperature differs from 110C.
Table 12.3.4.1
Temperature 85C 90C 95C 100C 105C 110C 115C 120C 125C
Rating factor of Imax 1.800 1.623 1.466 1.329 1.151 1.000 0.872 0.764 0.671
For example, Jmax (at 125C) = 0.671  Jmax (at 110C).
If the junction temperature is below 85C, please use the rating factor (1.800) at 85C or contact with TSMC
reliability.
12.3.4.2 Maximum DC Current for AP RDL Metal Lines (Tj =

110C)
The table provides the maximum allowed DC current, Imax for each of the metal wiring levels at junction
temperature of 110C. In the table, w (in μm) represents the drawn width of the metal line.
Table 12.3.4.2
Metal Wiring Level Imax (mA)
AP RDL (14.5KÅ ) 3.0  wx0.9
AP RDL (28KÅ ) 5.79  wx0.9
12.3.4.3 Maximum DC Current for AP RDL (RV) Vias (Tj =

110C)
The table provides the maximum allowed DC current, Imax for each of the contact and via at junction
temperature of 110C. In the table, the drawn sizes of contact and via are also noted.
Table 12.3.4.3
Interlevel Connection Imax (mA) Size
2
RV 12.15 per RV 3  3 μm
2
RV 5.4 per RV 2  2 μm
12.3.5 Cu Metal AC Operation
12.3.5.1 Pulsed Signal Terminology

The general terminology for a pulsed DC or AC signal is:
Period ()
Duration (tD)
For your convenience, you could measure the pulse width of Ipeak at half the peak to define the duration (tD).
The definition of Ipeak is:
I peak
 max  I (t ) 
I (t) I (t)
Ipeak  Ipeak
1/2 Ipeak
tD
duration Time, t Time, t
tD
duration
, period , period
12.3.5.2 Average Value of the Current

Iavg is the average value of the current, which is the effective DC current. Therefore, Iavg rules are identical to
Imax rules. Please refer to the DC EM sections. The temperature de-rating table is also applicable to the Iavg
rule for a junction temperature different from 110C.
The definition of Iavg is:

  
 I ( t ) dt  / 
I avg 
   0  
12.3.5.3 Root-Mean-Square Current

Irms is the root-mean-square of the current through a metal line. The definition of Irms is:
1/2

  
I ( t ) dt  / 
2
 
I rms
   0  
The following tables provide the Irms allowed for each of the metal wiring levels at a junction temperature of
110C. In the table, w (in μm) represents the drawn width of the metal line and ∆T (C) is the temperature rise
due to Joule heating.
Note to use Irms ∆T limitation:

The EM lifetime is a function of temperature and current density. The higher temperature will cause EM lifetime
degradation. Table 12.3.5.3 is the degradation factor for EM lifetime. The recommend temperature increase,
∆T is below < 5 °C. Because a 5 °C temperature increase is sufficient to degrade the EM lifetime by about
30%.
Table 12.3.5.3
∆T Temp TTF
110C 1
5C 115C 0.704
10C 120C 0.500
15C 125C 0.358
20C 130C 0.258
30C 140C 0.138
For M1MxMz combination, please refer to sections 12.3.5.3.1 and 12.3.5.3.2.

For M1MxMyMz, M1MxMr, and M1MxMy combinations, please refer to sections 12.3.5.3.3, 12.3.5.3.4,
12.3.5.3.5, and 12.3.5.3.6.
12.3.5.3.1 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMz

process, no My)
Table 12.3.5.3.1.1
M1 Sqrt [ 18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M2 Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M3 Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M4 Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M5 Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M6 Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M7 Sqrt [ 1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M8 Sqrt [ 0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M9 Sqrt [ 4.79  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.912 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M10 Sqrt [ 4.04  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.264 ) / ( w x0.9 - 0.020 + 0.0443 ) ]

M1 Sqrt [ 92.9  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
M2 Sqrt [ 25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M3 Sqrt [ 13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M4 Sqrt [ 9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M5 Sqrt [ 7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M6 Sqrt [ 5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M7 Sqrt [ 5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M8 Sqrt [ 4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M9 Sqrt [ 23.95  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.912 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M10 Sqrt [ 20.20  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.264 ) / ( w x0.9 - 0.020 + 0.0443 ) ]

Irms of M9 and M10 as the first and second Mz, respectively.
For example, 1P8M with M2 ~ M7 as Mx, and M8 as Mz, the Irms rules are:
Table 12.3.5.3.2.1
M1 Sqrt [ 18.58  ∆ T  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
M2 Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M3 Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M4 Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M5 Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M6 Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M7 Sqrt [ 1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M8 Sqrt [ 4.79  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.912 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Another example, 1P8M with M2 ~ M6 as Mx, M7 and M8 as Mz, the Irms rules are:
Table 12.3.5.3.2.2
M1 Sqrt [ 18.58  ∆ T  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
M2 Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M3 Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M4 Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M5 Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M6 Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M7 Sqrt [ 4.79  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.912 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M8 Sqrt [ 4.04  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.264 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
12.3.5.3.3 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMz

process)
Table 12.3.5.3.3.1
M1 Sqrt [ 18.58  ∆ T  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
Mx1 Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx2 Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
My1 Sqrt [ 1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
My2 Sqrt [ 1.46  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.806 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mz1 Sqrt [ 4.22  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mz2 Sqrt [ 3.63  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.519 ) / ( w x0.9 - 0.020 + 0.0443 ) ]

M1 Sqrt [ 92.90  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
0.008)2
Mx1 Sqrt [ 25.05  (w x0.9 - 0.008)  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
2
Mx2 Sqrt [ 13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9- 0.008 + 0.0443 ) ]
My1 Sqrt [ 9.00  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
My2 Sqrt [ 7.30  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.806 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mz1 Sqrt [ 21.10  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mz2 Sqrt [ 18.15  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.519 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 5x2y2z, then use Mx1 ~ Mx5, My1 ~ My2, and Mz1 ~ Mz2.
If the metal scheme is 1P10M with M1 + 6x1y2z, then use Mx1 ~ Mx6, My1, and Mz1 ~ Mz2
If the metal scheme is 1P9M with M1 + 5x2y1z, then use Mx1 ~ Mx5, My1 ~ My2, and Mz1.

Irms of M9 and M10 as the first and second Mz, respectively. Please refer to the section 2.5 of Metallization
Options for allowed metal schemes.
For example, 1P10M with M1 + 5x2y2z (M2 ~ M6 as Mx, M7 ~ M8 as My, and M9 ~ M10 as Mz), the Irms
rules are:
Table 12.3.5.3.4.1
M1 Sqrt [ 18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M2 (Mx1) Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M3 (Mx2) Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M4 (Mx3) Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M5 (Mx4) Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M6 (Mx5) Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M7 (My1) Sqrt [ 1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M8 (My2) Sqrt [ 1.46  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.806 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M9 (Mz1) Sqrt [ 4.22  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M10 (Mz2) Sqrt [ 3.63  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.519 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Another example, 1P10M with M1 + 6x1y2z (M2 ~ M7 as Mx, M8 as My, and M9 ~ M10 as Mz), the Irms rules
are:
Table 12.3.5.3.4.2
M1 Sqrt [ 18.58  ∆ T  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
M2 (Mx1) Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M3 (Mx2) Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M4 (Mx3) Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M5 (Mx4) Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M6 (Mx5) Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M7 (Mx6) Sqrt [ 1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M8 (My1) Sqrt [ 1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M9 (Mz1) Sqrt [ 4.22  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M10 (Mz2) Sqrt [ 3.63  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.519 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
One more example, 1P9M with M1 + 5x2y1z (M2 ~ M6 as Mx, M7 ~ M8 as My, and M9 as Mz), the Irms rules
are:
Table 12.3.5.3.4.3
M1 Sqrt [ 18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M2 (Mx1) Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M3 (Mx2) Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M4 (Mx3) Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M5 (Mx4) Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M6 (Mx5) Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
M7 (My1) Sqrt [ 1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M8 (My2) Sqrt [ 1.46  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.806 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
M9 (Mz1) Sqrt [ 4.22  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.167 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
12.3.5.3.5 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMr

process)
Table 12.3.5.3.5.1
M1 Sqrt [ 18.58  ∆ T  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
Mx1 Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx2 Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mr1 Sqrt [ 6.54  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.944 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mr2 Sqrt [ 5.27  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.413 ) / ( w x0.9 - 0.020 + 0.0443 ) ]

M1 Sqrt [ 92.90  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
Mx1 Sqrt [ 25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx2 Sqrt [ 13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mr1 Sqrt [ 32.70  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.944 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mr2 Sqrt [ 26.35  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.413 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x2r, then use Mx1 ~ Mx7, and Mr1 ~ Mr2.
If the metal scheme is 1P9M with M1 + 6x2r, then use Mx1 ~ Mx6, and Mr1 ~ Mr2
If the metal scheme is 1P9M with M1 + 7x1r, then use Mx1 ~ Mx7, and Mr1.
12.3.5.3.6 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMy

process, My/Vy are used as 2X top Metal/Via)
Table 12.3.5.3.6.1
M1 Sqrt [ 18.58  ∆ T  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
Mx1 Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx2 Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
My1_TM Sqrt [ 1.72  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.829 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
My2_TM Sqrt [ 1.61  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.954 ) / ( w x0.9 - 0.020 + 0.0443 ) ]

M1 Sqrt [ 92.90  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
Mx1 Sqrt [ 25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx2 Sqrt [ 13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
My1_TM Sqrt [ 8.60  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.829 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
My2_TM Sqrt [ 8.05  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.954 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
If the metal scheme is 1P9M with M1 + 7x1y, then use Mx1 ~ Mx7, and My1_TM.
12.3.5.3.7 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMzMu

process, Mu/Vu are used as top Metal/Via)
Table 12.3.5.3.7.1
M1 Sqrt [ 18.58  ∆ T  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
Mx1 Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx2 Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
My1 Sqrt [ 1.80  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mz1 Sqrt [ 4.25  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.034 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mu1 Sqrt [ 14.28  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.423 ) / ( w x0.9 - 0.020 + 0.0443 ) ]

M1 Sqrt [ 92.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx1 Sqrt [ 25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx2 Sqrt [ 13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
My1 Sqrt [ 9.00  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.469 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mz1 Sqrt [ 21.25  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.034 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mu1 Sqrt [ 71.40  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.423 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
If the metal scheme is 1P10M with M1 + 7x1z1u, then use Mx1 ~ Mx7, Mz1, and Mu1.
If the metal scheme is 1P9M with M1 + 5x1y1z1u, then use Mx1 ~ Mx5, My1, Mz1, and Mu1.
If the metal scheme is 1P6M with M1 + 4x1u, then use Mx1 ~ Mx4, and Mu1.
12.3.5.3.8 Root-Mean-Square Current for LK Dielectrics (1P10M M1MxMyMu

process, My/Vy are 2XTM, Mu/Vu are used as top Metal/Via)
Table 12.3.5.3.8.1
M1 Sqrt [ 18.58  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx1 Sqrt [ 5.01  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx2 Sqrt [ 2.78  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 1.92  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 1.47  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 1.19  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 1.00  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 0.86  ∆ T  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
My_TM Sqrt [ 1.72  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.829 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mu1 Sqrt [ 16.47  ∆ T  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.100 ) / ( w x0.9 - 0.020 + 0.0443 ) ]

M1 Sqrt [ 92.90  (w x0.9 -  ( w x0.9 - 0.008 + 0.246 ) / ( w x0.9 - 0.008 + 0.0443 )
0.008)2 ]
Mx1 Sqrt [ 25.05  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.284 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx2 Sqrt [ 13.90  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.513 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx3 Sqrt [ 9.60  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.742 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx4 Sqrt [ 7.35  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 0.970 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx5 Sqrt [ 5.95  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.199 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx6 Sqrt [ 5.00  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.428 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
Mx7 Sqrt [ 4.30  (w x0.9 - 0.008)2  ( w x0.9 - 0.008 + 1.657 ) / ( w x0.9 - 0.008 + 0.0443 ) ]
My_TM Sqrt [ 8.60  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 1.829 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
Mu1 Sqrt [ 82.35  (w x0.9 - 0.020)2  ( w x0.9 - 0.020 + 2.100 ) / ( w x0.9 - 0.020 + 0.0443 ) ]
12.3.5.4 Peak Current

Ipeak = max ( | I(t) | )
Ipeak is the current at which a metal line undergoes excessive Joule heating and can begin to melt. This current
should be used infrequently.
The limit for the peak current, Ipeak, can be calculated by using the following formula:
I peak _ DC
I peak

r
Note: the above equation is only applicable for frequency larger than 1 MHz and r larger than 0.05.
r is the duty ratio, which is equal to the pulse duration divided by the period,
tD
r 

where Ipeak_DC is provided in the following table. In the table, w (in μm) represents the drawn width of the metal
line.
Table 12.3.5.4
Metal Level Ipeak_DC (mA)
M1 25.0  (w x0.9 -0.008)
Mx 14.0  (w x0.9 -0.008)
My (2nd inter-layer metal) 18.0  (w x0.9 -0.020)
My (2XTM) 21.0  (w x0.9 -0.020)
Mz 63.0  (w x0.9 -0.020)
Mr 87.5  (w x0.9 -0.020)
Mu 202.8  (w x0.9 -0.020)
The Ipeak rule applies to the periodic AC or pulsed DC signals.

For a single event high current pulse or signals which cannot be specified by duty ratio, please follow the ESD
guidelines.
The Ipeak rules provided in this section are applicable to signals with a pulse width (tD) of less than 1sec. No
temperature adjustment factor for the Irms and Ipeak is given.
The Irms and Ipeak of contacts and vias do not include because the heating in contacts and vias is negligible and
is usually determined by metal or substrate. If the metal width is increased to some extent and only one via is
used in that metal, then the heating in the via cannot be considered negligible. However, if the design follows
the SM rules, via heating can be negligible.
12.3.6 AP RDL AC Operation

The general terminology for AP RDL is the same as Cu interconnects.
The following tables provides the maximum Irms allowed for AP RDL at a junction temperature of 110C. In the
table, w (in μm) represents the drawn width of the RDL line and ∆T (C) is the temperature rise due to Joule
heating.
Table 12.3.6
AP RDL (14.5KÅ ) Sqrt [ 2.54  ∆ T  w x0.9  ( w x0.9 + 2.924 ) ]
AP RDL (28KÅ ) Sqrt [ 4.90  ∆ T  w x0.9  ( w x0.9 + 2.924 ) ]
The Ipeak rule for AP RDL (14.5KÅ ) is 58 mA/um.
The Ipeak rule for AP RDL (28KÅ ) is 112 mA/um.
13 Appendix A Revision History

A.1 From Version 0.1 to 0.2
Rule Sec. No. Section Title Revision Description
1.1 Overview Remove 3.3V device
1.2 Reference Documentation Add MM/RF rules refere to· T-N45-CM-DR-001
2.1.1 Front-End Features Remove 3.3V device
2.1.1 Front-End Features Add SRAM size of DP and HC
2.1.2 Front-End Features Remove metal thickness
2.1.2 Front-End Features Change AL RDL to AP RDL
2.3 Power Supply and Operation Remove 3.3V device
Temperature Ranges
2.4 Cross–section Modify VIAy W/S to 0.14/0.14 from 0.13/0.15 in Figure 2.4.2 Cross-
section for 1P10M_7x2y
2.4 Cross–section Modify VIAy W/S to 0.14/0.14 from 0.13/0.15 in Figure 2.4.3 Cross-
section for 1P10M_5x2y2z
2.5 Metallization Options Modify Mask layer to “seven” from”six” in Table 2.5.1 Naming for
Different Metal Thicknesses
2.5 Metallization Options Modify Mask layer to “seven” from”six” in Table 2.5.2 Naming for
Different Metal Thicknesses
3.1 Mask Information, Key Process Remove 3.3V device
Sequence, and CAD Layout
3.1 Mask Information, Key Process Modify mask tone of 191, 152, and 118 from clear todark.
Sequence, and CAD Layers
3.1 Mask Information, Key Process Remove 3.3V at Description of mask 193.
3.1 Mask Information, Key Process Change CAD Layer to 117 from drived at mask 111.
3.1 Mask Information, Key Process Change 308 mask name to CB2 from CB, change mask ID to 107 from
Sequence, and CAD Layers 308, change CAD layer to 86;20 from 76 at option 1.
3.1 Mask Information, Key Process Change 308 mask name to CB2 from CB, change mask ID to 107 from
Sequence, and CAD Layers 308, change CAD layer to 86;0 from 76 at option 2.
3.1 Mask Information, Key Process Remove “FW” at Reference Layer in Logical Operation of mask 306,
Sequence, and CAD Layers change CAD layer to 86;20 from 86 at option 3.
3.1 Mask Information, Key Process Remove “FW” at Reference Layer in Logical Operation of mask 306,
Sequence, and CAD Layers change CAD layer to 86;0 from 86 at option 4.
3.1 Mask Information, Key Process Change VIAy mask type to ASF from DSF in Table 3.1.2 Mask
Sequence, and CAD Layers Name/ID/Grade/Type, OPC, and PSM Information
3.4 Special Recognition CAD Layer Add OD25_33 for 2.5V thick oxide (second gate oxide) overdrive to
Summary 3.3V
3.4 Special Recognition CAD Layer Add OD25_18 for 2.5V thick oxide (second gate oxide) underdrive to
Summary 1.8V
3.4 Special Recognition CAD Layer Modify Associated With of RH to “OD and PO resistor rules” from
Summary “guideline”.
3.4 Special Recognition CAD Layer Modify TSMC Default CAD Layer to 161;0 from 161, and remove “Also
Summary serves as an exclusion layer for dummy feature insertion checks.”
3.4 Special Recognition CAD Layer Add MOMDMY_1 for MOM Dummy layer rule at Table 3.4.1 Special
Summary Layer Summary
3.4 Special Recognition CAD Layer Add MOMDMY_AP for MOM Dummy layer rule at Table 3.4.1 Special
3.4 Special Recognition CAD Layer Add TCDDMY for MOM Dummy layer rule at Table 3.4.1 Special Layer
Summary Summary
3.4 Special Recognition CAD Layer Add RFIP_DMY for MOM Dummy layer rule at Table 3.4.1 Special
3.4 Special Recognition CAD Layer Add IP for MOM Dummy layer rule at Table 3.4.1 Special Layer
Summary Summary
3.4 Special Recognition CAD Layer Add ROM for ROM device at Table 3.4.1 Special Layer Summary
Summary
3.4 Special Recognition CAD Layer Add LUPWDMY for waiving latch up rules at Table 3.4.1 Special Layer
Summary Summary
3.4 Special Recognition CAD Layer Add ESDIMP for ESD implant. at Table 3.4.1 Special Layer Summary
Summary
3.4 Special Recognition CAD Layer
Add DFMEXCL at Table 3.4.1 Special Layer Summary
Summary
Add COROM at Table 3.4.1 Special Layer Summary
Summary
Add VIAxEXCL at Table 3.4.1 Special Layer Summary
Summary
3.5.1 General Purpose Superb (N45GS): Remove 3.3 device at Table 3.5.2 Device Truth Table for general
0.9V Core Design purpose superb
3.5.1 General Purpose Superb (N45GS): Modify 1.1V Varactor to “*” from “0” at Table 3.5.2 Device Truth Table
0.9V Core Design for general purpose superb
G.5 3.7.1 Design Grid Rules Remove the rule
3.7.2 OPC Recommendations and Remove the rule
OPC.R.1®
Guidelines
4.2.1 Derived Geometries Remove 3.3 device at OD2
4.4 Minimum Pitches Modify N+/P+ spacing to 0.16 from 0.18
4.4 Minimum Pitches Modify VIAy Pitch to 0.14/0.14 from 0.13/0.15.
4.4 Minimum Pitches VIAy  3 neighboring Pitch to 0.14/0.16 from 0.13/0.17.
OD.W.1® 4.5.1 Gate Oxide and Diffusion (OD) Layout Remove the rule
Rules (120)
OD.W.2 4.5.1 Gate Oxide and Diffusion (OD) Layout Modify the rule to “>= 0.12” from “=0.12~1.5”
Rules (120)
OD.W.2.1 4.5.1 OD Layout Rules Add new rule for NMOS
OD.W.2.2 4.5.1 OD Layout Rules Add new rule for PMOS
OD.A.1 4.5.1 OD Layout Rules Modify rule description to (This check doesn't include the patterns
filling 0.12*0.26 rectangular tile) from (This check doesn’t include
rectangle area with length ≧0.26um)
OD.L.1 4.5.1 OD Layout Rules Modify {ACTIVE (source) [width of rule description to 0.12 from 0.15
OD.L.2 4.5.1 OD Layout Rules Modify OD width of rule description to 0.12 from 0.15
OD.L.2gU 4.5.1 OD Layout Rules Modify rule description to Rs variation from Rs silicidation
DNW.EN.3 4.5.2 Deep N-Well (DNW) Layout Rules Modify rule value to 0.49 from 0.48
(119) [Optional]
NW.S.5 4.5.3 N-Well (NW) Layout Rules Modify rule value to 0.08 from 0.09
NW.S.6 4.5.3 N-Well (NW) Layout Rules Modify rule value to 0.08 from 0.09
NW.EN.1 4.5.3 N-Well (NW) Layout Rules Modify rule value to 0.08 from 0.09
NW.EN.2 4.5.3 N-Well (NW) Layout Rules Modify rule value to 0.08 from 0.09
NWROD.S.3® 4.5.4 N-Well Within OD (NWROD) Layout Modify the rule description to SPICE simulation accuracy from SPICE
Rules model accuracy.
NWROD.R.1® 4.5.4 N-Well Within OD (NWROD) Layout Remove the rule
Rules
NWROD.R.2gU 4.5.4 N-Well Within OD (NWROD) Layout Remove the rule
Rules
NWROD.R.3g 4.5.4 N-Well Within OD (NWROD) Layout The rule should be DRC checkable and the body (covered by marker
Rules layer) of NW resistor should be rectangular.
NWRSTI.EN.2® 4.5.5 N-Well Under STI (NWRSTI) Layout Modify the rule description to SPICE simulation accuracy from SPICE
Rules model accuracy.
NWRSTI.R.1® 4.5.5 N-Well Under STI (NWRSTI) Layout Remove the rule
Rules
NWRSTI.R.2g 4.5.5 N-Well Under STI (NWRSTI) Layout Remove the rule
Rules
NWRSTI.R.3g 4.5.5 N-Well Under STI (NWRSTI) Layout Add the rule description of “DRC can flag {NWDMY AND NW} is not a
Rules rectangle”.
NT_N.W.3 4.5.6 Native Device (NT_N) Layout Rules Remove 3.3V device)
OD2.EN.1 4.5.7 Thick Oxide (OD2) Layout Rules Remove 3.3V device
OD2.R.1 4.5.7 Thick Oxide (OD2) Layout Rules Remove 3.3V device
4.5.8 1.2V Core Oxide (OD_12) Layout Ad the new rule to provide 1.2V device
OD_12.W.1
Rules (12A)
OD_12.W.3
Rules (12A)
OD_12.S.1
Rules (12A)
OD_12.S.2
Rules (12A)
OD_12.S.3
Rules (12A)
OD_12.S.4
Rules (12A)
OD_12.S.6
Rules (12A)
OD_12.EN.1
Rules (12A)
OD_12.EN.2
Rules (12A)
OD_12.EX.3
Rules (12A)
OD_12.A.1
Rules (12A)
OD_12.A.2
Rules (12A)
OD_12.R.2
Rules (12A)
OD_12.R.3
Rules (12A)
OD_12.R.4
Rules (12A)
OD25_33.W.1 4.5.9 OD25_33 Layout Rules Add the rule to provide 2.5V overdrive to 3.3V
OD25_33.W.2 4.5.9 OD25_33 Layout Rules Add the rule to provide 2.5V overdrive to 3.3V
OD25_33.R.1 4.5.9 OD25_33 Layout Rules Add the rule to provide 2.5V overdrive to 3.3V
OD25_18.W.1 4.5.10 OD25_18 Layout Rules Add the rule to provide 2.5V underdrive to 1.8V
OD25_18.R.1 4.5.10 OD25_18 Layout Rules Add the rule to provide 2.5V underdrive to 1.8V
PO.W.1® 4.5.8 Poly (PO) Layout Rules (130) Remove this rule
PO.W.2 4.5.11 Poly (PO) Layout Rules (130) Add the rule description of (for 2.5V overdrive to 3.3V, please refer to
section 4.5.9) for overdrive
PO.W.3 4.5.11 Poly (PO) Layout Rules (130) Remove 3.3V device, remove the rule.
PO.W.4 4.5.11 Poly (PO) Layout Rules (130) Add the rule description of (for 2.5V underdrive to 1.8V, please refer
to section 4.5.10) for underdrive
PO.S.2 4.5.11 Poly (PO) Layout Rules (130) Modify rule description to “{PO OR SR_DPO}” from poly
PO.S.2.2 4.5.11 Poly (PO) Layout Rules (130) Remove this rule
PO.S.5 4.5.11 Poly (PO) Layout Rules (130) Remove this rule
PO.S.5® 4.5.11 Poly (PO) Layout Rules (130) Modify rule value to 0.06 from 0.07
PO.L.1 4.5.11 Poly (PO) Layout Rules (130) Modify PO width of rule description to 0.08 from 0.13
PO.DN.1 4.5.11 Poly (PO) Layout Rules (130) Modify rule description to add SR_DPO
PO.DN.2 4.5.11 Poly (PO) Layout Rules (130) Modify rule description to add SR_DPO
PO.DN.3 4.5.11 Poly (PO) Layout Rules (130) Modify rule description to add (except {RFDMY AND RFIP_DMY})
PO.R.7 4.5.11 Poly (PO) Layout Rules (130) Modify rule description to “(50;0 OR 186;0)”
PO.L.1gU 4.5.11 Poly (PO) Layout Rules (130) Modify rule description to Rs variation from Rs silicidation
SR_DPO.W.1 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.S.1 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.EN.1 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.EN.2 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.EX.1 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.EX.2 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.L.2 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.A.1 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.R.1 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.R.2U 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.R.4 4.5.12 SR_DPO Layout Rules Modify rule description to add SR_DPO rule
SR_DPO.R.5 4.5.12 SR_DPO Layout Rules Add the rule not to allow overlap of SRAM.
VTH_N.S.2 4.5.13 P+ Source/Drain Ion Implantation (PP) Modify rule value to 0.08 from 0.09
Layout Rules (197)
VTH_N.EN.2 4.5.13 P+ Source/Drain Ion Implantation (PP) Modify rule value to 0.08 from 0.09
Layout Rules (197)
VTH_N.L.1 4.5.13 High Vt NMOS (VTH_N) Layout Rules Add the rule
(11H)
VTH_P.S.2 4.5.14 N+ Source/Drain Ion Implantation (NP) Modify rule value to 0.08 from 0.09
Rules (198)
VTH_P.EN.2 4.5.14 N+ Source/Drain Ion Implantation (NP) Modify rule value to 0.08 from 0.09
Rules (198)
VTH_P.L.1 4.5.14 High Vt PMOS (VTH_P) Layout Rules Add the rule
(11G)
VTL_N.S.2 4.5.15 N+ Source/Drain Ion Implantation (NP) Modify rule value to 0.08 from 0.09
Rules (198)
VTL_N.EN.2 4.5.15 N+ Source/Drain Ion Implantation (NP) Modify rule value to 0.08 from 0.09
Rules (198)
VTL_N.L.1 4.5.15 Low Vt NMOS (VTL_N) Layout Rules Add the rule
(118)
4.5.16 Low Vt PMOS (VTL_P) Layout Rules Modify rule value to 0.08 from 0.09
VTL_P.S.2
(117)
4.5.16 Low Vt PMOS (VTL_P) Layout Rules Modify rule value to 0.08 from 0.09
VTL_P.EN.2
(117)
4.5.16 Low Vt PMOS (VTL_P) Layout Rules Add the rule
VTL_P.L.1
(117)
PP.S.2 4.5.17 P+ Source/Drain Ion Implantation (PP) Modify rule value to 0.08 from 0.09
Layout Rules (197)
PP.EX.1 4.5.17 P+ Source/Drain Ion Implantation (PP) Modify rule value to 0.08 from 0.09
Layout Rules (197)
PP.R.1 4.5.17 P+ Source/Drain Ion Implantation (PP) Modify rule value to 0.08 from 0.09
Layout Rules (197)
PP.L.1 4.5.17 P+ Source/Drain Ion Implantation (PP) Add the rule
Layout Rules (197)
NP.S.2 4.5.18 N+ Source/Drain Ion Implantation (NP) Modify rule value to 0.08 from 0.09
Rules (198)
NP.EX.1 4.5.18 N+ Source/Drain Ion Implantation (NP) Modify rule value to 0.08 from 0.09
Rules (198)
NP.R.1 4.5.18 N+ Source/Drain Ion Implantation (NP) Modify rule value to 0.08 from 0.09
Rules (198)
NP.L.1 4.5.18 N+ Source/Drain Ion Implantation (NP) Add the rule
Rules (198)
ESDIMP.W.1 4.5.20 ESD Implant (ESDIMP) Layout Rules Add the rule to provide ESD implant.
(MASK ID: 111)
ESDIMP.S.1 4.5.20 ESD Implant (ESDIMP) Layout Rules Add the rule to provide ESD implant.
(MASK ID: 111)
ESDIMP.EN.1 4.5.20 ESD Implant (ESDIMP) Layout Rules Add the rule to provide ESD implant.
(MASK ID: 111)
ESDIMP.EN.1® 4.5.20 ESD Implant (ESDIMP) Layout Rules Add the rule to provide ESD implant.
(MASK ID: 111)
ESDIMP.A.1 4.5.20 ESD Implant (ESDIMP) Layout Rules Add the rule to provide ESD implant.
(MASK ID: 111)
ESDIMP.A.2 4.5.20 ESD Implant (ESDIMP) Layout Rules Add the rule to provide ESD implant.
(MASK ID: 111)
ESDIMP.R.1 4.5.20 ESD Implant (ESDIMP) Layout Rules Add the rule to provide ESD implant.
(MASK ID: 111)
ESDIMP.R.2® u 4.5.20 ESD Implant (ESDIMP) Layout Rules Add the rule to provide ESD implant.
(MASK ID: 111)
RES.R.4 4.5.22 OD and Poly Resistor Layout Rules RES.12 is chaneged the guideline to rule RES.R.4
RES.R.5 4.5.22 OD and Poly Resistor Layout Rules RES.13 is chaneged the guideline to rule RES.R.5
RES.1gU 4.5.22 OD and Poly Resistor Layout Rules Remove the rule
RES.5g 4.5.22 OD and Poly Resistor Layout Rules Remove the rule
RES.12 4.5.22 OD and Poly Resistor Layout Rules Chanege the guideline to rule
RES.13 4.5.22 OD and Poly Resistor Layout Rules Chanege the guideline to rule
RES.14g 4.5.22 OD and Poly Resistor Layout Rules Remove the rule
RES.15g 4.5.22 OD and Poly Resistor Layout Rules Chanege the guideline to checkable, modify the rule description to
SPICE simulation accuracy from SPICE model accuracy.
VAR.W.1 4.5.23 MOS Varactor Layout Rules (VAR) Remove the rule description of “for the baseband circuit, according to
the SPICE model”
VAR.W.3 4.5.23 MOS Varactor Layout Rules (VAR) Add this rule for VAR.
VAR.W.4 4.5.23 MOS Varactor Layout Rules (VAR) Add this rule for VAR.
VAR.S.2® 4.5.23 MOS Varactor Layout Rules (VAR) Remove the rule
VAR.S.3® 4.5.23 MOS Varactor Layout Rules (VAR) Remove the rule
VAR.A.1® 4.5.23 MOS Varactor Layout Rules (VAR) Remove the rule
CO.S.5 4.5.24 Contact (CO) Layout Rules (156) Remove 3.3V device
CO.EN.0 4.5.24 Contact (CO) Layout Rules (156) Add the rule description of “Enclosure by OD is defined by either
{CO.EN.1 and CO.EN.1.1} or {CO.EN.1.3}”.
CO.EN.0® 4.5.24 Contact (CO) Layout Rules (156) Add the new recommendation.
CO.EN.1® 4.5.24 Contact (CO) Layout Rules (156) Modify the rule vaue to 0.04 from 0.03
CO.EN.1.1® 4.5.24 Contact (CO) Layout Rules (156) Add the new rule for recommended enclosure by OD
CO.EN.1.3 4.5.24 Contact (CO) Layout Rules (156) Add the new rule for enclosure by OD
CO.S.6g 4.5.24 Contact (CO) Layout Rules (156) Change the rule to checkable, and add “DRC can flag if the STRAP is
butted on source, one of STRAP and source is without CO.”
CO.R.1gU 4.5.24 Contact (CO) Layout Rules (156) Modify the rule description to “unexpected resistance variation.” from
“high Rs”
CO.R.5g 4.5.24 Contact (CO) Layout Rules (156) Change the guideline to “checkable” from uncheckable”. Modify the
rule description.
CO.R.6gU 4.5.24 Contact (CO) Layout Rules (156) Remove the rule
M1.S.8.1 4.5.25 M1 Layout Rules Modify to checkabke from unheckable.
M1.EN.1® 4.5.25 M1 Layout Rules Modify the rule value to 0.03 from 0.04
M1.EN.3 4.5.25 M1 Layout Rules Add the rule description of [four sides]
M1.A.1 4.5.25 M1 Layout Rules Modify the rule value to 0.0215 from 0.022
M1.A.2 4.5.25 M1 Layout Rules Modify the rule description to 0.17 from 0.21
M1.DN.1 4.5.20 Metal-1 (M1) Layout Rules (360) Modify rule area value.
M1.DN.3 4.5.20 Metal-1 (M1) Layout Rules (360) Modify rule area value.
M1.DN.3® 4.5.20 Metal-1 (M1) Layout Rules (360) Modify rule area value.
4.5.25 M1 Layout Rules Add the flow is the DRC implementation of M1.S.8, and M1.S.8.1
VIAx.EN.0 4.5.26 VIAx Layout Rules Add the new rule
VIAx.EN.1® 4.5.26 VIAx Layout Rules Modify refer section to 4.5.34 from 4.5.31, Modify rule value to 0.03
from 0.04
VIAx.EN.2® 4.5.26 VIAx Layout Rules Modify refer section to 4.5.34 from 4.5.31
VIAx.EN.4 4.5.26 VIAx Layout Rules Add one option of {VIAx.EN.4 and VIAx.EN.4.1}
VIAx.EN.4.1 4.5.26 VIAx Layout Rules Add one option of {VIAx.EN.4 and VIAx.EN.4.1}
VIAx.R.9gU 4.5.26 VIAx Layout Rules Modify refer section to 4.5.34 from 4.5.31
Mx.W.4® 4.5.27 Mx Layout Rules Remove the rule
Mx.S.5.1 4.5.27 Mx Layout Rules Add the new rule
Mx.S.8.1 4.5.27 Mx Layout Rules Modify to checkabke from unheckable.
Mx.EN.0 4.5.27 Mx Layout Rules Add the new rule
Mx.EN.1® 4.5.27 Mx Layout Rules Modify refer section to 4.5.34 from 4.5.31, Modify rule value to 0.03
from 0.04
Mx.EN.2® 4.5.27 Mx Layout Rules Modify refer section to 4.5.34 from 4.5.31
Mx.EN.3 4.5.27 Mx Layout Rules Add the new rule
Mx.EN.3.1 4.5.27 Mx Layout Rules Add the new rule
Mx.A.2 4.5.27 Mx Layout Rules Modify the rule description to 0.17 from 0.21
Mx.DN.1 4.5.27 Mx Layout Rules Modify rule area value.
Mx.DN.3 4.5.27 Mx Layout Rules Remove rule
Mx.DN.3® 4.5.27 Mx Layout Rules Remove rule
Mx.DN.5 4.5.27 Mx Layout Rules Modify rule value to 85% from 70%,
Modify rule value to “62.5μm x 62.5μm (stepping 31.25)” from “50μm x
50μm (stepping 25)”,
Modify rule value to 85% from 70%,
4.5.27 Mx Layout Rules Add the flow is the DRC implementation of Mx.S.8, and Mx.S.8.1
VIAy.W.1 4.5.28 VIAy Layout Rules Modify rule value to 0.14 from 0.13
VIAy.S.1 4.5.28 VIAy Layout Rules Modify rule value to 0.14 from 0.15
VIAy.S.2 4.5.28 VIAy Layout Rules Modify rule value to 0.16 from 0.17
VIAy.EN.1 4.5.28 VIAy Layout Rules Modify rule value to 0 from 0.005
VIAy.EN.1® 4.5.28 VIAy Layout Rules Modify rule value to 0.045 from 0.05, modify refer section to 4.5.34
from 4.5.31
VIAy.EN.2 4.5.28 VIAy Layout Rules Modify rule value to 0.045 from 0.05
VIAy.EN.2® 4.5.28 VIAy Layout Rules Modify rule value to 0.075 from 0.08, modify refer section to 4.5.34
from 4.5.31
VIAy.R.8® 4.5.28 VIAy Layout Rules Remove the rule
VIAy.R.9gU 4.5.28 VIAy Layout Rules Modify refer section to 4.5.34 from 4.5.31
My.EN.0 4.5.29 My Layout Rules Add the new rule
My.EN.0® 4.5.29 My Layout Rules Add the new rule
My.EN.1 4.5.29 My Layout Rules Modify the rule value to 0 from 0.005
My.EN.1® 4.5.29 My Layout Rules Modify refer section to 4.5.34 from 4.5.31. Modify the rule value to
0.05 from 0.045.
My.EN.2 4.5.29 My Layout Rules Modify the rule value to 0.045 from 0.05
My.EN.2® 4.5.29 My Layout Rules Modify refer section to 4.5.34 from 4.5.31. Modify the rule value to
0.08 from 0.075
4.5.29 My Layout Rules Remove rule description of My.DN.2, My.DN.3, and My.DN.5
My.DN.1 4.5.29 My Layout Rules Modify rule area value.
My.DN.2 4.5.29 My Layout Rules Remove the rule
My.DN.3 4.5.29 My Layout Rules Remove the rule
DMy.R.1 4.5.29 My Layout Rules Modify rule No. to DMy.R.1 from Dmy.R.1
VIAz.R.5gU 4.5.30 Top VIAz Layout Rules Modify refer section to 4.5.34 from 4.5.31
4.5.31 Top Mz Layout Rules Remove rule description of Mz.DN.2, Mz.DN.3,
Mz.DN.1 4.5.31 Top Mz Layout Rules Modify rule area value.
Mz.DN.2 4.5.31 Top Mz Layout Rules Remove rule
Mz.DN.3 4.5.31 Top Mz Layout Rules Remove rule
4.5.33 Top Mr Layout Rules Remove rule description of Mr.DN.2, Mr.DN.3
Mr.DN.1 4.5.31 Top Mr Layout Rules Modify rule area value.
Mr.DN.2 4.5.31 Top Mr Layout Rules Remove rule
Mr.DN.3 4.5.31 Top Mr Layout Rules Remove rule
Mr.R.2gU 4.5.33 Top Mr Layout Rules Add the rule for Mr
4.5.34 Via Layout Recommendations Re-arrange the section
MOM.S.2 4.5.35 MOM Layout Rules Add the rule to provide MOM
MOM.A.1** 4.5.35 MOM Layout Rules Add the rule to provide MOM
MOM.A.2** 4.5.35 MOM Layout Rules Add the rule to provide MOM
MOM.R.1gU 4.5.35 MOM Layout Rules Add the rule to provide MOM
RV.W.1 4.3.36 RV Layout Rules (CB VIA hole) Add the rule to provide RV Layout
RV.S.1 4.3.36 RV Layout Rules (CB VIA hole) Add the rule to provide RV Layout
RV.EN.1 4.3.36 RV Layout Rules (CB VIA hole) Add the rule to provide RV Layout
RV.R.1 4.3.36 RV Layout Rules (CB VIA hole) Add the rule to provide RV Layout
RV.R.2 4.3.36 RV Layout Rules (CB VIA hole) Add the rule to provide RV Layout
AP.W.1 4.3.37 AP-MD Layout Rules Add the rule to provide AP Layout
AP.W.2 4.3.37 AP-MD Layout Rules Add the rule to provide AP Layout
AP.S.1 4.3.37 AP-MD Layout Rules Add the rule to provide AP Layout
AP.EN.1 4.3.37 AP-MD Layout Rules Add the rule to provide AP Layout
AP.DN.1 4.3.37 AP-MD Layout Rules Add the rule to provide AP Layout
U
4.3.37 AP-MD Layout Rules Add the rule to provide AP Layout
AP.R.1 4.3.37 AP-MD Layout Rules Add the rule to provide AP Layout
LOGO.O.1 4.3.38 Product Labels and Logo Rules Remove rule description of AP
LOGO.R.2 4.3.38 Product Labels and Logo Rules Add rule description of OD.W.2.1, OD.W.2.2
SRAM.R.4U 4.5.39 SRAM Rules Add SRAM size of DP and HC
ROM.W.1 4.5.41 ROM Rules Add the rule to provide ROM
ROM.W.2 4.5.41 ROM Rules Add the rule to provide ROM
ROM.R.1U 4.5.41 ROM Rules Add the rule to provide ROM
ROM.R.2® U 4.5.41 ROM Rules Add the rule to provide ROM
A.R.6 4.5.45 Antenna Effect Prevention (A) Layout Modify rule description to 10M from M9.
Rules
A.R.9 4.5.45 Antenna Effect Prevention (A) Layout Modify rule description to VIA9 from VIA8, and modify rule description
Rules to VIA from Via.
A.R.10 4.5.45 Antenna Effect Prevention (A) Layout Modify rule value
Rules
A.R.11 4.5.45 Antenna Effect Prevention (A) Layout Modify rule value
Rules
A.R.7 4.5.45 Antenna Effect Prevention (A) Layout Remove rule description of diode area. Modify rule description to VIA9
Rules from VIA8, and modify rule description to VIA from Via.
A.R.8 4.5.45 Antenna Effect Prevention (A) Layout Remove rule description of diode area
Rules
Rules Modify rule value
Rules Modify rule value
PO.S.14m® 5.2 Layout Rules for the WPE (Well Add this rule for WPE
Proximity Effect)
PO.EN.1m® 5.2 Layout Rules for the WPE (Well Add this rule for WPE
Proximity Effect)
Proximity Effect)
Proximity Effect)
AN.R.44mgU 5.4.1 General Guidelines Add this rule for analog circuit
PO.EX.1m® 5.4.2 MOS Recommendations Add this rule for analog circuit
PO.EX.2m gU 5.4.2 MOS Recommendations Add this rule for analog circuit
AN.R.36mgU 5.4.5 Capacitor Guidelines Add this rule for analog circuit
AN.R.37mgU 5.4.5 Capacitor Guidelines Add this rule for analog circuit
AN.R.38mU 5.5.2 Matching Rules and Guidelines Add this rule for analog circuit
AN.R.9mgU 5.5.2 Matching Rules and Guidelines Modify rule description of “refer to the CO.R.5g”
AN.R.10mgU 5.5.2 Matching Rules and Guidelines Modify rule description
AN.R.39.mgU 5.5.2 Matching Rules and Guidelines Add this rule for analog circuit
AN.R.15mgU 5.5.3 Electrical Performance Rules and Modify rule description
Guidelines
AN.R.17mg 5.5.3 Electrical Performance Rules and Modify rule description
Guidelines
AN.R.40.mgU 5.5.3 Electrical Performance Rules and Add this rule for analog circuit
Guidelines
AN.R.41mgU 5.6 Burn-in Guidelines for Analog Circuits Add this rule for analog circuit
DOD.S.7.1 6.1 Dummy OD (DOD) Rules Remove the rule
DPO.S.3 6.2 Dummy Poly (DPO) Rules Add rule description “OR SR_DPO”
DPO.S.6.1 6.2 Dummy Poly (DPO) Rules Remove the rule
PO.DN.1 6.2 Dummy Poly (DPO) Rules Modify rule description to add SR_DPO
PO.DN.2 6.2 Dummy Poly (DPO) Rules Modify rule description to add SR_DPO
DTCD.W.1 6.3.1 Dummy TCD Rules Add this rule to provide Dummy TCD
DTCD.S.1 6.3.1 Dummy TCD Rules Add this rule to provide Dummy TCD
DTCD.DN.1® 6.3.1 Dummy TCD Rules Add this rule to provide Dummy TCD
DTCD.R.1 6.3.1 Dummy TCD Rules Add this rule to provide Dummy TCD
DMx.S.3 6.4 Dummy Metal (DM) Rules Remove rule description of (This check doesn't include Mx.)
DMx.S.5.1 6.4 Dummy Metal (DM) Rules Remove the rule
DMx.S.8 6.4 Dummy Metal (DM) Rules Modify rule value to 0 from 18
DMx.S.10 6.4 Dummy Metal (DM) Rules Remove the rule
Mx.DN.1 6.4 Dummy Metal (DM) Rules Modify rule area value.
Mx.DN.3® 6.4 Dummy Metal (DM) Rules Remove the rule
Mx.DN.2 6.4 Dummy Metal (DM) Rules Remove the rule
Mx.DN.4 6.4 Dummy Metal (DM) Rules Modify this rule to provide Mr
Mx.DN.5 6.4 Dummy Metal (DM) Rules Modify rule value to 85% from 70%
Metal 6.5.1 Dummy Pattern Filling Requirements Modify rule value to 85% from 70%,
PO.S.5® 7.2.1 Action-Required Rules Modify rule value to PO.S.4 from PO.S.5.
PO.S.5® 7.2.1 Action-Required Rules Modify rule value to 0.06 from 0.07
OPC.R.1® 7.2.2 Recommendations Remove the rule
OD.W.1® 7.2.2 Recommendations Remove the rule
NWROD.S.3® 7.2.2 Recommendations Modify the rule description to SPICE simulation accuracy from SPICE
model accuracy.
NWROD.R.1® 7.2.2 Recommendations Remove the rule.
NWRSTI.EN.2® 7.2.2 Recommendations Modify the rule description to SPICE simulation accuracy from SPICE
model accuracy.
NWRSTI.R.1® 7.2.2 Recommendations Remove the rule
PO.W.1® 7.2.2 Recommendations Remove this rule
ESDIMP.EN.1® 7.2.2 Recommendations Add the new rule
VAR.S.2® 7.2.2 Recommendations Remove the rule
VAR.S.3® 7.2.2 Recommendations Remove the rule
VAR.A.1® 7.2.2 Recommendations Remove the rule
CO.EN.1® 7.2.2 Recommendations Modify rule value to 0.03 from 0.04.
CO.EN.1.1® 7.2.2 Recommendations Adfd the rule for recommended enclosure by OD [at least two opposite
sides]
M1.EN.1® 7.2.2 Recommendations Modify rule value to 0.03 from 0.04.
M1.DN.3® 7.2.2 Recommendations Remove the rule
VIAx.EN.1® 7.2.2 Recommendations Modify rule value to 0.03 from 0.04.
VIAx.EN.2® 7.2.2 Recommendations Modify rule description to 4.5.34 from 4.5.29
Mx.W.4® 7.2.2 Recommendations Remove the rule
Mx.EN.1® 7.2.2 Recommendations Modify rule value to 0.03 from 0.04. Modify rule description to 4.5.34
from 4.5.29
Mx.EN.2® 7.2.2 Recommendations Modify rule description to 4.5.34 from 4.5.29
Mx.DN.3® 7.2.2 Recommendations Remove the rule
VIAy.EN.1® 7.2.2 Recommendations Modify rule value to 0.045 from 0.05.
VIAy.EN.2® 7.2.2 Recommendations Modify rule value to 0.075 from 0.08.
VIAy.R.8® 7.2.2 Recommendations Remove the rule
My.EN.1® 7.2.2 Recommendations Modify rule description to 4.5.34 from 4.5.29
My.EN.2® 7.2.2 Recommendations Modify rule value to 0.075 from 0.08. Modify rule description to 4.5.34
from 4.5.29
Mr.W.3® 7.2.2 Recommendations Add the rule
7.2.2.1 Grouping Table of Recommendations Modify rulw table.
G.6gU 7.2.3 Guidelines Add the rule
OD.L.2gU 7.2.3 Guidelines Modify rule description to Rs variation from Rs silicidation
DNW.R.6gU 7.2.3 Guidelines Add the rule
NWROD.R.2g 7.2.3 Guidelines Remove the Guidelines
NWROD.R.3g 7.2.3 Guidelines Modify the rule description to SPICE simulation accuracy from SPICE
model accuracy.
NWRSTI.R.2gu 7.2.3 Guidelines Remove the Guidelines
NWRSTI.R.3g 7.2.3 Guidelines Modify the rule description to SPICE simulation accuracy from SPICE
model accuracy.
PO.L.1gU 7.2.3 Guidelines Modify rule description to Rs variation from Rs silicidation
RES.1gU 7.2.3 Guidelines Remove the Guidelines
RES.5g 7.2.3 Guidelines Remove the Guidelines
RES.11g 7.2.3 Guidelines Change the Guidelines to rule
RES.12g 7.2.3 Guidelines Change the Guidelines to rule
RES.15g 7.2.3 Guidelines Chanege the guideline to checkable, modify the rule description to
SPICE simulation accuracy from SPICE model accuracy.
CO.S.6g 7.2.3 Guidelines Change the rule to checkable, and add “DRC can flag if the STRAP is
butted on source, one of STRAP and source is without CO.”
CO.R.1gU 7.2.3 Guidelines Modify the rule description to “unexpected resistance variation.” from
“high Rs”
CO.R.5g 7.2.3 Guidelines Change the guideline to “checkable” from uncheckable”. Modify the
rule description.
CO.R.6gU 7.2.3 Guidelines Remove the rule
VIAr.R.5gU 7.2.3 Guidelines Add the rule
Mz.R.2gU 7.2.3 Guidelines Add the rule
MOM.R.1gU 7.2.3 Guidelines Add the rule
7.3 Mechanical and Thermal Guidelines Remove the section
for FCBGA
7.3 DFM Service Add new section to provide DFM service
7.4 GDA die size optimization kit Add new section to provide GDA die size optimization kit
LUP.1 8.1 Layout Guidelines for Latch-Up Add new rule for Latch-Up
Prevention
Prevention
LUP.3.1 8.1 Layout Guidelines for Latch-Up Add new rule for Latch-Up
Prevention
Prevention
Prevention
LUP. 4 8.1 Layout Guidelines for Latch-Up Add new rule for Latch-Up
Prevention
Prevention
Prevention
Prevention
Prevention
LUP.7U 8.1 Layout Guidelines for Latch-Up Add new rule for Latch-Up
Prevention
ESD.warn.1 8.2.4.1 General Guideline for ESD Protection Add new rule for Latch-Up
ESD.1gU 8.2.4.1 General Guideline for ESD Protection Add new rule for Latch-Up
ESD.3g 8.2.4.1 General Guideline for ESD Protection Add new rule for Latch-Up
ESD.16GU 8.2.4.2 Regular I/O (2.5V/1.8V/1.1V/0.9V Add new rule for Latch-Up
RPO Device)
RPO Device)
ESD.18G 8.2.4.2 Regular I/O (2.5V/1.8V/1.1V/0.9V Add new rule for Latch-Up
RPO Device)
RPO Device)
RPO Device)
RPO Device)
RPO Device)
RPO Device)
ESD.24gU 8.2.4.3 HV Tolerant I/O (2.5V/1.8V RPO Add new rule for Latch-Up
device)
device)
ESD.26g 8.2.4.3 HV Tolerant I/O (2.5V/1.8V RPO Add new rule for Latch-Up
device)
device)
device)
device)
device)
device)
device)
device)
ESD.34gU 8.2.4.4 Power Clamp (0.9V, 1.1V, 1.8V and Add new rule for Latch-Up
2.5V Salicide Device)
ESD.35gU 8.2.4.4 Power Clamp (0.9V, 1.1V, 1.8V and Add new rule for Latch-Up
ESD.36g 8.2.4.4 Power Clamp (0.9V, 1.1V, 1.8V and Add new rule for Latch-Up
ESD.37g 8.2.4.4 Power Clamp (0.9V, 1.1V, 1.8V and Add new rule for Latch-Up
9.1 Terminology Add the section contents
9.2 Front-End Process Reliability Rules Add the section contents
and Models
9.3 Back-End Process Reliability Rules Add the section contents
9.4 Cu Metal Current Density (EM) Add the section contents
Specifications

1. 2.1.1 Front-End Features Change SRAM cell name to HCDP from HC.
Add two warnings:
1. Need to re-tapeout 12E, 12F, and 123 masks if OD GDS is
Mask Information, Key Process
1. 3.1 changed.
2. Need to re-tapeout 12E, 12F, 123, and 14D masks if Poly
GDS is changed.
2. 3.1 Change OD_12 mask tone to C from D.
3. 3.1 Change mask name to CB2_WB and CB2_FC from CB2.
Special Recognition CAD Layer
4. 3.4 Add new layer SRAM_HS for SRAM.
Summary
5. 3.4 Change description to HCDP from HC_DP at SRM_HCDP.
Summary
Special Recognition CAD Layer Add new layer RRuleRequire (182;1) for DFM Action-
6. 3.4
Summary Required recommendation.
Special Recognition CAD Layer Add new layer RRuleRequire (182;2) for DFM Recommended
7. 3.4
Summary recommendation.
Special Recognition CAD Layer Add new layer RRuleRequire (182;3) for DFM Recommended
8. 3.4
Summary Dimension for Analog Designs.
Special Recognition CAD Layer Add new layer RRuleRequire (182;11) for excluding DFM
9. 3.4
Summary action-required recommnedation check.
Special Recognition CAD Layer Add new layer RRuleRequire (182;12) for excluding DFM
10. 3.4
Summary recommendaed recommendation check.
Special Recognition CAD Layer Add new layer RRuleRequire (182;13) for excluding Rules and
11. 3.4
Summary Recommendations check for Analog Designs.
Gate Oxide and Diffusion (OD)
12. OD.A.1 4.5.1 Change rule description to 0.06*0.26 from 0.12*0.26.
Layout Rules (120)
Deep N-Well (DNW) Layout Rules
13. DNW.S.4 4.5.2 Change rule value to 0.8 from 1.0
(119) [Optional]
Deep N-Well (DNW) Layout Rules Change rule value to 1.0 from 1.2, and change rule
14. DNW.S.5 4.5.2
(119) [Optional] description to {RW OR PW} from RW.
1.2V Core Oxide (OD_12) Layout
15. OD_12.W.3 4.5.8 Change rule value to 0.07 from 0.06.
Rules (12A)
Remove rule description “Poly gates of all core devices can be
uni-directional in a chip with tighter SPICE corners. The
16. PO.R.7 4.5.11 Poly (PO) Layout Rules (130)
SPICE corners of the other poly gates perpendicular to the
uni-directional gates are 2 sigma wider”
17. PO.R.8 4.5.11 Poly (PO) Layout Rules (130) Add new rule for Floating Gate.
18. SR_DPO.R.6 4.5.12 SR_DPO Layout Rules Add new rule for SR_DPO insertion.
19. RES.R.15g 4.5.22 OD and Poly Resistor Layout Rules Change rule number to RES.R.15g from RES.15g.
20. VAR.W.4 4.5.23 MOS Varactor Layout Rules (VAR) Add label G in rule picture.
21. CO.W.2 4.5.24 Contact (CO) Layout Rules (156) Add the new rule for sealring.
22. CO.EN.5 4.5.24 Contact (CO) Layout Rules (156) Add rule picture
23. CO.EN.6 4.5.24 Contact (CO) Layout Rules (156) Add rule picture
24. M1.W.3 4.5.25 Metal-1 (M1) Layout Rules (360) Add rule description not to include the rule check in sealring.
25. VIAx.W.2 4.5.26 VIAx Layout Rules Add the new rule for sealring.
26. VIAx.W.3 4.5.26 VIAx Layout Rules Add the new rule for sealring.
27. Mx.W.3 4.5.27 Mx Layout Rules Add rule description not to include the rule check in sealring.
28. VIAy.W.2 4.5.28 VIAy Layout Rules Add the new rule for sealring.
32. VIAy.R.2 4.5.28 VIAy Layout Rules Add rule description not to include the rule check in sealring.
37. VIAz.W.2 4.5.30 Top VIAz Layout Rules Add the new rule for sealring.
38. VIAz.W.3 4.5.30 Top VIAz Layout Rules Add the new rule for sealring.
39. VIAz.EN.1 4.5.30 Top VIAz Layout Rules Add rule description not to include the rule check in sealring.
40. VIAz.R.2 4.5.30 Top VIAz Layout Rules Add rule description not to include the rule check in sealring.
41. VIAz.R.3 4.5.30 Top VIAz Layout Rules Add rule description not to include the rule check in sealring.
42. Mz.EN.1 4.5.31 Top Mz Layout Rules Add rule description not to include the rule check in sealring.
43. VIAr.W.2 4.5.32 Top VIAr Layout Rules Add the new rule for sealring.
44. VIAr.W.3 4.5.32 Top VIAr Layout Rules Add the new rule for sealring.
45. VIAr.EN.1 4.5.32 Top VIAr Layout Rules Add rule description not to include the rule check in sealring.
46. VIAr.R.2 4.5.32 Top VIAr Layout Rules Add rule description not to include the rule check in sealring.
47. VIAr.R.3 4.5.32 Top VIAr Layout Rules Add rule description not to include the rule check in sealring.
48. Mr.EN.1 4.5.33 Top Mr Layout Rules Add rule description not to include the rule check in sealring.
49. MOM.R.1 4.5.35 MOM Layout Rules Add new rule to forbid MOM with VIA.
50. MOMA.2 4.5.35 MOM Layout Rules Remove the rule
51. MOM.R.1gU 4.5.35 MOM Layout Rules Remove the guideline
RTMOM (Rotated Metal Oxide
52. 4.5.35.1 Remove Fig. 4.5.35.1.1
Metal) Capacitor Guidelines
53. RV.W.1 4.5.36 RV Layout Rules (306) [optional] Add rule description not to include the rule check in sealring.
54. SRAM.R.4U 4.5.39 SRAM Rules Change SRAM cell name to HCDP from HC.
55. SRAM.R.17 4.5.39 SRAM Rules Add rule description “and SRM (50;0)”
Remove rule description “Poly gates of all core devices can be
uni-directional in a chip with tighter SPICE corners. The
56. PO.R.7 4.5.39 SRAM Rules
SPICE corners of the other poly gates perpendicular to the
uni-directional gates are 2 sigma wider”
Remove the wording “in N45LP/N40LP process.” and add the
57. 4.5.41 ROM Rules wording “ROM can only be used for SVT NMOS, not allowed
for other VTs.”
Guidelines for Placing Seal Ring Add the section Guidelines for Placing Seal Ring and Corner
58. 4.5.44
and Corner Stress Relief Patterns Stress Relief Patterns
Chip Corner Stress Relief (CSR) Add the section for Placing Seal Ring and Corner Stress
59. 4.5.45
Pattern Relief Patterns
60. 4.5.46 Seal Ring Layout Rules Add the section for Seal Ring Layout Rules
Remove rule description OD.W.2, and add rule description
61. DTCD.R.3 6.3.1 Dummy TCD Rules
“OD.w.2.1, OD.W.2.2”
Change rule value to 0.11 from 0.14 in recommended, change
62. PO.EX.1® 7.2.2 Recommendations
rule value to 0.09 from 0.1 in min. rule.
U
63. MOM.R.1g 7.2.3 Guidelines Remove the guideline
DC Lifetime and Vmax : Vcc = 0.9V
+- 10% and 1.0V+- 5% for N40G,
64. 9.2.1.3.4 Add the wording “and 1.0V+- 5%”
Vmax will be determined after
qualification
+- 10% and 1.0V+- 5% for N40G,
qualification.
Lifetime Prediction Model for
66. 9.2.3.1 Negative Bias Temperature Add the wording “MTTF is the mean time to failure”
Instability
67. 9.2.3.4.2 Stress Conditions Change the wording to “75°C ~ 125°C” from “125°C ~ 175°C”
+- 10% and 1.0V+- 5% for N40G,
qualification.
Add the wording ” The rating factor is 2.077 for the case of
Rating factor for Maximum DC
69. 9.4.4 temperature below 100°C for Joule heating effect
Current
consideration.”
Change the VIAy wording to “0.126 x 0.126” from
70. 9.4.5.1 General
“0.117x0.117”
Dependence of metal length
71. 9.4.5.2 Add the wording “for DC”
(length<10mm for DC)
Dependence of metal length Change the VIAy wording to “0.126 x 0.126” from
72. 9.4.5.2
(length<10mm for DC) “0.117x0.117”

1. 1.2 Reference Documentation Add reference for SPICE, LVS, and SRAM.
2. 2.1.1 Front-End Features Add the description “Retrograde twin well CMOS technology
on <110> P- substrate (epitaxy wafer) (subtrate resistivity of 8-
12 Ω-cm)”
3. 2.1.1 Front-End Features Add SRAM cell offering for GL.
4. 2.1.1 Front-End Features Add MOS varactor 1.2V
5. 2.3 Power Supply and Operation Add the item of max. power supply at Table 2.3.1 Power
Temperature Ranges Supplies
6. 2.5 Metallization Options Change Mz thickness to 8500 from 9000
7. 3.1 Mask Information, Key Process Add the wording “5. In the tabe of section 3.1, “ * “ means
Sequence, and CAD Layers optional mask. “ # “ means non-design level mask which is no
need to draw (or design) this layer. This non-design level mask
is generated by logical operation from other drawn layers.”
8. 3.1 Mask Information, Key Process Add the warning of 12E and 12F.
9. 3.1 Mask Information, Key Process Modify OD derive layer “OD, DOD, DUMMYOD1~5,
Sequence, and CAD Layers DUMMYOD 7~12, DUMMYOD16, DPSRM, SRM_10TTP,
SRM_HCDP, SRM, NW, .SRM_10TTP, SRM_HCDP, SRM,
NW.SRM_10TTP, SRM_HCDP, SRM, NW”
10. 3.1 Mask Information, Key Process Modify 12E derive layer “NW, OD, OD2 (OD_18, OD_25,
Sequence, and CAD Layers OD_33), PO, NP, PP, CO, SRM;0, RH, VAR, POFUSE,
BJTDMY”
11. 3.1 Mask Information, Key Process Modify 12F derive layer “NW, OD, OD2 (OD_18, OD_25,
Sequence, and CAD Layers OD_33), PO, NP, PP, CO, SRM;0, RH, VAR, POFUSE,
BJTDMY”
12. 3.1 Mask Information, Key Process Modify NSDD mask to 13A from 14D, and derive layer is “PO,
Sequence, and CAD Layers DPO, SR_DPO”.
13. 3.1 Mask Information, Key Process Modify derive layer of mask 124 to “NW, OD2, PP, SRN;0,
Sequence, and CAD Layers BJTDMY, RH, VAR, POFUSE”.
14. 3.1 Mask Information, Key Process Add mask 11C if 0.8V and 0.9V SRAM cell are both used, and
Sequence, and CAD Layers derive layer of mask 11C is “SRM;2, SRM_HC, SRM_HCDP”.
15. 3.1 Mask Information, Key Process Add mask ESD mask layer to 189;0 from 147.
16. 3.1 Mask Information, Key Process Change mask name to CB2 from CB2_FC and CB2_WB, and
Sequence, and CAD Layers add CAD layer name CB2_WB (86;20) and CB2_FC (86;0)
17. 3.1 Mask Information, Key Process Add mask information of 11C, and modify 14D.
18. 3.1 Mask Information, Key Process Add Table 3.1.3 1.8V Mask to CAD layer mapping table
19. 3.1 Mask Information, Key Process Add Table 3.1.4 2.5V Mask to CAD layer mapping table
20. 3.4 Special Recognition CAD Layer Add OD18_15 (16;4) for OD18_15 Layout Rules
Summary
21. 3.4 Special Recognition CAD Layer Add SR_DOD (6;7) for OD layout rule
Summary
22. 3.4 Special Recognition CAD Layer Modify SRAM_HS layer number to (50;7) from (80;7)
Summary
23. 3.4 Special Recognition CAD Layer Modify description to “(cover bit-cell, strapping & edge cell)”
Summary from “(bit-cell only, not including strap & edge cell)” for
80;11~80;18.
24. 3.4 Special Recognition CAD Layer Remove ESD layers of ESDHV (147;0) and ESDREG (146;0).
Summary
25. 3.4 Special Recognition CAD Layer Remove Filler layer (181;0).
Summary
26. 3.5.1 General Purpose Superb (N45GS): Add Native NMOS (1.2V) in Table 3.5.2 Device Truth Table for
0.9V Core Design general purpose superb.
27. 3.5.1 General Purpose Superb (N45GS): Add description “(including 2.5V overdrive 3.3V)” in 2.5V
0.9V Core Design Varactor.
28. G.4 3.7.1 Design Grid Rules Add “(including SR_DOD)” for OD; (including SR_DPO) for PO
29. 3.9 Chip Implementation and Tape Out Add the new section
Checklist
30. 4.3 Definition of Layout Geometrical Change Projection picture
Terminology
31. 4.3 Definition of Layout Geometrical Add the description of one track, cut, channel width, channel
Terminology length, and vertex.
32. OD.W.1® 4.5.1 Gate Oxide and Diffusion (OD) Add rule description “(except RTMOMDMY (155;21) region)”
Layout Rules (120)
33. OD.W.2 4.5.1 Gate Oxide and Diffusion (OD) Remove rule description “(0.9V)” and remove rule description
Layout Rules (120) “(This check doesn’t include the regions covered by layers
NT_N and SR_ESD)”
34. OD.W.2.1 4.5.1 Gate Oxide and Diffusion (OD) Remove rule description “(0.9V)”
Layout Rules (120)
35. OD.W.2.2 4.5.1 Gate Oxide and Diffusion (OD) Remove rule description “(0.9V)”
Layout Rules (120)
36. OD.W.3 4.5.1 Gate Oxide and Diffusion (OD) Remove rule description “(0.9V)”, and add the rule description
Layout Rules (120) “Channel”.
37. OD.S.3 4.5.1 Gate Oxide and Diffusion (OD) Modify the picture
Layout Rules (120)
38. OD.S.6® 4.5.1 Gate Oxide and Diffusion (OD) Add rule description “{OD OR SR_DOD} “
Layout Rules (120)
39. OD.L.2 4.5.1 Gate Oxide and Diffusion (OD) Change the rule value to 60 from 18..
Layout Rules (120)
40. OD.L.3 4.5.1 Gate Oxide and Diffusion (OD) Remove the rule.
Layout Rules (120)
41. OD.L.4 4.5.1 Gate Oxide and Diffusion (OD) Remove rule description “(0.9V)”, and add the rule description
Layout Rules (120) “; and guard ring.”
42. OD.DN.0 4.5.1 Gate Oxide and Diffusion (OD) Add the new rule
Layout Rules (120)
43. OD.DN.1 4.5.1 Gate Oxide and Diffusion (OD) Add rule description “OR SR_DOD”
Layout Rules (120)
44. OD.DN.1.1 4.5.1 Gate Oxide and Diffusion (OD) Add the new rule
Layout Rules (120)
Layout Rules (120)
Layout Rules (120)
Layout Rules (120)
Layout Rules (120)
Layout Rules (120)
Layout Rules (120)
51. OD.R.1 4.5.1 Gate Oxide and Diffusion (OD) Add rule description “OR SR_DOD”
Layout Rules (120)
52. SR_DOD.W.1 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
53. SR_DOD.W.1® 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
54. SR_DOD.W.2 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
55. SR_DOD.S.1 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
56. SR_DOD.S.1.1 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
59. SR_DOD.S.3® 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
66. SR_DOD.EN.1 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
67. SR_DOD.EN.2 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
68. SR_DOD.A.1 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
69. SR_DOD.L.1 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
70. SR_DOD.L.2 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
71. SR_DOD.R.1 4.5.2 SR_DOD Layout Rules Add SR_DOD rule for OD layout
74. NW.S.3 4.5.4 N-Well (NW) Layout Rules Add rule description “with different potentials (*)”
75. NW.A.1 4.5.4 N-Well (NW) Layout Rules Change the rule value to 0.64 from 0.7
76. NW.A.2 4.5.4 N-Well (NW) Layout Rules Change the rule value to 0.64 from 0.7
77. NWROD.S.1 4.5.5 N-Well Within OD (NWROD) Layout Change the rule value to 1.0 from 1.2
Rules
78. NWROD.S.1 4.5.5 N-Well Within OD (NWROD) Layout Change the rule value to 1.0 from 1.2
Rules
79. NT_N.W.2 4.5.7 Native Device (NT_N) Layout Rules Add rule description “/1.2V”
80. NT_N.W.3 4.5.7 Native Device (NT_N) Layout Rules Add rule description “(for 2.5V overdrive to 3.3V, please refer
to section OD25_33 Layout Rules)”
81. NT_N.W.4 4.5.7 Native Device (NT_N) Layout Rules Add rule description “(for 2.5V underdrive to 1.8V, please refer
to section OD25_18 Layout Rules)”
82. NT_N.R.2 4.5.7 Native Device (NT_N) Layout Rules Add the new rule
83. NT_N.R.3 4.5.7 Native Device (NT_N) Layout Rules Add rule description “, pickup and RTMOMDMY (155;21)
region”
84. OD2.S.3 4.5.8 Thick Oxide (OD2) Layout Rules Add rule description “/1.2V”
(152)
85. OD_12.W.1 4.5.9 1.2V Core Oxide (OD_12) Layout Change the rule value to 0.34 from 0.32
Rules (12A)
86. OD_12.S.1 4.5.9 1.2V Core Oxide (OD_12) Layout Change the rule value to 0.34 from 0.32
Rules (12A)
87. OD_12.A.1 4.5.9 1.2V Core Oxide (OD_12) Layout Change the rule value to 0.64 from 0.7
Rules (12A)
88. OD_12.A.2 4.5.9 1.2V Core Oxide (OD_12) Layout Change the rule value to 0.64 from 0.7
Rules (12A)
89. OD_12.R.2 4.5.9 1.2V Core Oxide (OD_12) Layout Remove rule description”NT_N, VAR”
Rules (12A)
90. OD25_33.W.3 4.5.10 OD25_33 Layout Rules Add the rule to allow 2.5V overdrive 3.3V
91. OD25_18.W.2 4.5.11 OD25_18 Layout Rules Add the rule to allow 2.5V underdrive 1.8V
92. OD18_15.W.1 4.5.12 OD18_15 Layout Rules Add the new rule
93. OD18_15.R.1 4.5.12 OD18_15 Layout Rules Add the new rule
94. PO.W.4 4.5.13 Poly (PO) Layout Rules (130) Add the rule description “For 1.8V underdrive to 1.5V, please
refer to section OD18_15 Layout Rules.”
95. PO.W.5 4.5.13 Poly (PO) Layout Rules (130) Remove the rule
96. PO.W.6 4.5.13 Poly (PO) Layout Rules (130) Remove rule description “(0.9V)”
97. PO.S.2 4.5.13 Poly (PO) Layout Rules (130) Add PO.S.2 picture.
98. PO.S.2.1.1 4.5.13 Poly (PO) Layout Rules (130) Add rule description “Maximum”.
99. PO.EX.2® 4.5.13 Poly (PO) Layout Rules (130) Add rule description ” When you use poly space =0.16
(PO.S.2), please use =0.13 for this recommendation.”
100. PO.EX.2.1 4.5.13 Poly (PO) Layout Rules (130) Add the rule description “(For the edge gate, it is OK to follow
either PO.S.2.1.1 or PO.EX.2.1)”
101. PO.L.2 4.5.13 Poly (PO) Layout Rules (130) Remove the rule.
102. PO.DN.1.1 4.5.13 Poly (PO) Layout Rules (130) Add the new rule
103. PO.DN.2 4.5.13 Poly (PO) Layout Rules (130) Add rule description “OR SR_DOD”
104. PO.R.1 4.5.13 Poly (PO) Layout Rules (130) Modify rule description to “with” from “to have”
105. SR_DPO.W.1® 4.5.14 SR_DPO Layout Rules Add he new rule
106. SR_DPO.S.1® 4.5.14 SR_DPO Layout Rules Add he new rule
107. SR_DPO.L.1® 4.5.14 SR_DPO Layout Rules Add he new rule
108. SR_DPO.L.3® 4.5.14 SR_DPO Layout Rules Add he new rule
109. SR_DPO.R.6 4.5.14 SR_DPO Layout Rules Add rule description “(except RTMOMDMY)”
110. ESDIMP.W.1 4.5.20 ESD Implant (ESDIMP) Layout Move the rule to section 8.2.3 ESD Implant (ESDIMP) Layout
Rules (MASK ID: 111) Rules (MASK ID: 111)
111. RPO.EX.1 4.5.22 Resist Protection Oxide (RPO) Add the rule description “(This check doesn’t include the
Layout Rules (155) regions covered by the layer SDI)”
112. RPO.EX.1.1 4.5.22 Resist Protection Oxide (RPO) Add the rule description “(This check doesn’t include the
113. RPO.EX.1.2 4.5.22 Resist Protection Oxide (RPO) Add the rule description “(This check doesn’t include the
114. RES.W.1 4.5.23 OD and Poly Resistor Layout Rules Add rule description “(except RTMOMDMY (155;21) region).”
115. RES.S.1 4.5.23 OD and Poly Resistor Layout Rules Modify the rule description
116. RES.R.4 4.5.23 OD and Poly Resistor Layout Rules Add rule description “or RTMOMDMY (155;21) region”.
117. RES.R.15g 4.5.23 OD and Poly Resistor Layout Rules Add rule description “AND RPO”.
118. VAR.A.1 4.5.24 MOS Varactor Layout Rules (VAR) Add the new rule.
119. CO.S.5 4.5.25 Contact (CO) Layout Rules (156) Modify rule description to “I/O GATE” from “1.8V or 2.5V
GATE”
120. M1.EN.0 4.5.26 Metal-1 (M1) Layout Rules (360) Add rule description “either”
121. M1.L.1 4.5.26 Metal-1 (M1) Layout Rules (360) Remove the rule
122. M1.S.8 4.5.26 Metal-1 (M1) Layout Rules (360) Add rule picture.
123. M1.S.8.1 4.5.26 Metal-1 (M1) Layout Rules (360) Add rule picture.
124. M1.DN.0 4.5.26 Metal-1 (M1) Layout Rules (360) Add the new rule.
125. M1.DN.1 4.5.26 Metal-1 (M1) Layout Rules (360) Add rule description “window 125 um x 125 um, stepping 62.5
um”
126. M1.DN.1.1 4.5.26 Metal-1 (M1) Layout Rules (360) Add the new rule.
127. Mx.S.8 4.5.28 Mx Layout Rules Add rule picture
128. Mx.S.8.1 4.5.28 Mx Layout Rules Add rule picture
129. Mx.L.1 4.5.28 Mx Layout Rules Remove the rule
130. Mx.DN.0 4.5.28 Mx Layout Rules Add the new rule.
131. Mx.DN.1 4.5.28 Mx Layout Rules Add rule description “window 125 um x 125 um, stepping 62.5
um”
132. Mx.DN.1.1 4.5.28 Mx Layout Rules Add the new rule.
133. VIAy.W.2 4.5.29 VIAy Layout Rules Remove the rule description “(as inter-layer)”
134. VIAy.W.3 4.5.29 VIAy Layout Rules Remove the rule description “(as inter-layer)”
135. VIAy.W.4 4.5.29 VIAy Layout Rules Remove the rule
136. VIAy.W.5 4.5.29 VIAy Layout Rules Remove the rule
137. My.W.4® 4.5.30 My Layout Rules Remove the rule
138. My.L.1 4.5.30 My Layout Rules Remove the rule
139. My.DN.0 4.5.30 My Layout Rules Add the new rule.
140. My.DN.1 4.5.30 My Layout Rules Add rule description “window 125 um x 125 um, stepping 62.5
um”
141. My.DN.1.1 4.5.30 My Layout Rules Add the new rule.
142. VIAz.W.2 4.5.31 Top VIAz Layout Rules Change the rule value to 0.5 from 2
143. VIAz.W.3 4.5.31 Top VIAz Layout Rules Change the rule description to “Width of VIAz hole of seal ring”,
and change the rule value to 0.36 from 6
144. Mz.W.2 4.5.32 Top Mz Layout Rules Add the rule description “(This check doesn’t include the
regions covered by layers of LMARK, {INDDMY SIZING
22μm}, CB, and {UBM interact CBD}.)”
145. Mz.DN.0 4.5.32 Top Mz Layout Rules Add the new rule.
146. Mz.DN.1 4.5.32 Top Mz Layout Rules Add rule description “window 125 um x 125 um, stepping 62.5
um”
147. Mz.DN.1.1 4.5.32 Top Mz Layout Rules Add the new rule.
148. Mz.R.2gU 4.5.32 Top Mz Layout Rules Remove the rule
149. VIAr.W.2 4.5.33 Top VIAr Layout Rules Remove the rule description “1st”, and change the rule value to
0.5 from 2
150. VIAr.W.3 4.5.33 Top VIAr Layout Rules Change the rule description to “Width of VIAr hole of seal ring”,
151. Mr.DN.0 4.5.34 Top Mr Layout Rules Add the new rule.
152. Mr.DN.1 4.5.34 Top Mr Layout Rules Add rule description “window 125 um x 125 um, stepping 62.5
um”
153. Mr.DN.1.1 4.5.34 Top Mr Layout Rules Add the new rule.
154. Mr.R.2gU 4.5.34 Top Mr Layout Rules Remove the rule
155. RV.W.1 4.5.37 RV Layout Rules (306) Add the rule description “It is allowed both via dimensions in
same chip.”
156. AP.EN.1 4.5.38 Al Redistributional Layer (AP RDL) Change rule value to 0.5 from 0.7
Layout Rules (309) [optional]
157. AP.DN.1.1 4.5.38 Al Redistributional Layer (AP RDL) Add the new rule.
Layout Rules (309) [optional]
158. LOGO.S.1 4.5.39 Product Labels and Logo Rules Add the rule description “and non-dummy TCD”
159. SRAM.R.1U 4.5.40 SRAM Rules Remove rule description “If non-standard cells are used, TSMC
requires customers to submit a layout at least two months
before tape-out for TSMC to review and approve the use of
SRAM cells. Add rule description “Non-tsmc-standard cell is
not allowed, unless all logic rules are followed. (186;0 and 50;0
can not be used)”
160. SRAM.R.3U 4.5.40 SRAM Rules Change rule description to 8.0 from 2.0
161. SRAM.R.22 4.5.40 SRAM Rules Add the new rule
165. ROM.W.1 4.5.42 ROM Rules Change rule description to 0.12 from 0.18
166. SR_ESD.W.3 4.5.43 SR_ESD device Layout Rules Change rule description to 15~60 from 30~50
167. 4.5.44 Guidelines for Placing Seal Ring and Change gds file to V0.7A
Corner Stress Relief Patterns
168. VIAy.W.2 4.5.46 Seal Ring Layout Rules Remove the rule description “(as inter-layer)”
169. VIAy.W.3 4.5.46 Seal Ring Layout Rules Remove the rule description “(as inter-layer)”
170. VIAy.W.4 4.5.46 Seal Ring Layout Rules Remove the rule
171. VIAy.W.5 4.5.46 Seal Ring Layout Rules Remove the rule
172. VIAz.W.2 4.5.46 Seal Ring Layout Rules Change the rule value to 0.5 from 2
173. VIAz.W.3 4.5.46 Seal Ring Layout Rules Change the rule description to “Width of VIAz hole of seal ring”,
174. VIAr.W.2 4.5.46 Seal Ring Layout Rules Remove the rule description “1st”, and change the rule value to
0.5 from 2
175. VIAr.W.3 4.5.46 Seal Ring Layout Rules Change the rule description to “Width of VIAr hole of seal ring”,
176. 4.5.46 Seal Ring Layout Rules Add top view of seal ring of VIAz and VIAr
177. PO.S.14m® 5.2 Layout Rules for the WPE (Well Modify the rule value to 0.8 from 1.4.
Proximity Effect)
178. PO.EN.1m® 5.2 Layout Rules for the WPE (Well Modify the rule value to 1.0 from 1.4.
Proximity Effect)
179. PO.EN.2m® 5.2 Layout Rules for the WPE (Well Modify the rule value to 3.7 from 2.
Proximity Effect)
180. PO.EN.3m® 5.2 Layout Rules for the WPE (Well Modify the rule value to 2.3 from 1.8.
Proximity Effect)
181. PO.EX.2m® 5.4.2 MOS Recommendations Remove the rule
182. BJT.R.3® 5.4.3 Bipolar Transistor (BJT) Rules and Remove the rule
Recommendations
Recommendations
Recommendations
Recommendations
186. AN.R.36mgU 5.4.5 Capacitor Guidelines Add the rule description ” It is recommended not to use a very
long channel device in the design. In order to ensure the
channel relaxation time of the MOS capacitor (excluding
varactor) is enough to build up charge to the steady state, it is
recommended to use proper channel length at the high
operation frequency range. The operating frequency shall be
below 0.2 * gm / Cgate, where gm is the transconductance of
the transistor and Cgate is the gate-oxide capacitance.”
187. AN.R.9mgU 5.5.2 General Guidelines Modify rule description to CO.R.5g from CO.R.6g
188. AN.R.45mgU 5.5.2 General Guidelines Add the new rule
191. Mx.DN.1 6.4 Dummy Metal (DM) Rules Add rule description “window 125 um x 125 um, stepping 62.5
um”
192. 7.1.2.2 Capacitors Remove the section
193. PO.EX.2® 7.2.1 Poly (PO) Layout Rules (130) Add rule description ” When you use poly space =0.16
(PO.S.2), please use =0.13 for this recommendation.”
194. OD.W.1® 7.2.2 Recommendations Add rule description “(except RTMOMDMY (155;21) region)”
195. OD.S.6® 7.2.2 Recommendations Add rule description “{OD OR SR_DOD} “
196. SR_DOD.W.1® 7.2.2 Recommendations Add SR_DOD rule for OD layout
197. SR_DOD.S.3® 7.2.2 Recommendations Add SR_DOD rule for OD layout
198. SR_DPO.W.1® 7.2.2 Recommendations Add he new rule
199. SR_DPO.S.1® 7.2.2 Recommendations Add he new rule
200. SR_DPO.L.1® 7.2.2 Recommendations Add he new rule
201. SR_DPO.L.3® 7.2.2 Recommendations Add he new rule
202. My.W.4® 7.2.2 Recommendations Remove the rule
203. RES.R.15g 7.2.3 Guidelines Add rule description “AND RPO”.
204. My.W.4® 7.2.4 Grouping Table of Remove the rule
Recommendations
205. ESDIMP.S.1 8.2.3 ESD Implant (ESDIMP) Layout Move the rule to section 8.2.3 ESD Implant (ESDIMP) Layout
Rules (MASK ID: 111) Rules (MASK ID: 111) from 4.5.20
206. ESDIMP.EN.1 8.2.3 ESD Implant (ESDIMP) Layout Move the rule to section 8.2.3 ESD Implant (ESDIMP) Layout
207. ESDIMP.EN.1® 8.2.3 ESD Implant (ESDIMP) Layout Move the rule to section 8.2.3 ESD Implant (ESDIMP) Layout
208. ESDIMP.A.1 8.2.3 ESD Implant (ESDIMP) Layout Move the rule to section 8.2.3 ESD Implant (ESDIMP) Layout
209. ESDIMP.A.2 8.2.3 ESD Implant (ESDIMP) Layout Move the rule to section 8.2.3 ESD Implant (ESDIMP) Layout
210. ESDIMP.R.1 8.2.3 ESD Implant (ESDIMP) Layout Move the rule to section 8.2.3 ESD Implant (ESDIMP) Layout
211. ESDIMP.R.2® u 8.2.3 ESD Implant (ESDIMP) Layout Move the rule to section 8.2.3 ESD Implant (ESDIMP) Layout
212. SR_ESD.W.1 8.2.4 SR_ESD device Layout Rules Move the rule to section 8.2.4 SR_ESD device Layout Rules
from 4.5.42
from 4.5.42
from 4.5.42
215. SR_ESD.S.1 8.2.4 SR_ESD device Layout Rules Move the rule to section 8.2.4 SR_ESD device Layout Rules
from 4.5.42
216. SR_ESD.EX.1 8.2.4 SR_ESD device Layout Rules Move the rule to section 8.2.4 SR_ESD device Layout Rules
from 4.5.42
217. SR_ESD.L.1 8.2.4 SR_ESD device Layout Rules Move the rule to section 8.2.4 SR_ESD device Layout Rules
from 4.5.42
218. 9.4.5.3 Dependence of metal width (width ≥ Add the new section
1 µm for DC)

4. 1.1 Overview Add the description of CLN45LP, CLN40LP, CLN45LPG,
N40LPG, and N45/N40 MSRF.
5. 1.1 Overview Add the Warning: All tape-outs MUST be DRC clean.
6. 1.1 Overview Remove wording to prevent confusion. “The design rules
(or layout rules) are defined with….”
7. 1.2 Reference Documentation Remove the reference of MM/RF rules, since it is merged
into the same document.
8. 1.2 Reference Documentation Remove the reference of Wire bond and Flip Chip related
rules, since it is merged into the same document.
9. 1.2 Reference Documentation Change the DRC deck reference to “·T-N405-CL-DR-
001-X1 (X is the code of EDA tool, please refer to TSMC-
Online for the details) TSMC 45 NM CMOS LOGIC AND
40NM CMOS LOGIC DRC COMMAND FILE
(CLN45LP/LPG, CLN40LP/LPG)”.
10. 1.2 Reference Documentation Add the deck reference for Wire bond and Flip Chip
related deck
11. 1.2 Reference Documentation Add document reference of spice
 T-N45-CL-SP-032
TSMC 40NM CMOS LOGIC LOW POWER
1P10M+AL_RDL SALICIDE Cu_ELK 1.1V/1.8V
SPICE MODELS (CLN40LP)
 T-N45-CL-SP-004
 T-N45-CL-SP-012
 T-N45-CL-SP-010
TSMC 45 NM CMOS LOGIC GENERAL PURPOSE
SUPERB 1P10M+AL_RDL CU_ELK 0.9V/1.8V SPICE
MODELS
 T-N45-CL-SP-011
SUPERB 1P10M+AL_RDL CU_ELK 0.9&2.5V SPICE
MODEL 45GS(=40G)
12. 1.2 Reference Documentation Add document reference of Device formation examples
and LVS properties
 T-N45-CL-LS-001
1P10M SALICIDE DEVICE FORMATION EXAMPLES
AND LVS PROPERTIES
 T-N45-CL-LS-002
SUPERB 1P10M SALICIDE CU_ELK 0.9&2.5V
DEVICE FORMATION EXAMPLES AND LVS
PROPERTIES
13. 1.2 Reference Documentation Add document reference of LVS
 T-N45-CL-LS-001-X6 (X is the code of EDA tool,
please refer to TSMC-Online for the details)
PROPERTIES LVS COMMAND FILE
 T-N45-CL-LS-002-X7 (X is the code of EDA tool,
please refer to TSMC-Online for the details)
SUPERB 1P10M SALICIDE CU_ELK 0.9&2.5V
PROPERTIES
14. 1.2 Reference Documentation Add document reference of PDK
 TBD (please consult PDK team)
15. 1.2 Reference Documentation Add document reference of Qualification report
 T-N45-CL-QR-001
TSMC 45 NM CMOS LOGIC LOW POWER 1P7M
SALICIDE CU_LOWK 1.1/1.8V QUALIFICATION
REPORT- FAB12
 T-N45-CL-QR-005
SALICIDE CU_LOWK 1.1/2.5V QUALIFICATION
REPORT- FAB12
 T-N45-CL-QR-006
SALICIDE CU_ELK 1.1/1.8V CUP WIRE BOND PBGA
PACKAGE QUALIFICATION REPORT – 12 INCH
FAB
 T-N45-CL-QR-010
SUPERB 1P10M SALICIDE CU ELK 0.9V/2.5V
 T-N45-CL-QR-011
SUPERB 1P10M SALICIDE CU ELK 0.9/1.8V
16. 1.2 Reference Documentation Add document reference of Brief process flow
 T-N45-CL-PF-001
SALICIDE CU_ELK 1.1/1.8/1.1/2.5V BRIEF
PROCESS FLOW
 T-N40-CL-PF-002
1P10M SALICIDE CU_ELK 0.9&2.5V BRIEF
PROCESS FLOW
 T-N40-CL-PF-004
SALICIDE CU_ELK 1.1/1.8/1.1/2.5V BRIEF
PROCESS FLOW
 T-N45-CL-XE-001
TSMC 12 INCH CMOS LOGIC 45 NM LOW POWER
1P10M SALICIDE CU_ELK 1.1/1.8 DETAILED
PROCESS FLOW
 T-N45-CL-XE-003
TSMC 12 INCH CMOS LOGIC 45 NM GENERAL
PURPOSE SUPERB 1P10M SALICIDE CU_ELK
0.9&2.5 DETAILED PROCESS FLOW
17. 1.2 Test Line Layout Add document reference of test line layout
 E-MSS-02-02-024
TSMC TEST LINE LAYEROUT USER GUIDELINE
18. 2.1.1 Front-End Features Add LP (1.1V/2.5V or 1.1V/1.8V) at Dual gate oxide
process
19. 2.1.1 Front-End Features Add Dual core oxide N45LPG (0.9V/1.1V/1.8V(I/O)) and
N40LPG(0.9V/1.1V/3.3V(I/O)) at Dual core oxide process
20. 2.1.1 Front-End Features Add the SRAM cells offering table of N45
LP/N40LP/N45LPG/N40LPG
21. 2.1.1 Front-End Features Add 1.1V at Varactor
22. 2.1.2 Back-End Features Add Mu: top metal pitch is 4.0μm (W/S=2μm/2μm)
23. 2.1.2 Back-End Features Add the description of· Electrical fuse
24. 2.2 Devices Add the table of N45LP/N40LP and N45LPG/N40LPG at
Table 2.2.1 Available Vt in each technology
25. 2.3 Power Supply and Operation Add Table 2.3.1 Power Supplies
Temperature Ranges
26. 2.4 Cross–section Add Figure 2.4.5 Cross-section for 1P10M_7x1z1u
27. 2.4 Cross–section Add Figure 2.4.6 Cross-section for 1P10M_7x1y1u
28. 2.5 Metallization Options Add MM/RF information
29. 2.5 Metallization Options Add Table 2.5.1 N45LP/N40LP/N45LPG/N40LPG
Naming for Different Metal Thicknesses
30. 2.5 Metallization Options Add Table 2.5.2 N45LP/N40LP/N45LPG/N40LPG
Naming for Different Via Types
31. 2.5 Metallization Options Add Mu at Table 2.5.3 N40G Naming for Different Metal
Thicknesses
32. 2.5 Metallization Options Add VIAu at Table 2.5.4 N40G Naming for Different Via
Types
33. 2.5 Metallization Options Add Table 2.5.5 Metallization Option Table Reference
Guideline
34. 2.5 Metallization Options Add 1P7M_4X2R metal scheme at Table 2.5.8
Metallization Options for Mr
35. 2.5 Metallization Options Add Mu at Table 2.5.9 Top metal numbers My, Mz, Mr,
Mu for wire bond and flip chip. Forbid My for LF flip chip.
36. 2.5 Metallization Options Add Table 2.5.10 Metallization Options (Mu with second
inter-layer metal/via (My/Vy) are used, where the
dielectric film material for inter-layer My/Vy is “LK”.)
37. 2.5 Metallization Options Add Table 2.5.11 Metallization Options (Mu with top
metal/via (My/Vy, 2XTM) are used, where the dielectric
film material for top My/Vy is “USG”.)
38. 2.5 Metallization Options Add Table 2.5.12 Metallization Options (My/Vy are used
as second inter-layer Metal/Via, where the dielectric film
material for inter-layer My/Vy is “LK”.)
39. 2.5 Metallization Options Add Table 2.5.13 Metallization Options (My/Vy are used
as 2X top Metal/Via, where the dielectric film material for
top My/Vy is “USG”.)
40. 3.1 Mask Information, Key Process Add Table 3.1.1 Mask Name and ID, Key Process
Sequence, and CAD Layers Sequence, and CAD Layer for CLN45LP/CLN40LP
41. 3.1 Mask Information, Key Process Add Table 3.1.2 Mask Name and ID, Key Process
Sequence, and CAD Layers Sequence, and CAD Layer for CLN45LPG/N40LPG
42. 3.1 Mask Information, Key Process Add Table 3.1.4 N45LP/N40LP/N45LPG/N40LPG Mask
Sequence, and CAD Layers Name/ID/Grade/Type, OPC, and PSM Information. Add
Mu information.
43. 3.1 Mask Information, Key Process Add Table 3.1.8 N45LP/N40LP 1.8V Mask to CAD layer
Sequence, and CAD Layers mapping table
44. 3.1 Mask Information, Key Process Add Table 3.1.9 N45LP/N40LP 2.5V Mask to CAD layer
45. 3.1 Mask Information, Key Process Add Table 3.1.10 N45LPG 1.8V Mask to CAD layer
46. 3.1 Mask Information, Key Process Add Table 3.1.10 N45LPG 3.3V Mask to CAD layer
47. 3.1 Mask Information, Key Process Correct mask sequence of mask 197/198 for G &
Sequence, and CAD Layers LP/LPG to match real process sequence
48. 3.1 Mask Information, Key Process Add polyimide mask since it becomes general offer
49. 3.2 Metal/Via CAD Layer Information for Add Mu at Table 3.2.1 Metal CAD Layer Number, Name,
Metallization Options and Datatype
Add the description “CAD layer datatype of Mu metal is
“60” (that of dummy Mu layer is “61”), and CAD layer
datatype of its associated VIA (VIAu, the VIA under Mu)
is “40” (the same as that of VIAz due to the same via
size).”
50. 3.3 Dummy Pattern Fill CAD Layers Add Mu at Table 3.3.1 Dummy Pattern CAD Layer
Number, Name, and Datatype
51. 3.3 Dummy Pattern Fill CAD Layers Add dummy metal (datatype: 2) at Table 3.3.1 Dummy
Pattern CAD Layer Number, Name, and Datatype
52. 3.3 Dummy Pattern Fill CAD Layers Add DVIAx into Table 3.3.1
53. 3.4 Special Recognition CAD Layer Add the new layers of Ncap_NTN
Summary
54. 3.4 Special Recognition CAD Layer Add the new layers of HVD_N and HVD_P for HV device
Summary
55. 3.4 Special Recognition CAD Layer Add the new layers of M1_LV/MV/HV/5V &
Summary Mx_LV/MV/HV/5V for voltage of nets
56. 3.4 Special Recognition CAD Layer Add the new layers of TLDMY for transmission line
Summary
57. 3.4 Special Recognition CAD Layer Add the new layers of DVIAxEXCL for
Summary
58. 3.4 Special Recognition CAD Layer Change RTMOMDMY to MOMDMY
Summary
59. 3.4 Special Recognition CAD Layer Change MOMDMY (155;21) Associated With to ”
Summary OD.W.1® , OD.L.2, NT_N.R.3, SR_DPO.R.4,
SR_DPO.R.6, RES.W.1, RES.R.5,” from “PO.R.4”
60. 3.4 Special Recognition CAD Layer Add RFIP_DMY(161;1) Associated With to “OD.L.2,
Summary PO.DN.3, RES.R.4, RES.R.5”, and description “for tsmc
PDK cell”.
61. 3.4 Special Recognition CAD Layer Modify 186;0 decription to “SRAM DRC Violation waiver
Summary layer and OPC. Detail waived rule list, please refer to the
section of SRAM Rules. Before using SRAMDMY, please
make sure that TSMC has revised the SRAM library to
avoid real violations that are automatically waived by the
SRAMDMY marker layer.”
62. 3.4 Special Recognition CAD Layer Add 186;4 for LP
Summary
63. 3.4 Special Recognition CAD Layer Change 186;5 description to “SRAM periphery DRC layer
Summary can only be used in the word-line driver of TSMC SRAM
for N40G process. This layer is only to waive CO.S.3 and
G.1. And the SRAM and word-line driver must be
reviewed by TSMC’s R&D and PE even if customer uses
TSMC cell.”
64. 3.4 Special Recognition CAD Layer Add Associated With “SRAM rules “ at these rules of
Summary SRAMDMY;5PSRM, SRAM_HS, PRSRM, SRM_UHD,
SRM_HC, SRM_HD, SRM_LV, SRM_HCDP,
SRM_8TTP, SRM_10TTP, DUMMYOD1~DUMMYOD16,
DUMMYPO1~DUMMYPO7.
65. 3.4 Special Recognition CAD Layer Update ROM as tape out layer for N40G
Summary
66. 3.4 Special Recognition CAD Layer Add the new layers of DMxEXCL, WBDMY, SEALRING,
Summary SEALRING_DB, SEALRING_ALL , CSRBIB1DMY,
CSRBIB2DMY for Package and interconnect
67. 3.5 Device Truth Tables Add the description
·CLN45/CLN40 CMOS Logic Low Power (LP) technology
·CLN45/CLN40 CMOS LogicOGIC LP-based Triple Gate
Oxide (LPG) technology
Table 3.5.1 Device Truth Table for N45LP/N40LP
Table 3.5.4 Device Truth Table for N40G (N40G)
68. 3.5.1 N45/N40 Low Power (LP): 1.1V Core Add Table 3.5.1 Device Truth Table for N45LP/N40LP
Design
69. 3.5.2 N45LPG: 1.1V/0.9V Core Design Add Table 3.5.2 Device Truth Table for N45LPG
70. 3.5.2 N45LPG: 1.1V/0.9V Core Design Add Table 3.5.3 Device Truth Table for N40LPG
71. 3.5.3 N40G (N45GS) General Purpose Add Table 3.5.4 Device Truth Table for N40G (N45GS)
Superb (N40G): 0.9V Core Design
72. 3.6 Mask Requirement for Device options Add Table 3.6.1 Mask Requirement for N45LP/N40LP
(High/STD/Low VT)
73. 3.6 Mask Requirement for Device options Add Table 3.6.2 Mask Requirement for N45LPG/N40LPG
(High/STD/Low VT)
74. 3.6 Mask Requirement for Device options Add Table 3.6.3 Mask Requirement for N40G (N45GS)
(High/STD/Low VT)
75. G.1 3.7.1 Design Grid Rules Addth erule description “for LP/LPG and 186;4 for GS”
Add the rule description “For circuits of 110% size-up part
(40LP) can allow 1nm design grid. This is uncheckable.
Please refer to the chapter “N40LP Design Information”.
76. G.2 3.7.1 Design Grid Rules Add the rule description “(Except UBM, CBD[in UBM],
CB2[in UBM] region)”
77. G.4 3.7.1 Design Grid Rules Add rule description “VIAy”
78. G.6gU 3.7.1 Design Grid Rules Add the rule description “for GS/GL and 186;4 for
LP/LPG”.
79. 4.1 Layout Rule Conventions Add the description “· Rules denoted by “#” depend on
the capability of each individual probing/ assembly
house. These rules are checked by DRC, and may be
waived by customers with agreement from their
subcontractors.
Rules denoted by “t” applied for tsmc bumping only.
These rules are checked by DRC, and may be waived by
customers with agreement from a third-party bumping
house.”
80. 4.4 Minimum Pitches Add Mu pitch
81. OD.W.2.1GS 4.5.1 Gate Oxide and Diffusion (OD) Layout Change the rule number to OD.W.2.1GS from OD.W.2.1.
Rules (120) Add the rule description “for GS and LPG G device” and
exclude the regions of LOGO, TCDDMY.
82. OD.W.2.2GS 4.5.1 Gate Oxide and Diffusion (OD) Layout Change the rule number to OD.W.2.2GS from OD.W.2.2.
Rules (120) Add the rule description “for GS” and exclude the regions
of LOGO, TCDDMY.
83. OD.A.5 4.5.1 Gate Oxide and Diffusion (OD) Layout Add the new rule
Rules (120)
84. OD.L.2 4.5.1 Gate Oxide and Diffusion (OD) Layout Add the rule description “fand {RTMOMDMY(155;21)
Rules (120) SIZING 1.2um})”
85. OD.L.4 4.5.1 Gate Oxide and Diffusion (OD) Layout Replaced by OD.A.5
Rules (120)
86. OD.R.1 4.5.1 Gate Oxide and Diffusion (OD) Layout Change the rule description to “{(DOD OR SR_DOD) OR
Rules (120) NWDMY}” from “{DOD OR SR_DOD OR NWDMY}”
87. 4.5.1 Gate Oxide and Diffusion (OD) Layout Add the description at table note “Inder to cover the OSE
Rules (120) (refer to the section of Layout Guidelines for OSE (OD
Space Effect)) in GS process, it is important to follow the
layout guideline (refer to the section of How to reduce the
differences between pre-simulation and post-simulation)
and use TSMC DOD/DPO utility to reduce the gap
between SPICE and silicon.”
88. 4.5.1 Gate Oxide and Diffusion (OD) Layout Remove OD.W.2 picture
Rules (120)
89. 4.5.1 Gate Oxide and Diffusion (OD) Layout Revise OD.L.1 picture
Rules (120)
90. OD.DN.4® 4.5.1 Gate Oxide and Diffusion (OD) Layout Add the new rule
Rules (120)
Rules (120)
Rules (120)
Rules (120)
Rules (120)
Rules (120)
96. DOD.R.2® 4.5.1 Gate Oxide and Diffusion (OD) Layout Add the new rule
Rules (120)
97. 4.5.2 SR_DOD Layout Rules Add the description in the section head “For
N40G( N45GS ) process,it is important to turn on the
switch of FILL_SRDOD_SRDPO to control the OD space
effect.
However, these SRDOD/SRDPO patterns increase the
cycle time of mask making. Therefore, it's recommended
to turn off the switch of FILL_SRDOD_SRDPO for
N45LP/N40LP.”
98. SR_DOD.W.1® 4.5.2 SR_DOD Layout Rules Remove the rule
99. SR_DOD.R.4U 4.5.2 SR_DOD Layout Rules Add the new rule
100. DNW.S.2 4.5.3 Deep N-Well (DNW) Layout Rules (119) Add the description “with different potential”
[Optional]
101. NW.S.6 4.5.4 N-Well (NW) Layout Rules Add “except NW resistor”
102. NW.S.6.1 4.5.4 N-Well (NW) Layout Rules Add “except NW resistor”
103. NW.EN.1 4.5.4 N-Well (NW) Layout Rules Add “except NW resistor”
104. NWROD.R.4 4.5.5 N-Well Within OD (NWROD) Layout Add the new rule
Rules
Rules
Rules
107. NWROD. R.7 4.5.5 N-Well Within OD (NWROD) Layout Add the new rule
Rules
108. NT_N.W.2 4.5.7 Native Device (NT_N) Layout Rules Add the rule description “1.1V”, since 1.1V is for LP.
109. NT_N.W.3 4.5.7 Native Device (NT_N) Layout Rules Add the rule description “3.3V” for new option.
110. NT_N.R.2 4.5.7 Native Device (NT_N) Layout Rules Change the rule description “P+ACTIVE region is not
allowed in NT_N but PW STRAP is allowed.DRC only
can check P+ Gate is not allowed in NT_N.”
111. 4.5.8 Thick Oxide (OD2) Layout Rules (152) Add the 3.3V description in section head for new option.
112. OD2.EN.1 4.5.8 Thick Oxide (OD2) Layout Rules (152) Add the rule description “3.3V” for new option.
113. OD2.S.3 4.5.8 Thick Oxide (OD2) Layout Rules (152) Correct label from D to G
114. OD2.EN.1 4.5.8 Thick Oxide (OD2) Layout Rules (152) Correct label from G to D
115. OD2.R.1 4.5.8 Thick Oxide (OD2) Layout Rules (152) Add the rule description “3.3V” for new option.
116. DCO.W.1 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
117. DCO.W.2 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
118. DCO.S.1 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
(153) N45/N40LPG
(153) N45/N40LPG
(153) N45/N40LPG
(153) N45/N40LPG
(153) N45/N40LPG
(153) N45/N40LPG
(153) N45/N40LPG
(153) N45/N40LPG
127. DCO.EN.1 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
128. DCO.EN.2 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
129. DCO.EX.1 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
(153) N45/N40LPG
(153) N45/N40LPG. Add “Cut is not allowed if” to match DRC.
132. DCO.A.1 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
133. DCO.A.2 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
134. DCO.O.1 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
135. DCO.R.2 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
136. DCO.R.3 4.5.9 Dual Core Oxide (DCO) Layout Rules Add the new G device rule to provide dual core device for
(153) N45/N40LPG
137. OD_12.S.2 4.5.10 1.2V Core Oxide (OD_12) Layout Rules Add the rule description “OR GATE}“
(12A)
138. OD_12.EX.3 4.5.10 1.2V Core Oxide (OD_12) Layout Rules Add “Cut is not allowed if” to match DRC.
(12A)
139. OD_12.R.3 4.5.10 1.2V Core Oxide (OD_12) Layout Rules Add the rule description “(Except OD shared by core and
(12A) OD_12 is at same potential, DRC can not exclude this
exception.)“
140. OD25_33.W.1LP 4.5.11 OD25_33 Layout Rules Add the new rule for LP device
141. OD25_33.W.1GS 4.5.11 OD25_33 Layout Rules Change the rule number to “OD25_33.W.1GS” fro
“OD25_33.W.1”, since it is only for GS.
144. OD25_18.W.1GS 4.5.12 OD25_18 Layout Rules Add the new rule for PMOS
147. OD18_15.R.2 4.5.13 OD18_15 Layout Rules Add the new rule to prevent mis-use
148. PO.W.1U® 4.5.14 Poly (PO) Layout Rules (130) Re-add the rule.
149. PO.W.3 4.5.14 Poly (PO) Layout Rules (130) Add the new rule to provide 3.3V for N40LP and
N40LPG.
150. PO.W.6GS 4.5.14 Poly (PO) Layout Rules (130) Change the rule number to “PO.W.6GS” from “PO.W.6”
151. PO.W.8 4.5.14 Poly (PO) Layout Rules (130) Add the new rule for LPG G device
152. PO.S.2LP 4.5.14 Poly (PO) Layout Rules (130) Add the new rule for LP process.
153. PO.S.2® LP 4.5.14 Poly (PO) Layout Rules (130) Add the new rule for LP process.
154. PO.S.2GS 4.5.14 Poly (PO) Layout Rules (130) Change the rule number to” PO.S.2GS” from “PO.S.2”
155. PO.S.2.1LP 4.5.14 Poly (PO) Layout Rules (130) Add the new rule for LP/LPG
156. PO.S.2.1GS 4.5.14 Poly (PO) Layout Rules (130) Change the rule number to “PO.S.2.1GS” from
“PO.S.2.1”
157. PO.S.2.1.1GS 4.5.14 Poly (PO) Layout Rules (130) Change the rule description to “Maximum gate [channel
length ³ 0.08 μm] space to neighboring {PO OR
SR_DPO} [either one channel length ³ 0.08 μm] in core
device regions for GS”
Add the excluded region “LOGO” to align with the deck.
158. PO.S.4 4.5.14 Poly (PO) Layout Rules (130) Add the rule description “(except CSRDMY (166;0)
region)”
159. PO.S.5® LP 4.5.14 Poly (PO) Layout Rules (130) Add the enw rule for LP
160. PO.S.5® GS 4.5.14 Poly (PO) Layout Rules (130) Change the rule nember to “PO.S.5® GS” from “PO.S.5®”
161. PO.S.6® LP 4.5.14 Poly (PO) Layout Rules (130) Add the rule for LP/LPG
162. PO.S.6® GS 4.5.14 Poly (PO) Layout Rules (130) Change the rule nember to “PO.S.6® GS” from “PO.S.6®”
163. PO.S.6.1 4.5.14 Poly (PO) Layout Rules (130) Change the ruledescription to “L-shape PO space to OD
when PO and OD are in the same MOS [L-shape PO
length (R1) > 0.06 μm (R1) and L-shape PO length (R1)
£ 0.1 μm (R1)]”
164. PO.S.9 4.5.14 Poly (PO) Layout Rules (130) Add the rule description to “[in same RPO]” , and remove
the rule description “of {PO and RPO}”.
165. PO.S.16 4.5.14 Poly (PO) Layout Rules (130) Add the rule description “OR SR_DPO}”
166. PO.S.17® 4.5.14 Poly (PO) Layout Rules (130) Add the new rule
167. PO.S.18® GS 4.5.14 Poly (PO) Layout Rules (130) Add the new rule
168. PO.EX.2.1GS 4.5.14 Poly (PO) Layout Rules (130) Change the rule number to PO.EX.2.1GS from PO.EX.2.
169. 4.5.14 Poly (PO) Layout Rules (130) Add the description at table note “In order to meet the
tight requirement in terms of the complex photo, poly
critical dimension (CCD) control etching process, as well
as the PSE layout effect in GS (refer to the section of
Layout Guidelines for PSE (Poly Space Effect), it is
important to adopt TSMC DOD//DPO utility to reduce the
CD variation, and also reduce the gap between SPICE
model and silicon data.”
170. PO.DN.3 4.5.14 Poly (PO) Layout Rules (130) Waive MOMDMY(155;21)
171. PO.R.7 4.5.14 Poly (PO) Layout Rules (130) Waive 1TRAMDMY (160;0)
172. PO.DN.4® 4.5.14 Poly (PO) Layout Rules (130) Add the new rule
178. SR_DPO.W.1® 4.5.15 SR_DPO Layout Rules Remove the rule
179. 4.5.15 SR_DPO Layout Rules Add the description in the section head “For
N40G( N45GS ) process,it is important to turn on the
switch of FILL_SRDOD_SRDPO to control the OD space
effect.
N45LP/N40LP.”
180. 4.5.16 High Vt NMOS (VTH_N) Layout Rules Add 3.3V option at the section head.
(11H)
181. VTH_N.S.3 4.5.16 High Vt NMOS (VTH_N) Layout Rules Add the rule description “resistor”
(11H)
182. VTH_N.R.1 4.5.16 High Vt NMOS (VTH_N) Layout Rules Add VAR
(11H)
183. 4.5.17 High Vt PMOS (VTH_P) Layout Rules Add 3.3V option at the section head.
(11G)
184. VTH_P.S.3 4.5.17 High Vt PMOS (VTH_P) Layout Rules Add the rule description “resistor”
(11G)
185. VTH_P.R.1 4.5.17 High Vt PMOS (VTH_P) Layout Rules Change “including varactor gate” to VAR
(11G)
186. 4.5.18 Low Vt NMOS (VTL_N) Layout Rules Add 3.3V option at the section head.
(118)
187. VTL_N.S.3 4.5.18 Low Vt NMOS (VTL_N) Layout Rules Add the rule description “resistor”
(118)
188. VTL_N.R.1 4.5.18 Low Vt NMOS (VTL_N) Layout Rules Add VAR
(118)
189. 4.5.19 Low Vt PMOS (VTL_P) Layout Rules Add 3.3V option at the section head.
(117)
190. VTL_P.S.3 4.5.19 Low Vt PMOS (VTL_P) Layout Rules Add the rule description “resistor”
(117)
191. VTL_P.R.1 4.5.19 Low Vt PMOS (VTL_P) Layout Rules Change “including varactor gate” to VAR
(117)
192. PP.S.7 4.5.20 P+ Source/Drain Ion Implantation (PP) Add the rule description “resistor”
Layout Rules (197)
193. PP.EX.2 4.5.20 P+ Source/Drain Ion Implantation (PP) Add “except sealring(162;2)”
Layout Rules (197)
194. PP.EX.3 4.5.20 P+ Source/Drain Ion Implantation (PP) Add the rule description “resistor”
Layout Rules (197)
195. NP.S.7 4.5.21 N+ Source/Drain Ion Implantation (NP) Add the rule description “resistor”
Rules (198)
196. NP.EX.1 4.5.21 N+ Source/Drain Ion Implantation (NP) Add the rule description “except NWROD”
Rules (198)
197. NP.EX.2 4.5.21 N+ Source/Drain Ion Implantation (NP) Add the rule description “except NWROD”
Rules (198)
198. NP.EX.3 4.5.21 N+ Source/Drain Ion Implantation (NP) Add the rule description “resistor”
Rules (198)
199. 4.5.22 Layout Rules for LDD Mask Logical Remove the description at the section head “and
Operations rcommended”
200. 4.5.22 Layout Rules for LDD Mask Logical Remove the description at the Warning “and
Operations rcommended”
201. 4.5.24 OD and Poly Resistor Layout Rules Change resistor definition
Unsilicided OD resistor: {RH AND {RPO AND OD}} AND
RPDMY}
Silicided OD resistor: {RH AND OD} NOT RPO} AND
RPDMY}
Unsilicided PO resistor: {RH AND {RPO AND PO}} AND
RPDMY}
Silicided PO resistor: {RH AND PO} NOT RPO} AND
RPDMY}
202. RES.S.2 4.5.24 OD and Poly Resistor Layout Rules Add the new rule
203. HVD_N.W.1 4.5.25 HVD_N Layout Rules Add the new rule
204. HVD_N.S.1 4.5.25 HVD_N Layout Rules Add the new rule
210. HVD_N.EX.1 4.5.25 HVD_N Layout Rules Add the new rule
211. HVD_N.O.1 4.5.25 HVD_N Layout Rules Add the new rule
212. HVD_N.L.1 4.5.25 HVD_N Layout Rules Add the new rule
213. HVD_N.A.1 4.5.25 HVD_N Layout Rules Add the new rule
214. HVD_N.A.2 4.5.25 HVD_N Layout Rules Add the new rule
215. HVD_N.R.1 4.5.25 HVD_N Layout Rules Add the new rule
219. HVD_N.R.5® U 4.5.25 HVD_N Layout Rules Add the new rule
220. HVD_P.W.1 4.5.26 HVD_P Layout Rules Add the new rule
221. HVD_P.S.1 4.5.26 HVD_P Layout Rules Add the new rule
225. HVD_P.EX.1 4.5.26 HVD_P Layout Rules Add the new rule
226. HVD_P.EN.1 4.5.26 HVD_P Layout Rules Add the new rule
227. HVD_P.EN.2 4.5.26 HVD_P Layout Rules Add the new rule
228. HVD_P.O.1 4.5.26 HVD_P Layout Rules Add the new rule
229. HVD_P.L.1 4.5.26 HVD_P Layout Rules Add the new rule
230. HVD_P.A.1 4.5.26 HVD_P Layout Rules Add the new rule
231. HVD_P.A.2 4.5.26 HVD_P Layout Rules Add the new rule
232. HVD_P.R.1 4.5.26 HVD_P Layout Rules Add the new rule
236. HVD_P.R.5® U 4.5.26 HVD_P Layout Rules Add the new rule
238. 4.5.27 MOS Varactor Layout Rules (VAR) Add the VAR definition table
Add the description “NVAR: NMOS in NW
PVAR: PMOS in PW“.
239. VAR.W.4 4.5.27 MOS Varactor Layout Rules (VAR) Change 0.4 to 0.32
240. VAR.EN.1 4.5.27 MOS Varactor Layout Rules (VAR) Add “Cut is not allowed” to match DRC
241. VAR.A.1 4.5.27 MOS Varactor Layout Rules (VAR) Add the rule description “and LPG G device”
242. VAR.R.1 4.5.27 MOS Varactor Layout Rules (VAR) Add the rule description “DRC only checks VAR fully
cover gate.”
243. VAR.R.2 4.5.27 MOS Varactor Layout Rules (VAR) Remove the rule description “PW”
244. VAR.R.3 4.5.27 MOS Varactor Layout Rules (VAR) Add the description “AND NW)” for NW VAR
245. VAR.R.3.1 4.5.27 MOS Varactor Layout Rules (VAR) Add the new rule for PW VAR
246. VAR.R.5 4.5.27 MOS Varactor Layout Rules (VAR) Add the description “AND NW)” for NW VAR
247. VAR.R.5.1 4.5.27 MOS Varactor Layout Rules (VAR) Add the new rule for PW VAR
248. 4.5.27 MOS Varactor Layout Rules (VAR) Add the description at table note “and it is recommended
to design the varactor in the thicj oxide area to reduce
the leakage (AN.R.20mg).”
249. CO.W.1 4.5.28 Contact (CO) Layout Rules (156) Add the rule description “(Except Bbutted CO in SRAM
(186;0) region only)”
250. CO.S.1 4.5.28 Contact (CO) Layout Rules (156) Add the rule description “(Except SRAM (186;0) region)”
252. CO.S.2.1 4.5.28 Contact (CO) Layout Rules (156) Add the rule description “(Except SRAM (186;0) region)”
and remove “to neighboring CO”
253. CO.S.3 4.5.28 Contact (CO) Layout Rules (156) Change the rule for word line decode to word line driver.
Add the rule description “186;4 for GS.
Add the rule description “(Except SRAM (186;0) region)”
255. CO.S.5.1 4.5.28 Contact (CO) Layout Rules (156) Add the new rule
256. CO.EN.0 4.5.28 Contact (CO) Layout Rules (156) Add the rule description “(Except SRAM (186;0) region)”
Add the new option description “{CO.EN.1 and
CO.EN.1.2}”
258. CO.EN.1.1 4.5.28 Contact (CO) Layout Rules (156) Add the rule description “(Except SRAM (186;0) region)”
and “except STRAP”.
259. CO.EN.1.2 4.5.28 Contact (CO) Layout Rules (156) Change the rule description to “STRAP” from “pickup”
260. CO.EN.1.3 4.5.28 Contact (CO) Layout Rules (156) Add the rule description “(Except Butted CO in SRAM
(186;0) region only)”
265. CO.S.7® 4.5.28 Contact (CO) Layout Rules (156) Add the new rule
266. CO.R.4 4.5.28 Contact (CO) Layout Rules (156) Add “OR SR_DPO” to match DRC
267. CO.R.5g 4.5.28 Contact (CO) Layout Rules (156) Remove symmetric CO check due to replaced by
CO.S.7®
268. M1.W.3 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “sealring (162;2)”
269. M1.S.1.1 4.5.29 Metal-1 (M1) Layout Rules (360) Add the new rule for 5V device.
270. M1.S.5 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “(Except SRAM (186;0) region)”
271. M1.S.8.2 4.5.29 Metal-1 (M1) Layout Rules (360) Add the new rule for 5V device.
272. M1.S.9 4.5.29 Metal-1 (M1) Layout Rules (360) Add the new rule for 5V device.
273. M1.EN.1 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “(Except Butted CO in SRAM
(186;0) and CSRDMY (166;0) regions)”
274. M1.EN.2 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “(Except SRAM (186;0) and
CSRDMY (166;0) regions)”
275. M1.EN.3 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “(Except SRAM (186;0) and
276. M1.EN.3.1 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “(Except SRAM (186;0) and
277. M1.EN.3.2 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “(Except SRAM (186;0) and
278. M1.EN.5® 4.5.29 Metal-1 (M1) Layout Rules (360) Add the new rule
279. M1.A.1 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “(Except SRAM (186;0) region)”
280. M1.A.1® 4.5.29 Metal-1 (M1) Layout Rules (360) Add the new rule
281. M1.EN.4 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “(except CSRDMY (166;0)
region)”
282. M1.A.2 4.5.29 Metal-1 (M1) Layout Rules (360) Add the rule description “(Except SRAM (186;0) region)”
283. M1.DN.4 4.5.29 Metal-1 (M1) Layout Rules (360) Relax from 40% to 50%
284. M1.R.2 4.5.29 Metal-1 (M1) Layout Rules (360) Add the new rule
285. 4.5.29 Metal-1 (M1) Layout Rules (360) Add 5V information at table note
286. VIAx.S.1.1 4.5.30 VIAx Layout Rules (Mask ID: 378, 379, Add the new rule for 5V device
373, 374, 375, 376, 377)
287. VIAx.R.2 4.5.30 VIAx Layout Rules (Mask ID: 378, 379, Add the rule description “(VIA1.R.2 except SRAM (186;0)
373, 374, 375, 376, 377) region)”
288. VIAx.R.4 4.5.30 VIAx Layout Rules (Mask ID: 378, 379, Add the rule description “(VIA1.R.4 except SRAM (186;0)
373, 374, 375, 376, 377) region)”
289. VIAx.R.12 4.5.30 VIAx Layout Rules (Mask ID: 378, 379, Add the new rule for dummy VIA
373, 374, 375, 376, 377)
290. DVIAx.R.3 4.5.30 VIAx Layout Rules (Mask ID: 378, 379, Add the new rule for dummy VIA
373, 374, 375, 376, 377)
291. Mx.W.3 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the rule description “sealring (162;2)”
384, 385, 386, 387, 388)
292. Mx.S.1.1 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the new rule for 5V device
384, 385, 386, 387, 388)
293. Mx.S.5 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the rule description “(M2.S.5 except SRAM (186;0)
384, 385, 386, 387, 388) region)”
294. Mx.S.8.2 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the new rule for 5V device
384, 385, 386, 387, 388)
295. Mx.S.9 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the new rule for 5V device
384, 385, 386, 387, 388)
296. Mx.EN.2 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the rule description “(except sealring (162;2)
384, 385, 386, 387, 388) regions)”
297. Mx.EN.3 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the rule description “(except sealring (162;2)
384, 385, 386, 387, 388) regions)”
298. Mx.EN.3.1 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the rule description “(except sealring (162;2)
384, 385, 386, 387, 388) regions)”
299. Mx.A.1 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the rule description “(Except SRAM (186;0) region)”
384, 385, 386, 387, 388)
300. Mx.A.1® 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the new rule
384, 385, 386, 387, 388)
301. Mx.A.2 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the rule description “(Except SRAM (186;0) region)”
384, 385, 386, 387, 388)
302. Mx.DN.4 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Relax from 40% to 50%
384, 385, 386, 387, 388)
303. Mx.DN.5 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the rule description “sealring (162;2)”
384, 385, 386, 387, 388)
304. Mx.R.3 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add the new rule
384, 385, 386, 387, 388)
305. 4.5.31 Mx Layout Rules (Mask ID: 380, 381, Add 5V information at table note
384, 385, 386, 387, 388)
306. VIAy.R.2 4.5.32 VIAy Layout Rules (Mask ID: 379, 373, Add the rule description “sealring (162;2)”
374, 375, 376, 377, 372, 37A)
374, 375, 376, 377, 372, 37A)
374, 375, 376, 377, 372, 37A)
374, 375, 376, 377, 372, 37A)
374, 375, 376, 377, 372, 37A)
311. VIAy.R.10 4.5.32 VIAy Layout Rules (Mask ID: 379, 373, Add the rule to prevent mis-use
374, 375, 376, 377, 372, 37A)
312. My.DN.4 4.5.33 My Layout Rules (Mask ID: Second Relax from 40% to 50%
Inter-layer Metal (385, 386, 387, 388)
and Top Metal (381, 384, 385, 386, 387,
388, 389, 38A))
313. My.R.3 4.5.33 My Layout Rules (Mask ID: Second Add the new rule
and Top Metal (381, 384, 385, 386, 387,
388, 389, 38A))
314. VIAz.EN.1 4.5.34 Top VIAz Layout Rules (Mask ID: 379, Add the rule description “sealring (162;2)”
373, 374, 375, 376, 377, 372, 37A)
315. VIAz.R.2 4.5.34 Top VIAz Layout Rules (Mask ID: 379, Add the rule description “sealring (162;2)”
373, 374, 375, 376, 377, 372, 37A)
316. VIAz.R.3 4.5.34 Top VIAz Layout Rules (Mask ID: 379, Add the rule description “sealring (162;2)”
373, 374, 375, 376, 377, 372, 37A)
317. VIAz.R.6 4.5.34 Top VIAz Layout Rules (Mask ID: 379, Add the rule to prevent mis-use
373, 374, 375, 376, 377, 372, 37A)
318. Mz.EN.1 4.5.35 Top Mz Layout Rules (Mask ID: 381, Add the rule description “sealring (162;2)”
384, 385, 386, 387, 388, 389, 38A)
319. Mz.DN.4 4.5.35 Top Mz Layout Rules (Mask ID: 381, Relax from 40% to 50%
384, 385, 386, 387, 388, 389, 38A)
320. Mz.R.2 4.5.35 Top Mz Layout Rules (Mask ID: 381, Add the new rule
384, 385, 386, 387, 388, 389, 38A)
321. VIAr.EN.1 4.5.36 Top VIAr Layout Rules (Mask ID: 376, Add the rule description “sealring (162;2)”
377, 372, 37A)
322. VIAr.R.2 4.5.36 Top VIAr Layout Rules (Mask ID: 376, Add the rule description “sealring (162;2)”
377, 372, 37A)
323. VIAr.R.3 4.5.36 Top VIAr Layout Rules (Mask ID: 376, Add the rule description “sealring (162;2)”
377, 372, 37A)
324. VIAr.R.6 4.5.36 Top VIAr Layout Rules (Mask ID: 376, Add the rule to prevent mis-use
377, 372, 37A)
325. Mr.EN.1 4.5.37 Top Mr Layout Rules (Mask ID: 387, Add the rule description “sealring (162;2)”
388, 389, 38A)
326. Mz.DN.4 4.5.37 Top Mr Layout Rules (Mask ID: 387, Relax from 40% to 50%
388, 389, 38A)
327. Mr.R.2 4.5.37 Top Mr Layout Rules (Mask ID: 387, Add the new rule
388, 389, 38A)
328. 4.5.38 Via Layout Recommendations Remove via enclosure information
329. MOM.A.1** 4.5.39 MOM Layout Rules Change the rule description to “ the following figure” from
“figure 4.5.35.1”. Add 3.3V/5V rules and relax rules for <=
2.5V.
330. 4.5.39.1 RTMOM (Rotated Metal Oxide Metal) Add RTMOM information. Add mismatch information
PDK Capacitor Guidelines
331. 4.5.40 Top VIAu Layout Rules Add VIAu rules
332. Mu.W.1 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
333. Mu.W.2 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
334. Mu.S.1 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule and relaxing from 2 to 1
335. Mu.EN.1 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
336. Mu.EN.2 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
337. Mu.A.1 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
338. Mu.A.2 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
339. Mu.R.1 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
340. Mu.R.2U 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
341. Mu.DN.1 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
342. Mu.DN.1.1 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule and tighten from 70% to 50% for
Mu.S.1 relaxing from 2 to 1
343. Mu.DN.2 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
344. Mu.DN.2.1 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
345. Mu.R.3U 4.5.41 Mu (Ultra Thick Metal) Layout Rules Add the new rule
348. IND.W.1 4.5.42 INDDMY Layer Identified Inductor Add the new rule and add dummy metal check
Layout Rules
Layout Rules
Layout Rules
Layout Rules
Layout Rules
Layout Rules
Layout Rules
Layout Rules
Layout Rules
357. IND.W.10 4.5.42 INDDMY Layer Identified Inductor Add the new rule
Layout Rules
358. IND.S.1 4.5.42 INDDMY Layer Identified Inductor Add the new rule and add dummy metal check
Layout Rules
Layout Rules
Layout Rules
Layout Rules
Layout Rules
363. IND.S.6 4.5.42 INDDMY Layer Identified Inductor Add the new rule and add dummy metal check. Relaxing
Layout Rules from 2 to 1
Layout Rules
Layout Rules
Layout Rules
367. IND.S.10 4.5.42 INDDMY Layer Identified Inductor Add the new rule
Layout Rules
368. IND.R.1 4.5.42 INDDMY Layer Identified Inductor Add the new rule & waive TLDMY
Layout Rules
369. IND.R.2 4.5.42 INDDMY Layer Identified Inductor Add the new rule
Layout Rules
Layout Rules
Layout Rules
372. IND.R.5 4.5.42 INDDMY Layer Identified Inductor Add the new rule & waive TLDMY
Layout Rules
373. IND.R.6U 4.5.42 INDDMY Layer Identified Inductor Add the new rule
Layout Rules
Layout Rules
Layout Rules
Layout Rules
377. IND.DN.1 4.5.42 INDDMY Layer Identified Inductor Add the new rule. Add TLDMY.
Layout Rules
378. IND.DN.2 4.5.42 INDDMY Layer Identified Inductor Add the new rule
Layout Rules
Layout Rules
Layout Rules
381. IND.DN.4.1 4.5.42 INDDMY Layer Identified Inductor Add the new rule
Layout Rules
382. IND.DN.5U 4.5.42 INDDMY Layer Identified Inductor Add the new rule
Layout Rules
Layout Rules
Layout Rules
Layout Rules
386. 4.5.44 SRAM Rules Add Table 4.5.44.1 SRAM Truth Table in TSMC offering
cells
387. SRAM.A.1 4.5.44 SRAM Rules Add the new rule
388. SRAM.R.7U 4.5.44 SRAM Rules Change the rule for word line decode to word line driver.
Add 186;4 for LP
389. SRAM.R.12 4.5.44 SRAM Rules Add 186;4 for LP
390. SRAM.R.14 4.5.44 SRAM Rules Add the rule description “It waives SRAM DRC violations
as listed in table 4.5.44.1.“
391. SRAM.R.15 4.5.44 SRAM Rules Waive 1TRAMDMY (160;0). Add 5th condition to prevent
fatal error.
392. SRAM.R.18 4.5.44 SRAM Rules Remove the rule
393. SRAM.R.21 4.5.44 SRAM Rules Waive 1TRAMDMY (160;0)
394. SRAM.R.24 4.5.44 SRAM Rules Add the rule description “except (80;15) and (80;17),”
399. SRAM.R.30U 4.5.44 SRAM Rules Add the new rule
402. SRAM.R.33.0 4.5.44 SRAM Rules Add the new rule
412. SRAM.R.8gU 4.5.44 SRAM Rules Change the rule description to “channel length” from
“gate length”.
Change the rule description to “channel width” from “gate
width”.
413. 4.5.44 SRAM Rules Add Table 4.5.44.2 Rule List Waived by SRAMDMY
(186;0)
414. NPre.W.1 4.5.45 NPreDOSRM (50;21) Layout Rules Add the new rule
415. NPre.S.1 4.5.45 NPreDOSRM (50;21) Layout Rules Add the new rule
421. NPre.EN.1 4.5.45 NPreDOSRM (50;21) Layout Rules Add the new rule
422. NPre.EX.1 4.5.45 NPreDOSRM (50;21) Layout Rules Add the new rule
425. NPre.O.1 4.5.45 NPreDOSRM (50;21) Layout Rules Add the new rule
426. NPre.A.1 4.5.45 NPreDOSRM (50;21) Layout Rules Add the new rule
429. NPre.R.1 4.5.45 NPreDOSRM (50;21) Layout Rules Add the new rule
430. NPre.R.2 4.5.45 NPreDOSRM (50;21) Layout Rules Add the new rule
431. NPre.L.1 4.5.45 NPreDOSRM (50;21) Layout Rules Add the new rule
432. 4.5.46 SRAM Periphery (Word Line Change the section name to “SRAM Periphery (Word
DecoderDriver) Rules Line Driver) Rules” from “SRAM Periphery (Word Line
Decoder) Rules”
433. WLD.R.2 4.5.46 SRAM Periphery (Word Line Change the rule description to “186;4/5” from “186;5”.
DecoderDriver) Rules
434. WLD.R.3 4.5.46 SRAM Periphery (Word Line Add the new rule
435. WLD.R.6 4.5.46 SRAM Periphery (Word Line Change the rule description to “186;4/5” from “186;5”.
436. WLD.R.7 4.5.46 SRAM Periphery (Word Line Change the rule description to “SRAMDMY (186;0)
DecoderDriver) Rules SIZING 100 μm must cover SRAMDMY (186;5) or
(186;4)” from “SRAMDMY (186;0) SIZING 200 μm must
cover SRAMDMY (186;5)”
439. CO2.W.1 4.5.47 SRAM CO2 Layout Rule (100;0) for Add the new rule
Embedded DRAM (eDRAM) Process
440. CO2.R.1 4.5.47 SRAM CO2 Layout Rule (100;0) for Add the new rule
441. CO2.R.2 4.5.47 SRAM CO2 Layout Rule (100;0) for Add the new rule
442. CO2.R.3U 4.5.47 SRAM CO2 Layout Rule (100;0) for Add the new rule
443. 4.5.48 ROM Rules Add the description at section head “circuit design, which
provides more precisely SPICE simulation”
444. 4.5.49 Antenna Effect Prevention (A) Layout Change section no.
Rules
445. 4.5.50 Product Labels and Logo Rules Change section no.
446. LOGO.R.2 4.5.50 Product Labels and Logo Rules Add OD.DN.4® ~OD.DN.7® , PO.DN.4® ~PO.DN.7®
447. LOGO.O.1 4.5.50 Product Labels and Logo Rules Remove DOD, DPO due to DOD.S.9 & DPO.S.8
removed and add DMx_O to match DRC
448. CSR.R.1 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
449. CSR.R.2 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Remove the rule label
450. CSR.R.4 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Remove the rule label
451. CSR.W.1 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
452. CSR.L.1 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
455. CSR_DM.W.1 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
456. CSR_DM.S.1 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
458. CSR_DM.O.1 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
459. CSR_DV.W.1 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
460. CSR_DV.S.1 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
461. CSR_DV.EN.1 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
462. CSR_DM.W.2 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
465. CSR_DV.W.2 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
466. CSR_DV.S.2 4.5.51.2 Chip Corner Stress Relief (CSR) Pattern Add the new rule
468. BiB.R.1 4.5.51.3 Box in Box (BiB) Pattern inside CSR Add the new rule
469. BiB.W.1 4.5.51.3 Box in Box (BiB) Pattern inside CSR Add the new rule
472. BiB.S.1 4.5.51.3 Box in Box (BiB) Pattern inside CSR Add the new rule
475. BiB.L.1 4.5.51.3 Box in Box (BiB) Pattern inside CSR Add the new rule
479. BiB.EN.1 4.5.51.3 Box in Box (BiB) Pattern inside CSR Add the new rule
482. BiB.R.4 4.5.51.3 Box in Box (BiB) Pattern inside CSR Add the new rule
483. SR.S.1 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule and allow M1~AP for VSS connection.
484. SR.R.1 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
485. CO.W.2 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
486. VIAx.W.2 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
487. VIAx.W.3 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
488. VIAx.EN.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
489. VIAx.EN.6 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
490. VIAx.S.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
491. VIAx.S.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
492. Mx.W.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
493. Mx.W.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
494. VIAy.W.2 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
495. VIAy.W.3 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
496. VIAy.EN.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
497. VIAy.EN.6 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
498. VIAy.S.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
499. VIAy.S.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
500. My.W.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
501. My.W.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
502. VIAz.W.2 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
503. VIAz.W.3 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
504. VIAz.EN.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
505. VIAz.EN.5.1 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
506. VIAz.EN.6 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
507. VIAz.S.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
508. VIAz.S.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
509. Mz.W.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
510. Mz.W.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
511. VIAr.W.2 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
513. VIAr.EN.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
514. VIAr.EN.6 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
515. VIAr.S.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
516. VIAr.S.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
517. Mr.W.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
518. Mr.W.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
519. VIAu.W.2 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
520. VIAu.W.3 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
521. VIAu.EN.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
522. VIAu.EN.6 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
523. VIAu.S.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
524. VIAu.S.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
525. Mu.W.4 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
526. Mu.W.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
527. CB.W.3 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
528. CB.EN.2 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
529. AP.W.3 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
530. CB2.W.5 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
531. PM.R.3 4.5.51.4.1 Seal Ring Wall Layout Rules Add the new rule
533. 4.5.51.4.2 DMV in Assembly Isolation Layout Add the new rule
SR_DM.W.1
Rules
SR_DM.S.1
Rules
SR_DM.S.2
Rules
SR_DM.O.1
Rules
SR_DV.W.1
Rules
SR_DV.S.1
Rules
SR_DV.EN.1
Rules
SR.R.2
Rules
SR.R.3
Rules
542. 4.5.51.4.3 CDU (Critical Dimension Uniformity) Add the new rule
CDU.R.1
pattern in Assembly Isolation Rules
543. 4.5.51.4.3 CDU (Critical Dimension Uniformity) Add the new rule
CDU.R.2
544. CO.W.3 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
545. VIAx.W.4 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
546. VIAx.W.5 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
547. VIAx.EN.7 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
548. VIAx.S.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
549. Mx.W.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
550. VIAy.W.4 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
551. VIAy.W.5 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
552. VIAy.S.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
553. VIAy.S.7 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
554. My.W.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
555. VIAz.W.4 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
556. VIAz.W.5 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
557. VIAz.S.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
558. VIAz.S.7 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
559. Mz.W.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
560. VIAr.W.4 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
561. VIAr.W.5 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
562. VIAr.S.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
563. VIAr.S.7 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
564. Mr.W.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
565. Mu.W.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
566. VIAu.W.4 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
567. VIAu.W.5 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
568. VIAu.EN.7 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
569. VIAu.S.6 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
570. VIAu.S.7 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
571. CB.W.4 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
572. CB.EN.3 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
573. AP.W.4 4.5.51.5 Scribe Line Dummy Bar Layout Rules Add the new rule
574. CSR_DM.W.2 4.5.51.6.1 Chip Corner Stress Relief (CSR) Pattern Add the new rule
575. CSR_DM.S.3 4.5.51.6.1 Chip Corner Stress Relief (CSR) Pattern Add the new rule
576. CSR_DM.S.4 4.5.51.6.1 Chip Corner Stress Relief (CSR) Pattern Add the new rule
577. CSR_DV.W.2 4.5.51.6.1 Chip Corner Stress Relief (CSR) Pattern Add the new rule
578. CSR_DV.EN.2 4.5.51.6.1 Chip Corner Stress Relief (CSR) Pattern Add the new rule
579. VIAz.W.4 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
580. VIAz.W.5 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
581. VIAz.EN.7 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
582. VIAz.S.6 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
583. Mz.W.4 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
584. Mz.W.5 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
585. VIAu.W.1 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
586. VIAu.W.2 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
587. VIAu.EN.1 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
588. VIAu.S.1 4.5.51.6.2 Seal Ring Layout Rules in Mu option Add the new rule
589. Mu.W.4 4.5.51.6.2 Scribe Line Dummy Bar Layout Rules Add the new rule
592. VIAu.W.3 4.5.51.6.3 Scribe Line Dummy Bar Layout Rules Add the new rule
593. VIAu.W.4 4.5.51.6.3 Scribe Line Dummy Bar Layout Rules Add the new rule
594. VIAu.EN.2 4.5.51.6.3 Scribe Line Dummy Bar Layout Rules Add the new rule
595. VIAu.S.2 4.5.51.6.3 Scribe Line Dummy Bar Layout Rules Add the new rule
596. 5 Layout Guidelines for the Device Move “section 4.6 Layout Guidelines for the Device
Geometry Effect Geometry Effect” to “chapter 6 Layout Guidelines for the
Device Geometry Effect”
597. PO.S.14m® 5.1 Layout Rules for the WPE (Well Move from the section “Layout Rules for the WPE (Well
Proximity Effect) Proximity Effect)”, only change section number
598. PO.EN.1mGS® 5.1 Layout Rules for the WPE (Well Move from the section “Layout Rules for the WPE (Well
Proximity Effect) Proximity Effect)”
599. PO.EN.1mLP® 5.1 Layout Rules for the WPE (Well Move from the section “Layout Rules for the WPE (Well
Proximity Effect) Proximity Effect)” and correct LOP
600. PO.EN.2m® 5.1 Layout Rules for the WPE (Well Move from the section “Layout Rules for the WPE (Well
601. PO.EN.3mGS® 5.1 Layout Rules for the WPE (Well Move from the section “Layout Rules for the WPE (Well
602. PO.EN.3mLP® 5.1 Layout Rules for the WPE (Well Move from the section “Layout Rules for the WPE (Well
Proximity Effect) Proximity Effect)” and correct LOP
603. M1.W.3 6.1.3 Stress Migration and Wide Metal Add the rule description “sealring (162;2)”
Spacing Rules Adjustment
604. Mx.W.3 6.1.3 Stress Migration and Wide Metal Add the rule description “sealring (162;2)”
Spacing Rules Adjustment
605. 6.1.4.1 Non-shrinkable Rules Change the rule number to #CB2.P.1 from #CB.P.1S.
#CB2.P.1
Relax 55 to 50 for staggered to align wire bond rule V1.1.
606. 6.1.4.1 Non-shrinkable Rules Change the rule number to #CB2.W2 from #CB.W2 and
#CB2.W.2
remove rule for single in-line to align wire bond rule V1.1.
607. 6.1.5 Flip Chip Bump Rules Remove the warning of bump pitch to bump pitch change
in V1.1.
608. UBM.A.1 6.1.5.1 Non-shrinkable Rules Remove the rule
609. UBM.EN.1 6.1.5.1 Non-shrinkable Rules Add the rule
610. BP.W.4 6.1.5.1 Non-shrinkable Rules Add the rule
611. BP.EN.5 6.1.5.1 Non-shrinkable Rules Add the rule
612. BP.EN.7 6.1.5.1 Non-shrinkable Rules Add the rule
613. RES.2m 7.2.4 Resistor Rules Remove this rule since RES.W.1 & RES.R.1 can cover it.
614. NWROD.R.1m 7.2.4 Resistor Rules Remove “DRC can’t check…..”
615. NWRSTI.R.1m 7.2.4 Resistor Rules Remove “DRC can’t check…..”
616. AN.R.7m 7.3.2 Matching Rules and Guidelines Add and remove some description
617. AN.R.12m 7.3.2 Matching Rules and Guidelines Add description
618. PO.S.5m® 7.4.2 MOS Recommendations Change the rule value to 0.2 from 0.1
619. PO.S.6.1m® 7.4.2 MOS Recommendations Add the new rule
620. 8.1 Dummy OD (DOD) Rules Add the description “For N40G( N45GS ) process,it is
important to turn on the switch of FILL_SRDOD_SRDPO
to control the OD space effect.
N45LP/N40LP.”
621. DOD.S.9 8.1 Dummy OD (DOD) Rules Remove the rule
622. 8.2 Dummy Poly (DPO) Rules Add the description “For N40G( N45GS ) process,it is
important to turn on the switch of FILL_SRDOD_SRDPO
to control the OD space effect.
N45LP/N40LP.”
623. DPO.S.8 8.2 Dummy Poly (DPO) Rules Remove the rule
624. DTCD.R.2 8.3 Dummy TCD rule and Filling Guideline Remove mVTL and add OD_12, HVD_N, HVD_P
SR_DOD SR_DPO
625. 8.4 Dummy Metal (DM) Rules Modify the section wording
626. DMx.W.1 8.4 Dummy Metal (DM) Rules Relax M1 & Mx for DVIAx insertion
627. DMx.S.1 8.4 Dummy Metal (DM) Rules Relax M1 & Mx for DVIAx insertion
628. DMx.EN.2 8.4 Dummy Metal (DM) Rules Add the new rule
629. DMx.S.9 8.4 Dummy Metal (DM) Rules Remove the rule
630. Mx.DN.1.1 8.4 Dummy Metal (DM) Rules Correct item 2 from 32 to 31.5
Correct item 3 from 25 to 31.5
Update item 4 Bond pad (Mtop/Mtop-1) to match DRC
631. Mx.DN.4 8.4 Dummy Metal (DM) Rules Relax from 40% to 50%
632. DMx_O.R.1 8.4 Dummy Metal (DM) Rules Add the new rule
633. DVIAx.W.1 8.5 Dummy VIA (DVIA) Rules Add the new rule
634. DVIAx.S.1 8.5 Dummy VIA (DVIA) Rules Add the new rule
635. DVIAx.S.2 8.5 Dummy VIA (DVIA) Rules Add the new rule
636. DVIAx.EN.1 8.5 Dummy VIA (DVIA) Rules Add the new rule
637. DVIAx.R.1 8.5 Dummy VIA (DVIA) Rules Add the new rule
640. PO.S.5® LP 9.2.1 Action-Required Rules Add the new rule
641. PO.S.5® GS 9.2.1 Action-Required Rules Add the new rule
642. PO.S.6® LP 9.2.1 Action-Required Rules Add the new rule
643. PO.S.6® GS 9.2.1 Action-Required Rules Add the new rule
644. SR_DOD.W.1® 9.2.2 Recommendations Remove the rule
645. OD.DN.4® 9.2.2 Recommendations Add the new rule
651. DOD.R.2® 9.2.2 Recommendations Add the new rule
652. PO.W.1U® 9.2.2 Recommendations Add the new rule
653. PO.S.2® LP 9.2.2 Recommendations Add the new rule
654. PO.S.17® 9.2.2 Recommendations Add the new rule
655. PO.S.18® LP 9.2.2 Recommendations Add the new rule
656. PO.S.18® GS 9.2.2 Recommendations Add the new rule
657. SR_DPO.W.1® 9.2.2 Recommendations Remove the rule
658. PO.DN.4® 9.2.2 Recommendations Add the new rule
664. CO.EN.3® 9.2.2 Recommendations Correct typo of min. value from 0.03 to 0.02
665. CO.S.7® 9.2.2 Recommendations Add the new rule
666. M1.EN.5® 9.2.2 Recommendations Add the new rule
667. M1.A.1® 9.2.2 Recommendations Add the new rule
668. Mx.A.1® 9.2.2 Recommendations Add the new rule
669. SR_DOD.R.4U 9.2.3 Guidelines Add the new rule
670. SR_DOD.W.1® 9.2.4 Grouping Table of Recommendations Remove the rule
671. SR_DPO.W.1® 9.2.4 Grouping Table of Recommendations Remove the rule
672. PO.W.1U® 9.2.4 Grouping Table of Recommendations Add the new rule
673. PO.S.2® LP 9.2.4 Grouping Table of Recommendations Add the new rule
675. PO.S.5® GS 9.2.4 Grouping Table of Recommendations Add the new rule
677. PO.S.6® GS 9.2.4 Grouping Table of Recommendations Add the new rule
678. PO.S.17® 9.2.4 Grouping Table of Recommendations Add the new rule
679. LUP.WARN.1 10.1.2.4 Layout Rules and Guidelines for Latch- Add the new rule
up Prevention
680. LUP.1 10.1.2.4 Layout Rules and Guidelines for Latch- Add the new rule
up Prevention
up Prevention
682. LUP.3.1.1 10.1.2.4 Layout Rules and Guidelines for Latch- Add the new rule
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
692. LUP. 4 10.1.2.4 Layout Rules and Guidelines for Latch- Add the new rule
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
704. LUP.7gU 10.1.2.4 Layout Rules and Guidelines for Latch- Add the new rule
up Prevention
up Prevention
up Prevention
707. ESDIMP.W.1 10.2.3 ESD Implant (ESDIMP) Layout Rules Add the new rule
(MASK ID: 111)
708. ESDIMP.S.1 10.2.3 ESD Implant (ESDIMP) Layout Rules Add the new rule
(MASK ID: 111)
709. ESDIMP.EN.1 10.2.3 ESD Implant (ESDIMP) Layout Rules Add the new rule
(MASK ID: 111)
710. ESDIMP.EN.1® 10.2.3 ESD Implant (ESDIMP) Layout Rules Add the new rule
(MASK ID: 111)
711. ESDIMP.A.1 10.2.3 ESD Implant (ESDIMP) Layout Rules Add the new rule
(MASK ID: 111)
712. ESDIMP.A.2 10.2.3 ESD Implant (ESDIMP) Layout Rules Add the new rule
(MASK ID: 111)
713. ESDIMP.R.1 10.2.3 ESD Implant (ESDIMP) Layout Rules Add the new rule
(MASK ID: 111)
714. ESDIMP.R.2® u 10.2.3 ESD Implant (ESDIMP) Layout Rules Add the new rule
(MASK ID: 111)
715. SR_ESD.W.1 10.2.4 SR_ESD device Layout Rules Add the new rule
716. SR_ESD.W.2 10.2.4 SR_ESD device Layout Rules Add the new rule and relax ">=0.1~0.15" to “>=0.1”
717. SR_ESD.W.3 10.2.4 SR_ESD device Layout Rules Add the new rule
718. SR_ESD.S.1 10.2.4 SR_ESD device Layout Rules Add the new rule
719. SR_ESD.EX.1 10.2.4 SR_ESD device Layout Rules Add the new rule
720. SR_ESD.L.1 10.2.4 SR_ESD device Layout Rules Add the new rule
721. SR_ESD.R.1 10.2.4 SR_ESD device Layout Rules Add the new rule
722. ESD.WARN.1 10.2.9.1 General Guideline for ESD Protection Add the new rule
723. ESD.WARN.2 10.2.9.1 General Guideline for ESD Protection Add the new rule
724. ESD.1g 10.2.9.1 General Guideline for ESD Protection Add the new rule
725. ESD.2gU 10.2.9.1 General Guideline for ESD Protection Add the new rule
733. ESD.9.1gU 10.2.9.1 General Guideline for ESD Protection Add the new rule
744. ESD.16g 10.2.9.2 Regular I/O (3.3V/2.5V/1.8V/1.1V/0.9V Add the new rule
RPO Device)
RPO Device)
RPO Device)
747. ESD.18.1g 10.2.9.2 Regular I/O (3.3V/2.5V/1.8V/1.1V/0.9V Add the new rule
RPO Device)
RPO Device)
RPO Device)
RPO Device)
RPO Device)
RPO Device)
RPO Device)
RPO Device)
755. ESD.24g 10.2.9.3 HV Tolerant I/O Add the new rule
758. ESD.26.1g 10.2.9.3 HV Tolerant I/O Add the new rule
759. ESD.26.2g 10.2.9.3 HV Tolerant I/O Add the new rule
768. ESD.35gU 10.2.9.3 HV Tolerant I/O Add the new rule
769. ESD.37g 10.2.9.4 Power Clamp Device (Ncs) Add the new rule
770. ESD.37.1g 10.2.9.4 Power Clamp Device (Ncs) Add the new rule
771. ESD.38g 10.2.9.4 Power Clamp Device (Ncs) Add the new rule
775. ESD.43gU 10.2.9.4 Power Clamp Device (Ncs) Add the new rule
779. ESD.47g 10.2.9.5 5V HVMOS protection (Field Device) Add the new rule
788. HIA.1gU 10.2.9.6 High Current Diode (HIA_DIO) Add the new rule
797. ESD.56gU 10.2.9.7 CDM Protection for Cross Domain Add the new rule
Interface
Interface
799. ESD.57.1gU 10.2.9.7 CDM Protection for Cross Domain Add the new rule
Interface
Interface
Interface
Interface
Interface
Interface
805. 11 CLN45LP/LPG Reliability Rules Add the chapter for CLN45LP/LPG Reliability Rules & Mu
related rules
806. 12 CLN40LP/LPG/45GS(=40G) Reliability Add the chapter for CLN40LP/LPG/45GS(=40G)
Rules Reliability Rules & Mu related rules

1. Merge T-N45-CL-DR-021 ( dummy TCD rule, V1.0)
2. 1.1 Overview Modify Mu thickness from 34KA to 35KA
3. Modify Mu: top metal pitch from 4um to 3um (W/S = 2um/2um
2.1.2 Back-End Features
to 2um/1um)
4. Power Supply and Operation
2.3 Add “**” for only drain side can be applied to 5V.
Temperature Ranges
5. Modify M10 from W/S =2.0/2.0 to 2.0/1.0 for 1P10M, top
2.4 Cross-section
Mz/Mu (TM) and top My (2XTM)/Mu (TM).
6. Modify Table 2.5.1 Mx thickness from 1400 to 1500 and Mu
2.5 Metallization Options
thickness from 34000 to 35000
7. Mask Information, Key Process
3.1 Remove the 3.3V wording at table 3.1.1
8. Mask Information, Key Process Add NT_N in the reference layer in logical operation and OPC
3.1
Sequence, and CAD Layers of mask 117 at table 3.1.3
9. Special Recognition CAD Layer Add the special layers: LOWMEDN/ TCDDMY_H/
3.4
Summary TCDDMY_V/ ICOVL
10. Remove the wording of “4.6 CRN45/CRN40(RF) Layout Rules
4 Layout Rules and Recommendations
and Guidelines”.
11. Definition of Layout Geometrical Add the comparison table for seal ring/ protection ring/ guard
4.3
Terminology ring
12. Definition of Layout Geometrical Add the definition of layout geometrical terminology of Hole
4.3
Terminology width/ Enclosed space
13. SR_DOD.DN.1® 4.5.2 SR_DOD Layout Rules Add the new rule
14. SR_DPO.DN.1® 4.5.15 SR_DPO Layout Rules Add the new rule
15. Metal-1 (M1) Layout Rules (Mask ID:
M1.DN.6 4.5.29 Add the new rule
360)
16. VIAx Layout Rules (Mask ID: 378, Add the description for “Except sealring (162,2) and
VIAx.W.1 4.5.30
379, 373, 374, 375, 376, 377) {LOWMEDN NOT (LOWMEDN SIZING -4 µm)} region”
17. VIAx Layout Rules (Mask ID: 378,
VIAx.R.2 4.5.30 Add the description for “Except VIA bar region”
379, 373, 374, 375, 376, 377)
379, 373, 374, 375, 376, 377)
379, 373, 374, 375, 376, 377)
379, 373, 374, 375, 376, 377)
379, 373, 374, 375, 376, 377)
22. VIAx Layout Rules (Mask ID: 378, Add the description for “Except {LOWMEDN NOT
VIAx.R.8® 4.5.30
379, 373, 374, 375, 376, 377) (LOWMEDN SIZING -4 µm)}”
23. VIAx Layout Rules (Mask ID: 378, Add the description for “Except {LOWMEDN NOT
VIAx.R.9gU 4.5.30
379, 373, 374, 375, 376, 377) (LOWMEDN SIZING -4 µm)}”
24. Mx Layout Rules (Mask ID: 380, 381,
Mx.DN.6 4.5.31 Add the new rule
384, 385, 386, 387, 388)
Mx.DN.7 4.5.31 Add the new rule
384, 385, 386, 387, 388)
Mx.DN.8® 4.5.31 Add the new rule
384, 385, 386, 387, 388)
DMx.R.4® U 4.5.31 Add the new rule
384, 385, 386, 387, 388)
28. 4.5.32 LOWMEDN Layout Rules Add this section
29. INDDMY Layer Identified Inductor Add the description for “and Vx in {LOWMEDN NOT
IND.R.1 4.5.45
Layout Rules (LOWMEDN SIZING -4 µm)}”
30. INDDMY Layer Identified Inductor Add the description for “and Mx in {(LOWMEDN NOT
IND.R.5 4.5.45
Layout Rules (LOWMEDN SIZING -5 µm)) interact VIAx bar}”
31. Al Redistributional Layer (AP RDL)
AP.W.2® U 4.5.40 Correct rule no. from AP.W.2U to AP.W.2® U
Layout Rules (Mask ID:309)
32. 4.5.42 MOM Layout Rules Modify Mu thickness from 34KA to 35KA
33. MOM.R.2 4.5.42 MOM Layout Rules Add the new rule
34. 4.5.44 Mu (Ultra Thick Metal) Layout Rules Modify Mu thickness from 34KA to 35KA
35. ROM.R.3® 4.5.51 ROM Rules Add the new rule
36. Modify the description of the figure from “In tsmc’s ROM
4.5.51 ROM Rules
cell, …” to “Suggested to add dummy poly (17;0)….”.
37. LOGO.O.1 4.5.53 Product Labels and Logo Rules Modify the rule’s description to remove “or DMx, DMx_O”
38. SR.R.7 4.5.54.4 Seal Ring Layout Rules Add the new rule
39. SR.R.8U 4.5.54.4 Seal Ring Layout Rules Add the new rule
40. Dummy TCD rule and Filling
8.3 Merge from T-N45-CL-DR-021
Guideline
41. Add DOD.R.2® , SR_DOD.DN.1® and SR_DPO.DN.1® for
DTCD.R.3 8.3.1 Dummy TCD Rules
waived items
42. Remove the description “It’s not appeared square dummy
8.3.2 Dummy TCD layout Summary TCD in TSMC’s auto-fill ultilities V1.2b (documents: T-N45-CL-
DR-001-C2 and T-N45-CL-DR-001-H2).”
43. 8.4 Dummy TCD Design Information Merge from T-N45-CL-DR-021
44. In Chip Overlay (ICOVL) Rule And
8.5 Add this section
Filling Guideline
45. DMx.S.7 8.6 Dummy Metal (DM) Rules Remove this rule since overlap is allowed.
46. DMx.S.8 8.6 Dummy Metal (DM) Rules Remove this rule since overlap is allowed.
47. Mx.DN.6 8.6 Dummy Metal (DM) Rules Add the new rule
48. DMx.R.4® 8.6 Dummy Metal (DM) Rules Add the new rule
49. OD.DN.4® 9.2.2 Recommendations Remove the value of min rule
50. OD.DN.6® 9.2.2 Recommendations Remove the value of min rule
51. SR_DOD.DN.1® 9.2.2 Recommendations Add the new rule
52. SR_DPO.DN.1® 9.2.2 Recommendations Add the new rule
53. M1.EN.5® 9.2.2 Recommendations Correct the value of min rule
54. Add the description for “Except {LOWMEDN NOT
VIAx.R.8® 9.2.2 Recommendations
(LOWMEDN SIZING -4 µm)}”
55. Mx.DN.8® 9.2.2 Recommendations Add the new rule
56. ROM.R.3® 9.2.2 Recommendations Add the new rule
57. SR_DOD.DN.1®
SR_DPO.DN.1® Add these new rules at grouping table of recommendations
9.2.4 Grouping Table of Recommendations
Mx.DN.8® and define to 1st priority for chip level
ROM.R.3®
58. Layout Rules and Guidelines for
LUP.5.5.2 10.1.2.4 Correct the typo from “≥” to “<”
Latch-up Prevention
59. 10.2.4 SR_ESD device Layout Rules Remove the OD.L.4 for SR_ESD waived rules
60. 10.2.9.5 5V HVMOS protection (Field Device) Modify VSS to VDD of the figure 10.2.29
A.6 From Version 1.3 to 1.3_1

Correct the typo in table 2.5.1: For N45LP/LPG, Mx/ Mu
1. 2.5 Metallization Options
thickness change to 1400/34000.
Correct the typo in the note of table 2.5.10: EU Flip Chip
2. 2.5 Metallization Options design please refer T-N45-CL-DR-003 V1.1 instead of LF Flip
Chip.
3. 3.4 Correct CAD usage for HVD_N/ HVD_P/ HIA_Dummy
Summary
Poly (PO) Layout Rules (Mask ID:
4. PO.W.3LP 4.5.14 Modify the rule No. from PO.W.3 to PO.W.3LP
130)
5. PO.EX.2.1GS 4.5.14 Modify the rule’s description from PO.EX.2.1 to PO.EX.2.1GS
130)
Metal-1 (M1) Layout Rules (Mask ID: Modify the rule’s description for additional area checking
6. M1.DN.6 4.5.29
360) methodologies to flag large empty ELK areas.
Metal-1 (M1) Layout Rules (Mask ID:
7. M1.DN.6® 4.5.29 Add the recommendation for IP level
360)
8. 4.5.29 Add the information of M1.DN.6® for IP level in table notes
360)
VIAx Layout Rules (Mask ID: 378,
9. VIAx.W.1 4.5.30 Modify the rule’s description to add {VIAx bar INSIDE…}.
379, 373, 374, 375, 376, 377)
Modify the rule’s description to remove “The DVIAx CAD layer
(TSMC default, 52;1 for DVIA2) must be different from the
10. DVIAx.R.3 4.5.30 VIAx CAD layer and to add “To comply tsmc dummy utility,
379, 373, 374, 375, 376, 377)
DRC will flag as violation when the area ratio of (DVIAx to
DMx) & (DVIAx to DMx+1) are < 1% at the same time.”.
Mx Layout Rules (Mask ID: 380, 381, Modify the rule’s description for additional area checking
11. Mx.DN.6 4.5.31
384, 385, 386, 387, 388) methodologies to flag large empty ELK areas.
Mx Layout Rules (Mask ID: 380, 381,
12. Mx.DN.6® 4.5.31 Add the recommendation for IP level
384, 385, 386, 387, 388)
13. Mx.DN.7® 4.5.31 Add the recommendation for IP level
384, 385, 386, 387, 388)
Mx Layout Rules (Mask ID: 380, 381, Add the information of Mx.DN.6® / Mx.DN.7 and Mx.DN.7® for
14. 4.5.31
384, 385, 386, 387, 388) IP level in table notes
Modify the rule to add 0.005um checking tolerance for
15. LOWMEDN.R.4 4.5.32 LOWMEDN Layout Rules
VIAx.EN.8/ Mx.EN.4 for 45-degree protection ring.
Modify the rule’s description to “For C-shape ring,” to confirm
16. LOWMEDN.R.6 4.5.32 LOWMEDN Layout Rules that DRC only flag one closed-ring and at least 2 C-shape
rings.
17. LOWMEDN.R.9 4.5.32 LOWMEDN Layout Rules Remove
18. VIAx.EN.8 4.5.32 LOWMEDN Layout Rules Relax the rule spec from 0.265 to 0.21
19. Mx.EN.4 4.5.32 LOWMEDN Layout Rules Relax the rule spec from 0.265 to 0.21
1. Relax the rule spec from 1.21E+06 to 1.31E+06
20. MOM.A.1** 4.5.42 MOM Layout Rules 2. Relax sidewall area of total metals in MOM without Via for
different applied voltage
Modify the rule’s description to remove FW since metal fuse is
21. Mu.DN.2 4.5.44 Mu (Ultra Thick Metal) Layout Rules
not offered in N45/N40.
Modify the rule’s description to add “(This check doesn’t
22. LOGO.S.1 4.5.53 Product Labels and Logo Rules include the M1/ Mx protection ring inside {LOWMEDN NOT
(LOWMEDN SIZING -4 um)} region)”.
23. DTCD.R.2 8.3.1 Dummy TCD Rules Modify the rule’s description to exclude LOGO region
Modify the rule’s description from OD.W.2.1/ OD.W.2.2 to
24. DTCD.R.3 8.3.1 Dummy TCD Rules
OD.W.2.1GS/ OD.W.2.2GS
25. ICOVL.R.1 8.5.1 In Chip Overlay (ICOVL) Rules Modify the rule’s description to add OD.W.2.2GS
M1.DN.6®
26. Mx.DN.6® 9.2.2 Recommendations Add
Mx.DN.7®
M1.DN.6®
27. Mx.DN.6® 9.2.4 Grouping Table of Recommendations Add
Mx.DN.7®
1. Re-name the section title from “DFM Service” to “Model-
based DFM”.
28. 9.3 Model-based DFM
2. Remove the description: TSMC provides the following DFM
service through TSMC on-line system.
1. Re-name the section title from “DFM LPC (Layout
Patterning Check, Shape Simulation) Service” to “DFM LPC
DFM LPC (Layout Patterning Check,
29. 9.3.1 (Layout Patterning Check, Shape Simulation)”.
Shape Simulation)
2. Remove the description: Layout fixing recommendation for
the LPC hot spot will be provided.
1. Re-name the section title from “DFM VCMP (Virtual
Chemical Mechanical Polishing, Thickness Simulation)
DFM VCMP (Virtual Chemical
Service” to “DFM VCMP (Virtual Chemical Mechanical
30. 9.3.2 Mechanical Polishing, Thickness
Polishing, Thickness Simulation)”.
Simulation)
2. Remove the description: VCMP hot spot and layout
recommendation will be provided.
1. Re-name the section title from “DFM YSA (Yield Sensitivity
Analysis) Service” to “DFM YSA (Yield Sensitivity
31. 9.3.3 DFM YSA (Yield Sensitivity Analysis) Analysis)”.
2. Remove the description: A layout recommendation will be
provided.
A.7 From Version 1.3_1 to 2.0

1. Modify Mu thickness from 35KA to “34KÅ or 35KÅ”.
1. 1.1 Overview
2. Modify the description grammar.
1. Modify the section title from “Reference Documentation” to
“Reference Document”.
2. Remove brief process flow.
3. Modify the document title of T-N45-CL-LE-001 about GDS
layer usage.
4. Modify LF Flip Chip DRM/DRC.
5. Add DFM guideline documents.
2. 1.2 Reference Document 6. Add and modify some SPICE documents.
7. Modify LVS document numbers and add LVS document,
T-N40-CL-LS-001-X1.
8. Add PDK document, T-N40-CL-SP-051-K1.
9. Remove T-N40-CL-CL-005 from SRAM document list, and
modify the document title of T-000-CL-RP-002 by adding
“AND ECC GUIDELINE”.
10. Add qual reports for HVMOS.
1. N40LP/ N40LPG-LP SRAM: Remove Vcc_nom = 1.0V.
3. 2.1.1 Front-End Features 2. Remove N40LP-ULP SRAM cell offering.
3. Add “D299 and D589 in N40GL process belong to N40G.”.
4. 2.1.2 Back-End Features Modify LF FC information.
1. Modify N45LPG and N40LPG devices.
5. 2.2 Devices 2. Modify the section number of MOS Varactor Layout Rules
(VAR).
Power Supply and Operation
6. 2.3 Modify 5V HVMOS information.
Temperature Ranges
1. Modify Vu/Mu by Vu1/Mu1, respectively.
2. Modify VyTM1 by VyTV1.
7. 2.5 Metallization Options
3. Modify the top metal requirement table for WB/FC, Table
2.5.10, by referring to the related design rule manuals.
1. Add a warning message as “If ≥ one of the above CAD
layer is revised, both 12E and 12F must be re-taped out.”
2. Remove duplicate layers for mask 120 in all technologies.
3. Remove CAD layer 15 for mask 152 in N45LP/N40LP.
4. Mask 117, VTL_P, is a must if N40LP HVPMOS_18 is
used, and add HVD_P for mask 117 in N40LP.
5. Remove mask 11Q, VTC_P3, due to the removal of
N40LP-ULP SRAM in N40LP.
6. Update the reference CAD layers for mask 155 and Mask
to CAD layer mapping tables in N45/N40LP.
7. Add CB2_WB into the reference layer list of mask 307,
AP, for wire bond w/o AP RDL in all technologies.
8. Add the drawing option of mask 009, PM, for wire bond by
CAD layer as 5;0 in all technologies.
9. Modify bond pad by bump pad for FC in all technologies.
10. Add mask 020, UBM, for FC in all technologies.
Mask Information, Key Process 11. Add “OD2, PO, PP, CO” into the reference layers of mask
8. 3.1
Sequence, and CAD Layers 120 (OD) into N40G process.
12. Mask 11H, VTH_N, is a must if N40G SRAM is used.
13. Update Mask to CAD layer mapping tables for mask 116
in all technologies.
14. Add HVD_N/HVD_P into “N45LP/N40LP 1.8V Mask to
CAD layer mapping table” and “N45LP/N40LP 2.5V Mask
to CAD layer mapping table”.
15. Separate “N45LP/N40LP 1.8V Mask to CAD layer
mapping table” into two tables (N40LP 1.8V and N45LP
1.8V).
16. Separate “N45LP/N40LP 2.5V Mask to CAD layer
mapping table” into two tables (N40LP 2.5V and N45LP
2.5V).
17. Revise OD_33 (15;0) to OD_18 (16:0) for N45LPG 1.8V
Mask to CAD layer mapping table.
18. Revise OD_18 (16:0) to OD_33 (15;0) for N40LPG 3.3V
Mask to CAD layer mapping table.
Special Recognition CAD Layer 1. Modify RH CAD layer from 117 to 117;0, and mark RH as
9. 3.4
Summary a DRC CAD layer, too.
2. Add RHDMY1 (117;4).
3. Remove NONSENDMY (255;11), since no rule uses this
layer.
4. Rename SRAMDMY (186;4) to SRAMDMY;4 (186;4) and
SRAMDMY (186;5) to SRAMDMY;5 (186;5)
5. Modify SR_ESD information by adding ”for N40G ESD
device only”.
10. 3.5 Device Truth Tables 1. Add Device Truth Table for N40LP 5V HVMOS_18.
1. Modify RPO from 0 to 1#a for HV NMOS and HV PMOS,
N45/N40 Low Power (LP): 1.1V Core
11. 3.5.1 and add a table note about the reason.
Design
2. Add Device Truth Table for N40LP 5V HVMOS_18.
1. Rename from “N45LPG: 1.1V/0.9V Core Design” to
“N45LPG/N40LPG: 1.1V/0.9V Core Design”.
2. Remove Native NMOS (1.1V), Native NMOS (0.9V), and
N45LPG/N40LPG: 1.1V/0.9V Core
12. 3.5.2 Native I/O NMOS (1.8V) from N45LPG truth table.
Design
3. Add 0.9V Varactor, 1.1V Varactor, and 1.8V Varactor into
N45LPG truth table,
4. Remove Native NMOS (0.9V) from N40LPG truth table.
N40G (N45GS) General Purpose 1. Add ESD NMOS (0.9V), nch_hia.
13. 3.5.3
Superb: 0.9V Core Design 2. Add SR_ESD and SDI layers.
Rename MOMDMY(155;n) to MOMDMY_n(155;n) (n = 1~8)
14. 3.5.4 MOM
and DMEXCL(150;n) to DMnEXCL(150;n) (n = 1~10)
1. Rename RFDMY(161;1) to RFIP_DMY(161;1) and
15. 3.5.5 Inductor INDDMY(144;31) to DMYDIS(144;31).
2. Correct 166;1 to 161;1 for RFIPDMY.
1. Switch 186;5 for GS/GL and 186;4 for LP/LPG.
2. Add AP[in UBM], CB2_WB/CB2_FC[in Cu_PPI of WLCSP
16. G.1 3.7.1 Design Grid Rules
process], PM1/Cu_PPI (for WLCSP process), and PM2[in
UBM for WLCSP process] into the exception.
Add AP[in UBM], CB2_WB/CB2_FC[in Cu_PPI of WLCSP
17. G.2 3.7.1 Design Grid Rules process], PM1/Cu_PPI (for WLCSP process), and PM2[in
Add AP[in UBM], CB2_WB/CB2_FC[in Cu_PPI of WLCSP
18. G.3 3.7.1 Design Grid Rules process], PM1/Cu_PPI (for WLCSP process), and PM2[in
OPC Recommendations and
19. 3.7.2 Modify cell names’ characters from 64 to 127.
Guidelines
20. 3.8 Design Hierarchy Guidelines Modify the description grammar.
Chip Implementation and Tape Out
21. 3.9 Refine the description.
Checklist
1. Add another definitions, table notes, and figures for NW1V
and NW2V.
2. Add the definition of RW STRAP to align DRC coding.
3. Move the definition of RW from section 4.5.3, Deep N-Well
22. 4.2.1 Derived Geometries
(DNW) Layout Rules (Mask ID: 119) [Optional], to align
DRC coding.
4. Add the definition of PW to align DRC coding.
5. Add the definition of BTC.
23. 4.2.2 Speciall Definition Add the definition of BTC.
Add the following definitions.
1. A INTERACT B.
2. A NOT INTERACT B.
3. A INSIDE B.
4. A NOT INSIDE B.
5. A OUTSIDE B.
Definition of Layout Geometrical 6. A NOT OUTSIDE B.
24. 4.3
Terminology 7. A ABUT B.
8. A AND B.
9. A OR B.
10. A CUT B.
11. B CUT A.
12. A NOT CUT B.
13. Corner = Vertex.
Gate Oxide and Diffusion (OD) Layout
25. OD.W.1® 4.5.1 Add TCDDMY into the exception.
26. OD.S.6® 4.5.1 Remove this recommendation for mask ESD concern.
27. OD.A.1 4.5.1 Modify the description from tile to tiles.
28. OD.A.2 4.5.1 Modify the description from length to lengths.
29. OD.A.4 4.5.1 Gate Oxide and Diffusion (OD) Layout Modify the description from length to lengths.
Gate Oxide and Diffusion (OD) Layout Modify the description by adding “the”, and rename from
30. OD.A.5.GS 4.5.1
Rules (Mask ID: 120) OD.A.5GS to OD.A.5.GS.
31. OD.L.1 4.5.1 Add “if no CO in M region”
1. Remove “(CB sizing 2) for high speed/RF products”.
32. OD.DN.0 4.5.1 2. Modify the description from while to when.
3. Modify the description by adding “is ≥”.
1. Modify the description by adding “the“ and “with “.
Gate Oxide and Diffusion (OD) Layout 2. Add “is as follows”.
33. OD.DN.4® 4.5.1
Rules (Mask ID: 120) 3. Remove “Channel length <= 0.05um” from the gate
definition.
1. Modify the description by adding “the“ and “with”.
2. Add “is as follows”.
34. OD.DN.5® 4.5.1 3. Remove “Channel length <= 0.05um” from the gate
definition.
4. Relax the spec from 55% to 70%.
Gate Oxide and Diffusion (OD) Layout 2. Add “is as follows”.
35. OD.DN.6® 4.5.1
Rules (Mask ID: 120) 3. Remove “Channel length <= 0.05um” from the gate
definition.
2. Add “is as follows”.
36. OD.DN.7® 4.5.1 3. Remove “Channel length <= 0.05um” from the gate
definition.
Gate Oxide and Diffusion (OD) Layout 1. Modify the description by adding “the“ and “with”.
37. OD.DN.8® 4.5.1
Rules (Mask ID: 120) 2. Correct the typo from unaslicided to unsalicided.
Gate Oxide and Diffusion (OD) Layout 1. Modify the description by adding “the“ and “with”.
38. OD.DN.9® 4.5.1
Rules (Mask ID: 120) 2. Correct the typo from unaslicided to unsalicided.
Gate Oxide and Diffusion (OD) Layout 1. Modify the rule number from DOD.R.2® to DOD.R.4® .
39. DOD.R.4® 4.5.1
Rules (Mask ID: 120) 2. Modify the op. from ≥ to .
40. DNW.S.5 4.5.2 Remove "with" from "INTERACT with".
(Mask ID: 119) [Optional]
Deep N-Well (DNW) Layout Rules Remove this rule (the definition of RW instead a rule actually)
41. DNW.R.2 4.5.2
(Mask ID: 119) [Optional] and move it to section 4.2.1, Derived Geometries.
1. Remove "with" from "INTERACT with".
42. DNW.R.3U 4.5.2 2. Modify the rule number from DNW.R.3 to DNW.R.3U as
DRC unchecked.
43. DNW.R.4U 4.5.2 Remove "with" from "INTERACT with".
44. DNW.R.7 4.5.2 Add this rule.
45. 4.5.3 N-Well (NW) Layout Rules Add table notes.
46. NW.W.1 4.5.3 N-Well (NW) Layout Rules Exclude SRAMDMY to comply with the current DRC coding.
47. NW.S.7 4.5.3 N-Well (NW) Layout Rules Remove "with" from "INTERACT with".
48. NW.EN.3 4.5.3 N-Well (NW) Layout Rules Remove "with" from "INTERACT with".
Modify the rule number from NW.R.1gU to NW.R.1g as DRC
49. NW.R.1g 4.5.3 N-Well (NW) Layout Rules
checked.
U
50. NW.R.2 4.5.3 N-Well (NW) Layout Rules Add this rule.
N-Well Resistor Within OD (NWROD)
51. NWROD.R.5 4.5.4 Modify the description from is to are.
Layout Rules
52. NWROD.R.6 4.5.4 Modify the description by adding “the“.
Layout Rules
1. Modify the description from while to when and from 2 to
53. NWROD.R.7 4.5.4 two.
Layout Rules
2. Modify the description by adding “have a”.
54. NWROD.R.8g 4.5.4 Add this guideline.
Layout Rules
N-Well Resistor Within OD (NWROD) Modify the figure for NWROD.W.1 from S-shape to line
55. 4.5.4
Layout Rules shape.
N-Well Resistor Under STI (NWRSTI)
56. NWRSTI.O.1 4.5.5 Remove "with" from "INTERACT with".
Layout Rules
N-Well Resistor Under STI (NWRSTI)
57. NWRSTI.R.4g 4.5.5 Add this guideline.
Layout Rules
N-Well Resistor Under STI (NWRSTI) Modify the figure for NWRSTI.W.1 from S-shape to line
58. 4.5.5
Layout Rules shape.
Refine the statement in front of the rule table for Native
59. 4.5.6 Native Device (NT_N) Layout Rules
NMOS.
60. NT_N.W.2 4.5.6 Native Device (NT_N) Layout Rules Dedicate this rule for N45LP/N45LPG/N40G.
61. NT_N.W.2.1 4.5.6 Native Device (NT_N) Layout Rules Add this rule for N40LP/N40LPG by separating NT_N.W.2.
62. NT_N.R.3 4.5.6 Native Device (NT_N) Layout Rules
2. Add one figure for NT_N.R.3.
Thick Oxide (OD2) Layout Rules
63. OD2.W.3 4.5.7 Add this rule.
(Mask ID: 152)
Thick Oxide (OD2) Layout Rules
64. OD2.S.8 4.5.7 Add this rule.
(Mask ID: 152)
Dual Core Oxide (DCO) Layout Rules
65. DCO.W.2 4.5.8 Exclude SRAMDMY as what NW.W.1 has done in DRC.
(Mask ID: 153)
Add “This is not a mask layer” into the description in front of
66. 4.5.10 OD25_33 Layout Rules
the rule table.
67. OD25_33.W.1.LP 4.5.10 OD25_33 Layout Rules Rename from OD25_33.W.1LP to OD25_33.W.1.LP.
68. OD25_33.W.1.GS 4.5.10 OD25_33 Layout Rules Rename from OD25_33.W.1GS to OD25_33.W.1.GS.
Add “This is not a mask layer” into the description in front of
71. 4.5.11 OD25_18 Layout Rules
the rule table.
75. PO.W.1® U 4.5.13 Rename from PO.W.1U® to PO.W.1® U.
130)
76. PO.W.3.LP 4.5.13 Rename from PO.W.3LP to PO.W.3.LP.
130)
Poly (PO) Layout Rules (Mask ID: Add CDUDMY into the exception and rename from
77. PO.W.6.GS 4.5.13
130) PO.W.6GS to PO.W.6.GS..
78. 4.5.13 Remove Figure PO.S.1.1® due to no this rule.
130)
1. Modify the description from It to This and from the to a.
79. PO.S.2.LP 4.5.13 2. Modify the description by adding “a”.
130)
3. Rename from PO.S.2LP to PO.S.2.LP.
80. PO.S.2.LP® 4.5.13 Rename from PO.S.2® LP to PO.S.2.LP® .
130)
1. Modify the description from the to a.
81. PO.S.2.GS 4.5.13 2. Modify the description by adding “a”.
130)
3. Rename from PO.S.2GS to PO.S.2.GS.
130)
83. PO.S.5.GS® 4.5.13 Rename from PO.S.5® GS to PO.S.5.GS® .
130)
130)
85. PO.S.6.GS® 4.5.13 Rename from PO.S.6® GS to PO.S.6.GS® .
130)
Poly (PO) Layout Rules (Mask ID: 1. Modify the description from 2 to two.
86. PO.S.10 4.5.13
130) 2. Modify the description from space to spaces.
87. PO.S.15 4.5.13 Modify the description from interact to interacts.
130)
1. Add Label U.
88. PO.S.18.GS® 4.5.13 2. Add one figure.
130)
3. Rename from PO.S.18® GS to PO.S.18.GS® .
89. PO.L.1 4.5.13 Modify the description from nearest to the nearest.
130)
1. Remove “(CB sizing 2) for high speed/RF products”.
90. PO.DN.2 4.5.13 2. Modify the description from while to when.
130)
3. Add the before width and is before ≥.
91. PO.DN.3 4.5.13 Add TCDDMY into the exception.
130)
Poly (PO) Layout Rules (Mask ID: 1. Modify the description by adding “the“ and “with”.
92. PO.DN.4® 4.5.13
130) 2. Modify the description by adding “is as follows”.
93. PO.DN.5® 4.5.13
94. PO.DN.6® 4.5.13
95. PO.DN.7® 4.5.13
Poly (PO) Layout Rules (Mask ID: 2. Modify the description by adding “is as follows”.
96. PO.DN.8® 4.5.13
130) 3. Correct the typo from unaslicided to unsalicided.
4. Correct the typo from OD local density to PO local density.
97. PO.DN.9® 4.5.13
3. Correct the typo from unaslicided to unsalicided.
1. Modify the description from It to Floating gate and from is
to are.
98. PO.R.8 4.5.13 2. Modify the description by deleting “for floating gate”
130)
3. Modify the description from connect to connected.
4. Modify the description by adding “is as follows”
99. PO.R.9 4.5.13 Add this rule.
130)
1. Modify the information for SENDMY (255;8) from OD
density to PO density.
Poly (PO) Layout Rules (Mask ID: 2. Add a table note and a figure about using POs with the
100. 4.5.13
130) same or similar channel length neighboring with a critical
device.
3. Refine the figures of PO.S.2.
1. Modify the definition of Silicided OD resistor from “{RH
AND OD} NOT RPO} AND RPDMY}” to “{RH AND OD}
NOT INTERACT RPO} AND RPDMY}” by adding
“INTERACT”.
101. 4.5.22 OD and Poly Resistor Layout Rules 2. Modify the definition of Silicided PO resistor from “{RH
AND PO} NOT RPO} AND RPDMY}” to “{RH AND PO}
NOT INTERACT RPO} AND RPDMY}” by adding
“INTERACT”.
3. Refine the unsilicided figures and add two silicided figures.
1. Modify the description grammar by adding “of”.
102. RES.R.1 4.5.22 OD and Poly Resistor Layout Rules 2. Add the exception of RHDMY1 (117;4) region for non-
precision usage.
103. RES.R.3 4.5.22 OD and Poly Resistor Layout Rules Remove one unnecessarily right-hand-side curved bracket, }.
104. RES.R.16g 4.5.22 OD and Poly Resistor Layout Rules Add this guideline.
Add this rule to prevent a NP OD resistor from misusing to
109. RES.R.21 4.5.22 OD and Poly Resistor Layout Rules
become a NW strap.
Add this rule to prevent a PP OD resistor from misusing to
110. RES.R.22 4.5.22 OD and Poly Resistor Layout Rules
become a PW strap.
1. Add this section to separate HVMOS_25 from HVMOS
(HVMOS_25 and HVMOS_18).
111. 4.5.23 HVMOS_25 Layout Rules 2. Copy the statement that HVMOS_25 is only allowed for
N45LP/N40LP.
3. Consolidate some rules from T-N40-CL-DR-020.
112. HVD_N25.W.1 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Rename the rule number from HVD_N.W.1 to HVD_N25.W.1.
113. HVD_N25.W.2 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Add this rule by being consolidated from T-N40-CL-DR-020.
114. HVD_N25.S.1 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Rename the rule number from HVD_N.S.1 to HVD_N25.S.1.
1. Add this rule by being consolidated from T-N40-CL-DR-
020.
2. Revise from “{CO INSIDE PO} space to HVD_N in PO
120. HVD_N25.S.7 4.5.23.1 HVD_N Layout Rules for HVMOS_25 end-cap direction” to “{CO INSIDE PO} space to {OD AND
HVD_N} in PO end-cap direction” and the rule spec from
0.28um to 0.52um w/o DRC change.
3. Revise Op. from Q to Q0 and update the figure.
121. HVD_N25.S.8 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Add this rule by being consolidated from T-N40-CL-DR-020.
Add this rule by moving and modifying CO.S.5.1 and relaxing
124. HVD_N25.S.11 4.5.23.1 HVD_N Layout Rules for HVMOS_25
the Op. from = to ≥.
125. HVD_N25.S.12 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Add this rule.
126. HVD_N25.EN.1 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Add this rule by being consolidated from T-N40-CL-DR-020.
Rename the rule number from HVD_N.EX.1 to
127. HVD_N25.EX.1 4.5.23.1 HVD_N Layout Rules for HVMOS_25
HVD_N25.EX.1.
128. HVD_N25.O.1 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Rename the rule number from HVD_N.O.1 to HVD_N25.O.1.
Rename the rule number from HVD_N.L.1 to HVD_N25.L.1.
129. HVD_N25.L.1 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Add the description of "exact shrinkable dimension is 0.88um
for N40".
130. HVD_N25.A.1 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Rename the rule number from HVD_N.A.1 to HVD_N25.A.1.
131. HVD_N25.A.2 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Rename the rule number from HVD_N.A.2 to HVD_N25.A.2.
132. HVD_N25.R.1 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Rename the rule number from HVD_N.R.1 to HVD_N25.R.1.
Rename the rule number from HVD_N.R.5® U to
136. HVD_N25.R.5® U 4.5.23.1 HVD_N Layout Rules for HVMOS_25
HVD_N25.R.5® U.
137. HVD_N25.R.7 4.5.23.1 HVD_N Layout Rules for HVMOS_25 Add this rule by being consolidated from T-N40-CL-DR-020.
138. HVD_P25.W.1 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Rename the rule number from HVD_P.W.1 to HVD_P25.W.1.
139. HVD_P25.W.2 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Add this rule by being consolidated from T-N40-CL-DR-020.
140. HVD_P25.S.1 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Rename the rule number from HVD_P.S.1 to HVD_P25.S.1.
144. HVD_P25.S.6 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Add this rule by being consolidated from T-N40-CL-DR-020.
020.
2. Revise from “{CO INSIDE PO} space to HVD_P in PO
145. HVD_P25.S.7 4.5.23.2 HVD_P Layout Rules for HVMOS_25 end-cap direction” to “{CO INSIDE PO} space to {OD AND
HVD_P} in PO end-cap direction” and the rule spec from
Add this rule by moving and modifying CO.S.5.1 and relaxing
149. HVD_P25.S.11 4.5.23.2 HVD_P Layout Rules for HVMOS_25
the Op. from = to ≥.
150. HVD_P25.S.12 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Add this rule.
Rename the rule number from HVD_P.EX.1 to
151. HVD_P25.EX.1 4.5.23.2 HVD_P Layout Rules for HVMOS_25
HVD_P25.EX.1.
Rename the rule number from HVD_P.EN.1 to
152. HVD_P25.EN.1 4.5.23.2 HVD_P Layout Rules for HVMOS_25
HVD_P25.EN.1.
Rename the rule number from HVD_P.EN.2 to
153. HVD_P25.EN.2 4.5.23.2 HVD_P Layout Rules for HVMOS_25
HVD_P25.EN.2.
154. HVD_P25.EN.3 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Add this rule by being consolidated from T-N40-CL-DR-020.
156. HVD_P25.O.1 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Rename the rule number from HVD_P.O.1 to HVD_P25.O.1.
1. Rename the rule number from HVD_P.L.1 to
HVD_P25.L.1.
157. HVD_P25.L.1 4.5.23.2 HVD_P Layout Rules for HVMOS_25 2. Remove “with from “{GATE INTERACT with HVD_P}”.
3. Add the description of "exact shrinkable dimension is
0.66um for N40".
158. HVD_P25.A.1 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Rename the rule number from HVD_P.A.1 to HVD_P25.A.1.
159. HVD_P25.A.2 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Rename the rule number from HVD_P.A.2 to HVD_P25.A.2.
160. HVD_P25.R.1 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Rename the rule number from HVD_P.R.1 to HVD_P25.R.1.
1. Rename the rule number from HVD_P.R.4 to
163. HVD_P25.R.4 4.5.23.2 HVD_P Layout Rules for HVMOS_25 HVD_P25.R.4.
2. Add “the” before “same”.
Rename the rule number from HVD_P.R.5® U to
164. HVD_P25.R.5® U 4.5.23.2 HVD_P Layout Rules for HVMOS_25
HVD_P25.R.5® U.
166. HVD_P25.R.8 4.5.23.2 HVD_P Layout Rules for HVMOS_25 Add this rule by being consolidated from T-N40-CL-DR-020.
1. Add this section to separate HVMOS_18 from HVMOS
(HVMOS_25 and HVMOS_18) by consolidating T-N40-CL-
168. 4.5.24 HVMOS_18 Layout Rules DR-020, HVMOS_18 DRM.
2. Add the statement that HVMOS_18 is only allowed for
N40LP by consolidating T-N40-CL-DR-020.
1. Add this section for N40LP HVNMOS_18 by consolidating
T-N40-CL-DR-020, HVMOS_18 DRM.
169. 4.5.24.1 HVD_N Layout Rules for HVMOS_18
2. Add the statement that HVNMOS_18 is only allowed for
020.
2. Revise from “{CO INSIDE PO} space to HVD_N in PO
178. HVD_N18.S.7 4.5.24.1 HVD_N Layout Rules for HVMOS_18 end-cap direction” to “{CO INSIDE PO} space to {OD AND
HVD_N} in PO end-cap direction” and the rule spec from
183. HVD_N18.S.12 4.5.24.1 HVD_N Layout Rules for HVMOS_18 Add this rule.
184. HVD_N18.EN.1 4.5.24.1 HVD_N Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
185. HVD_N18.EX.1 4.5.24.1 HVD_N Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
186. HVD_N18.O.1 4.5.24.1 HVD_N Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
187. HVD_N18.L.1 4.5.24.1 HVD_N Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
188. HVD_N18.A.1 4.5.24.1 HVD_N Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
189. HVD_N18.A.2 4.5.24.1 HVD_N Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
194. HVD_N18.R.5® U 4.5.24.1 HVD_N Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
1. Add this section for N40LP HVPMOS_18 by consolidating
T-N40-CL-DR-020, HVMOS_18 DRM.
196. 4.5.24.2 HVD_P Layout Rules for HVMOS_18
2. Add the statement that HVPMOS_18 is only allowed for
020.
2. Revise from “{CO INSIDE PO} space to HVD_P in PO
204. HVD_P18.S.7 4.5.24.2 HVD_P Layout Rules for HVMOS_18 end-cap direction” to “{CO INSIDE PO} space to {OD AND
HVD_P} in PO end-cap direction” and the rule spec from
209. HVD_P18.S.12 4.5.24.2 HVD_P Layout Rules for HVMOS_18 Add this rule.
210. HVD_P18.EX.1 4.5.24.2 HVD_P Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
215. HVD_P18.O.1 4.5.24.2 HVD_P Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
216. HVD_P18.L.1 4.5.24.2 HVD_P Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
217. HVD_P18.A.1 4.5.24.2 HVD_P Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
218. HVD_P18.A.2 4.5.24.2 HVD_P Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
223. HVD_P18.R.5® U 4.5.24.2 HVD_P Layout Rules for HVMOS_18 Add this rule by being consolidated from T-N40-CL-DR-020.
HVMOS Guard-Ring Rules and
1. Add this section from T-N40-CL-DR-020.
227. 4.5.25 Guidelines for HVMOS_25 and
2. The section should be also applied for HVMOS_25.
HVMOS_18
228. 4.5.26 MOS Varactor Layout Rules (VAR) Modify the description grammar and “GS” by “N40G (=
N45GS).
229. VAR.A.1 4.5.26 MOS Varactor Layout Rules (VAR) Add one right-hand-side parenthesis, ), after OD2}.
Contact (CO) Layout Rules (Mask ID:
230. CO.S.3® 4.5.27 Modify the description by adding a full stop.
156)
Contact (CO) Layout Rules (Mask ID: Remove this rule by moving CO.S.5.1 to HVD_N25.S.11 &
231. CO.S.5.1 4.5.27
156) HVD_P25.S.11 and relaxing the Op. from = to ≥.
1. Modify the description from Fully to Full.
Contact (CO) Layout Rules (Mask ID:
232. CO.S.7® 4.5.27 2. Remove “Channel length  0.05um”.
156)
3. Exclude SDI region.
Metal-1 (M1) Layout Rules (Mask ID: Align CAD layer usage to rename "SRAM (186;0)" to
233. 4.5.28
360) "SRAMDMY;0 (186;0)" in this section.
Metal-1 (M1) Layout Rules (Mask ID: 1. Modify the description from 2 to two.
234. M1.S.5 4.5.28
360) 2. Modify the description from space to spaces.
235. M1.S.7® 4.5.28 Remove this recommendation for mask ESD concern.
360)
236. M1.S.9 4.5.28 Modify the description grammar.
360)
Metal-1 (M1) Layout Rules (Mask ID: 1. Add  between metal width and 0.11um.
237. M1.EN.5® 4.5.28
360) 2. Add  into Op.
238. M1.A.1® 4.5.28 Add  in Op.
360)
239. M1.A.2 4.5.28 Modify the label from P to O.
360)
240. M1.A.3 4.5.28 Modify the label from Q to Q1.
360)
241. M1.DN.6 4.5.28 Simplify the rule description.
360)
Metal-1 (M1) Layout Rules (Mask ID: 1. This recommendation only checks IP edge.
242. M1.DN.6® 4.5.28
360) 2. Simplify the rule description.
243. M1.R.2 4.5.28 Modify the rule description to meet the DRC coding.
360)
1. Add “No 5V device offering for FEOL, except HVMOS” into
the table note.
244. 4.5.28 2. Modify the grammar in the table note.
360)
3. Modify the DRC method about M1.S.1.1, M1.S.8,
M1.S.8.1, M1.S.8.2, and M1.S.9 to meet the DRC coding.
245. VIAx.R.11 4.5.29 Add three left-hand-side parentheses, (.
379, 373, 374, 375, 376, 377)
246. VIAx.R.13 4.5.29 Add this rule.
379, 373, 374, 375, 376, 377)
VIAx Layout Rules (Mask ID: 378, Add “No 5V device offering for FEOL, except HVMOS” into
247. 4.5.29
379, 373, 374, 375, 376, 377) the table note.
248. Mx Layout Rules (Mask ID: 380, 381, 1. Modify the description from 2 to two.
Mx.S.5 4.5.30
384, 385, 386, 387, 388) 2. Modify the description from space to spaces.
1. Modify the description from 2 to two and space to spaces.
3. Refine condition 2 by adding “i.e. either one of the two line-
end vias follows the rule, and DRC will treat the other one
249. Mx.S.5.1 4.5.30 does not violate this rule”.
384, 385, 386, 387, 388)
4. Add one figure to explain condition 2.
5. Correct the typo from “conbinations” to “combinations”.
6. Correct the typo in the figure for Mx enclosure Vx-1 of S1 =
0.115um from 0.350um to 0.035um.
250. Mx.S.7® 4.5.30 Remove this recommendation for mask ESD concern.
384, 385, 386, 387, 388)
251. Mx.S.9 4.5.30 Modify the description grammar.
384, 385, 386, 387, 388)
Mx Layout Rules (Mask ID: 380, 381, 1. Refine the rule description.
252. Mx.A.1 4.5.30
384, 385, 386, 387, 388) 2. Modify the label from K to O.
Mx Layout Rules (Mask ID: 380, 381, 1. Add ≥ in Op.
253. Mx.A.1® 4.5.30
Mx Layout Rules (Mask ID: 380, 381, 1. Refine the rule description.
254. Mx.A.2 4.5.30
255. Mx.A.3 4.5.30 Modify the label from L to Q1.
384, 385, 386, 387, 388)
256. Mx.DN.5 4.5.30 Modify the description from top2 to top two.
384, 385, 386, 387, 388)
257. Mx.DN.6 4.5.30 Simplify the rule description.
384, 385, 386, 387, 388)
Mx Layout Rules (Mask ID: 380, 381, 1. This recommendation only checks IP edge.
258. Mx.DN.6® 4.5.30
384, 385, 386, 387, 388) 2. Simplify the rule description.
259. Mx.DN.7 4.5.30 Modify the description grammar.
384, 385, 386, 387, 388)
Mx Layout Rules (Mask ID: 380, 381, 1. This recommendation only checks IP edge.
260. Mx.DN.7® 4.5.30
384, 385, 386, 387, 388) 2. Modify the description grammar.
261. Mx.R.3 4.5.30 Modify the rule description to meet the DRC coding.
384, 385, 386, 387, 388)
1. Add “No 5V device offering for FEOL, except HVMOS” into
the table note.
262. 4.5.30 2. Modify the grammar in the table note.
384, 385, 386, 387, 388)
3. Modify the DRC method about Mx.S.1.1, Mx.S.8, Mx.S.8.1,
Mx.S.8.2, and Mx.S.9 to meet the DRC coding.
Remove VIAx.W.6 in the rule description from this rule (add
263. LOWMEDN.R.4 4.5.31 LOWMEDN Layout Rules
the checking tolerance as 0.005um into VIAx.W.6).
264. LOWMEDN.R.5 4.5.31 LOWMEDN Layout Rules Add a remark about inductor simulation.
1. Add another spec as 0.075um.
2. Copy the checking tolerance as 0.005um for width =
0.070um from LOWMEDN.R.4.
265. VIAx.W.6 4.5.31 LOWMEDN Layout Rules
3. Add another checking tolerance as 0.010um for width =
0.075um.
4. Add “[INSIDE LOWMEDN]”.
VIAy Layout Rules (Mask ID: 379, Exclude SEALRING_ALL (162;2) region to align the current
266. VIAy.W.1 4.5.32
373, 374, 375, 376, 377, 372, 37A) DRC coding.
VIAy Layout Rules (Mask ID: 379,
267. VIAy.R.13 4.5.32 Add this rule.
373, 374, 375, 376, 377, 372, 37A)
My Layout Rules (Mask ID: Second
268. My.S.6® 4.5.33 Remove this recommendation for mask ESD concern.
and Top Metal (381, 384, 385, 386,
387, 388, 389, 38A))
269. My.DN.4 4.5.33 Add one right-hand-side parenthesis, ).
and Top Metal (381, 384, 385, 386,
387, 388, 389, 38A))
270. My.R.3 4.5.33 Modify the rule description to meet the DRC coding.
and Top Metal (381, 384, 385, 386,
387, 388, 389, 38A))
271. 4.5.33 Modify the grammar in the table note.
and Top Metal (381, 384, 385, 386,
387, 388, 389, 38A))
Top VIAz Layout Rules (Mask ID:
Exclude SEALRING_ALL (162;2) region to align the current
272. VIAz.W.1 4.5.34 379, 373, 374, 375, 376, 377, 372,
DRC coding.
37A)
Top VIAz Layout Rules (Mask ID:
273. VIAz.R.13 4.5.34 379, 373, 374, 375, 376, 377, 372, Add this rule.
37A)
Top Mz Layout Rules (Mask ID: 381,
274. Mz.DN.4 4.5.35 Add one right-hand-side parenthesis, ).
384, 385, 386, 387, 388, 389, 38A)
275. Mz.R.2 4.5.35 Modify the rule description to meet the DRC coding.
384, 385, 386, 387, 388, 389, 38A)
384, 385, 386, 387, 388, 389, 38A)
Top VIAr Layout Rules (Mask ID: 376, Exclude SEALRING_ALL (162;2) region to align the current
277. VIAr.W.1 4.5.36
377, 372, 37A) DRC coding.
Top VIAr Layout Rules (Mask ID: 376,
278. VIAr.R.13 4.5.36 Add this rule.
377, 372, 37A)
Top Mr Layout Rules (Mask ID: 387,
279. Mr.DN.4 4.5.37 Add one right-hand-side parenthesis, ).
388, 389, 38A)
280. Mr.R.2 4.5.37 Modify the rule description to meet the DRC coding.
388, 389, 38A)
388, 389, 38A)
1. Modify CB CAD layer from 43 to 76.
282. 4.5.38 RV Layout Rules (Mask ID: 306) 2. Refine the description about RV for EM and ESD
protection.
Modify that RV 2umx2um is only allowed in polyimide
283. RV.W.1 4.5.38 RV Layout Rules (Mask ID: 306)
process.
Add “SIZING 22um” to align the current DRC coding and
284. RV.R.1 4.5.38 RV Layout Rules (Mask ID: 306)
IND.R.8.
Al Redistributional Layer (AP RDL) Modify the checking method by adding “by {{AP/AP-MD
285. AP.W.2 4.5.39
Layout Rules (Mask ID: 309) SIZING 0.995um} SIZING -0.995um}”, since AP.S.1 waives
space in the sample polygon.
Al Redistributional Layer (AP RDL)
286. AP.W.5 4.5.39 Add this rule for 28KÅ AP.
Layout Rules (Mask ID: 309)
287. AP.S.1 4.5.39 Waive space in the sample polygon.
288. 4.5.40 Via Layout Recommendations Modify the description grammar.
289. MOM.DN.1® 4.5.41 MOM Layout Rules Add this recommendation.
290. 4.5.41 MOM Layout Rules
2. Modify the content since FMOM is offered.
2. Add the definition of finger length.
RTMOM (Rotated Metal Oxide Metal)
291. 4.5.41.1 3. PDK offered MOM also supports dummy metal insertion in
PDK Capacitor Guidelines
unused M1&Mx layers by using parameter “dmflag=1” to
turn on dummy metal and “dmflag=0” to trun-off.
Top VIAu Layout Rules (Mask ID:
292. 4.5.42 Remove Mu.
373, 374, 375, 376, 377, 372, 37A)
293. Mu.DN.2 4.5.43 Mu (Ultra Thick Metal) Layout Rules Modify the description grammar.
1. Remove FW, since metal fuse is not available for
294. Mu.DN.2.1 4.5.43 Mu (Ultra Thick Metal) Layout Rules N45/N40.
295. Mu.R.5 4.5.43 Mu (Ultra Thick Metal) Layout Rules Modify the rule description to meet the DRC coding.
2. Add a note to refer to LOWMEDN rules for the usage of
INDDMY Layer Identified Inductor
296. 4.5.44 inductor with protection ring.
Layout Rules
3. Add a table note for inductor PDK (already added Dummy
OD/PO).
297. IND.R.2 4.5.44 Modify the description from 4 to four.
Layout Rules
Layout Rules
Layout Rules
300. IND.DN.1 4.5.44 Modify the description from “in” to “on a”.
Layout Rules
INDDMY Layer Identified Inductor Modify the description from while the to during and from while
301. IND.DN.4 4.5.44
Layout Rules to when.
INDDMY Layer Identified Inductor Modify the description from while the to during and from while
302. IND.DN.4.1 4.5.44
Layout Rules to when.
303. IND.DN.5U 4.5.44 Modify the description by adding a full stop.
Layout Rules
304. IND.DN.8® 4.5.44 Add this recommendation and table note 9.
Layout Rules
305. IND.DN.9® 4.5.44 Add this recommendation and table note 9.
Layout Rules
306. IND.R.15gU 4.5.44 Add this guideline.
Layout Rules
Modify the contents about dummy OD/PO patterns insertion
307. 4.5.45.2.1 Introduction to PDK T-line
into INDDMY regions. (Table note 5)
1. Revise from “Any violations must inform TSMC to review.”
to “Any violation is not allowed.”
2. Remove N40LP-ULP offering.
3. Modify the information about the mix run of N40G and
N40GL.
4. Add one warning message about SRAM design. (1) TSMC
SRAM cells can’t be changed. (2) Customized SRAM cells
308. 4.5.46 SRAM Rules
must comply with the logic rules and use logic SPICE
model.
5. Add one warning information: “You can’t design SRAM
layout just by complying with the following the rules. The
SRAM rules in this document are used to prevent
unexpected layout errors during macro or chip
implementation, but not used for SRAM design.”
309. SRAM.BTC.S.1 4.5.46 SRAM Rules Add this rule.
Revise this rule: TSMC SRAM array is forbidden to be
312. SRAM.R.1U 4.5.46 SRAM Rules
changed .
Revise this rule for Customer-designed SRAM cell designed
by logic rules.
U
314. SRAM.R.3 4.5.46 SRAM Rules Remove this rule due to being replaced SRAM.WARN.1.
315. SRAM.R.6U 4.5.46 SRAM Rules Revise this rule by referring to section 1.2.
Revise this rule since (1) TSMC SRAM can’t be changed (2)
duplicate of SRAM.R.12.
Rename from SRAMDMY (186;5)/ SRAMDMY (186;4) to
317. SRAM.R.12 4.5.46 SRAM Rules
SRAMDMY;5 (186;5)/ SRAMDMY;4 (186;4).
Revise this rule by (1) removing SRAM array layout since it
318. SRAM.R.16U 4.5.46 SRAM Rules can’t be changed, (2) adding IP tage in front of name, and (3)
referring to section 1.2.
Modify this rule for SRM;0 (50;0) to cover NMOS gate and
319. SRAM.R.26 4.5.46 SRAM Rules
PMOS gate at the same time.
320. SRAM.R.30 U
4.5.46 SRAM Rules Replace “library” by “the same SRAM”.
321. SRAM.R.42 4.5.46 SRAM Rules Add this rule.
Align the rule description with that in chapter 4 by adding “and
322. PO.R.7 4.5.46 SRAM Rules
RAM1TDMY (160;0)”.
323. SRAM.R.8gU 4.5.46 SRAM Rules Remove this guideline since TSMC SRAM can’t be changed.
324. SRAM.WARN.1 4.5.46 SRAM Rules Add this rule.
325. SRAM.WARN.2 4.5.46 SRAM Rules Add this rule.
Revise the statement about NPreDOSRM: (1) TSMC SRAM
326. 4.5.47 NPreDOSRM (50;21) Layout Rules can’t be changed. (2) NPreDOSRM can’t be designed by logic
rules.
1. Rename the section title from “SRAM CO2 Layout Rule
(100;0) for Embedded DRAM (eDRAM) Process” to
SRAM CO2 (100;0) Layout Rule for “SRAM CO2 (100;0) Layout Rule for Embedded DRAM
327. 4.5.49
Embedded DRAM (eDRAM) Process (eDRAM) Process”.
3. Add “designed by logic rules” in back of SRAM.
SRAM CO2 (100;0) Layout Rule for
328. CO2.R.1 4.5.49 Modify the description by adding “the”.
1. Add “CO2 (100;0) must exist inside BTC”.
2. Modify M1 by {M1 AND SRM}.
3. Modify “without interact M1” by “without interacting with
M1”.
SRAM CO2 (100;0) Layout Rule for
329. CO2.R.2 4.5.49 4. Modify “The area of CO2 not covered by M1” by “The area
of {CO2 NOT M1}”.
5. Add “in SRM_LV (80;15). In the other SRAMs, CO2 must
be fully inside M1 (the area of {CO2 NOT M1} should be
equal to 0um2)”.
SRAM CO2 (100;0) Layout Rule for Modify the description grammar, add “designed by logic
330. CO2.R.3U 4.5.49
Embedded DRAM (eDRAM) Process rules”, and remove “R&D and”.
331. 4.5.50 ROM Rules Add “ROM is a tape-out required layer for N40G”.
332. ROM.R.4 4.5.50 ROM Rules Add this rule for SPICE accuracy.
333. 4.5.50 ROM Rules Update the figure.
1. Add “A protection OD means diode, STRAP, source, drain,
Antenna Effect Prevention (A) Layout and so on.” to meet DRC coding.
334. 4.5.51
Rules 2. Modify diode by OD in the table notes.
3. Modify the typo from increamnetal to incremental.
Antenna Effect Prevention (A) Layout
335. A.R.0 4.5.51 Modify diode by protection OD to meet DRC coding.
Rules
336. A.R.7 4.5.51 Modify diode by OD to meet DRC coding.
Rules
Rules
338. A.R.8.1 4.5.51 Modify diode by OD to meet DRC coding.
Rules
Rules
Rules
341. 4.5.51.3 CO Via1 – Via9 Antenna Ratio Correct a typo from VIA8 to VIA9.
342. LOGO.S.1 4.5.52 Product Labels and Logo Rules Also exclude seal ring and CSR regions.
343. 4.5.53 Seal Ring Overview Modify the description grammar.
Modify the description grammar and revise PM from optional
344. 4.5.53.1 Guidelines for Placing Seal Ring
to V for Flip Chip required.
Metallization Options Using Mu as the
345. 4.5.53.1.4 Modify the description by adding “the”.
Top Metal
Chip Corner Stress Relief (CSR)
346. CSR.R.1 4.5.53.2 Modify the description from 4 to four and adding “a”
Pattern
Chip Corner Stress Relief (CSR) 1. Modify “CB or CBD” by adding RV.
347. CSR.R.2 4.5.53.2
Pattern 2. Modify the description by adding “an”
1. Modify the description from must to musts and add “a”
Chip Corner Stress Relief (CSR)
348. CSR.R.4 4.5.53.2 before seal ring.
Pattern
2. Add “DRC does not check CSR and BiB related rules w/o
those dummy layers.”
Chip Corner Stress Relief (CSR) 1. Modify the description grammar in the remark.
349. 4.5.53.2
Pattern 2. Add “on-silicon dimension” into the remark.
350. 4.5.53.3 Box in Box (BiB) Pattern inside CSR Modify the description grammar.
2. Remove the information about 6um-wide assembly
351. 4.5.53.4 Seal Ring Layout Rules
isolation just for reference only and depending on the
capability of assembly house.
352. 4.5.53.4.1 Seal Ring Wall Layout Rules Modify the description grammar.
2. Add “Each M1~AP pattern in assembly isolation region
353. SR.S.1 4.5.53.4.1 Seal Ring Wall Layout Rules
must be connecting to inner seal ring” to meet DRC
coding.
354. SR.R.1 4.5.53.4.1 Seal Ring Wall Layout Rules 2. Add “DRC does not check seal ring related rules w/o those
layers.”
355. VIAx.S.9 4.5.53.4.1 Seal Ring Wall Layout Rules Add this rule to prevent misusing.
356. VIAy.S.8 4.5.53.4.1 Seal Ring Wall Layout Rules Add this rule to prevent misusing.
357. VIAz.S.8 4.5.53.4.1 Seal Ring Wall Layout Rules Add this rule to prevent misusing.
358. VIAr.S.8 4.5.53.4.1 Seal Ring Wall Layout Rules Add this rule to prevent misusing.
359. VIAu.S.8 4.5.53.4.1 Seal Ring Wall Layout Rules Add this rule to prevent misusing.
360. CB.W.3 4.5.53.4.1 Seal Ring Wall Layout Rules Add RV and (Tolerance 0.01 μm)..
1. Correct the typo from Enclousure to Enclosure.
361. CB.EN.2 4.5.53.4.1 Seal Ring Wall Layout Rules 2. Add RV and (Tolerance 0.01 μm).
3. Add “in inner seal ring”.
2. Modify the rule number from SR.R.4U to SR.R.4 (DRC
362. SR.R.4 4.5.53.4.1 Seal Ring Wall Layout Rules
checked).
3. Add DRC checking method.
1. Add “TSMC will use LOP to remove {CB2_WB OR
363. 4.5.53.4.1 Seal Ring Wall Layout Rules CB2_FC} at SLDB and outer seal ring regions.”
2. Add post-LOP figures.
2. Remove the following masks from seal ring digital tone
table.
DMV in Assembly Isolation Layout  CAPACITOR-MET-TOP (182)
364. 4.5.53.4.2
Rules  CAPACITOR-MET-BOTTOM (183)
 MG-NM-HK-ETCH (13C)
 MG-PM-HK-ETCH (13D)
 MG-ON-HK-ETCH (13E)
CDU (Critical Dimension Uniformity)
365. 4.5.53.4.3 Modify the description grammar.
2. Add “TSMC will use LOP to remove {CB2_WB OR
366. 4.5.53.5 Scribe Line Dummy Bar Layout Rules
CB2_FC} at SLDB and outer seal ring regions.”
3. Add post-LOP figures.
367. CB.W.4 4.5.53.5 Scribe Line Dummy Bar Layout Rules Add RV and (Tolerance 0.01 μm).
1. Correct the typo from Enclousure to Enclosure.
368. CB.EN.3 4.5.53.5 Scribe Line Dummy Bar Layout Rules
2. Add RV and (Tolerance 0.01 μm).
Layout Rules for the WPE (Well
369. PO.S.14.GSm® 5.1 Rename from PO.S.14mGS® to PO.S.14.GSm® .
Proximity Effect)
370. PO.S.14.LPm® 5.1 Rename from PO.S.14mLP® to PO.S.14.LPm® .
Proximity Effect)
371. PO.EN.1.GSm® 5.1 Rename from PO.EN.1mGS® to PO.EN.1.GSm® .
Proximity Effect)
372. PO.EN.1.LPm® 5.1 Rename from PO.EN.1mLP® to PO.EN.1.LPm® .
Proximity Effect)
Proximity Effect)
Proximity Effect)
Proximity Effect)
Proximity Effect)
Layout Rules for the WPE (Well 1. Modify the description grammar.
377. 5.1
Proximity Effect) 2. Add N45GS=N40G.
378. 5.2.1 What is LOD? Modify the description grammar.
How to have a precise LOD
379. 5.2.2 Modify the description grammar.
Simulation
380. 5.3.3 How to reduce the differences 1. Modify DOD to OD.
between pre-simulation and post- 2. Refine the description of Standard cell array by adding
simulation OD/PO in front of FILLER cells and updating from DOD to
dummy OD.
3. Modify DOD to OD in Figure 5.3.3.1.
4. Modify Figure 5.3.3.2 by on four sides OD/PO FILLER cells
and dummy OD.
How to reduce the differences
381. 5.4.3 between pre-simulation and post- Modify DPO to SR_DPO.
simulation on N40G circuit?
382. 5.5.1 What is d-CESL effect? Modify the description from has to have.
383. 6 N40LP/LPG Design Information Modify the chapter title by adding LPG.
384. PO.S.2.LP.S 6.1.2 Non-shrinkable Rules Rename from PO.S.2LP to PO.S.2.LP.S.
OD25_33.W.1.LP
385. 6.1.2 Non-shrinkable Rules Rename from OD25_33.W.1LP to OD25_33.W.1.LP.S.
.S
OD25_33.W.2.LP
386. 6.1.2 Non-shrinkable Rules Rename from OD25_33.W.2LP to OD25_33.W.2.LP.S.
.S
Add this rule by copying that in chapter 4, and rename from
387. HVD_N25.W.2.S 6.1.2 Non-shrinkable Rules
HVD_N25.W.2 to HVD_N25.W.2.S.
388. HVD_N25.S.11.S 6.1.2 Non-shrinkable Rules
HVD_N25.S.11 to HVD_N25.S.11.S.
389. HVD_N25.O.1.S 6.1.2 Non-shrinkable Rules
HVD_N25.O.1 to HVD_N25.O.1.S.
390. HVD_N25.L.1.S 6.1.2 Non-shrinkable Rules
HVD_N25.L.1 to HVD_N25.L.1.S.
391. HVD_P25.W.2.S 6.1.2 Non-shrinkable Rules
HVD_P25.W.2 to HVD_P25.W.2.S.
392. HVD_P25.S.11.S 6.1.2 Non-shrinkable Rules
HVD_P25.S.11 to HVD_P25.S.11.S.
393. HVD_P25.O.1.S 6.1.2 Non-shrinkable Rules
HVD_P25.O.1 to HVD_P25.O.1.S.
394. HVD_P25.L.1.S 6.1.2 Non-shrinkable Rules
HVD_P25.L.1 to HVD_P25.L.1.S.
Stress Migration and Wide Metal
Align the rule description with that in chapter 4 to add “if no
395. OD.L.1.S 6.1.3 Spacing Rules Adjustment (Rule
CO in M region”, and rename from OD.L.1 to OD.L.1.S.
Relaxing)
Stress Migration and Wide Metal Align the rule description with that in chapter 4 to add “and
396. OD.L.2.S 6.1.3 Spacing Rules Adjustment (Rule {MOMDMY(155;21) SIZING 1.2um}”, and rename from
Relaxing) OD.L.2 to OD.L.2.S.
397. PO.L.1.S 6.1.3 Spacing Rules Adjustment (Rule Rename from PO.L.1 to PO.L.1.S.
Relaxing)
398. M1.W.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from M1.W.3 to M1.W.3.S.
Relaxing)
399. M1.S.2.S 6.1.3 Spacing Rules Adjustment (Rule Rename from M1.S.2 to M1.S.2.S.
Relaxing)
400. M1.S.2.1.S 6.1.3 Spacing Rules Adjustment (Rule Rename from M1.S.2.1 to M1.S.2.1.S.
Relaxing)
Relaxing)
Relaxing)
Relaxing)
Relaxing)
Relaxing)
Relaxing)
407. M1.S.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from M1.S.3 to M1.S.3.S.
Relaxing)
Align the rule description with that in chapter 4, and rename
408. VIAx.R.2.S 6.1.3 Spacing Rules Adjustment (Rule
from VIAx.R.2 to VIAx.R.2.S.
Relaxing)
409. VIAx.R.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from VIAx.R.3 to VIAx.R.3.S.
Relaxing)
Relaxing)
Relaxing)
Relaxing)
413. VIAx.R.11.S 6.1.3 Spacing Rules Adjustment (Rule
from VIAx.R.11 to VIAx.R.11.S.
Relaxing)
414. Mx.W.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mx.W.3 to Mx.W.3.S.
Relaxing)
415. Mx.S.2.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mx.S.2 to Mx.S.2.S.
Relaxing)
416. Mx.S.2.1.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mx.S.2.1 to Mx.S.2.1.S.
Relaxing)
Relaxing)
Relaxing)
Relaxing)
Relaxing)
Relaxing)
Relaxing)
423. Mx.S.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mx.S.3 to M1xS.3.S.
Relaxing)
424. VIAy.R.2.S 6.1.3 Spacing Rules Adjustment (Rule
from VIAy.R.2 to VIAy.R.2.S.
Relaxing)
425. VIAy.R.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from VIAy.R.3 to VIAy.R.3.S.
Relaxing)
Relaxing)
Relaxing)
Relaxing)
Relaxing)
430. My.W.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from My.W.3 to My.W.3.S.
Relaxing)
431. My.S.2.S 6.1.3 Spacing Rules Adjustment (Rule Rename from My.S.2 to My.S.2.S.
Relaxing)
432. My.S.2.1.S 6.1.3 Spacing Rules Adjustment (Rule Rename from My.S.2.1 to My.S.2.1.S.
Relaxing)
Relaxing)
Relaxing)
435. VIAz.R.2.S 6.1.3 Spacing Rules Adjustment (Rule Rename from VIAz.R.2 to VIAz.R.2.S.
Relaxing)
436. VIAz.R.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from VIAz.R.3 to VIAz.R.3.S.
Relaxing)
437. Mz.W.2.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mz.W.2 to Mz.W.2.S.
Relaxing)
438. Mz.S.2.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mz.S.2 to Mz.S.2.S.
Relaxing)
439. Mz.S.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mz.S.3 to Mz.S.3.S.
Relaxing)
440. VIAr.R.2.S 6.1.3 Spacing Rules Adjustment (Rule Rename from VIAr.R.2 to VIAr.R.2.S.
Relaxing)
441. VIAr.R.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from VIAr.R.3 to VIAr.R.3.S.
Relaxing)
442. Mr.W.2.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mr.W.2 to Mr.W.2.S.
Relaxing)
443. Mr.S.2.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mr.S.2 to Mr.S.2.S.
Relaxing)
444. Mr.S.3.S 6.1.3 Spacing Rules Adjustment (Rule Rename from Mr.S.3 to Mr.S.3.S.
Relaxing)
445. 6.1.4 Pad Rule for Wire Bond Correct the DRM title and add “the”.
446. 6.1.5 Flip Chip Bump Rules Add two lead-free (LF) flip chip DRMs.
1. Modify the description about 90% scaling.
2. Modify the information about the embedded scaling factor,
How to design for CLN40LP/LPG
447. 6.2.1 0.9, for SPICE and RC extraction.
shrink technology
3. Add the information about PDK.
4. Add the information about non-shrinkable rules.
How to prepare a new design of
448. 6.2.2 Add Figure 6.2.2.1.
CLN40LP/LPG
2. Modify IP_MIG by LP_IP_MIG and the CAD layer from
CLN45LP/LPG Design Migration to 63:45 to 63;45.
449. 6.2.3
CLN40LP/LPG Technology 3. Add “Modify size-up layout by swapping BJT with original
BJT. Layout fixing will be necessary due to BJT routing
reconnect and size-up induced DRC violation.”
Remove the description about RC delay impact and
450. 6.2.4.2 RC Extraction Guidelines
technology file with scaling factor 0.9.
Remove “However, figure 7.2.1 is not always valid for every
kind of MOS. Please contact TSMC to access the detail
451. AN.R.2mgU 7.2.1 General Guidelines
mismatch characterization report. Refer to the square root
1 WL
area model ( ) (Figure 7.2.1.1).”
452. AN.R.46mgU 7.2.1 General Guidelines Add (Figure 7.3.2.6) and one figure.
453. AN.R.47mgU 7.2.1 General Guidelines Add “Refer to figure 7.2.1.1” and one figure.
454. PO.S.6.1m® 7.2.2 MOS Recommendations Add (Figure 7.2.2.2) and one figure.
455. PO.EX.2mgU 7.2.2 MOS Recommendations Add (Figure 7.2.2.1).
456. AN.R.71mgU 7.2.2 MOS Recommendations Add this guideline and one figure.
1. Modify the description to meetTSMC’s utility, and add all
457. AN.R.3mU 7.3.1 General Rules and Guidelines related dummy layers.
2. Modify the figure by adding one layout.
Modify the description grammar from “Avoid to have” to
458. AN.R.4mgU 7.3.1 General Rules and Guidelines
“Avoid having”..
459. AN.R.7mU 7.3.2 Matching Rules and Guidelines Modify the description by adding “M1 is the most critical” and
remove (all metal layers need to be considered).
460. AN.R.9mgU 7.3.2 Matching Rules and Guidelines Modify the description by removing (Figure 7.3.9).
U Modify the description by adding “All the routing should be
461. AN.R.10mg 7.3.2 Matching Rules and Guidelines
symmetrical to avoid mismatch”.
Modify the description by removing “And the dimension of the
462. AN.R.12mgU 7.3.2 Matching Rules and Guidelines
protection diode should be the same”.
463. AN.R.46mg U
7.3.2 Matching Rules and Guidelines Modify the description by adding “(Figure 7.3.2.6)”.
464. AN.R.47mgU 7.3.2 Matching Rules and Guidelines Add “Refer to figure 7.2.1.1”.
465. AN.R.60mgU 7.3.2 Matching Rules and Guidelines Add this guideline and one figure.
Electrical Performance Rules and
474. AN.R.40mgU 7.3.3 Modify the rule number from AN.R.40.mgU to AN.R.40mgU.
Guidelines
475. AN.R.72mgU 7.3.3 Add this guideline and one figure.
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
Guidelines
481. AN.R.76mgU 7.3.3 Add this guideline.
Guidelines
1. Re-name the section title from “Dummy OD (DOD) Rules”
Dummy OD (DOD/SR_DOD) Rules to “Dummy OD (DOD/SR_DOD) Rules and Guidelines”.
482. 8.1
and Guidelines 2. Modify the description grammar.
3. Remove inductor (INDDMY).
483. DOD.S.10 8.1.1 DOD Layout Rules Remove this rule and modify the figure.
484. DOD.EN.2 8.1.1 DOD Layout Rules Remove this rule and modify the figure.
Remove “(CB sizing 2) for high speed/RF products” w/o DRC
485. OD.DN.0 8.1.1 DOD Layout Rules
impact.
486. IND.DN.8® 8.1.1 DOD Layout Rules Add this recommendation by copying from chapter 4.
Re-locate “SR_DOD Layout Rules” from chapter 4 to chapter
487. 8.1.2 SR_DOD Layout Rules
8.
488. SR_DOD.S.10 8.1.2 SR_DOD Layout Rules Remove this rule and modify the figure.
489. SR_DOD.EN.2 8.1.2 SR_DOD Layout Rules Remove this rule and modify the figure.
490. SR_DOD.R.4gU 8.1.2 SR_DOD Layout Rules Modify the description by adding “the“.
1. Re-name the section title from “Dummy Poly (DPO) Rules”
Dummy Poly (DPO/SR_DPO) Rules to “Dummy Poly (DPO/SR_DPO) Rules and Guidelines”.
491. 8.2
and Guidelines 2. Modify the description grammar.
3. Remove Inductor (INDDMY).
492. DPO.S.9 8.2.1 DPO Layout Rules Remove this rule and modify the figure.
493. DPO.EN.1 8.2.1 DPO Layout Rules Remove this rule and modify the figure.
494. IND.DN.9® 8.2.1 DPO Layout Rules Add this recommendation by copying from chapter 4.
Remove “(CB sizing 2) for high speed/RF products” w/o DRC
495. PO.DN.2 8.2.1 DPO Layout Rules
impact.
Re-locate “SR_DPO Layout Rules” from chapter 4 to chapter
496. 8.2.2 SR_DPO Layout Rules
8.
497. 8.3.1 Dummy TCD Rules Modify the description grammar.
498. DTCD.S.1 8.3.1 Dummy TCD Rules Remove one unnecessarily right-hand-side curved bracket, }.
Modify the rule number in the rule description from
499. DTCD.R.3 8.3.1 Dummy TCD Rules PO.S.18® GS to PO.S.18.GS® and from DOD.R.2® to
DOD.R.4® to align that in chapter 4.
1. Add the purpose of dummy TCD and the recommended
500. 8.4.1 Overview implementing stage.
2. Correct “TCD dummy” by “dummy TCD”.
Design Consideration of Dummy TCD
501. 8.4.2 Correct “TCD dummy” by “dummy TCD”.
Insertion
502. 8.4.3 Dummy TCD Marco Placement
2. Add dummy TCD implementing information.
503. 8.4.4 P&R Dummy TCD Rule Check 1. Correct “TCD dummy” by “dummy TCD”.
2. Add reference utility after P&R.
504. 8.4.5 Dummy TCD Marcos Insertion Flow
2. Modify the figure.
505. 8.4.6 TCD Library Kits Correct “TCD dummy” by “dummy TCD”.
1. Modify the ICOVL gds files from *_20100706.gds to
*_20101210.gds to remove two unnecessary PR boundary
506. 8.5.1 In Chip Overlay (ICOVL) Rules
layers.
2. Add die size definitions for N45LP/N45LPG.
Modify the rule number from ICOVL.S.2® U to ICOVL.S.2®
507. ICOVL.S.2® 8.5.1 In Chip Overlay (ICOVL) Rules
(DRC checked).
(DRC checked).
(DRC checked).
Modify the rule number from ICOVL.W.1® U to ICOVL.W.1®
510. ICOVL.W.1® 8.5.1 In Chip Overlay (ICOVL) Rules
(DRC checked).
1. Modify the rule number from ICOVL.W.2® U to
511. ICOVL.W.2® 8.5.1 In Chip Overlay (ICOVL) Rules ICOVL.W.2® (DRC checked).
2. Correct OVL_CT_PO by OVL_CO_PO.
(DRC checked).
(DRC checked).
(DRC checked).
Modify the rule number from ICOVL.EN.1® U to ICOVL.EN.1®
515. ICOVL.EN.1® 8.5.1 In Chip Overlay (ICOVL) Rules
(DRC checked).
Modify the rule number from ICOVL.EN.2® U to ICOVL.EN.2®
516. ICOVL.EN.2® 8.5.1 In Chip Overlay (ICOVL) Rules
(DRC checked).
Modify the rule number from ICOVL.R.9® U to ICOVL.R.9®
517. ICOVL.R.9® 8.5.1 In Chip Overlay (ICOVL) Rules
(DRC checked).
(DRC checked).
(DRC checked).
(DRC checked).
(DRC checked).
(DRC checked).
(DRC checked).
(DRC checked).
(DRC checked).
(DRC checked).
(DRC checked).
(DRC checked).
1. Modify the rule number from ICOVL.R.21® U to
ICOVL.R.21® (DRC checked) in both the rule table and
the figure.
2. Modify the explanation in the figure from “{Chip SIZING X
direction by -2380um and SIZING Y direction by -3035um}”
to “{Chip SIZING -2380um}” to align the rule description.
1. Modify the rule number from ICOVL.R.22® U to
ICOVL.R.22® (DRC checked) in both the rule table and
the figure.
2. Modify the explanation in the figure from “(Chip SIZING Y
direction by -3035um)” to “(Chip SIZING -2380um)” to align
the rule description.
Dummy Pattern Insertion in Design
8.5.3.6 Modify “TCD dummy” by “dummy TCD” in the figure.
Phase
531. 8.6 Dummy Metal (DM) Rules Modify the description grammar.
532. DMx.EN.1 8.6 Dummy Metal (DM) Rules Remove this rule and modify the figure.
533. Mx.DN.5 8.6 Dummy Metal (DM) Rules Modify the description from 2 to two and add “the”.
534. Mx.DN.6 8.6 Dummy Metal (DM) Rules Align the rule description with that in chapter 4.
535. Mx.DN.6® 8.6 Dummy Metal (DM) Rules Add this recommendation by copying that in chapter 4.
536. Mx.DN.7 8.6 Dummy Metal (DM) Rules Add this rule by copying that in chapter 4.
539. DMx.R.4® U 8.6 Dummy Metal (DM) Rules Rename from DMx.R.4® to DMx.R.4® U (DRC unchecked).
540. DMx.R.3 8.6 Dummy Metal (DM) Rules Add “Only”.
1. Modify efficiency by filling rate.
541. 8.7 Dummy VIA (DVIAx) Rules
542. DVIAx.S.2 8.7 Dummy VIA (DVIAx) Rules Modify the label from C to D.
543. DVIAx.EN.1 8.7 Dummy VIA (DVIAx) Rules Modify the label from D to C.
544. DVIAx.R.3 8.7 Dummy VIA (DVIAx) Rules Align the rule description with that in chapter 4.
545. 8.8.1 Dummy Pattern Filling Requirements
2. Modify the statement in DVIAx requirement.
Blockage Layer
(ODBLK/POBLK/DMxEXCL/
DVIAxEXCL) Requirements and
Recommendations
547. 8.8.4 Dummy Pattern Filling Guidelines Modify the description grammar.
1. Modify the description grammar for OD Mask Revision
Decision Flow.
2. Modify the description grammar for PO Mask Revision
Decision Flow.
Dummy Pattern Re-fill Evaluation
548. 8.8.6 3. Modify the description grammar for Mx Mask Revision
Flow Chart
Flow.
4. Modify the description grammar for VIAx Mask Revision
Flow.
5. Add Mx into VIAx Mask Revision Flow.
Layout Tips for Minimizing Critical
Areas
550. 9.1.2.1 Transistors Modify the description grammar.
2. Remove “Then, the white space around IP would be filled
551. 9.1.2.1.1 Improvement of poly CD uniformity with dummy PO/OD.”
3. Re-locate two sentences from chip integration to IP design.
4. Add a recommendation about unidirectional gate in a chip.
552. 9.1.2.1.2 Device impact by CO placement Modify the description grammar.
553. 9.1.2.1.3 Device impact by local OD/PO density 2. Modify the recommended max OD density from 55% to
70% to follow OD.DN.5® and OD.DN.7® .
554. 9.1.2.1.4 Device impact by OSE/PSE Modify the description grammar.
555. 9.1.3 Electrical Wiring Modify the description grammar.
556. PO.EX.2® 9.2.1 Action-Required Rules Align the description in chapter 4.
557. OD.W.1® 9.2.2 Recommendations Align the description in chapter 4.
558. OD.S.6® 9.2.2 Recommendations Align chapter 4 to remove this recommendation.
559. OD.DN.4® 9.2.2 Recommendations 2. Modify the description by adding “is as follows”.
3. Remove channel length <= 0.05um.
2. Modify the description by adding “is as follows”.
560. OD.DN.5® 9.2.2 Recommendations
562. OD.DN.7® 9.2.2 Recommendations
3. Correct a typo from unaslicided to unsalicided.
3. Correct a typo from unaslicided to unsalicided.
1. Rename from DOD.R.2® to DOD.R.4® .
2.
565. DOD.R.4® 9.2.2 Recommendations 3. Modify the op. from ≥ to .Refine the description and add
SEALRING_ALL (162;2) as another exception to align that
in chatper 4.
566. PO.W.1® U 9.2.2 Recommendations Rename from PO.W.1U® to PO.W.1® U.
567. PO.S.2.LP® 9.2.2 Recommendations Rename from PO.S.2® LP to PO.S.2.LP® .
568. PO.S.4.1® 9.2.2 Recommendations Align the description in chapter 4.
1. Align the description in chapter 4 by removing “at 0.2um
569. PO.S.18.GS® 9.2.2 Recommendations location”.
2. Rename from PO.S.18® GS to PO.S.18.GS® .
570. PO.DN.4® 9.2.2 Recommendations
576. HVD_N25.R.5® U 9.2.2 Recommendations Align chapter 4 to add this recommendation.
577. HVD_P25.R.5® U 9.2.2 Recommendations Align chapter 4 to add this recommendation.
578. HVD_N18.R.5® U 9.2.2 Recommendations Align chapter 4 to add this recommendation.
579. HVD_P18.R.5® U 9.2.2 Recommendations Align chapter 4 to add this recommendation.
580. HVD_GR.R.7® U 9.2.2 Recommendations Align chapter 4 to add this recommendation.
581. CO.S.3® 9.2.2 Recommendations Modify the description by adding a full stop.
582. CO.EN.0® 9.2.2 Recommendations Align chapter 4 to add this recommendation.
1. Modify the description from Fully to Full.
583. CO.S.7® 9.2.2 Recommendations 2. Remove “Channel length  0.05um”.
3. Exclude SDI regions.
584. M1.S.7® 9.2.2 Recommendations Align chapter 4 to remove this recommendation.
585. M1.EN.0® 9.2.2 Recommendations Align chapter 4 to add this recommendation.
586. M1.EN.5® 9.2.2 Recommendations Add .
1. This recommendation only checks IP border.
587. M1.DN.6® 9.2.2 Recommendations
2. Simplify the rule description.
588. VIAx.EN.0® 9.2.2 Recommendations Align chapter 4 to add this recommendation.
589. Mx.S.7® 9.2.2 Recommendations Align chapter 4 to remove this recommendation.
590. Mx.EN.0® 9.2.2 Recommendations Align chapter 4 to add this recommendation.
591. Mx.DN.6® 9.2.2 Recommendations
592. Mx.DN.7® 9.2.2 Recommendations
U
593. DMx.R.4® 9.2.2 Recommendations Align chapter 4 to add this recommendation.
594. LOWMEDN.R.8® U 9.2.2 Recommendations Align chapter 4 to add this recommendation.
595. My.S.6® 9.2.2 Recommendations Align chapter 4 to remove this recommendation.
596. My.EN.0® 9.2.2 Recommendations Align chapter 4 to add this recommendation.
597. AP.W.2® U 9.2.2 Recommendations Align chapter 4 to add this recommendation.
598. MOM.DN.1® 9.2.2 Recommendations Align chapter 4 to add this recommendation.
599. IND.DN.8® 9.2.2 Recommendations Align chapter 4 to add this recommendation.
600. IND.DN.9® 9.2.2 Recommendations Align chapter 4 to add this recommendation.
601. ROM.R.2® U 9.2.2 Recommendations Align chapter 4 to add this recommendation.
602. DTCD.DN.1® 9.2.2 Recommendations Align chapter 8 to add this recommendation.
603. ICOVL.S.1® 9.2.2 Recommendations Align chapter 8 to add this recommendation.
608. ICOVL.W.1® 9.2.2 Recommendations Align chapter 8 to add this recommendation.
613. ICOVL.EN.1® 9.2.2 Recommendations Align chapter 8 to add this recommendation.
614. ICOVL.EN.2® 9.2.2 Recommendations Align chapter 8 to add this recommendation.
615. ICOVL.R.2® U 9.2.2 Recommendations Align chapter 8 to add this recommendation.
620. ICOVL.R.7® 9.2.2 Recommendations Align chapter 8 to add this recommendation.
636. NW.R.1g 9.2.3 Guidelines Rename from NW.R.1gU to NW.R.1g (DRC checked).
637. NWROD.R.3g 9.2.3 Guidelines Align the rule description with that in chapter 4.
638. NWROD.R.8g 9.2.3 Guidelines Align chapter 4 to add this guideline.
639. NWRSTI.R.3g 9.2.3 Guidelines Align the rule description with that in chapter 4.
640. NWRSTI.R.4g 9.2.3 Guidelines Align chapter 4 to add this guideline.
641. RES.R.15g 9.2.3 Guidelines Align the rule description with that in chapter 4.
642. RES.R.16g 9.2.3 Guidelines Align chapter 4 to add this guideline.
647. CO.R.5g 9.2.3 Guidelines Align the rule description with that in chapter 4.
648. IND.R.15gU 9.2.3 Guidelines Align chapter 4 to add this guideline.
649. 9.2.4 Grouping Table of Recommendations Modify SPICE by Simulation Accuracy.
Remove this recommendation since PO.S.5.LP® and
650. PO.S.5® 9.2.4 Grouping Table of Recommendations
PO.S.5.GS® have been existed in this section.
651. OD.S.6® 9.2.4 Grouping Table of Recommendations Align chapter 4 to remove this recommendation.
652. DOD.R.4® 9.2.4 Grouping Table of Recommendations Rename from DOD.R.2® to DOD.R.4® .
653. PO.W.1® U 9.2.4 Grouping Table of Recommendations Rename from PO.W.1U® to PO.W.1® U.
654. PO.S.2.LP® 9.2.4 Grouping Table of Recommendations Rename from PO.S.2® LP to PO.S.2.LP® .
656. PO.S.5.GS® 9.2.4 Grouping Table of Recommendations Rename from PO.S.5® GS to PO.S.5.GS® .
Remove this recommendation since PO.S.6LP® and
660. PO.S.6.® 9.2.4 Grouping Table of Recommendations
PO.S.6GS® have been existed in this section.
661. HVD_N25.R.5® U 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
662. HVD_P25.R.5® U 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
663. HVD_N18.R.5® U 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
664. HVD_P18.R.5® U 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
665. HVD_GR.R.7® U 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
666. CO.EN.0® 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
667. M1.S.7® 9.2.4 Grouping Table of Recommendations Align chapter 4 to remove this recommendation.
668. M1.EN.0® 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
669. VIAx.EN.0® 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
670. Mx.S.7® 9.2.4 Grouping Table of Recommendations Align chapter 4 to remove this recommendation.
671. Mx.EN.0® 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
672. DMx.R.4® U 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
673. LOWMEDN.R.8® U 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
674. My.S.6® 9.2.4 Grouping Table of Recommendations Align chapter 4 to remove this recommendation.
675. My.EN.0® 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
676. AP.W.2® U 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
677. MOM.DN.1® 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
678. IND.DN.8® 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
679. IND.DN.9® 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
680. PO.S.14.GSm® 9.2.4 Grouping Table of Recommendations Align chapter 5 to add this recommendation.
681. PO.S.14.LPm® 9.2.4 Grouping Table of Recommendations Align chapter 5 to add this recommendation.
682. PO.EN.1.GSm® 9.2.4 Grouping Table of Recommendations Align chapter 5 to add this recommendation.
683. PO.EN.1.LPm® 9.2.4 Grouping Table of Recommendations Align chapter 5 to add this recommendation.
688. PO.S.5m® 9.2.4 Grouping Table of Recommendations Align chapter 7 to add this recommendation.
689. PO.S.6m® 9.2.4 Grouping Table of Recommendations Align chapter 7 to add this recommendation.
690. PO.S.6.1m® 9.2.4 Grouping Table of Recommendations Align chapter 7 to add this recommendation.
691. PO.EX.1m® 9.2.4 Grouping Table of Recommendations Align chapter 7 to add this recommendation.
692. BJT.R.2® 9.2.4 Grouping Table of Recommendations Align chapter 7 to add this recommendation.
693. BJT.R.7® 9.2.4 Grouping Table of Recommendations Align chapter 7 to add this recommendation.
694. DTCD.DN.1® 9.2.4 Grouping Table of Recommendations Align chapter 8 to add this recommendation.
695. ICOVL.S.1® 9.2.4 Grouping Table of Recommendations Align chapter 8 to add this recommendation.
700. ICOVL.W.1® 9.2.4 Grouping Table of Recommendations Align chapter 8 to add this recommendation.
705. ICOVL.EN.1® 9.2.4 Grouping Table of Recommendations Align chapter 8 to add this recommendation.
706. ICOVL.EN.2® 9.2.4 Grouping Table of Recommendations Align chapter 8 to add this recommendation.
707. ICOVL.R.2® U 9.2.4 Grouping Table of Recommendations Align chapter 8 to add this recommendation.
712. ICOVL.R.7® 9.2.4 Grouping Table of Recommendations Align chapter 8 to add this recommendation.
728. NW.R.1g 9.2.4 Grouping Table of Recommendations Rename from NW.R.1gU to NW.R.1g (DRC checked).
729. NWROD.R.8g 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this guideline.
730. NWRSTI.R.4g 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this guideline.
731. RES.R.16g 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this guideline.
736. IND.R.15gU 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this guideline.
737. ROM.R.2® U 9.2.4 Grouping Table of Recommendations Align chapter 4 to add this recommendation.
738. 9.4 GDA Die Size Optimization Kit Modify the description.
739. 9.4.1 What is MFU? Add this section.
740. 9.4.2 Design Guidelines for Higher MFU Add this section.
Recommended GDA criteria MFU >
741. 9.4.3 Modify from > 65% to > 80%.
80%
742. 9.4.4 MFU Reference Table for N45 Add this section.
743. 9.4.5 MFU Reference Table for N40 Add this section.
1. Correct a typo from concerations to concentration.
744. 10.1.1 Latch-up Introduction
2. Modify the description of Fig. 10.1.6.
Special Definition in Latch-up Remove the description about the DRC methods to recognize
745. 10.1.2.1
Prevention MOS/ACTIVE for latch-up.
746. 10.1.2.2 Latch-up Dummy Layers Summary Remove the section of “SDI Dummy Layer (CAD layer: 122)”.
LUPWDMY Dummy Layer (CAD
747. 10.1.2.2.1 Remove SDI in Fig. 10.1.8.
layer: 255;1)
RES200 Dummy Layer (CAD layer:
748. 10.1.2.2.2 Refine the description and the figure.
255;9)
2. Remove “The Active/MOS OD covered by SDI (122;0).”
749. 10.1.2.3.1 DRC methodology for LUP.1
3. Remove “The Active OD is used for Resistor.”
4. Refine the description about the same guard ring for
different type devices.
5. Modify the figures.
750. 10.1.2.3.2 DRC methodology for LUP.2 Refine the description and figure.
1. Add “ACTIVE”.
751. 10.1.2.3.3 DRC methodology for LUP.3 group 2. Remove “I” and “II” from “The excluded case “I” and “II” in
LUP.1.”
1. Correct the typo from LUP.3 to LUP.5.
752. 10.1.2.3.5 DRC methodology for LUP.5 group
2. Add “ACTIVE”.
Layout Rules and Guidelines for
753. 10.1.2.4 Add a statement before the rule table.
Latch-up Prevention
754. LUP.2 10.1.2.4 Add “(≤15um)” after “within 15um” and refine the description.
Latch-up Prevention
Layout Rules and Guidelines for Give this rule number to the existed rule description and
755. LUP.3.0 10.1.2.4
Latch-up Prevention refine the description.
756. LUP.3.1.0 10.1.2.4 Give this rule number to the existed rule description.
Latch-up Prevention
Latch-up Prevention
Latch-up Prevention
Latch-up Prevention
Latch-up Prevention
Layout Rules and Guidelines for Modify the figure number from Figure 10.1.11 to Figure
761. LUP.4 10.1.2.4
Latch-up Prevention 10.1.14.
Latch-up Prevention
Latch-up Prevention
Latch-up Prevention
Latch-up Prevention
Latch-up Prevention
767. 10.1.2.4 Revise Figure 10.1.15.
Latch-up Prevention
768. 10.1.3 Test Specification and Requirements Modify from JEDEC JC-40.2 to JEDEC 78.
Correct a typo from vaules to values, and modify from 200V
769. 10.2.1 ESD introduction
MM to 100V MM.
770. 10.2.4 SR_ESD device Layout Rules Add “except nch_hia_mac”.
771. 10.2.5.1 SDI Dummy Layer Modify the description.
772. 10.2.6 ESD circuits Definition Modify the description.
773. 10.2.6.2 HV tolerant IO Add “(stacked gate)”.
774. 10.2.7 Requirements for ESD Implant Masks Modify the description and the table number.
DRC methodology to identify ESD Modify the title and the description from devices to MOSFET
775. 10.2.8.1
MOSFET and the table number..
DRC methodology to identify ESD
776. 10.2.8.2 Add MOS into the section title.
MOS Source and Drain
777. 10.2.8.3 DRC methodology for ESD.1g Modify the description.
778. 10.2.8.6 DRC methodology for ESD.7g Modify space from < 2.4um to < 1.2um.
779. 10.2.8.7 DRC methodology for finger width Modify the description.
DRC methodology for ESD.20g,
780. 10.2.8.9 Add ESD.42g into the section title and the figure title.
ESD.28g, ESD.29g, and ESD.42g
781. 10.2.9 ESD Guidelines Modify the description.
782. 10.2.9.1 General Guideline for ESD Protection Correct a typo from gudielines to guidelines.
Modify the description and relax to allow thin oxide protecting
783. ESD.1g 10.2.9.1 General Guideline for ESD Protection
thick oxide.
784. ESD.6g 10.2.9.1 General Guideline for ESD Protection Modify the description.
U Refine the rule number and modify the description for core
785. ESD.9.1g 10.2.9.1 General Guideline for ESD Protection
MOS only & the spec (remove -0.12).
786. ESD.9.2gU 10.2.9.1 General Guideline for ESD Protection Add this guideline.
Modify the description and relax from connecting to Power
789. ESD.12g 10.2.9.1 General Guideline for ESD Protection
and I/O pads to connecting to I/O pad only.
790. ESD.62gU 10.2.9.1 General Guideline for ESD Protection Rename the rule number from ESD.47gU
791. 10.2.9.4 Power Clamp Device (Ncs) Modify the description.
Add “fully silicided type” and “and Figure 10.2.27” into the rule
792. ESD.37g 10.2.9.4 Power Clamp Device (Ncs)
description.
Add “fully silicided type” and “and Figure 10.2.27” into the rule
793. ESD.37.1g 10.2.9.4 Power Clamp Device (Ncs)
description.
794. ESD.38g 10.2.9.4 Power Clamp Device (Ncs) Modify the description.
795. ESD.38.1g 10.2.9.4 Power Clamp Device (Ncs) Modify the description.
798. ESD.39g 10.2.9.4 Power Clamp Device (Ncs) Add this guideline.
803. ESD.43gU 10.2.9.4 Power Clamp Device (Ncs) Remove this guideline.
Modify the DRC definitions by adding “NOT RPDMY” and the
806. 10.2.9.5 5V HVMOS protection (Field Device)
figure numbers.
HIA_Dummy Layer (CAD layer:
807. 10.2.9.6.3.1 Modify HIA_Dummy Layer from 168:0 to 168;0.
168;0)
U
808. HIA.1g 10.2.9.6.3.2 High current diodes protection Modify the description.
809. HIA.2gU 10.2.9.6.3.2 High current diodes protection Modify the description.
810. HIA.12gU 10.2.9.6.3.2 High current diodes protection Add this guideline.
811. HIA.9gU 10.2.9.6.3.2 High current diodes protection Modify the description.
814. 10.2.9.6.3.2 High current diodes protection Modify the figures.
CDM Protection for Cross Domain
815. 10.2.9.7 Modify the description.
Interface
CDM Protection for Cross Domain Rename the rule number from ESD.56gU and modify the
816. ESD.58gU 10.2.9.7
Interface description & the spec from 20 to 8.
817. ESD.59gU 10.2.9.7 Rename the rule number from ESD.57gU.
Interface
Rename the rule number from ESD.57.1gU and modify the
818. ESD.59.1gU 10.2.9.7 description & the spec from 0.38um to 0.42um to meet
Interface
PO.W.3LP.
819. ESD.59.2gU 10.2.9.7 Rename the rule number from ESD.57.2gU.
Interface
820. ESD.59.3gU 10.2.9.7 Rename the rule number from ESD.57. 3gU.
Interface
821. ESD.59.4gU 10.2.9.7 Rename the rule number from ESD.57.4gU.
Interface
Interface
Interface
Add "3.3V/2.5V NMOS for RPO (unsilicided) type Power
824. 10.2.9.8 RPO and ESD Implant Summary
Clamp" the I/O device group
Stress condition and Measurement
825. 10.2.10.1 Modify the content.
condition
826. 10.2.11 Tips for the ESD/LU Design Add this section.
827. 10.2.12 Tips for the Power ESD Protection Modify the section title and the content.
828. 10.2.12.1 Approach Remove this section.
829. 11.2.1 I/O Over Drive Voltage Modify the section title and the content.
830. 11.2.2 Gate Oxide Integrity Modify the section title and the content.
831. 11.2.2.3.1 Measurement Conditions Modify the content.
832. 11.2.2.3.4 DC Lifetime and Vmax Modify the section title and the content.
833. 11.2.3 Hot Carrier Injection Effect Modify the section title.
834. 11.2.3.2 Failure Mechanism Modify the content.
835. 11.2.3.3.3 Dimension Ranges of Stress Devices Add this section.
836. 11.2.3.3.4 Failure Criteria and Spec Modify the content.
DC Lifetime and Vmax: Vcc = 1.1V +-
837. 11.2.3.3.5 Modify the section title and the content.
10% and 1.2V +- 5% for N45LP
DC Lifetime and Vmax:
Vcc = 1.1V +- 10% and 1.2V +- 5%
838. 11.2.3.3.6 for N45LPG_LP, Vmax= 1.26V Modify the section title and the content.
Vcc = 0.9V+10% and 1.0V +- 5% for
N45LPG_G
Negative Bias Temperature Instability
839. 11.2.4 Modify the section title.
(NBTI)
840. 11.2.4.3 Failure Mechanism Modify the content.
841. 11.2.4.4.2 Stress Conditions Modify the content.
842. 11.2.4.4.3 Failure Criteria Modify the content.
DC Lifetime and Vmax : Vcc = 1.1V +-
843. 11.2.4.4.4 Modify the section title and the description.
10% and 1.2V +-5% for N45LP
DC Lifetime and Vmax :
Vcc = 1.1V +- 10% and 1.2V +- 5%
for N45LPG_LP, Vcc = 0.9V+10%
and 1.0V +- 5% for N45LPG_G
845. 11.2.5 N45 Poly Current Density Modify the section title and the content.
846. 11.2.6 N45 Poly EM Joule heating Modify the section title.
847. 11.2.6.1 Irms Current Modify the section title and the content.
848. 11.2.6.2 Ipeak Modify the content.
849. 11.2.7 N45 OD Current Density Modify the section title.
850. 11.3.1 Stress Migration (SM) Modify the section title.
851. 11.3.2 Low-k Dielectric Integrity Modify the section title.
852. 11.3.3.5.1 General Modify the section title and the content.
Imax dependence on metal length
(length ≤ 10um)
Imax dependence on metal width
(width ≥ 0.5 µm)
855. 11.3.3.5.4 Stacked Vias Modify the content.
DC Operation, Required Number of
856. 11.3.3.5.5 Modify the content.
Vias
Maximum DC Current for AP RDL
Metal Lines (Tj = 110C)
858. 11.3.5.3 Root-Mean-Square Current Modify the content.
Root-Mean-Square Current for LK
859. 11.3.5.3.1 Dielectrics (1P10M M1MxMz process, Modify the section title and the content.
no My)
860. 11.3.5.3.2 Dielectrics (other metallization Modify the section title and the content.
861. 11.3.5.3.3 Dielectrics (1P10M M1MxMyMz Modify the section title and the content.
process)
Dielectrics (1P10M M1MxMr process)
864. 11.3.5.3.6 Dielectrics (1P10M M1MxMy process, Modify the section title and the content.
My/Vy are used as 2X top Metal/Via)
Dielectrics (1P10M M1MxMyMzMu
process, Mu/Vu are used as top
Metal/Via)
Dielectrics (1P10M M1MxMyMu
process, My/Vy are 2XTM, Mu/Vu are
used as top Metal/Via)
867. 11.3.5.4 Peak Current Modify the content.
868. 11.3.6 AP RDL AC Operation Modify the content.
869. 12.2.1 I/O Over Drive Voltage Modify the section title and the content.
870. 12.2.2 Gate Oxide Integrity Modify the section title and the content.
871. 12.2.2.1 Gate Oxide Lifetime Prediction Model Modify the content.
872. 12.2.2.3.1 Measurement Conditions Modify the content.
873. 12.2.2.3.4 DC Lifetime and Vmax Modify the section title and the content.
874. 12.2.3 Hot Carrier Injection Effect Modify the section title.
10% and 1.2V +- 5% for N40LP
10% and 1.2V +- 5% for N40LPG_LP,
Vcc = 0.9V+10% and 1.0V +- 5% for
N40LPG_G
10% and 1.0V+- 5% for N40G
Negative Bias Temperature Instability
878. 12.2.4 Modify the section title.
(NBTI)
879. 12.2.4.4.3 Failure Criteria Modify the content.
10% and 1.2V +- 5% for N40LP
10% and 1.2V +- 5% for N40LPG_LP,
Vcc = 0.9V+10% and 1.0V +- 5% for
N40LPG_G
10% and 1.0V+- 5% for N40G
883. 12.2.5 N40 Poly Current Density Add this section.
884. 12.2.6 N40 Poly EM Joule heating Add this section.
885. 12.2.6.1 Irms current Add this section.
886. 12.2.6.2 Ipeak Add this section.
887. 12.2.7 N40 OD Current Density Add this section.
888. 12.3.1 Stress Migration (SM) Modify the section title.
889. 12.3.2 Low-k Dielectric Integrity Modify the section title.
890. 12.3.3.5.1 General Modify the content.
Imax dependence on metal length
(length ≤ 10µm)
Imax dependence on metal width
(width ≥ 0.5µm)
893. 12.3.3.5.4 Stacked Vias Modify the content.
DC Operation, Required Number of
894. 12.3.3.5.5 Modify the content.
Vias
Maximum DC Current for AP RDL
Metal Lines (Tj = 110C)
896. 12.3.5.3 Root-Mean-Square Current Modify the content.
897. 12.3.5.3.1 Dielectrics (1P10M M1MxMz process, Modify the section title and the content.
no My)
899. 12.3.5.3.3 Dielectrics (1P10M M1MxMyMz Modify the section title and the content.
process)
Dielectrics (1P10M M1MxMr process)
902. 12.3.5.3.6 Dielectrics (1P10M M1MxMy process, Modify the section title and the content.
My/Vy are used as 2X top Metal/Via)
Dielectrics (1P10M M1MxMyMzMu
process, Mu/Vu are used as top
Metal/Via)
Dielectrics (1P10M M1MxMyMu
process, My/Vy are 2XTM, Mu/Vu are
used as top Metal/Via)
905. 12.3.5.4 Peak Current Modify the content.
906. 12.3.6 AP RDL AC Operation Modify the content.

Consolidate N40LP+ DRM T-N40-CL-DR-019 section 1.1
1. 1.1 Overview
overiew content in this section.
2. 2.1.1 Front-End Features
SRAM cells offering in this section.
3. 2.2 Devices
device offering in table 2.2.1
Power supply and operation Consolidate N40LP+ DRM T-N40-CL-DR-019 section 1.1
4. 2.3
temperature ranges power supplies in table 2.3.1
Modify Mr/VIAr mask layers start from M6/VIA5 in table 2.5.1
5. 2.5 Metallization options
and 2.5.2
6. 2.5 Metallization options Delete table 2.5.8 and 2.5.9 due to table conflict
7. 3.1 Refine the warning of re-tapeout 12E and 12F
8. 3.1 Change OD description in table 3.1.1
Consolidate N40LP+ DRM T-N40-CL-DR-019 table 2.1.1
Mask Information, Key Process Mask Name and ID, Key Process Sequence, and CAD Layer
9. 3.1
Sequence, and CAD Layers for CLN40LP+ (1.1V Core and 2.5V I/O Design) in this section
table 3.1.2.
12. 3.1 N40LP Plus (N40LP+) Mask Name/ID/Grade/Type, OPC, and
PSM Information in this section table 3.1.5
13. 3.1 N40LP Plus (N40LP+) 2.5V Mask to CAD layer mapping table
in this section table 3.1.13
Add special recognition cad layer for N40LP+ (DCO_LPP and
14. 3.4 DCODMY_SC), logic inductors (INDDMY_MD and
Summary
INDDMY_HD), AAIO (LUPWDMY_2) and LMARK.
N45/N40 Low Power (LP): 1.1V Core Modify the mark of RPO and VTL_P for 5V HVMOS from “1” to
15. 3.5.1
Design “0”.
N45/N40 Low Power (LP): 1.1V Core
16. 3.5.1 Delete OD_33 device offering for N40LP/N45LP
Design
N40 Low Power Plus (N40LP+): 1.1V
17. 3.5.2 Device Truth Table for N40LP Plus (N40LP+): 1.1V Core and
Core and 2.5V I/O Design
2.5V I/O Design in this section table 3.5.2
Mask requirement for device options
18. 3.6 Mask Requirement for N40LP Plus (N40LP+): 1.1V Core and
(High/STD/Low VT/Ultra Low VT Plus)
2.5V I/O Design in this section table 3.6.2
19. 3.7.1 Design Grid Rules Add N40LP+ ULTV_N, ULVT_P, DCO_LPP in G.4 and G.6gU.
20. OD.A.5.GS 4.5.1 Add “For GS”
21. OD.DN.0 4.5.1 Add INDDMY_MD excluded region.
Gate Oxide and Diffusion (OD) Layout Correct rule no. in the figure. (Remove OD.L.3 and correct
22. 4.5.1
Rules (Mask ID: 120) DOD.R.4® )
23. NW.R.1g 4.5.3 N-Well (NW) Layout Rules Add DRC methodology.
Thick Oxide (OD2) Layout Rules Consolidate N40LP+ DRM T-N40-CL-DR-019 OD2.R.2.LPP in
24. OD2.R.2.LPP 4.5.7
(Mask ID: 152) this section.
25. PO.DN.2 4.5.13 Add INDDMY_MD excluded region.
130)
Poly (PO) Layout Rules (Mask ID: Correct rule no. in the figure from PO.S.4 to
26. 4.5.13
130) PO.S.4.1/PO.S.4.1® .
Ultra Low Vt Plus Devices Layout Consolidate N40LP+ DRM T-N40-CL-DR-019 section 3.2.2
27. 4.5.18
Rules Ultra Low Vt Plus Devices Layout Rules in the section 4.5.18
DCO_LPPLUS (DCO_LPP) Layout Modify “Cut STRAP” as “Cut ACTIVE” for N40LP+ standard
28. DCO_LPP.EX.3 4.5.18.1
Rules (Mask ID: 153) cell.
29. 4.5.27 MOS Varactor Layout Rules (VAR) Add N45LPG VAR summary
Contact (CO) Layout Rules (Mask ID: Relax “{COs INSIDE {HVD_N OR HVD_P}} which projection
30. CO.S.7® 4.5.28
156) space to GATE0.8 μm” to align p cell HVMOS layout
VIAy Layout Rules (Mask ID: 379,
31. 4.5.33 Remove the redundant illustration of VIAy.R.8®
373, 374, 375, 376, 377, 372, 37A)
32. My.DN.1 4.5.34 Add “INDDMY_MD exception”
and Top Metal (381, 384, 385, 386,
387, 388, 389, 38A))
33. Mz.W.2 4.5.36 Add “INDDMY_MD exception”
384, 385, 386, 387, 388, 389, 38A)
34. Mz.DN.1 4.5.36 Add “INDDMY_MD exception”
384, 385, 386, 387, 388, 389, 38A)
35. Mz.DN.1.1 4.5.36 Add “INDDMY_MD exception”
384, 385, 386, 387, 388, 389, 38A)
Top VIAr Layout Rules (Mask ID: 375, Revise VIAr start from VIA5 to match section 2.5 metalization
36. VIAr.0U 4.5.37
376, 377, 372, 37A) option
Top Mr Layout Rules (Mask ID: 386, Revise Mr start from M6 to match section 2.5 metalization
37. Mr.0U 4.5.38
387, 388, 389, 38A) option
38. Mr.W.2 4.5.38 Add “INDDMY_MD exception”
387, 388, 389, 38A)
Top Mr Layout Rules (Mask ID: 386, Add “INDDMY_MD exception”
39. Mr.DN.1 4.5.38
387, 388, 389, 38A)
Top Mr Layout Rules (Mask ID: 386, Add “INDDMY_MD exception”
40. Mr.DN.1.1 4.5.38
387, 388, 389, 38A)
41. RV.R.1 4.5.39 RV Layout Rules (Mask ID: 306) Add “INDDMY_MD exception”
42. RV.R.2 4.5.39 RV Layout Rules (Mask ID: 306) Add “INDDMY_MD”
43. AP.R.1 4.5.40 Add “INDDMY_MD”
44. MOM.DN.1® 4.5.42 MOM Layout Rules Add “for M1/Mx layers”
45. Mu.W.2 4.5.44 Mu (Ultra Thick Metal) Layout Rules Add “INDDMY_MD exception”
46. Mu.DN.2 4.5.44 Mu (Ultra Thick Metal) Layout Rules Add “INDDMY_MD exception”
47. Mu.DN.2.1 4.5.44 Mu (Ultra Thick Metal) Layout Rules Add “INDDMY_MD exception”
Add inductor rules overview for original low density inductor
48. 4.5.45 Inductor Layout Rules
and logic inductors.
INDDMY layer identified inductor Correct the description “inter-metal” and “top My” to match
49. IND.R.5 4.5.45.1
layout rules DRC.
INDDMY layer identified inductor Add “INDDMY_MD”
50. IND.DN.1 4.5.45.1
layout rules
IND.DN.4 INDDMY layer identified inductor Add “INDDMY_MD exception”
51. 4.5.45.1
layout rules
IND.DN.4.1 INDDMY layer identified inductor Add “INDDMY_MD exception”
52. 4.5.45.1
layout rules
INDDMY layer identified inductor Add “INDDMY_MD”
53. IND.DN.7 4.5.45.1
layout rules
INDDMY_MD Layer Identified Inductor Add this section
54. 4.5.45.2
Layout Rules
INDDMY_HD Layer Identified Inductor Add this section
55. 4.5.45.3
Layout Rules
Change from “interact with” to “overlaps to allow abutment and
56. ROM.R.4 4.5.51 ROM Rules
relax NW/HVD_N/VTH_N/VTL_N AND OD.
Change the seal ring gds of 1P10M sample GDS file for using
57. 4.5.54.1 Guidelines for Placing Seal Ring
Mr as top metal. (Add 1P7M-4x2r)
Add 1P7M-4x2r metallization option in Mr seal ring to match
Metallization Options Using Mr as the
58. 4.5.54.1.3 section 2.5 metallization options. Correct typo of 1P8M-5x2r
Top Metal
Via6 from “58;80*” to “56;80*”
59. VIAy.EN.6 4.5.54.4.1 Seal Ring Wall Layout Rules Correct typo from “bar” to “hole”
60. 4.5.54.4 Seal Ring Layout Rules Delete the seal ring mask tone table.
Layout Rules for the WPE (Well Add “For LP process, only NW layout will impact both core and
61. 5.1
Proximity Effect) IO PMOS WPE calculation” in figure 5.1.1
62. 9.2.4 Grouping table of recommendations Add IND_MD.DN.8® and IND_MD.DN.9®
Special Definition in Latch-up Add guard-band, N+ guard-band, P+guard-band and OD
63. 10.1.2.1
Prevention injector definition.
LUPWDMY_2 Dummy Layer (CAD Add this section
64. 10.1.2.2.3
layer: 255;18)
65. 10.1.2.3.1 DRC methodology for LUP.1 Refine the description.
66. 10.1.2.3.2 DRC methodology for LUP.2 Change active/MOS OD as OD injector
Layout Rules and Guidelines for Change active as OD injector
67. LUP.1 10.1.2.4
Latch-up Prevention
Layout Rules and Guidelines for Change “MOS connected to an I/O pad” as OD injector
68. LUP.2 10.1.2.4
Latch-up Prevention
Layout Rules and Guidelines for Add 1.8V
69. LUP.3.5.0 10.1.2.4
Latch-up Prevention
Layout Rules and Guidelines for Change “active connected to an I/O pad” as OD injector
70. LUP.4 10.1.2.4
Latch-up Prevention
Layout Rules and Guidelines for Change “NMOS/PMOS” as “N+OD injector/P+OD injector”
71. LUP.5.1.0 10.1.2.4
Latch-up Prevention
72. LUP.5.2.0 10.1.2.4
Latch-up Prevention
73. LUP.5.3.0 10.1.2.4
Latch-up Prevention
74. LUP.5.4.0 10.1.2.4
Latch-up Prevention
75. LUP.5.5.0 10.1.2.4
Latch-up Prevention
Layout Rules and Guidelines for Area Add this section.
76. 10.1.2.5
I/O Latch-up Prevention
77. 10.1.3 Test specification and requirements Correct from “+/-200mA” to “+/-100mA”
ESD Implant (ESDIMP) Layout Rules Delete this rule and move the recommendation to description.
78. ESDIMP.R.2® U 10.2.3
(MASK ID: 111)
CDM Protection for Cross Domain Relax channel length from fixed value 0.08 to a range 0.07-
79. ESD.59.4gU 10.2.9.7
Interface 0.08
Imax dependence on metal width Correct Mr W ≥ 0.5 and Mu W ≥ 2.0 to match min. width rule
80. 11.3.3.5.3
(width ≥ 0.5 µm)
Imax dependence on metal width Correct Mr W ≥ 0.5 and Mu W ≥ 2.0 to match min. width rule
81. 12.3.3.5.3
(width ≥ 0.5µm)

1. 2.1.1 Front-End Features Add HDDP(HP) = 0.589um^2* SRAM offering
2. 3.1 Modify FEOL RTO warning.
Mask Information, Key Process Add 11E and 11F in the table 3.1.1 and modify the
3. 3.1
Sequence, and CAD Layers description of mask RPO2.
4. 3.1 Modify 11E and 11F in the table 3.1.2
Mask Information, Key Process Modify the content of “Reference Layer in Logical Operation
5. 3.1
Sequence, and CAD Layers and OPC” in table 3.1.1~3.1.4
6. 3.4 Add ULVT_N and ULVT_P in the table 3.4.1
Summary
Delete “including 2.5V overdrive 3.3V” of 2.5V varactor
7. 3.5 Device Truth Tables
device in the table 3.5.1.1 and 3.5.2
8. G.4 3.7.1 Design Grid Rules Correct typo.
9. G.6gU 3.7.1 Design Grid Rules Correct typo.
Deep N-Well (DNW) Layout Rules (Mask
10. DNW.S.2 4.5.2 Add DRC check methodology.
ID: 119) [Optional]
Deep N-Well (DNW) Layout Rules (Mask
11. DNW.R.7 4.5.2 Relax spec as 5.0E+05
ID: 119) [Optional]
12. HVD_P18.S.9 4.5.25.2 HVD_P Layout Rules for HVMOS_18 Modify spec as 1.82
Contact (CO) Layout Rules (Mask ID: Modify {COs INSIDE {HVD_N OR HVD_P}} which projection
13. CO.S.7® 4.5.28
156) space to GATE as m
14. AP.S.1.1 4.5.40 Add this rule
15. DMu.R.1 4.5.44 Mu (Ultra Thick Metal) Layout Rules Align deck code to add this rule.
16. CSR_DM.W.1 4.5.54.2 Chip Corner Stress Relief (CSR) Pattern Modify table no as 4.5.54.2.1
17. CSR_DM.S.1 4.5.54.2 Chip Corner Stress Relief (CSR) Pattern Modify table no as 4.5.54.2.1
18. CSR_DM.S.2 4.5.54.2 Chip Corner Stress Relief (CSR) Pattern Modify table no as 4.5.54.2.1
19. CSR_DM.O.1 4.5.54.2 Chip Corner Stress Relief (CSR) Pattern Modify table no as 4.5.54.2.1
20. CSR_DV.W.1 4.5.54.2 Chip Corner Stress Relief (CSR) Pattern Modify table no as 4.5.54.2.1
21. CSR_DV.S.1 4.5.54.2 Chip Corner Stress Relief (CSR) Pattern Modify table no as 4.5.54.2.1
22. CSR_DV.EN.1 4.5.54.2 Chip Corner Stress Relief (CSR) Pattern Modify table no as 4.5.54.2.1
23. SR.R.7 4.5.54.4.1 Seal Ring Wall Layout Rules Add CB/CBD/RV bar
CDU (Critical Dimension Uniformity) Modify CDU is a must as you added sealring by yourself.
24. 4.5.54.4.3
pattern in Assembly Isolation Rules Remove CDU sample gds.
25. 8.3.1 Dummy TCD Rules Re-organize content.
26. DTCD.DN.2 8.3.1 Dummy TCD Rules Add this rule.
Layout Guidelines for Latch-Up and I/O
27. 10 Add a foreword.
ESD
28. 10.1.1 Latch-up Introduction Delete Fig. 10.1.6 LUP.8gU
29. 10.1.2.1 Special Definition in Latch-up Prevention Add OD injector voltage definition
30. 10.1.2.1 Special Definition in Latch-up Prevention Modify Fig. 10.1.7 to Fig. 10.1.6
31. 10.1.2.2 Latch-up Dummy Layers Summary Re-organize section content
LUPWDMY Dummy Layer (CAD layer:
32. 10.1.2.2.1 Modify Fig. 10.1.8 to Fig. 10.1.7
255;1)
Re-organize 10.1.2.3.1 as section 10.1.2.3.1 ~ 10.1.2.3.3
33. 10.1.2.3 DRC methodology for Latch-up Rules
and delete Fig. 10.1.10
34. 10.1.2.3.4 DRC methodology for LUP.2 Modify Fig. 10.1.11 to Fig. 10.1.9
35. 10.1.2.3.6 DRC methodology for LUP.4 Modify Fig. 10.1.12 to Fig. 10.1.10
Re-organize rule description and modify Fig. 10.1.13 to Fig.
Layout Rules and Guidelines for Latch-
36. LUP.2 10.1.2.4 10.1.11, Fig. 10.1.14 to Fig. 10.1.12, Fig. 10.1.15 to Fig.
up Prevention
10.1.13 and Fig. 10.1.16 to Fig. 10.1.14
37. LUP.2.1U 10.1.2.4 Add this rule
up Prevention
38. LUP.3.0 10.1.2.4 Re-organize rule description
up Prevention
39. LUP.3.1.0 10.1.2.4 Modify as core PMOS to NMOS
up Prevention
40. LUP.3.2.0 10.1.2.4 Modify as 1.8V/1.5V PMOS to NMOS
up Prevention
41. LUP.3.3.0 10.1.2.4 Modify as 2.5V PMOS to NMOS
up Prevention
42. LUP.3.4.0 10.1.2.4 Modify as 3.3V PMOS to NMOS
up Prevention
43. LUP.3.5.0 10.1.2.4 Modify as 5V PMOS to NMOS
up Prevention
1. Modify to check from OD injector.
2. Modify to check the space between N+OD injector and
44. LUP.5.1.0 10.1.2.4 core PMOS;
up Prevention
3. Modify to check the space between core P+OD injector
and the NMOS;
45. LUP.5.2.0 10.1.2.4 1.8V/1.5V PMOS;
up Prevention
3. Modify to check the space between 1.8V/1.5V P+OD
injector and the NMOS;
46. LUP.5.3.0 10.1.2.4 2.5V PMOS;
up Prevention
3. Modify to check the space between 2.5V P+OD injector
and the NMOS;
47. LUP.5.4.0 10.1.2.4 3.3V PMOS;
up Prevention
3. Modify to check the space between 3.3V P+OD injector
and the NMOS;
48. LUP.5.5.0 10.1.2.4 5V PMOS;
up Prevention
3. Modify to check the space between 5V P+OD injector
and the NMOS;
49. LUP.5.6.0U 10.1.2.4 Add this rule
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
54. LUP.7gU 10.1.2.4 Delete this rule and add in the section 10.2.11 design tip
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
up Prevention
60. LUP.8gU 10.1.2.4 Delete this rule and add in the section 10.2.11 design tip
up Prevention
61. 10.1.2.4 Add figure 10.1.15 and 10.1.16
up Prevention
Layout Rules and Guidelines for Area I/O Re-organize the foreword and add figure 10.1.19 and
62. 10.1.2.5
Latch-up Prevention 10.1.20
Delete the passed condition of the latch up test and modify
63. 10.1.3 Test Specification and Requirements
Fig. 10.1.19 to Fig. 10.1.21 and Fig. 10.1.20 to Fig. 10.1.22
Correct typo as “The connectivity is broken by resistor for
64. 10.2.8.3 DRC methodology for ESD.1g
this check”
65. 10.2.11 Tips for the ESD/LU Design Re-organize this section
66. 10.2.12 Tips for the Power ESD Protection Re-organize this section

1. 4.2.2 Special Definition Redefine prime chip and assembly isolation
2. 4.3 Definition of Layout Geometrical Terminology Add prime chip
3. DM1.R.1 4.5.29 Metal-1 (M1) Layout Rules (Mask ID: 360) Refine wording; no DRC change
VIAx Layout Rules (Mask ID: 378, 379, 373, 374,
4. VIAx.R.13.1 4.5.30 Add new rule to prevent BEOL Cu dent
375, 376, 377)
VIAx Layout Rules (Mask ID: 378, 379, 373, 374,
5. VIAx.R.13.2 4.5.30 Add new rule to prevent BEOL Cu dent
375, 376, 377)
Mx Layout Rules (Mask ID: 380, 381, 384, 385,
6. DMx.R.1 4.5.31 Refine wording; no DRC change
386, 387, 388)
VIAy Layout Rules (Mask ID: 379, 373, 374, 375,
7. VIAy.R.13.1 4.5.33 Add new rule to prevent BEOL Cu dent
376, 377, 372, 37A)
VIAy Layout Rules (Mask ID: 379, 373, 374, 375,
8. VIAy.R.13.2 4.5.33 Add new rule to prevent BEOL Cu dent
376, 377, 372, 37A)
My Layout Rules (Mask ID: Second Inter-layer
9. DMy.R.1 4.5.34 Metal (385, 386, 387, 388) and Top Metal (381, Refine wording; no DRC change
384, 385, 386, 387, 388, 389, 38A))
Top VIAz Layout Rules (Mask ID: 379, 373, 374,
10. VIAz.R.13.1 4.5.35 Add new rule to prevent BEOL Cu dent
375, 376, 377, 372, 37A)
Top VIAz Layout Rules (Mask ID: 379, 373, 374,
11. VIAz.R.13.2 4.5.35 Add new rule to prevent BEOL Cu dent
375, 376, 377, 372, 37A)
Top Mz Layout Rules (Mask ID: 381, 384, 385,
12. DMz.R.1 4.5.36 Refine wording; no DRC change
386, 387, 388, 389, 38A)
Top VIAr Layout Rules (Mask ID: 375, 376, 377,
13. VIAr.0U 4.5.37 Delete this rule
372, 37A)
14. VIAr.R.13.1 4.5.37 Add new rule to prevent BEOL Cu dent
372, 37A)
15. VIAr.R.13.2 4.5.37 Add new rule to prevent BEOL Cu dent
372, 37A)
Top Mr Layout Rules (Mask ID: 386, 387, 388,
16. Mr.0U 4.5.38 Delete this rule
389, 38A)
Top Mr Layout Rules (Mask ID: 386, 387, 388,
17. DMr.R.1 4.5.38 Refine wording; no DRC change
389, 38A)
1. Change rule name from SR.S.1 to SR.R.9
18. SR.R.9 4.5.54.4.1 Seal Ring Wall Layout Rules
2. Update rule to align current S/R
RM.WARN.1,
RM.WARN.2,
19. RM.WARN.3, 4.5.55 Resistor Warning Rules Add new section to prevent misuse
RM.WARN.4,
RM.WARN.5
20. CB2.W.2 6.1.4.1 Non-shrinkable Rules Revise to prime chip edge; no DRC change
21. UBM.EN.1t 6.1.5.1 Non-shrinkable Rules Revise to prime chip edge; no DRC change
22. AN.R.13mU 7.3.3 Electrical Performance Rules and Guidelines Revise to prime chip edge; no DRC change
23. DMx.EN.2 8.6 Dummy Metal (DM) Rules Correct rule description; no DRC change
24. DMx.R.1 8.6 Dummy Metal (DM) Rules Refine wording; no DRC change
25. DMx.R.3 8.6 Dummy Metal (DM) Rules Refine wording; no DRC change
26. 10.1.2.1 Special Definition in Latch-up Prevention Update the OD injector definition
Layout Rules and Guidelines for Latch-up
27. LUP.WARN.1 10.1.2.4 Add warning for improper LUP switch usage
Prevention
28. LUP.2.1U 10.1.2.4 Refine the rule descirption
Prevention
29. LUP.5.0 10.1.2.4 Add description
Prevention
LUP.5.1.0,
LUP.5.2.0,
LUP.5.3.0, Layout Rules and Guidelines for Latch-up
30. 10.1.2.4 Refine wording
LUP.5.4.0, Prevention
LUP.5.5.0
LUP.9gU
ESD.NET.1gU,
ESD.WARN.3U,
ESD.1.1gU,
ESD.9.0gU,
31. 10.2.9.1 General Guideline for ESD Protection Add new uncheckable guidelines and rules
ESD.9.5gU,
ESD.9.6gU,
ESD.14.3gU,
ESD.14.4gU
ESD.2gU,
ESD.9gU,
ESD.10gU,
ESD.11gU,
ESD.11.1gU,
32. 10.2.9.1 General Guideline for ESD Protection Delete the guidelines
ESD.11.2gU,
ESD.11.3gU,
ESD.13gU,
ESD.14gU,
ESD.62gU
ESD.1gU,
ESD.8gU,
ESD.9.1gU,
33. ESD.9.2gU, 10.2.9.1 General Guideline for ESD Protection Refine wording
ESD.9.3gU,
ESD.9.4gU,
ESD.15gU
34. ESD.34g 10.2.9.3 HV Tolerant I/O Refine wording
35. ESD.35gU 10.2.9.3 HV Tolerant I/O Delete the guideline
36. ESD.45gU 10.2.9.4 Power Clamp Device (Ncs) Refine wording
37. ESD.45.1gU 10.2.9.4 Power Clamp Device (Ncs) Add new uncheckable guideline
HIA.1gU,
38. 10.2.9.6.3.2 High current diodes protection Refine wording
HIA.2gU
39. HIA.3gU 10.2.9.6.3.2 High current diodes protection Add new uncheckable guideline
40. HIA.4gU 10.2.9.6.3.2 High current diodes protection Refine wording; rename from HIA.3gU to HIA.4gU
41. HIA.5gU 10.2.9.6.3.2 High current diodes protection Refine wording; rename from HIA.4gU to HIA.5gU
42. HIA.6gU 10.2.9.6.3.2 High current diodes protection Rename from HIA.5gU to HIA.6gU
HIA.6gU,
HIA.7gU,
HIA.8gU,
43. HIA.9gU, 10.2.9.6.3.2 High current diodes protection Delete the guidelines
HIA.10gU,
HIA.11gU,
HIA.12gU
Update the table and move from section 10.2.9.8 to
44. 10.2.9.7 RPO and ESD Implant Summary
section 10.2.9.7
ESD.60.0gU,
45. 10.2.9.8 CDM Protection for Cross Domain Interface Add new uncheckable guidelines
ESD.61.1gU
Refine wording; rename from ESD.58gU to
46. ESD.61gU 10.2.9.8 CDM Protection for Cross Domain Interface
ESD.61gU
47. ESD.62.1gU 10.2.9.8 CDM Protection for Cross Domain Interface
ESD.62.1gU
Refine wording; rename from ESD.59.1gU to
ESD.62.2gU
ESD.62.3gU
ESD.62.4gU
ESD.62.5gU
52. ESD.63gU 10.2.9.8 CDM Protection for Cross Domain Interface
ESD.63gU
U
53. ESD.61g 10.2.9.8 CDM Protection for Cross Domain Interface Delete the guideline
54. 10.3 ESD Back-End Reliability Guidelines Update this section to align N28
55. 10.3.3 Maximum ESD Current Density for Resistor Add the max ESD current density table for resistor
Add the max ESD current density table for via and
56. 10.3.4 Maximum ESD Current Density for Via, and Metal
metal
57. ESD.CD.1gU 10.3.5 Minimum ESD Current for ESD Device Add new uncheckable guideline
58. ESD.CD.2gU 10.3.5 Minimum ESD Current for ESD Device Add new uncheckable guideline
59. 10.4 Tips for the ESD/Latchup design Update tips for the ESD/Latch-up design
60. 10.5 ESD testing methodology Update the ESD testing methodology

1. 2.5 Metallization Options Align Mx, Mr thicknesses with SPICE model
Add VIAu Information into Table 3.1.5 about
Mask Information, Key Process N45LP/N40LP/N40LP+/N45LPG/N40LPG Mask
2. 3.1
Sequence, and CAD Layers NameID/Grade/Type, OPC, and PSM and Table 3.1.6 N40G
Mask Name/ID/Grade/Type, OPC and PSM Information
N45/N40 Low Power (LP): 1.1V Core Add N-Well Psub Diode in N45LP/N40LP/N40LP/N45LPG/
3. 3.5.1
Design N40LPG /N40G device truth table.
4. OD.W.2.2GS 4.5.1 Remove SR_ESD waiver
5. DNW.R.7.1 4.5.2 Add rule DNW.R.7.1
6. 4.5.27 MOS Varactor Layout Rules (VAR) Add RF model offering information table
7. AP.S.1 4.5.40 Add rule AP.S.1
Add OD.S.1® , OD.W.1® , PO.S.1® , PO.S.2.LP® , PO.S.5.LP® ,
PO.S.5.GS® , PO.S.6.LP® , PO.S.6.GS® , PO.EX.1® ,
PO.EX.2® , CO.S.3® , CO.EN.1® , CO.EN.1.1® , CO.EN.3® ,
8. 4.5.47 SRAM Rule CO.R.5g, M1.S.1® , M1.A.1® , M1.EN.1® , M1.EN.2® ,
M1.EN.5® , VIA1.EN.2® , VIA1.EN.1® , M2.S.1® , M2.A.1® ,
M2.EN.1® , M2.EN.2® , VIA2.EN.1® , VIA2.EN.2® , M3.S.1® ,
M3.A.1® , M3.EN.1® , M3.EN.2® in table 4.5.47.2
9. 4.5.54.1 Guidelines for Placing Seal Ring Update seal-ring GDS
10. AP.W.3 4.5.54.4.1 Seal Ring Wall Layout Rules Modify rule
11. AP.EN.2 4.5.54.4.1 Seal Ring Wall Layout Rules Add rule AP.EN.2
12. 9.3 Model-based DFM Remove the chapter - Model-based DFM

1. 1.2 Reference Document Add automotive DRM in reference document
2. 3.5.1 N45/N40 Low Power (LP): 1.1V Core Design Update device truth table
DNW.R.7.2 4.5.2 Deep N-Well (DNW) Layout Rules (Mask ID: Add
3.
119) [Optional]
AP.S.1 4.5.40 Al Redistributional Layer (AP RDL) Layout Add
4.
5. MOM.R.6 4.5.42 MOM Layout Rules Add
4.5.42.1 MOM (Metal Oxide Metal) PDK Capacitor Wording enhancement (MOM with poly shielding
6.
Guidelines guideline)
7. A.R.0 4.5.52 Antenna Effect Prevention (A) Layout Rules Update
8. A.R.6.1 4.5.52 Antenna Effect Prevention (A) Layout Rules Add
12. A.R.8.3.1 4.5.52 Antenna Effect Prevention (A) Layout Rules Add
13. A.R.8.3.2 4.5.52 Antenna Effect Prevention (A) Layout Rules Add
SR.AP.W.3 4.5.54.4.1 Seal Ring Wall Layout Rules DRC/DRM alignment ( change rule no AP.W.3 and
14.
wording enhancement)
15. SR.R.5 4.5.54.4.1 Seal Ring Wall Layout Rules Add
16. AN.R.29mgU 7.3.4.1 Power and Ground Delete
17. 10.2.4 SR_ESD device Layout Rules (N40G only) Typo

1 1.2 Reference Document Add DENMOS DRM to align deck
4.5.2 Deep N-Well (DNW) Layout Rules (Mask ID: 119) Modify “DNW cut N+ ACTIVE” to “ N+ ACTIVE cut DNW”,
2 DNW.R.5
[Optional] align DRC coding
4.5.7 Thick Oxide (OD2) Layout Rules (Mask ID: 152) Modify “OD2 cut {ACTIVE OR GATE}” to “{ACTIVE OR
3 OD2.S.2
GATE} cut OD2”, align DRC coding
4.5.10 OD25_33 Layout Rules Modify “OD25_33 can’t cut GATE” to “GATE cut OD25_33
4 OD25_33.R.1
is not allowed”, align DRC coding
4.5.11 OD25_18 Layout Rules Modify “OD25_18 can’t cut GATE” to “GATE cut OD25_18
5 OD25_18.R.1
is not allowed”, align DRC coding
My Layout Rules (Mask ID: Second Inter-layer Metal
6 My.DN.1 4.5.34 (385, 386, 387, 388) and Top Metal (381, 384, 385, Modify
386, 387, 388, 389, 38A))
My Layout Rules (Mask ID: Second Inter-layer Metal
7 My.DN.1.a 4.5.34 (385, 386, 387, 388) and Top Metal (381, 384, 385, Add
386, 387, 388, 389, 38A))
Top Mz Layout Rules (Mask ID: 381, 384, 385, 386,
8 Mz.DN.1 4.5.36 Modify
387, 388, 389, 38A)
Top Mr Layout Rules (Mask ID: 386, 387, 388, 389,
9 Mr.DN.1 4.5.38 Modify
38A)
10 MOM.R.6 4.5.42 MOM Layout Rules Modify
11 Mu.DN.2 4.5.44 Mu (Ultra Thick Metal) Layout Rules Modify
12 IND.DN.4 4.5.45.1 INDDMY Layer Identified Inductor Layout Rules Delete
13 IND.DN.4.1 4.5.45.1 INDDMY Layer Identified Inductor Layout Rules Delete
14 IND_MD.DN.4 4.5.45.2 INDDMY_MD Layer Identified Inductor Layout Rules Delete
15 IND_MD.DN.4.1 4.5.45.2 INDDMY_MD Layer Identified Inductor Layout Rules Delete
16 SRAM.R.29 4.5.47 SRAM Rules Delete LP, only for LPG
17 A.R.8.7 4.5.52 Antenna Effect Prevention (A) Layout Rules Update
18 DRM.R.1 4.5.56 DRM and DRC Completeness Add
19 AN.R.86mgU 7.3.2 Matching Rules and Guidelines Add
20 AN.R.50mgU 7.4 Burn-in Guidelines for Analog Circuits Add
21 FPAD.R.1m® U 7.4 Burn-in Guidelines for Analog Circuits Add
22 DOD.S.4gU 8.1.1 DOD Layout Rules Delete
23 DPO.S.4gU 8.2.1 DPO Layout Rules Delete
24 DMx.S.6gU 8.6 Dummy Metal (DM) Rules Delete
DRC methodology to identify ESD MOS Source and
25 10.2.8.2 Modify wording from “not broken” to “broken” to align DRC
Drain
26 10.2.8.7 DRC methodology for finger width Modify wording from “not broken” to “broken” to align DRC

Eetop - CN TN45CLDR001 2 6

Uploaded by

Copyright:

Available Formats

Eetop - CN TN45CLDR001 2 6

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Eetop - CN TN45CLDR001 2 6

Uploaded by

Copyright:

Available Formats

SECURITY B

tsmc Taiwan Semiconductor Manufacturing Co., LTD

Ver. Eff_Date ECN No. Author Change Description

2.5 09-19-18 E120201838097 M. H. Yang Please refer to Appendix A.12 Revision

2.4 07-29-16 E120201631098 M. S. Hsieh Please refer to Appendix A.11 Revision

Document No. : T-N45-CL-DR-001

Ver. Eff_Date ECN No. Author Change Description

2.2 12-01-14 E120201436190 Y. L. Chen Please refer to Appendix A.9 Revision

2.1 06-28-13 E120201316032 Y. L. Chen 1.Please refer to Appendix A.8 Revision

2.0 07-31-12 E120201231088 C. M. Kao Please refer to Appendix A.7 Revision

1.3_1 12-15-10 E070201048072 C. M. Kao Please refer to Appendix A.6 Revision

1.3 09-03-10 E070201036011 M. C. Lee Please refer to Appendix A.5 Revision

1.2 09-30-09 E070200935010 Y. M. Chen Please refer to Appendix A.4 Revision

1.1 06-30-08 E120200826098 C. H. Lu Please refer to Appendix A.3 Revision

1.0 01-31-08 E120200802093 C. H. Lu Please refer to Appendix A.2 Revision

0.2 10-18-07 E120200742028 C. H. Lu Please refer to Appendix A.1 Revision

0.04 01-05-07 E120200704034 C. T. Tsai Original

TSMC 45/40 NM CMOS LOGIC AND

Document No. : T-N45-CL-DR-001

TSMC 45/40 NM CMOS LOGIC AND MS_RF DESIGN RULE

9 DESIGN FOR MANUFACTURING (DFM) ...................................................................................................................... 368

Warning: All tape-outs MUST be DRC clean.

1.2 Reference Document

2.1 Semiconductor Process

2.1.1 Front-End Features

 Triple gate oxide process

**D299 and D589 in N40GL process belong to N40G.

 Self-aligned Ni-silicided drain, source, and gate

2.1.2 Back-End Features

Table 2.2.1 Available Vt in each technology

2.3 Power Supply and Operation Temperature

Figure 2.4.1 Cross-section for 1P10M_7x2z

Cross section (1P10M as inter Mx, top My(2XTM))

Figure 2.4.2 Cross-section for 1P10M_7x2y

Cross section (1P10M as inter Mx/My, top Mz(TM))

Figure 2.4.3 Cross-section for 1P10M_5x2y2z

Cross section (1P10M as inter Mx, top Mr)

Figure 2.4.4 Cross-section for 1P10M_7x2r

Cross section (1P10M as inter Mx, top Mz/Mu (TM))

Figure 2.4.5 Cross-section for 1P10M_7x1z1u

Cross section (1P10M as inter Mx, top My(2XTM)/Mu(TM))

Figure 2.4.6 Cross-section for 1P10M_7x1y1u

2.5 Metallization Options

Table 2.5.1 N40G/N45LP/N40LP/N45LPG/N40LPG Naming for Different Metal

Metal type Code N40G/ Mask layers

Table 2.5.2 N40G/N45LP/N40LP/N45LPG/N40LPG Naming for Different Via Types

Via type Code N40G/ Mask layers

Table 2.5.5 Metallization Options for Mr

3 General Layout Information

3.1 Mask Information, Key Process Sequence,

FBEOL option2 (Flip chip without AP RDL)

FBEOL option3 (Wire bond with AP RDL)

FBEOL option4 (Flip chip with AP RDL)

FBEOL option2 (Flip chip without AP RDL)

FBEOL option3 (Wire bond with AP RDL)

FBEOL option4 (Flip chip with AP RDL)

FBEOL option1 (Wire bond without AP RDL)

FBEOL option2 (Flip chip without AP RDL)

FBEOL option3 (Wire bond with AP RDL)