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This document provides details about a major project on designing and implementing an FPGA-based system for detecting arrhythmic ECG signals using VHDL. The project was undertaken by two students, Nayini Srija and Sai Abhinav Reddy Gogula, under the guidance of Dr. D. Haripriya at Anurag University's Department of ECE for the academic year 2023-2024. The abstract describes the proposed system which leverages an FPGA implementation with Verilog HDL to identify ventricular fibrillation and ventricular tachycardia in ECG signals. It highlights features such as parallel processing, hardware acceleration, and a modular architecture to enable accurate and efficient real-time arr

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32 views4 pages

Abstract Sample

This document provides details about a major project on designing and implementing an FPGA-based system for detecting arrhythmic ECG signals using VHDL. The project was undertaken by two students, Nayini Srija and Sai Abhinav Reddy Gogula, under the guidance of Dr. D. Haripriya at Anurag University's Department of ECE for the academic year 2023-2024. The abstract describes the proposed system which leverages an FPGA implementation with Verilog HDL to identify ventricular fibrillation and ventricular tachycardia in ECG signals. It highlights features such as parallel processing, hardware acceleration, and a modular architecture to enable accurate and efficient real-time arr

Uploaded by

gogulaabhinavreddy15
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We take content rights seriously. If you suspect this is your content, claim it here.
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ANURAG UNIVERSITY

DEPARTMENT OF ECE
ACADEMIC YEAR: 2023–2024
MAJOR PROJECT WORK DETAILS AND ABSTRACT

Title of the project: “Design and Implementation of FPGA


based arrhythmic ECG signals using VHDL.”

Project Batch Number: C21

Project Associates:
S.No Roll No. Name
1 20EG104320 Nayini Srija
2 20EG104335 Sai Abhinav Reddy Gogula

Project Guide Dr. D. Haripriya

Signature of Guide
ABSTRACT:
This project presents a approach for arrhythmia detection in electrocardiogram (ECG)
signals using a Field-Programmable Gate Array (FPGA) implementation with Verilog
Hardware Description Language (HDL). The proposed system focuses on the
identification of Ventricular Fibrillation/Ventricular Tachycardia to enhance the
accuracy and real-time processing capabilities of traditional ECG monitoring systems.
The FPGA-based arrhythmia detection system leverages parallel processing and
hardware acceleration to achieve low-latency, high-throughput analysis of ECG
signals. The Verilog HDL is employed for efficient hardware design, enabling the
implementation of complex algorithms for signal processing and feature extraction. The
system incorporates a comprehensive set of signal processing techniques, including
filtering, feature extraction, and classification algorithms, to discern Ventricular
Fibrillation/Ventricular Tachycardia from abnormal heartbeats.
The design utilizes a scalable and modular architecture, allowing for easy customization
and adaptation to different arrhythmia detection scenarios. The FPGA implementation
enhances the computational efficiency of the system, making it well-suited for real-
time applications such as continuous ECG monitoring in clinical settings. The proposed
solution not only offers accurate detection of arrhythmia but also ensures rapid response
times critical for timely medical intervention.
Experimental results demonstrate the effectiveness of the FPGA-based arrhythmia
detection system in accurately identifying Ventricular Fibrillation/Ventricular
Tachycardia. The system exhibits promising performance metrics, including
sensitivity, specificity, and overall accuracy, highlighting its potential as a robust and
efficient solution for real-time arrhythmia detection in clinical environments. The
proposed FPGA-based approach contributes to the advancement of ECG monitoring
systems by providing a hardware-accelerated solution that combines accuracy, speed,
and adaptability.
BLOCK DIAGRAM:
REFERENCES:
[1] Yared Daniel Daydulo, Bheema Lingaiah Thamineni, and Ahmed Ali Dawud,
“Cardiac arrhythmia detection using deep learning approach and time frequency
representation of ECG signals,” BMC Medical Informatics and Decision Making, vol.
23, no. 1, Oct. 2023, doi: https://doi.org/10.1186/s12911-023-02326-w.
[2] L. V. R. Kumari, Y. P. Sai, N. Balaji, and K. Viswada, “FPGA Based Arrhythmia
Detection,” Procedia Computer Science, vol. 57, pp. 970–979, 2015, doi:
https://doi.org/10.1016/j.procs.2015.07.495.
[3] M. Hossain, M. Sheikh, A. Islam, Uddin, Hossain, and Khan, “FPGA based Heart
Arrhythmia’s Detection Algorithm FPGA based Heart Arrhythmia’s Detection
Algorithm,” ACEEE Int. J. on Information Technology, vol. 3, no. 1, p. 4, 2013.
[4] S. Modepalli and S. Nag, “International Journal of Research Publication and
Reviews Efficient FPGA Implementation of a Real-Time ECG Arrhythmia Detection
Algorithm for Wearable Healthcare Devices,” International Journal of Research
Publication and Reviews, vol. 4, no. 11, pp. 1575–1585, 2023.
[5] K. Meddah, M. Kedir Talha, M. Bahoura, and H. Zairi, “FPGA‐based system for
heart rate monitoring,” IET Circuits, Devices & Systems, vol. 13, no. 6, pp. 771–782,
Aug. 2019, doi: https://doi.org/10.1049/iet-cds.2018.5204.
[6] Y.-H. Chen, C.-W. Lu, S.-W. Chen, M.-H. Tsai, S.-Y. Lin, and R.-S. Chen, “VLSI
Implementation of QRS Complex Detector Based on Wavelet Decomposition,” IEEE
Access, vol. 10, pp. 134758–134768, 2022, doi:
https://doi.org/10.1109/access.2022.3231267.
[7] F. Karataş, İ. Koyuncu, M. Alçın, and M. Tuna, “Design and implementation of
FPGA-based arrhythmic ECG signals using VHDL for biomedical calibration
applications,” International Advanced Researches and Engineering Journal, vol. 05,
no. 03, pp. 0-0003, 2021, doi: https://doi.org/10.35860/iarej.918874.

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