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ELEC 3509 Lab 3 - New

This lab report examines the performance of a 741 operational amplifier circuit. Simulation results were compared to theoretical calculations of the circuit's parameters, including differential gain, input offset voltage, transistor gains, slew rate, frequency response, and cutoff frequency. The simulations matched closely with predicted values, validating the circuit design and analysis. Engaging in both theoretical calculations and practical simulations provided a valuable learning experience about operational amplifier characteristics.

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0% found this document useful (0 votes)
65 views17 pages

ELEC 3509 Lab 3 - New

This lab report examines the performance of a 741 operational amplifier circuit. Simulation results were compared to theoretical calculations of the circuit's parameters, including differential gain, input offset voltage, transistor gains, slew rate, frequency response, and cutoff frequency. The simulations matched closely with predicted values, validating the circuit design and analysis. Engaging in both theoretical calculations and practical simulations provided a valuable learning experience about operational amplifier characteristics.

Uploaded by

孫笑川258
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ELEC 3509 Lab 3

Lab 3 Report

Student: Elias Zhu


Student number: 101228812
Objective:

This laboratory exercise aims to acquaint students with a two-stage operational amplifier (op-

amp). Historically, the 741 op-amp served as a cornerstone in the field of circuit engineering

due to its cost-effectiveness and commendable performance, particularly at audio

frequencies. However, advancements in technology have led to the development of op-amps

that surpass the capabilities of their predecessors. Modern op-amps exhibit superior speed,

affordability, compactness, reduced noise, and enhanced efficiency. Furthermore, the shift

towards digital signal processing is gradually rendering traditional op-amp filters obsolete.

Introduction:

The analysis of the operational amplifier involves the examination of transistor parameters

within the circuit. Subsequently, these parameters are simulated using Multisim to compare

calculated and measured values. Figure 1 depicts the schematic of the 741 op-amp utilized

in this experiment, while Figure 2 provides the corresponding parameter values.

Figure 2: The component values


*Prelab is attached in appendix B.
Questions

1. Explain the difference in role of V10 and V5. Why are both needed?

The DC voltage at the input, denoted as V10, is employed for calculating the

differential voltage, while V5 is supplied to Q1 and Q2 to determine the

common-mode input voltage.

2. What is the purpose of Q7 and R3 in this circuit? What difference would there be if

instead of both, the collector and base of Q5 were shorted as in the current mirror

in Lab 1? You may want to consider the impact of Q16.

Q7 and R3 collaborate to establish a current mirror circuit, functioning as an

active load for the input. If Q5 experiences a short, Q16 will generate a

substantial IB, potentially destabilizing the circuit.

3. What is the role of C1 and what would happen if it were absent?

To curtail noise in the output, C1 is utilized to limit the frequency.

4. The circuit uses ideal current sources. How would these be implemented in a real

circuit? What differences in performance might be seen as a result? The answer is


not finite output impedance since the output impedances are already modeled by

R11, R12 and R13.

In practical design, it would be substituted with a current mirror, resulting in

a different gain.

5. What is the purpose of V2? How would V2 be implemented in a real circuit?

V2 serves the purpose of providing a stable biasing voltage to Q14 and Q20

6. Why are 3 stages used in this op-amp design? Why bother with the third stage if it

provides such a low gain?

The three stages encompass the differential input stage, the gain stage, and the

output stage. The initial stage serves as the input, the second stage regulates

the overall circuit gain, and the final stage establishes a quiescent bias current

in the output transistors.

7. What is the DC power consumption of the entire circuit (assume no input signal).

The DC power consumption of the entire circuit is attributable to both the

current sources and the voltage sources.


Simulation:
Differential Sweep

1. The DC sweeps.

The DC sweeps are shown in figure 3.

Figure 3: The DC sweeps

The transition is between 1.7V and 4.9V

The output voltage swings is shown in Figure 3 as well.

The output swing = 4.9V – 1.6V = 3.3V

Compare to prelab value (3.2V), they are very close.

The differential gain -35kv/v, which is different from theoretical value -51kv/v.

This error may due to cursors are not located at exact right position. The actual

value in lad should be around -50kv/v, since the result matches prediction. The

error may be from measurement mistake.

The input offset voltage (Vd) as below figure 5 shows.


Figure 4: The input offset voltage (Vd)

The input offset is 515.67μV

2. Transistor parameter

The comparison of pre-lab calculated values and experimental value is shown below.

Table 1: pre-lab in-lab value comparison

*detailed data is listed in appendix A

Actual gain is calculated below.


Stage 1 gain.

Rout1 = ro6 (1+gm6 (R2 // rΠ2)) + (R2 // rΠ2)

= 7.35MΩ * (1 + 394ΜA/V * (1kΩ//(193/404μA/V))) + (1kΩ//(193/404μA/V)

=10.25MΩ

=(95.969+1)[95.969/(95.969+1)*1/(757μA/V)+3.968MΩ//50KΩ//(126.865/(2

6 mA/V)+100Ω+126.865/(26 mA/V)*100Ω*26 mA/V

= 1.39MΩ

RL1 = Rout1 // Rin2 = (10.25//1.39)MΩ = 1.22MΩ

Av1 = 4.4μA/V (1.22MΩ // 7.35MΩ // 1.90MΩ) = 272.5

Stage 2 Gain calculation:

Rin 3 = RL = 17.21MΩ
→ Av2 = -(r_o16//R_9//(r_π17+R_8+r_π17*R_8*g_m17))/( 〖 r_e16+r 〗

_o16//R_9//(r_π17+R_8+r_π17*R_8*g_m17))*(g_m17

(R_L//R_12))/(1+R_8*g_m17+R_8/r_π17 )

Av2 = -195v/v

Stage 3 gain

Av3 = 1v/v

Total gain = Av1*Av2*Av3 = 53.1 kv/v

Table 2: gain comparison between prelab and in-lab data

According to the data comparison, the in-lab value meets the expected value calculated
in prelab section. The main difference may be due to the β assumption is different

from the actual β parameter.

3. Vo vs V5

Figure 5: Vo vs V5 at dc sweep condition

4. Slew rate

Figure 6: slew rate at positive


Positive slew rate = 289.83kv/s = 0.29 v/μs

Figure 7: negative slew rate

Negative slew rate = -273kv/s = -0.27v/μs

The pre-lab prediction of slew rate is around 0.31 V/μs, it somewhat close to

the experimental value, however there is still gap between two sets of value.

More research may be needed.


5. Frequency response

Figure 8: Frequency response graph

The unity gain point is found in the plot around 1.026MHz. This is very close

to predicted value 1MHz from prelab.

The max/initial gain in the plot has a gain 95dB


Figure 9: cutoff frequency

Cutoff frequency is found about 19Hz, it meets the prediction.

Hardware testing:
Comment: The waveform and magnitude proves that the experiment matches

the reality and predicts the correct behavior of circuit.

Conclusion:

In summary, this experiment is structured to scrutinize the characteristics of

741 operational amplifiers. The analysis involves evaluating and comparing the
calculated and simulated parameters of the operational amplifier transistors.

Additionally, simulations and calculations were performed for the common-

mode range and slew rate. The observed amplitude of the signal amplified by

the operational amplifier contributed valuable insights. Engaging with

simulation software during this lab has equipped us with practical experience,

which is anticipated to be instrumental in our future endeavors.

Appendix A: parameter found for transistors

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