8086 Instruction Set - 1

 Data transfer instructions (including I/O

transfers),
 Binary arithmetic instructions,
 Decimal (BCD, ASCII) arithmetic instructions,
 Logical instructions,
 Shift and rotate instructions,
 Control transfer instructions.

2/3/2024 1
 Data Transfer Instructions

2/3/2024 2
 Data Transfer instructions essentially
copy the data and do not affect any flags
(except of course the POPF instruction
which modifies all the flags as per the
stack top word)

2/3/2024 3
MOV
 Stands for move, it is actually copy, that is, when
data is moved from one register source to a
destination register, source is not destroyed,
only, there will be a copy of this data in the
destination register

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XCHG
 Exchange instruction exchanges data between
registers or between register and memory

2/3/2024 5
PUSH

 Push causes the data in the source register to

be copied on to the stack top

2/3/2024 6
POP
 Pop causes the stack top moved to (that is,
removed from the stack and loaded onto) the
destination register or memory specified by the
instruction

2/3/2024 7
 IN: Copy data from a port
IN accumulator, port
 The IN instruction reads from an input port into
AL or AX (only these two registers), to be
specified in the instruction

 The port address is generally in the register DX

 But if it is 8-bits or less, then it can also be

directly given in the instruction

2/3/2024 8
  Ex:
IN AL,0C8H;Input a byte from port address 0C8H to AL
IN AX,34H; Input a word from port address 034H to AX

MOV DX,0FF78H ;Initialize DX to point to port

IN AL, DX ;Input a byte from 8 bit port 0FF78h to AL
IN AX,DX ; Input a word from 16 bit port 0FF78h to AX

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OUT: output a byte or word to a port
OUT port, accumulator

 The OUT instruction outputs the data in register

AX or AL (only) to be specified in the instruction
to the output port indicated directly in the
instruction if the port address is 8 bits or less, or
in the register DX (for addresses 16 bits or less)

2/3/2024 10
Examples:

out 16h, ax; write to output port at address 16h from reg. ax

out dx, ax; write to output port at address in dx from reg. ax

out 23h, al; write to output port at address 23h from reg al

out dx, al; write to output port at address in dx from reg al

2/3/2024 11
CBW (Convert byte to word)
 The source register AL and the destination AX
are both implied and not specifically mentioned
in this instruction

 This instruction is used to extend the 8-bit

integer (signed number) in reg. AL to 16- bit
integer in AX

 The process is called sign extension

2/3/2024 12
 If the number in AL is positive, AH will be loaded
with 00 hex, else AH will be loaded with FF hex

Example: cbw

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CWD (Convert Word to Double Word)

 Convert word in reg. AX (implied and not stated

in the instruction) to double word in regs. DX:AX
(also implied and not stated)

 That is, sign extend from AX into DX:AX

Example: cwd

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 Among all the data transfer instructions
popf is the only instruction that affects and
modifies the flags

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 Binary Arithmetic Instructions

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 All binary arithmetic instructions update
the flag register based on the result of the
operation performed

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ADD
 Adds the first operand (destination operand) and
the second operand (source operand) and
stores the result in the destination operand

 The destination operand can be a register or a

memory location; the source operand can be an
immediate, a register, or a memory location

 Two memory operands cannot be used in

one instruction

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 When an immediate value is used as an operand, it is
sign-extended to the length of the destination operand
format

 The ADD instruction performs integer addition

DEST ← DEST + SRC;

 The OF, SF, ZF, AF, PF, and CF flags are set according
to the result

Examples: ADD AX, BX

ADD [BX + 4], DX
ADD CX, 2[SI]
ADD DX, 123 H
2/3/2024 19
ADC
 Adds with carry

 Same as ADD with the following change in the

operation:

DEST ← DEST + SRC + CF;

 The OF, SF, ZF, AF, PF, and CF flags are set
according to the result

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Example…
data segment
a db 0ABh
b db 0A5h
c dw ?
data ends
code segment
assume cs:code, ds:data
start:
mov ax, data
mov ds, ax
mov al, a
add al, b
mov ah, 00h
adc ah, 00h
mov c, ax
mov ah, 4ch
int 21h
code ends
end start

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SUB
 Subtraction

 Follows the same rules as ADD with the

following change in the operation:

DEST ← DEST – SRC;

 The OF, SF, ZF, AF, PF, and CF flags are set
according to the result

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SBB
 Subtract with borrow

 Same as SUB with the following change in the

operation:

DEST ← DEST – (SRC + CF);

 The OF, SF, ZF, AF, PF, and CF flags are set
according to the result

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CMP

 Compare two operands

 Compares the first source operand with the second

source operand and sets the status flags in the
FLAGS register according to the results

 The comparison is performed by subtracting the

second operand from the first operand and then
setting the status flags in the same manner as the
SUB instruction

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 When an immediate value is used as an operand, it is
sign extended to the length of the first operand

Operation:

temp ← SRC1 − SRC2;

 In case an immediate value is used, then

temp ← SRC1 − Sign Extend (SRC2);

 The CF, OF, SF, ZF, AF, and PF flags are set
according to the result

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 Examples:

CMP AX, 24 H; (24 is sign extended to 16 bits before

subtraction, because AX is a 16-bit register)

CMP BYTEPTR[BX], -24 H; (no sign extension done,

data in bytes are being handled)

CMP BX, SI

CMP AL, [BX]; (BX will be taken only as a byte pointer,

as AL is a byte register)

2/3/2024 26
MUL

 Performs an unsigned multiplication of the first

operand (destination operand) and the second
operand (source operand) and stores the result
in the destination operand

 The destination operand is an implied operand

located in register AL or AX (depending on the
size of the operand)

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 The source operand is located in a general-
purpose register or a memory location

Operation:

IF byte operation
THEN
AX ← AL ∗ SRC
ELSE (* word operation *)
DX:AX ← AX ∗ SRC

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 Flags Affected

The OF and CF flags are set to 0 if the upper half of

the result is 0; otherwise, they are set to 1

The SF, ZF, AF, and PF flags are undefined

Examples:
MUL BX
MUL WORDPTR [BX + DI]48 H
MUL BYTEPTR [SI]
MUL CL

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IMUL : multiply signed numbers
IMUL source
 Integer (signed) multiply

 Similar to MUL, except the data are considered

as signed integers

 Flags are also affected similarly as for MUL

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Examples:
IMUL BH ;Signed byte in AL times signed byte
in BH ; result in AX
;69x14
;AL=01000101=45h=69 decimal
;BH=0000 1110=0Eh=14 decimal
IMUL BH;AX=03C6H=+966 decimal
; MSB=0,positive result magnitude in true form.

;-28x59
;AL=11100100=E4H=-1CH=-28 decimal
;BH=00111011=3BH=+59 decimal
IMUL BH;AX=F98CH=-1652 decimal
;MSB=1,negative result magnitude in 2’s complement form.

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DIV:

 Divide the unsigned integer dividend in the

accumulator by the unsigned integer divisor
specified in the instruction

 If the divisor specified is a word register or word

memory, the dividend is considered to be the double
word in DX:AX and the quotient of division will be in
register AX, with the remainder in register DX and
the divisor word specified in the instruction will not
be altered

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 If the divisor specified in the instruction is a byte
register or byte memory, then the accumulator
will be the word register AX

 The quotient of the division will be in AL register,

and AH register will have the remainder

 In case of word division, if the divisor word is not

greater than the part of the dividend word in DX,
then the quotient obviously will not fit into the
register AX

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 Execution of DIV instruction in such a case will
cause a division overflow exception to be
generated, and operating system should take
care of this exception

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Examples of DIV instruction:

DIV BX;
DIV WORDPTR [DI];
DIV CL;
DIV BYTEPTR [SI];

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IDIV : devide by signed byte or word
IDIV source

 Integer divide, same as DIV but the data and the

results are considered as signed integers

 The CF, OF, SF, ZF, AF, and PF flags are

undefined, when IDIV is executed

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Examples:
IDIV BH ;Signed word in AX/ signed byte in BH;

;AX=00000011 10101011=03ABH=939 decimal

;BH=1101 0011=D3=-2DH=-45 decimal
IDIV BH ;Quotient: AL=ECH=-14H=-20 decimal
;remainder: AH=27H=+39 decimal

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INC
 Increment register or memory

 This involves only a single operand

 Adds 1 to the destination operand, while

preserving the state of the CF flag

 The destination operand can be a register or a

memory location

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 This instruction allows a loop counter to be updated
without disturbing the CF flag

 If we use an ADD instruction with an immediate

operand of 1 to perform an increment operation that
does update the CF flag

Operation:
DEST ← DEST + 1;

 The CF flag is not affected. The OF, SF, ZF, AF,

and PF flags are set according to the result

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DEC
 Similar to INC, this instruction does the
operation:
DEST ← DEST – 1;

 The CF flag is not affected

 The OF, SF, ZF, AF, and PF flags are set

according to the result

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NEG: Form 2’s complement
NEG destination
 Replaces the value of operand (the destination
operand) with its two’s complement

 This operation is equivalent to subtracting the

operand from 0

 The destination operand is located in a general-

purpose register or a memory location
DEST ← – (DEST)

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Flags Affected

 The CF flag set to 0 if the source operand is 0;

otherwise it is set to 1

 The OF, SF, ZF, AF, and PF flags are set

according to the result

 Ex: ;AL=0000 0110H=06H

NEG AL ; replace number in AL with its 2’s complement
;RESULT:1111 1010=FAH

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 Decimal (BCD, ASCII)
Arithmetic Instructions

2/3/2024 43
DAA: Decimal adjust accumulator (AL) after BCD
addition
 Adjusts the sum of two packed BCD values to
create a packed BCD result

 The AL register is the implied source and

destination operand

 The DAA instruction is only useful when it

follows an ADD instruction that adds (binary
addition) two 2 - digit, packed BCD values and
stores a byte result in the AL register

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 The DAA instruction then adjusts the contents of
the AL register to contain the correct 2-digit,
packed BCD result

 If a decimal carry is detected, the CF and AF

flags are set accordingly

 If the lower nibble in AL after an addition is

greater than 9 or AF was set by the addition,
then the DAA instruction will add 6 to the lower
nibble in AL

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 If the result in the upper nibble of AL is now
greater then 9 or if the carry flag was set by the
addition or correction, then DAA instruction will
add 60H to AL

2/3/2024 46
Example 1:
; AL = 0101 1001 = 59 BCD
; BL = 0011 0101 = 35 BCD
ADD AL, BL ; AL = 1000 1110 = 8EH
DAA ; Add 0110 Because 1110 > 9
; AL = 1001 0100 = 94 BCD

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Example 2:
; AL = 1000 1000 = 88 BCD
; BL = 0100 1001 = 49 BCD
ADD AL, BL ; AL = 1101 0001=D1h, AF = 1
DAA ; Add 0110 because AF=1
; AL = 1101 0111 = D7H
; 1101 > 9 so add 0110 0000
; AL = 0011 0111 = 37 BCD, CF = 1

2/3/2024 48
 Flags affected

 The CF and AF flags are set if the adjustment of

the value results in a decimal carry in either digit
of the result

 The SF, ZF, and PF flags are set according to

the result

 The OF flag is undefined

2/3/2024 49
DAS: Decimal adjust after BCD subtraction
 Adjusts the result of the subtraction of two packed
BCD values to create a packed BCD result

 The AL register is the implied source and destination

operand

 The DAS instruction is only useful when it follows a

SUB instruction that subtracts (binary subtraction)
one 2-digit packed BCD value from another and
stores a byte result in the AL register

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 The DAS instruction then adjusts the contents of the
AL register to contain the correct 2-digit, packed
BCD result

 If a decimal borrow is detected, the CF and AF flags

are set accordingly

 The CF and AF flags are set if the adjustment of the

value results in a decimal borrow in either digit of the
result

 The SF, ZF, and PF flags are set according to the

result. The OF flag is undefined

2/3/2024 51
Examples:
;AL=1000 0110=86BCD
; BH=0101 0111=57BCD
SUB AL,BH ;AL=0010 1111=2FH,CF=0
DAS ;Lower nibble of result is 1111,so DAS automatically subtracts
0000 0110 to give AL=0010 1001=29BCD

;AL=0100 1001=49BCD
;BH=0111 0010=72BCD
SUB AL,BH ;AL=1101 0111=D7H,CF=1
DAS ;Subtracts 0110 0000(-60H) bcoz 1101 in upper nibble >9
;AL=01110111=77BCD,CF=1
;CF=1 means borrow was needed

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AAA: ASCII adjust AL after addition
 Adjusts the sum of two unpacked BCD values to
create an unpacked BCD result

 The AAA instruction works only on the AL

register .It is the implied source and destination
operand for this instruction

 The AAA instruction is only useful when it

follows an ADD instruction that adds (binary
addition) two unpacked BCD values and stores a
byte result in the AL register
2/3/2024 53
Example:
;assume AL=0011 0101,ASCII5 BL=0011 1001,ASCII 9

ADD AL,BL; Result: AL=01101110=6EH,Which is

incorrect BCD

AAA; Now AL=0000 0100,Unpacked BCD 4.

;CF=1 indicates answer is 14 decimal

2/3/2024 54
 The AAA instruction then adjusts the contents of the
AL register to contain the correct 1-digit unpacked
BCD result

 If the addition produces a decimal carry, the AH

register increments by 1, and the CF and AF flags
are set

 If there was no decimal carry, the CF and AF flags

are cleared and the AH register is unchanged

 In either case, bits 4 through 7 of the AL register are

set to 0
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 The AF and CF flags are set to 1 if the
adjustment results in a decimal carry otherwise
they are set to 0

 The OF, SF, ZF, and PF flags are undefined

2/3/2024 56
IF ((AL AND 0FH) > 9) OR (AF = 1)
THEN
AL ← AL + 6;
AH ← AH + 1;
AF ← 1;
CF ← 1;
ELSE
AF ← 0;
CF ← 0;
AL ← AL AND 0FH;

2/3/2024 57
AAS: ASCII adjust AL after subtraction
 Adjusts the result of the subtraction of two
unpacked BCD values to create a unpacked BCD
result

 The AL register is the implied source and

destination operand for this instruction

 The AAS instruction is only useful when it follows

a SUB instruction that subtracts (binary
subtraction) one unpacked BCD value from
another and stores a byte result in the AL
2/3/2024 58
 The AAA instruction then adjusts the contents of
the AL register to contain the correct 1-digit
unpacked BCD result

 If the subtraction produced a decimal carry, the

AH register decrements by 1, and the CF and
AF flags are set. If no decimal carry occurred,
the CF and AF flags are cleared, and the AH
register is unchanged

 In either case, the AL register is left with its top

nibble set to 0

2/3/2024 59
Example:
;assume BL=0011 1001=39h=ASCII 9
AL=0011 0101=35h=ASCII5
ASCII9-ASCII5
SUB AL,BL ; Result: AL=0000 0100=BCD 04 and CF=0
AAS ; result:AL=0000 0100= BCD 04 and CF=0;no borrow required

;assume AL=0011 0101=35h=ASCII5

BL=0011 1001=39h=ASCII 9
;ASCII 5-ASCII9
SUB AL,BL; Result: AL=1111 1100=-4 in 2’s compliment and CF=1

AAS; result: AL=0000 0100= BCD 04 and CF=1; borrow needed

2/3/2024 60
IF ((AL AND 0FH) > 9) OR (AF = 1)
THEN
AL ← AL – 6;
AH ← AH – 1;
AF ← 1;
CF ← 1;
ELSE
CF ← 0;
AF ← 0;
AL ← AL AND 0FH;

2/3/2024 61
AAM: ASCII adjust AX after multiply
 Adjusts the result of the multiplication of two
unpacked BCD values to create a pair of
unpacked (base 10) BCD values

 AAM works only after the multiplication of two

unpacked BCD bytes and it works only on an
operand in AL.

 After the 2 unpacked BCD digits(one BCD digit

per byte) are multiplied, the AAM instruction is
used to adjust the product to two unpacked BCD
digits in AX
2/3/2024 62
 The AAM instruction then adjusts the contents of
the AX register to contain the correct 2-digit
unpacked (base 10) BCD result

Example:
;AL=0000 0101=unpacked BCD 5
; BH=0000 1001=unpacked BCD 9
MUL BH ;AL x BH; result in AX
;AX=00000000 00101101=002DH
AAM ;AX=00000100 00000101=0405H
;which is unpacked BCD for 45
2/3/2024 63
AAD: ASCII adjust AX before division

 AAD converts two unpacked BCD digits in AH and AL to

the equivalent binary number in AL

 Adjusts two unpacked BCD digits (the least significant

digit in the AL register and the most significant digit in
the AH register) so that a division operation performed
on the result will yield a correct unpacked BCD value

 The AAD instruction is only useful when it precedes a

DIV instruction that divides (binary division) the adjusted
value in the AX register by an unpacked BCD value

2/3/2024 64
 The AAD instruction sets the value in the AL register
to (AL + (10 * AH)), and then clears the AH register
to 00H

 The value in the AX register is then equal to the

binary equivalent of the original unpacked two digit
(base 10) number in registers AH and AL

2/3/2024 65
Example:
;AX =0607H unpacked BCD for 67 decimal
;CH=09H
AAD; result: AX=0043=43H=67 decimal
DIV CH; devide AX by unpacked BCD in CH
;quotient:AL=07 unpacked BCD
;remainder : AH=04 unpacked BCD
;flags undefined after DIV

2/3/2024 66
 Logical Instructions

2/3/2024 67
AND

 Performs a bitwise AND operation on the

destination (first) and source (second) operands
and stores the result in the destination operand
location

 The source operand can be an immediate, a

register, or a memory location; the destination
operand can be a register or a memory location

2/3/2024 68
 Each bit of the result is set to 1 if both
corresponding bits of the first and second
operands are 1; otherwise, it is set to 0

Operation:
DEST ← DEST AND SRC;

Flags Affected:
 The OF and CF flags are cleared; the SF, ZF,
and PF flags are set according to the result; The
state of the AF flag is undefined

2/3/2024 69
OR
 Performs a bitwise inclusive OR operation
between the destination (first) and source
(second) operands and stores the result in the
destination operand location

 The source operand can be an immediate, a

register, or a memory location; the destination
operand can be a register or a memory location

2/3/2024 70
 Each bit of the result of the OR instruction is set
to 0 if both corresponding bits of the first and
second are 0; otherwise it is set to 1

Operation:
DEST ← DEST OR SRC;

Flags Affected:
 The OF and CF flags are cleared; the SF, ZF,
and PF flags are set according to the result; The
state of the AF flag is undefined

2/3/2024 71
XOR

 Performs a bitwise exclusive OR (XOR)

operation on the destination (first) and source
(second) operands and stores the result in the
destination operand location

 The source operand can be an immediate, a

register, or a memory location; the destination
operand can be a register or a memory location

2/3/2024 72
 Each bit of the result is 1 if the corresponding
bits of the operands are different; each bit is 0 if
the corresponding bits are the same

Operation:
DEST ← DEST XOR SRC;

Flags Affected:
 The OF and CF flags are cleared; the SF, ZF,
and PF flags are set according to the result; The
state of the AF flag is undefined

2/3/2024 73
NOT

 Performs a bitwise NOT operation (each 1 is set

to 0, and each 0 is set to 1) or does 1’s
complementing on the destination operand and
stores the result in the destination operand
location

 The destination operand can be a register or a

memory location

2/3/2024 74
 Operation:
DEST ← NOT DEST;

Flags Affected:
None

2/3/2024 75
TEST
 Bitwise AND the two sources operands, ignore the
outcome, but preserve the nature of the result in
the flag register

 This instruction computes the bit-wise logical AND

of first operand (source 1 operand) and the
second operand (source 2 operand) and sets the
SF, ZF, and PF status flags according to the result

 The result is then discarded

2/3/2024 76
 Operation:

TEMP ← SRC1 AND SRC2;

SF ← MSB(TEMP);
IF TEMP = 0
THEN ZF ← 1;
ELSE ZF ← 0;
PF ← Parity of the lower 8-bits of TEMP;
CF ← 0;
OF ← 0;
(*AF is Undefined*)

2/3/2024 77
 Shift and Rotate
Instructions

2/3/2024 78
 Shift and rotate instructions shift the data by one
or more bits towards either left or right, straight
or in a circular fashion

 The carry flag is always involved in these

operations

2/3/2024 79
Shift Instructions…

 Shift instructions position or move numbers to

the left or right within a register or memory
location

 Two are logical shifts and two are

arithmetic shifts

2/3/2024 80
 The logical shifts move a 0 into the
rightmost bit position for a logical left shift and
a 0 into the leftmost bit position for a logical
right shift

 The arithmetic and logical left shifts are

identical

2/3/2024 81
 The arithmetic and logical right shifts are
different because the arithmetic right shift
copies the sign-bit through the number,
while the logical right shift copies a 0
through the number

 Logical shift operations function with

unsigned numbers, and arithmetic shifts
function with signed numbers

2/3/2024 82
 Logical shifts multiply or divide unsigned
data, and arithmetic shifts multiply or divide
signed data

 A shift left always multiplies by 2 for each bit

position shifted, and a shift right always
divides by 2 for each bit position shifted

2/3/2024 83
 The logical shift instructions are SHL, SHR

 The arithmetic shift instructions are SAL,

SAR

2/3/2024 84
SHL – Shift Operand Bits Left, Put Zero in
LSBs

SHL Destination, Count

2/3/2024 85
 As a bit is shifted out of the LSB position, a
zero is put in the LSB position

 The MSB will be shifted to CF

CF  MSB LSB  0

2/3/2024 86
 If the desired number of shifts is 1, this can be
specified by putting a 1 in the count position of the
instruction

 For shifts of more than 1 bit position, the desired

number of shifts is loaded into the CL register

Example:
MOV CL, 05H
SHL AX, CL

2/3/2024 87
SAL – Shift Operand Bits Left, Put Zero in
LSBs

SAL Destination, Count

2/3/2024 88
 As a bit is shifted out of the LSB position, a
zero is put in the LSB position

 The MSB will be shifted to CF

CF  MSB LSB  0

2/3/2024 89
 If the desired number of shifts is 1, this can be
specified by putting a 1 in the count position of the
instruction

 For shifts of more than 1 bit position, the desired

number of shifts is loaded into the CL register

Example:
MOV CL, 05H
SAL AX, CL

2/3/2024 90
SHR – Shift Operand Bits Right, New MSB = 0

SHR Destination, Count

2/3/2024 91
 This instruction shifts each bit in the specified
destination some number of bit positions to
the right

 As a bit is shifted out of the MSB position, 0

is put in the MSB position

 The LSB will be shifted into CF

2/3/2024 92
0  MSB LSB  CF

2/3/2024 93
 If the desired number of shifts is 1, this can be
specified by putting a 1 in the count position of
the instruction

 For shifts of more than 1 bit position, the desired

number of shifts is loaded into the CL register

Example:
MOV CL, 03H
SHR AL, CL

2/3/2024 94
SAR

2/3/2024 95
 This Arithmetic shift right instruction copies
the sign bit through the number

SAR Destination, Count

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 If the desired number of shifts is 1, this can be
specified by putting a 1 in the count position of the
instruction

 For shifts of more than 1 bit position, the desired

number of shifts is loaded into the CL register

Example:
MOV CL, 03H
SAR AL, CL

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ROL – Rotate All Bits of Operand Left, MSB
to LSB
ROL Destination, Count
 This instruction rotates all the bits in a
specified word or byte to the left some number
of bit positions

CF MSB LSB

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 If the desired number of shifts is 1, this can
be specified by putting a 1 in the count
position of the instruction

 For shifts of more than 1 bit position, the

desired number of shifts is loaded into the CL
register

Example:
MOV CL, 03H
ROL AL, CL

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ROR – Rotate All Bits of Operand Right,
LSB to MSB
ROR Destination, Count
 This instruction rotates all the bits in a
specified word or byte to the right some
number of bit positions

CF MSB LSB

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 If the desired number of shifts is 1, this can be
specified by putting a 1 in the count position of the
instruction

 For shifts of more than 1 bit position, the desired

number of shifts is loaded into the CL register

Example:
MOV CL, 03H
ROR AL, CL

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 For the ROL and ROR instructions, the original
value of the CF flag is not a part of the result,
but the CF flag receives a copy of the bit that
was shifted from one end to the other

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RCL (Rotate Left including carry)
 The RCL instruction shifts the CF flag into the
least-significant bit and shifts the most
significant bit into the CF flag

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RCR (Rotate Right including carry)
 The RCR instruction shifts the CF flag into the
most-significant bit and shifts the least-
significant bit into the CF flag

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2/3/2024 105
 Control Transfer
Instructions

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 The intelligence in any program lies in the ability
of the program to follow different courses of
action based on intermediate results produced
during the working of the program; that way, the
program is enabled to perform data sensitive
tasks

 This capability is obtained by context sensitive

jump operations, in contrast to the normal
sequential cyclical operation of fetching the next
instruction and executing it, in the order in which
it is found in the program

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JMP: Jump instruction

 Transfers program control to a different point in

the instruction stream without recording return
information

 This instruction can be used to execute three

different types of jumps: Near Jump, Short Jump
and Far Jump…

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 Near jump—A jump to an instruction within the
current code segment (the segment currently
pointed to by the CS register), sometimes referred to
as an intra segment jump

 Short jump—A near jump where the jump range is

limited to –128 to +127 from the current IP value

 Far jump—A jump to an instruction located in a

different segment than the current code segment, is
sometimes referred to as an inter segment jump

The CS register is not changed on near and short jumps…

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 Conditional Jump Instructions…

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 MNEMONIC CONDITION TESTED

JA/JNBE(jump if above/jump if not below (CF AND ZF) =0

or equal)

JAE/JNB/JNC(jump if above or CF=0

equal/jump if not below /jump if no carry)

JB/JNAE/JC(jump if below/jump if not CF=1

above or equal/jump if carry)

JBE/JNA(jump if below or equal/jump if (CF OR ZF)=1

not above)

JCXZ(jump if CX register is zero) CX = 0

JE/JZ(jump if equal/jump if zero) ZF = 1

JG/JNLE(jump if greater/jump if not less ((SF XOR OF) OR ZF )

than of equal) =0
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 MNEMONIC CONDITION TESTED
JGE/JNL(jump if greater than or (SF XOR OF)=0
equal/jump if not less than)

JL/JNGE(jump if less than/jump if (SF XOR OF)=1

not greater than or equal)

JLE/JNG(jump if less than or ((SF XOR OF) OR ZF )=1

equal/jump if not greater)

JNE/JNZ(jump if not equal/jump if ZF=0

not zero)

JNO(jump if no overflow) OF=0 (not overflow)

JNP/JPO(jump if no parity/jump if PF=0 (not parity/parity
parity odd) odd)
JNS(jump if not signed, jump if SF=0 (not sign)
positive)
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 MNEMONIC CONDITION TESTED

JO(jump if overflow) OF=1 (overflow)

JP/JPE(jump if parity/jump if parity PF (Parity / parity equal)

even)

JS(jump if signed) SF=1 (Sign)

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LOOP Instruction

 The LOOP instructions are basically conditional

jump instructions which have the format

LOOP LABEL

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 LOOP instruction combines 2 operations in each
instruction

 The first operation is to decrement the CX

register by 1

 The second operation is to check the CX register

and, in some cases, also the zero flag to decide
whether to do a jump to the specified label

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LOOP(jump to specified label if cx≠0 Loop Until CX=0
after auto decrement)

LOOPE / LOOPZ(loop while Loop if zero flag is set and

cx≠0 and zf=1) CX !=0

LOOPNE / LOOPNZ(loop while Loop if zero flag not set and

cx≠0 and zf=0) CX !=0

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CALL
 Call instruction is a returnable jump to the destination or the
target address provided in the instruction

 This instruction can be used to execute two different types

of calls:

 Near call — A call to a procedure within the current code

segment (the segment currently pointed to by the CS
register), sometimes referred to as an intra segment call

 Far call — A call to a procedure located in a different

segment than the current code segment, sometimes
referred to as an inter segment call

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 When executing a near call, the processor
pushes the value of the IP register (which
contains the offset of the instruction following the
CALL instruction) onto the stack (for use later as
a return-instruction pointer)

 The processor then branches to the address in

the current code segment specified with the
target operand

 The CS register is not changed on near calls

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 When executing a far call, the processor pushes
the current value of both the CS and IP registers
onto the stack for use as a return-instruction
pointer

 The processor then performs a ―far branch‖ to

the code segment and offset specified with the
target operand for the called procedure

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RET
 The RET (return) instruction returns control back
from the procedure to the program that has
called the procedure

 The control will be returned to the instruction

following the procedure call

 This instruction transfers program control to a

return address located on the top of the stack

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 The address is usually placed on the stack by a
CALL instruction, and the return is made to the
instruction that follows the CALL instruction

 The optional source operand specifies the

number of stack bytes to be released after the
return address is popped; the default is none

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INT –interrupt program execution
INT type
 These instructions are software interrupt procedure
calls

 The term type in the instruction format refers to a

number between 0 to 255 which identifies interrupt

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When an 8086 executes an INT instruction it will

 Decrements the stack pointer by 2 and push the flags

onto the stack

 Decrements the stack pointer by 2 and push the

contents of CS onto stack

 Decrement the stack pointer by 2 and push the offset of

the next instruction(IP) after the INT instruction on the
stack

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 Get a new value of IP from an absolute memory address
of 4 times the type specified in the instruction
Ex: for INT 8 instruction, a new IP will be read from
address 00020H.

 Get a new value for CS from an absolute memory

address of 4 times the type specified in the instruction
plus 2
Ex: for an INT 8 instruction the new value of CS will be
read from address 00022H

 Reset both IF and TF .other flags are not affected

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IRET: Return from interrupt

 The IRET instruction performs a far return to the

interrupted program or procedure

 During this operation, the processor pops the

return instruction pointer, return code segment
selector, and FLAGS image from the stack to the
IP, CS, and FLAGS registers, respectively, and
then resumes execution of the interrupted
program or procedure

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