Chapter 02

Chapter-2
Instructions & Instruction Sequencing

Instruction: - An instruction is single operation of a processor defined by an instruction set
architecture. An instruction may be any representation of an element of an executable program.
The instruction includes:
1. OP-code
2. Operand
OP-code: -
Specifying the operation to be perform such as add, sub, mul, load etc.
Operand: -
An instruction normally has one or more specifiers for operands (i.e., data) on which the operation
should be act. Depending on architecture the operands may be register values, maybe values in the
stack or the memory value etc.
Number of Operands: -
Instruction sets may be categorized by the maximum of operand explicitly specified in the
instruction.
0(Zero) Operand: -
All arithmetic operation take place using the top one or two positions on the stack. One operand
push and pop instruction are used to access to memory: Push a, push b, add pop c.
1(One)Operand: -
Most instruction specified a single write operation (e.g a register, a memory location and a constant)
with the accumulative and left operand: load a, add b, store c.
2(Two) Operand: -
Many CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer)
machine fall under these categories.
a) CISC
Load a, reg1; add reg1, b: store reg1, c
b) RISC
Reducing memory loads the instruction would be load a, reg1; load b, reg2; add reg1, reg2; store
reg2, c
3(Three) Operand: -
Allowing better reuse of data.
CISC
It becomes either a single instruction add a, b, c or more typically: Move a, reg1, add reg1, b, c.
As most machines are limited two, two memory operands.
RISC
Due to large number of nits needed to encode the register. Arithmetic instruction uses registers only
two operands load/store instructions are needed load a, reg1; load b, reg2; add reg1, reg2 →reg3, c
Instruction format: -
Instruction format is consisting of bits and bits appear in memory words. The bits of the instruction
divided into groups called field.
Instruction format consists of 3 fields. The format of an instruction is usually in rectangular box.
a) Mode Field: - It is a one-bit field, symbolized as I in format. It specifies the way the operand or,
the effective address is determined.
b) Operation Code Field: - It is 4 bits field. It specifies the processor operation to be performed
such as add, subtraction, division, modulus etc.
c) Address Field: - It is 11 bits field. It is designated to memory address or processor register.
15 14 11 0
Mode OP Address
Field Code Field
Address Instruction: -
Computer with 3 address instruction formats can use each address field to specify either a processor
each address field to specify either a processor register or memory operand.
The 3-address instruction can be represented symbolically as ADD (operation to be performed) Z x Y

(designation) source operand
Its meaning ADD the content of memory location x and y and place the result in location z i.e.,
z← x + y
EX: X = (A+B) * (C+D)
ADD R1, A, B R1 ←M[A] +M[B]
ADD R2, C, D R2 ←M[C] +M[D]
MUL R1, R2 M[X} = R1+R2
It has a2 processor register R1 and R2. M[A] is the operand of memory address symbolized by A.
Address Instruction: -
Two address instruction are common in commercial computer each address field can specify either a
processor register or a memory word.
EX X= (A+B) *(C+D)
MOV R1 A R1← M[A]
ADD R1 B R1 ←R1+M[B]
MOV R2 C R2 ←M[C]
ADD R2 D R2 ←R2 + M[D]
MUL R1 R2 R1 ←R1 *R2
MOV X R1 M[X] ←R1
The MOV instruction move or transfer the operands to and from memory 4 processor resister.
One Address Instruction: - One address instruction use an implied accumulator [AC] register or all
data manipulation.
One address instruction has the command
ADD A
(On specified operand as assumed to be stored in fixed location, commonly in a processor register
called the accumulator.)
Meaning: - Add the content of memory location A to the content of accumulator register and place
the sum back into the accumulator.
[AC] ← [AC] + R1
AC← AC + R
Load: - The load instruction copies of content of memory location A into the accumulator.
Store: - Store instruction copies the content of accumulation into the memory location A.
EX = (A+B) * (C+D)
Load A AC ← M[A]
ADD B AC ← AC + M[B]
Store T M[T] ← AC
Load C AC ← M[C]
ADD D AC ← AC + M[D]
MUL T AC ← AC * M[T]
Store X M[X] ← AC
T is temporary memory location for storing intermediate result.
Zero (0) Address Instruction: -
The instruction does not require address field for the instruction ADD and MUL. The push, pop
instruction needs an address field to specify the operand.
EX X= (A+B) * (C+D)
PUSH A TOS← A
PUSH B TOS← B
ADD TOS← A+B
PUSH C TOS← C
PUSH D TOS← D
ADD TOS← C+D
MUL TOS← (C+D) * (A+B)
POP M[X] ← TOS
TOS means ‘TOP of the stack’.
Addressing Modes: -
The operation field of an instruction specifies the operation to be performed. The way the operands
are chosen during program execution is dependent on the addressing mode of the instruction. The
mode field is used to locate the operands need for operation.
Register Mode: -
In this mode the operand is specified indirectly simple in the definition of the instruction.
Instructions of this type are 1- byte instruction. The instruction “complement accumulator”. It is an
implied mode instruction because the operand in the accumulator register is implied in the
definition of the instruction. All register reference instruction that uses an accumulator are implied
mode instruction.
Immediate Mode: -
An immediate mode instruction has an operand field rather than an address field. The operand field
contains the actual operand field to be used in conjunction the actual operation specified in the
instruction. Immediate mode instructions are useful for initializing registers to a constant value.
Direct Address Mode: -
In this mode the effective address is equal to the address part of the instruction. The operand
resides in memory and its address is given directly by the address field of the instruction.

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Chapter-2

Instructions & Instruction Sequencing

The instruction includes:

Load a, reg1; add reg1, b: store reg1, c

Allowing better reuse of data.

Field Code Field

The 3-address instruction can be represented symbolically as ADD (operation to be performed) Z x Y

EX: X = (A+B) * (C+D)

ADD R1, A, B R1 ←M[A] +M[B]

ADD R2, C, D R2 ←M[C] +M[D]

MUL R1, R2 M[X} = R1+R2

ADD R2 D R2 ←R2 + M[D]

MUL R1 R2 R1 ←R1 *R2

MOV X R1 M[X] ←R1

One address instruction has the command

T is temporary memory location for storing intermediate result.

Zero (0) Address Instruction: -

ADD TOS← A+B

ADD TOS← C+D

MUL TOS← (C+D) * (A+B)

POP M[X] ← TOS

TOS means ‘TOP of the stack’.

Direct Address Mode: -

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