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Physical Design and Sign Off

Physical Design & Signoff FDP University Program 2023 focuses on physical design and signoff. The document introduces Sanjay Kumar, who has over 13 years of experience in semiconductor physical design. It then provides an agenda covering topics like ASIC design flow, placement and routing, physical design introduction, synthesis, floorplanning, physical signoff, timing signoff, and power analysis. Finally, it discusses the mission and engagements of the physical design team.

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100% found this document useful (3 votes)
3K views43 pages

Physical Design and Sign Off

Physical Design & Signoff FDP University Program 2023 focuses on physical design and signoff. The document introduces Sanjay Kumar, who has over 13 years of experience in semiconductor physical design. It then provides an agenda covering topics like ASIC design flow, placement and routing, physical design introduction, synthesis, floorplanning, physical signoff, timing signoff, and power analysis. Finally, it discusses the mission and engagements of the physical design team.

Uploaded by

Agnathavasi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Physical Design &

Signoff
FDP University Program 2023

Sanjay Kumar
Let me introduce myself

❖ With 13+ years of experience in semiconductor industry.


❖ Graduated from NIT Calicut in Electronics and Communication Engineering.
❖ Currently managing the SoC Physical Design team for General Purpose Micro
(GPM) products in ST, Greater Noida.
❖ Contributed to multiple successful tape-outs of products ranging from 180nm
to 5nm technologies in consumer, automotive and industrial application.
❖ As part of SoC Physical Design, I have driven key initiatives in implementation
of high-speed complex subsystems, and critical IPs for best-in-class power,
performance, and area.
❖ In addition, have multiple publications / presentations and tech poster in
various forums.
Agenda

# ASIC Design Flow # Placement and Routing

# Physical Design Introduction # Physical Signoff

# Synthesis # Timing Signoff

# Floorplan (IO-Ring) # Power & IR Drop Analysis

3
ASIC Design Flow
System Partitioning
Specification

Architectural Design Floor Planning

RTL Design &


Verification Placement

Synthesize the
Design CTS

Routing
Placement &
Routing
Physical
Design

Timing & Physical


Parasitic Extractions
Signoff

Mask Preparation Physical Verification

Fabrication Formal Verification

Packaging & testing Static Timing Analysis

Chip IR Drop & Power Analysis

4
Physical Design Team Mission

Physically implement most optimized system-on-


chip designs while meeting project schedule, high
level Power Performance Area targets/budgets and
package constraints.

5
Physical Design Team Engagements

• Interface with…
• SOC FE team to define PPA budgets
• Technology providers (ST or external)
Digital IP
• Package solution team

• Define & optimize implementation methodologies Analog/Flash/IOs/RAMs


CAD providers
• Define the right toolset to support these methodologies
• Define & deliver the SOC implementation schedule &
resource plan
• Propose IP/SOC changes for better and most optimized
SOC
SOC Design Technology Platform
• Top level planning/pad-ring construction/Analog integration
• Physical signoff checks BE Operations
• Packaging assessment
Physical Design flow - scope

Back End Design needs:


Front End Design
• Chip architecture
must guarantee: understanding
• Functionality • Front end know how
• Technology information
• Testability
• Implementation and
• Reliability Production steps know how
RTL • Knowledge of testability
code requirements
• Backend CAD tools deep
knowledge
Physical Design Introduction
❑ Structural representation to Physical Design i.e., RTL to GDSII Synthesis

❑ Stages: Import Design


❑ Synthesis
Floorplan
❑ Placement and Routing (PnR)
❑ Signoff
Power Plan APR
❑ Objectives:
Placement
❑ Timing
❑ Congestion Clock Tree Synthesis
❑ Area
❑ Power Routing

❑ Possible Issues:
Parasitic Physical Formal
❑ Timing Violations Extraction Verification Verification
❑ Congestion Issues
❑ Design Rule Violations Static Timing Analysis
Signoff
Power, IR Drop
Analysis

Tape-out
Synthesis
Synthesis (1/2)

❑ Process of transferring HDL to Gate-level netlist and described as


❑ Synthesis = Translation + Logic Optimization + Mapping
❑ HDL => Generic Boolean Logic => Optimization => Mapping => Netlist

if(high_bits == 2’b10)begin Translate (HDL Compiler)


residue = state_table[i];
end
else begin
residue = 16’h0000;
end Optimize + Mapping
HDL Source
(RTL)

Timing Info.
Generic Boolean Design Area
(GTECH) Design Power

Target Technology
Synthesis (2/2)

❑ Goal of Synthesis RTL


Constraint
UPF
s
❑ To get a Gate-level Netlist
❑ Logic Optimization
❑ Inserting DFT Logic
Technology Synthesis Floorplan
❑ Logic Equivalence between RTL and Netlist should be maintained. Tool or physical
Library
constraints
❑ Inputs of Synthesis
❑ RTL: HDL files
❑ Library views
❑ Constraints Synthesized
Gate-Level
❑ Floorplan DEF (for physical synthesis) Netlist
❑ UPF (Power intent for power aware synthesis)

❑ Outputs of Synthesis
❑ Netlist
❑ QoR Reports (timings, area, cell count etc.)
❑ UPF
Library Views (1/2)

❑ LIBRARY: Consolidated Data for Use in Designing a ❑ Memories:


System On Chip. ❑ Memories like SRAM, DRAM, ROM etc.
❑ Implemented as generator and configure various size of memory.
❑ Various Types of Libraries:
❑ Supports many features like redundancy, masking etc.
❑ CORE Libraries
❑ IO Libraries ❑ Analog and Mixed Signal Libraries:
❑ Memories ❑ These IPs provides unique functions
❑ Analog and Mixed Signal ❑ Examples are PLL, ADC, DAC, USB, SATA etc

❑ CORE Libraries: ❑ Types of Views:


❑ Group of basic logic functional cells, called std cells. ❑ HDL models
❑ Type of cells: AND, OR, Flops, Latch etc. ❑ Timing Libs
❑ Physical/logic/timing/electric models are present ❑ Schematic
❑ Symbol
❑ IO Libraries:
❑ Layout (LEF/GDSII)
❑ IO buffers are designed for specific process technology.
❑ Abstract and more …
❑ Power/Ground IOs for chip supply
❑ IOs are with protection of ESD events.
Place and Route
PnR Inputs (1/2)

❑ Netlist/Verilog ❑ Liberty Exchange Format (LEF)


❑ Std. cell instance name & drive strength ❑ Cell Abstract View / The Physical Library
❑ Macros & memories instances ❑ Std Cell LEF
❑ Design module definitions ❑ Macro LEF
❑ Interconnection details ❑ IO LEF

❑ Constraints ❑ Technology File


❑ Timing Constraints like Clock Definitions (clock period, duty cycle) and ❑ Defines Units, Design Rules for Layers and VIAS as per technology
uncertainties. ❑ Physical and Electrical Parameters
❑ Timing Exceptions (False Paths, Asynchronous Paths). ❑ Metal direction/pitch/width/offset/thickness/resistance/capacitance etc.
❑ Delay Constraints (Latency, Input Delay, Input Transition, Output Load and ❑ Site/Unit Tile definition
Output Transition)
❑ Design rule constraints like Max. Cap / Transition / Fanout. ❑ Interconnect Parasitic File
❑ Used for layer parasitic extraction
❑ Liberty Timing Files
❑ Contains layer/via cap and resistance values in lookup table
❑ Cell Logical View / The timing Library
❑ Std Cell Lib, Macro Lib, IO lib ❑ Map file
❑ Gate Delay ❑ Useful if is there is 2 different naming convections in Technology file, LEF
or Interconnect Parasitic file
PnR Inputs (2/2)

❑ Power Specification File


DFT inserted Netlist Timing Constraints Power Connectivity Info
❑ Power Modes & Power Domains
❑ Tie Up supply & Tie Low supply
❑ Power Nets & GND Nets

❑ Optimization Directives
❑ Don’t Use Cells SoC Implementation Tool
❑ Don’t Touch
❑ Size only

❑ Clock Tree Constraints


❑ Root Pin Definition
❑ Insertion delay and skew targets
❑ Max Cap/Tran limits (DRVs)
1. GDSII File
❑ List of Buffers/Inverters for CTS 2. Optimized Gate Level
Netlist
❑ NDRs for Clock Routes
3. QoR Reports
❑ Macro Models if applicable.
Import Design
❑ The following input files information are loaded to the PnR Synthesis
tool
Import Design
❑ Netlist (.v/ .vhd/ .edif)
❑ Physical Libraries (.lef)
Floorplan
❑ Timing Libraries (.lib)
❑ Technology Files Power Plan

❑ Constraints (.sdc)
Placement
❑ IO Info. File (optional)
❑ Power Spec. File (optional) Clock Tree Synthesis
❑ Optimization Directives (optional)
❑ Clock Tree Spec. File (optional at floorplan stage) Routing

❑ DEF/ FP (optional if floorplan is not done)


Parasitic Physical
❑ Sanity Checks Extraction Verification
Formal
Verification
❑ Sanity Checks mainly checks the quality of netlist in terms of timing
❑ It also consists of checking the issues related to Library files, Timing Static Timing Analysis
Constraints, IOs and Optimization Directives.
Power, IR Drop
❑ Netlist Sanity Checks like floating pins, un-driven i/p ports, unloaded o/p Analysis
ports multiple drivers etc.
Tape-out
Floorplan

❑ To achieve best PPA Synthesis

❑ To minimize issues like placement density, congestion, Import Design


timing challenges
Floorplan
❑ To Reduce wire length and making routing easy.
Power Plan
❑ To reduce Si cost
Placement

Clock Tree Synthesis

Routing

Parasitic Physical Formal


Extraction Verification Verification

Static Timing Analysis

Power, IR Drop
Analysis

Tape-out
Floorplan

❑ Important Terminologies in Floorplan


❑ Utilization PMU/SMPS
❑ Manufacturing Grid Std cell logic

❑ Std Cells Site / Placement Tile / Unit Tile


USB/HDMI
❑ Std Cell Rows
❑ Placement Grid IO Ring
Video
❑ Routing Grid and Routing Track Encoder
❑ Flight-Line / Fly-Line
❑ Macros PLL
Memories
❑ Steps in Floorplan MIPI CSI
❑ Initialize fp with Chip & Core Aspect Ratio (AR) and with Core Utilization
❑ Initialize fp Row Configuration & Cell Orientation
❑ Provide the Core to Pad/ IO spacing (Core to IO clearance) ADC / DAC
ARM
❑ Pins/ Pads Placement Processor
❑ Macro Placement by Fly-line Analysis
❑ Blockage Management (Placement/ Routing)
IO-Ring Introduction

❑ Interface between the package and the chip


❑ Type of IOs
❑ IO and core Power Pads
❑ Signal Pads
❑ Corner PADs
❑ Protection from outside aggression (ESD)

❑ IOs are abutted to create PAD Ring


❑ Multi Voltage Design support
❑ Multi Package Compatibility
IO-Ring

❑ IO Placement
❑ Chip Level => IO Pads and Block Level => IO Pins
❑ Pin is a logical entity and is a property of a Port and Port is a physical
entity and only 1 Pin associated with it.
❑ Netlist will have Pins and Layout will have Ports
❑ Different types of IO PADs IO Cells
❑ Signal Pads/Pins
❑ Core Power Pads/Pins
❑ IO Power Pads/Pins
❑ Corner Pads
❑ Filler Pads (Fill the gaps between IO pads to get the Ring Connectivity)
❑ Physical-only pads that are not part of the input Gate level Netlist need to
be inserted prior to reading IO constraints.
Core Area
❑ IO Pads enables the design to operate at different voltages with the help
of Level Shifters, Pre-Drivers (at Core Voltage) Post-Drivers (at IO
Voltage)
Power Plan

❑ To connect power to the chip by considering issues like EM and IR Drop Synthesis

❑ Levels of Power Distribution Import Design

❑ Rings : VDD & VSS Rings are created around the core and Macro
Floorplan
❑ Stripes: VDD & VSS Power Stripes are created in the core area
Power Plan
❑ Special Route (Rails)
❑ Connect VDD & VSS to the std cells Placement

❑ Power Vias Clock Tree Synthesis


❑ Insert Visa between ring/grid, and horizontal and vertical grid
Routing
❑ Trunks
❑ Connects ring to Power Pad
Parasitic Physical Formal
❑ Trunk is a piece of metal that connects IO Pad and Core Ring Extraction Verification Verification

Static Timing Analysis

Power, IR Drop
Analysis

Tape-out
Pre-Placement

❑ Physical Only Cells (Well Taps, End Caps)


❑ These cells do not have signal connectivity and connect only to the power and ground rails
❑ End Caps ensure that gaps do not occur between the Well and Implant Layers and prevents DRC violations
❑ Well Taps help to tie Substrate and N-wells to VDD and VSS levels and thus prevent Latch-up

❑ Special Cells (Spare cells, Decap Cells)


❑ Spare Cells for ECO and Decaps for avoiding Instantaneous Voltage Drop (IVD)

❑ Cell Padding
❑ Cell Padding is done to reserve space for avoiding Routing Congestion
❑ Cell Padding adds Hard Constraints to Placement
❑ The Constraints are honored by Cell, Legalization, CTS, and Timing Optimization.
Placement

❑ Automated std cell placement on placement tracks.


❑ Placement Objectives
❑ Total wire length
❑ Routability
❑ Performance
❑ Power
❑ Heat distribution

❑ Timing checks at Placement stage


❑ Only Setup Time check, since clock is ideal at placement stage

❑ Placement Methods
❑ Timing Driven Placement
❑ Congestion Driven Placement
Clock Tree Synthesis (1/3)

❑ What is clocks Tree ?


❑ Clock Spec file from SDC
❑ Definition of Clocks
❑ Clock Balance Constraints
❑ Stop & Ignore pins
❑ Macro pin insertion delay
❑ Exclusive Sink Groups
❑ Early Clock for Dividers
Clock
Constraints
Routing NDR
Lib cell
Selection

Clock Skew Clock Clock Net Clock


Insertion Width & Power
Target Shielding
Clock Tree Synthesis (2/3)

❑ Skew: Most important concern for Clock Networks.


❑ Due to variations in trace length, metal width and height, coupling caps.
❑ Also due to variations in local clock load, local power supply, local gate
length and threshold, local temperature.

❑ Power: Major power consumer.


❑ Clock cell switches at every clock cycle.

❑ Noise:
❑ Clock is often very strong aggressor
❑ May need shielding

❑ Delay:
❑ Clock Insertion Delay is important
❑ Good transition on clock network.
Clock Tree Synthesis (3/3)

❑ Before CTS, all Clock Pins are driven by a single Clock


Source.

❑ After CTS, the buffer tree is built to balance the loads and
minimize the skew.
Routing (1/3)

❑ Routing Objectives : Connections are routed as connected


logically
❑ Routed paths must meet setup & hold timing margin.
❑ DRVs max. Capacitance/ Transition must be under the
limit.
Multi-level Interconnection (MLI)
❑ Metal traces must meet foundry physical DRC Technology Layer stacks
requirements.
❑ Layout geometries should meet Current Density
specification.
Routing (2/3)

❑ Trial/Global Routing:
❑ Routable path for the nets driving/ driven pins in a shortest distance.
❑ Does not consider DRC rules, which gives an overall view of routing and congested nets
❑ Assign net to specific routable window, i.e Global Route Cell (GRC)
❑ Avoid congested areas and also long detours and avoid routing over blockages
❑ Avoid routing for pre-route nets such as Rings/Stripes/Rails
❑ Uses Steiner Tree and Maze algorithm

❑ Track Assignment:
❑ Takes the Global Routed Layout and assigns each nets to the specific Tracks and layer geometry
❑ It does not follow the physical DRC rules but will do the timing aware Track Assignment.

❑ Detail/Nano Routing:
❑ It follows up with the track routed net segments.
❑ It Performs complete DRC aware and timing driven routing
❑ Final routing for the design built after the CTS and the timing is freeze.
Routing (3/3)

❑ Grid Based Routing:


❑ Metal traces (routes) are built along and centered upon routing tracks.
❑ Various types of grids are Manufacturing Grid, Routing Grid (Pitch) and Placement Grid.
❑ Grid dimension should be multiple of Manufacturing Grid.

❑ Routing Preferences:
❑ Typically Routing only in “Manhattan” N/S E/W directions.
❑ Spacing checks with the adjacent layers.
❑ Width check for all layers and via dimension rules.

❑ Layer Routing directions:


❑ Each metal layer has its own preferred routing direction and are defined in a technology rule file.
❑ M1: Horizontal, M2: Vertical , M3: Horizontal, M4: Vertical and so on…
❑ In some cases, we can avoid following preferred routing direction for smart routing (Non-preferred direction)
Post Routing Optimization

❑ Signal Integrity (SI) Optimization by NDRs and Shielding


for the sensitive nets
❑ Types of Shielding for sensitive nets
❑ Same layer shielding
❑ Adjacent layer/ Coaxial shielding

❑ Metal Fill: Filling up empty metal tracks.


❑ Floating Metal Fills
❑ Grounded Metal Fills
Signoff
Signoff

❑ Physical Verification: DRC and LVS ❑ Timing Signoff


❑ DRC: Fabrication related rules : Spacing and Notch etc ❑ Design meets frequency specs

❑ LVS: layout versus schematic : GDSII versus CDL. ❑ No setup – hold violations
❑ All DRVs met (max-capacitance, max-transition, fan-out)

❑ Power Signoff
❑ Static: IR Drop Analysis
❑ Dynamic: IR Drop Analysis
Physical Verification (DRC)

• Design Rule Check (DRC) is the process of checking


physical layout data against fabrication-specific rules
specified by the foundry to ensure successful fabrication.
• Process specific design rules must be followed by drawing
layouts to avoid any manufacturing defects during the
fabrication of an IC.
• As Technology Shrinks
• Number of Design Rules are increasing
• Complexity of Routing Rules is increasing
• Increasing the number of objects involved
• More Design Rules depending on Width, Halo, Parallel Length

• Violating a design rule might result in a non-functional


circuit or low Yield.
Physical Verification (DRC)

❑ Design Rule examples:


❑ Maximum Rules: Manufacturing of large continuous regions can lead to
stress cracks. So ‘wide metal’ must be ‘slotted’ (holes)
❑ Grid: All corner points must lie on a minimal grid, otherwise an “off grid
error” is produced
❑ Minimum Spacing: The minimum spacing between objects on a single
layer
❑ Minimum Width: The min width rule specifies the minimum width of
individual shapes on a single layer
❑ Minimum Enclosure/ Overlap: Implies that the second layer is fully
enclosed by the first one
❑ Notch: The rule specifies the minimum spacing rule for objects on the
same net, including defining the minimum notch on a single-layer, merged
object
❑ Minimum Cut: the minimum number of cuts a via must have when it is on
a wide wire
Physical Verification (LVS)

• Layout Versus Schematic (LVS) verifies the connectivity of


a Verilog Netlist and Layout Netlist (Extracted Netlist from
GDS)
• Tool extracts circuit devices and interconnects from the
layout and saved as Layout Netlist (SPICE format)
• As LVS performs comparison between 2 Netlist, it does
not compare the functionalities of both the Netlist
• Input Requirements
• LVS Rule deck
• Verilog Netlist
• Physical layout database (GDS)
• Spice Netlist (Extracted by the tool from GDS)

• LVS checks examples


• Short Net Error, Open Net Error, Extract errors, Compare errors
Timing Signoff

❑ To check if the design meets timing constraints in all ❑ STA: Principle…


situations. ❑ To time any and every single gate & wire
❑ Sum up these delays on any timing path
❑ Static Timing Analysis : Computes both minimum and well
as maximum range of delay values of all possible ❑ Check versus the constraints if timing is met

combination of inputs
❑ First stage STA done at gate level netlist.
❑ Where does timing come from ?
❑ Gates: PVT (operating conditions)
❑ Connections: (load Cap, and input tran).
❑ Wire: parasitic (resistance, Capacitance)

Delay in Gates (G1, G2) + Delay in wires (W1, W2, W3) < Expected delay on the path
Parasitic Extraction

• Capacitance : C = εo*W*H / d
• Transistors: Depends on area of transistor gate, physical of materials,
thickness of insulator, diffusion to substrate
• Poly to Substrate: Parallel plate and fringing.

• Capacitance between conductors: Coupling cap, Area cap,


Fringing cap and Crossover cap.
• Coupling Cap / Lateral Cap
• Fringing Cap
• Parallel/Crossover Cap
• Area Cap
Static Timing Analysis

❑ Default #4 types of timing paths: Combo 4


❑ In2Reg Logic
❑ Reg2Out
❑ Reg2Reg
Combo
❑ In2Out 1 2 Logic 3
❑ Setup and Hold check
❑ Max Transition and Max Capacitance check Combo Combo
Logic Logic

1 Input to Register Paths 3 Register to Output Paths

2 Register to Register Paths 4 Input To Output Paths


IR Drop Analysis

• Why worry about IR drop analysis ? • Static Components


• Poor-floor planning • Subthreshold Leakage
• Problems in power routing such as: Unconnected contact arrays, Power • Tunneling Current
grid discontinuities. • Reverse Biased diode leakage
• Insufficient power pins
• Incorrect power-pin placement
• Dynamic Components
• Faster clocks => higher power consumption, need to offset by scaling C • Switching and Short circuit analysis
and Vdd • Charging and discharging of the load capacitances.
• Shrinking wire cross-sections => higher wire and via resistances values • Short circuit current through PMOS and NMOS transistors when they are
partially on.
• Power dissipation on the silicon will happen because of
following reasons. • Power Distribution : Ohm’s law applicable
• Static components
• Dynamic components
• Power distributions
Tape-out
Tape-out

• Chip is ready to be manufactured ☺

SCHEMATIC PHOTOLITHOGRAPHY CHIP ON WAFER


MASK

LAYOUT MASK LAYERS


Thank You !
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