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Chapter 1
Introduction
Overview of computer architecture
What is computer?
 A computer is a machine that can be instructed to carry out sequences of arithmetic or
logical operations automatically via computer programming.
 An electronic device for storing and processing data, typically in binary form, according to
instructions given to it in a variable program.
 The basic components of a modern digital computer are: Input Device, Output Device,
Central Processor Unit (CPU), mass storage device and memory. A Typical modern
computer uses LSI Chips. Four Functions about computer are:
Block diagram of a basic computer

RU

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What is microprocessor and micro controller
A. What is Microprocessor?
 A processor is built from a large number of integrated circuits.
 A microprocessor is a processor packaged as a single Ic(chip).
 A microcomputer is a computer that uses a microprocessor as its CPU.
 8-bit, 16-bit, 32-bit microprocessor: refers to number of bits manipulated in one operation.
 It requires external memory to execute programs.
 It cannot directly interface to I/O devices, peripheral chips are needed.
B. Block diagram of a basic microprocessor with external resources
Below is the generic block diagram of a microprocessor system. It consists of the bus that
we introduced during the discussion on memory interfacing. This bus includes the data that
can be passed bidirectionally between the microprocessor and its external resources such as
memory, address lines that define the chip and the memory location within the chip of the
external resources, and the control lines orchestrating the transfers.

C. Internal block diagram of Microprocessor

Microprocessor consists of an ALU, register unit, and a

control unit. ALU performs arithmetical and logical
operations on the data received from the memory or an
input device. Register unit consists of registers identified
by letters like B, C, D, E, H, L and accumulator. The
control unit controls the flow of data and instructions
within the computer.

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A. What is microcontroller?
 A microcontroller is a computer implemented on a single chip.
 Everything a microprocessor has plus (for example):
o Memory
o Timer
o AD and DA converters (Analog-to-digital converter)
o Memory controller
o Parallel and Serial ports
 Microcontrollers are used mainly for dedicated applications in embedded systems
(appliances, mechanical / electrical control).
B. Basic example of 8051 Microcontroller

 16-bit Microcontroller
 on chip ROM(8KB) and on chip RAM (128 bytes)
 two 16-bit timer/counter.
 four 8-bit ports for input/output
 fully duplex serial receiver/transmitter.
 no prefetching of instruction.
 16 address pins
C. Internal block diagram of Microcontroller

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Overview of 8086/8088 MP
8086 Microprocessor was designed by Intel in 1976. It is a 16-bit Microprocessor having 20
address lines and 16 data lines that provides up to 1MB storage. It consists of powerful
instruction set, which provides operations like multiplication and division easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is
suitable for system having multiple processors and Minimum mode is suitable for system having a
single processor.
The most prominent features of a 8086 microprocessor are as follows
 Size − 8086 is 16-bit microprocessor.
 Address Bus 8086 has 20-bit address bus.
 Memory 8086 can access up to 1 Mb of memory.
 Instruction 8086 has an instruction queue.
 Pipelining 8086 supports a pipelined architecture.
 I/O 8086 can access 2^16 = 65,536 I/O's.
Internal Architecture of 8086/8088
The following diagram depicts the architecture of a 8086 Microprocessor

Segment
register

GPRs

Pointer Reg
Index Reg

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8086 Functional Units
8086 Microprocessor is divided into two functional units.
A. BIU (Bus Interface Unit).
B. EU (Execution Unit)
BIU (Bus Interface Unit).
BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the memory
as well as writing data to the ports and the memory. EU has no direction connection with
System Buses so this is possible with the BIU. EU and BIU are connected with the Internal
Bus.
It has the following functional parts −
 Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next
instructions and stores them in the instruction queue. When EU executes instructions and is
ready for its next instruction, then it simply reads the instruction from this instruction queue
resulting in increased execution speed.
− Fetching the next instruction while the current instruction executes is called pipelining.
 Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses
of instructions and data in memory, which are used by the processor to access memory
locations. It also contains 1 pointer register IP (instruction pointer), which holds the address
of the next instruction to executed by the EU.
o CS − It stands for Code Segment. It is used for addressing a memory location in the
code segment of the memory, where the executable program is stored.
o DS − It stands for Data Segment. It consists of data used by the program and is
accessed in the data segment by an offset address or the content of other register
that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data and addresses
during execution.
o ES − It stands for Extra Segment. ES
is additional data segment, which is
used by the string to hold the extra
destination data.

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 Instruction pointer/ program counter − It is a 16-bit register used to hold the address of
the next instruction to be executed.
EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then decode
and execute those instructions. Its function is to control operations on data using the instruction
decoder & ALU. EU has no direct connection with system buses as shown in the above figure,
it performs operations over data through BIU.
Let us now discuss the functional parts of 8086 microprocessors.
ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result
stored in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags
and Control Flags.
Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the list of
conditional flags −
 Carry flag − This flag indicates an overflow condition for arithmetic operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from
lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry
given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to BCD
conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order
8-bits of the result contains even number of 1’s, then the Parity Flag is set. For odd number
of 1’s, the Parity Flag is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero
else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is
negative, then the sign flag is set to 1 else set to 0.
 Overflow flag − This flag represents the result when the system capacity is exceeded.
Control Flags

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Control flags controls the operations of the execution unit. Following is the list of control flags −
 Trap flag − It is used for single step control and allows the user to execute one instruction
at a time for debugging. If it is set, then the program can be run in a single step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for
interrupt disabled condition.
 Direction flag − It is used in string operation. As the name suggests when it is set then
string bytes are accessed from the higher memory address to the lower memory address and
vice-a-versa.
X X X X OF DF IF TF SF ZF X AF X PF X CF

 X marked undefined bits (unused bits)

 Underline marked 3 control flags
 The other is Status flag.
General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers
can be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid
register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX,
BX, CX, and DX respectively.
 AX register − It is also known as accumulator register. It is used to store operands for
arithmetic operations.
 BX register − It is used as a base register. It is used to store the starting base address of the
memory area within the data segment.
 CX register − It is referred to as counter. It is used in loop instruction to store the loop
counter.
 DX register − This register is used to hold I/O port address for I/O instruction.

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pointer and index registers

 These registers contain the offsets of data and instructions
 The offset refers to the distance of a variable, label, or instruction from its base segment
 Are used with arrayed data (such as strings, arrays and other data structures containing
multiple elements). They increase the processing speed of such data structures
 Can be used in arithmetic and other operations.
SP (stack pointer):
 Contains an assumed offset value of the top of the stack
 Combined with the SS register form the complete logical address of the top of the stack
 The stack is maintained as a LIFO with its bottom at the start of the stack segment
(specified by the SS segment register)
 The top of the stack (the location of the last data in the stack) is specified by the offset
stored in the SP register
BP (base pointer):
 As it is with the stack pointer, this register can hold an offset from the SS register
 It is usually used by subroutines to locate variables that were passed on the stack by a
calling program
 Unlike the SP register, the BP can be used to specify the offset of other program segments
SI (source index):
 Used in conjunction with the DS register to point to data locations in the data segment
 Used with string movement instructions. It would point to the source string.
DI (destination index):
 Similar function to the SI
 Used in conjunction with the ES register in string operations. In string movement
instructions, it points to the destination string
IP (Instruction Pointer):
 This is the register used for accessing instructions
 While the CS register contains the segment number of the next instruction, the IP contains
the offset of that instruction in the code segment

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 As was shown in the section on the fetch-execute cycle in the first unit, the IP register gets
updated by the control unit every time an instruction is executed such that it will always
point to the next instruction
 Unlike other registers, the IP cannot be manipulated by instructions (i.e. it cannot appear
as an operand in any instruction)

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Chapter 2
8086 uP Pin Diagram
 8086uP have 40-pin DIP (Dual Inline Package) chip. Let us now discuss in detail the pin
configuration of 8086 Microprocessor.
8086 Pin Diagram
Here is the pin diagram of 8086 microprocessor

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Pins Detail Description
 Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its
operation.
 Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations.
Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
 Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8-AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.
 Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it
carries 4-bit address and later it carries status signals.
 S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer
of data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it
is active.
BH A Status
E 0
0 0 16 bits
0 1 Lower 8 bit is High
1 0 Upper 8 bits High
1 1 Idle

 Read($\overline{RD}$)
It is available at pin 32 and is used to read signal for Read operation.
 Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready
to transfer data. When it is low, it indicates wait state.

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 RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.

A0 Status
CS FFFF
IS 0000
All flags should be clear
DS 0000
ES 0000
SS 0000
IQ empty
 INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt
or not.
 NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.
 $\overline{TEST}$
This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.

MN/MX/overlineIt stands for Minimum/Maximum and is available at pin 33. It indicates
what mode the processor is to operate in; when it is high(pin connect to microprocessor
VCC), it works in the minimum mode and when it is Low, it works in the maximum mode
 INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.
 ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a
valid address on the address/data lines.

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 DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286.
The transreceiver is a device used to separate data from the address/data bus.
 DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is transmitted out and
vice-a-versa.
 M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at
pin 28.
 WR
It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
 HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
 HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
 QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide
the status of instruction queue. Their conditions are shown in the following table.
QS0 QS1 Status
0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent byte from the queue
 S0, S1, S2

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These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26,
27, and 28. Following is the table showing their status
S2 S1 S0 Status
0 0 0 Interrupt acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
 LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave
the system bus. It is activated using the LOCK prefix on any instruction and is available at
pin 29.
 RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends acknowledgment.
RQ/GT0 has a higher priority than RQ/GT1.
Minimum Mode Configuration
 In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode
by strapping its MN/MX pin to logic 1. Means it connect the pin into uP VCC.
 In this mode, all the control signals are given out by the microprocessor chip itself. There is
a single microprocessor in the minimum mode system
Maximum mode Interface signals
 In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
 In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
 In the maximum mode, there may be more than one microprocessor in the system
configuration.
 The components in the system are same as in the minimum mode system.

Hardware Organization of the memory address space

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 The 8088/86 microcomputer supports 1 Mbytes of external memory.
 The memory of an 8088/86-based microcomputer is organized as 8-bit bytes, not as 16-bit
words.
 Physical memory address Starting from 0H – FFFFFH
 The 8088 can access two consecutive bytes as word of data. Lower address byte and higher
address byte
Physical memory organization:
 The 8086’s 1Mbyte memory address space is
divided in to two independent 512Kbyte banks:
the low (even) bank and the high (odd) bank.
Data bytes associated with an even address
(00000H, 00002H, etc.) reside in the low bank,
and those with odd addresses (00001H,
00003H, etc.) reside in the high bank.
 Address bits A1 through A19 select the storage
location that is to be accessed. They are applied
to both banks in parallel. A0 and bank high
enable (BHE) are used as bank-select signals.
Example the following graphs
Case 1: When a byte of data at an odd address
(such as X+1) is to be accessed:
 A0 is set to logic 1 to disable the low bank of memory.
 BHE is set to logic 0 to enable the high bank.

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Case 2: When a byte of data at an even address

(such as X) is to be accessed:

 A0 is set to logic 0 to enable the low bank of memory.

 BHE is set to logic 1 to disable the high bank.

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Chapter 3

Addressing mode
Efficient software development for the microprocessor requires a complete
familiarity with the addressing modes employed by each instruction. In this
chapter, the MOV (move data) instruction is used to describe the data-
addressing modes. The MOV instruction transfers bytes or words of data
between two registers or between registers and memory
The data-addressing modes include register, immediate, direct, register
indirect, base plus index, register-relative, and base relative-plus-index in the
8086 through the 80286 microprocessors.
Data-Addressing Modes
Because the MOV instruction is a very common and flexible instruction, it provides a basis for the
explanation of the data-addressing modes. the MOV instruction and defines the direction of data
flow. The source is to the right and the destination is to the left, next to the opcode MOV. (An
opcode, or operation code, tells the microprocessor which operation to perform.) This direction of
flow, which is applied to all instructions
These types of addressing mode are supported by MOV opcode
MOV REG, memory
MOV memory, REG
MOV REG, REG
MOV memory, immediate
MOV REG, immediate
The MOV instruction showing the source, destination, and direction of data flow.

MOV AX, BX

Destination Source
 The second operand (source) to the first operand (destination).
 the source operand can be an immediate value, general-purpose register or memory
location.
 the destination register can be a general-purpose register, or memory location.

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A. Immediate addressing
Register addressing transfers a copy of a byte or word from the source Immediate addressing
transfers the source, an immediate byte, word, doubleword, or quadword of data, into the
destination register or memory location.
Syntax: Operand Reg/Memorey Add, immediate Value
Example: MOV AL, 22H ; instruction copies a byte-sized 22H into register AL
B. Register addressing
Register addressing transfers a copy of a byte or word from the source
register or contents of a memory location to the destination register or
memory location.
Syntax: Operand Reg/Memorey Add, RegName
Example: The MOV CX, DX ;instruction copies the word-sized contents of register DX
into register CX.

C. Direct Data addressing

Direct addressing moves a byte or word between a memory location and
a register. The instruction set does not support a memory-to-memory
transfer, except with the MOVS instruction.
Example: The MOV CX, LIST ; instruction copies the word-sized
contents of memory location LIST into register CX.) In the 80386 and
above, a doubleword-sized memory location can also be addressed.
D. Register Indirect Addressing
Register indirect addressing transfers a byte or word between a register
and a memory location addressed by an index or base register. The
index and base registers are SP, BP, DI, and SI.
(Example: The MOV AX, [BX] instruction copies the word-sized data
from the data segment offset address indexed by BX into register AX.)
E. Base plus index

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Base-plus-index addressing transfers a byte or word between a register
and the memory location addressed by a base register (BP or BX) plus
an index register (DI or SI).
Example: The MOV [ ], CL instruction copies the byte-sized contents of
register CL into the data segment memory location addressed by BX
plus DI.

F. Register relative
Register relative addressing moves a byte or word between a register
and the memory location addressed by an index or base register plus a
displacement.
(Example: MOV AX,[ ] or
MOV AX, ARRAY[BX]. The first instruction loads AX from the data
segment address formed by BX plus 4. The second instruction
loads AX from the data segment memory location in ARRAY plus
the contents of BX.)
G. Base relative plus index
register and the memory location addressed by a base and an index
register plus a displacement.
Example: MOV AX, ARRAY [BX + DI]
MOV AX, [BX+DI+4]
These instructions load AX from a data segment memory location. The
first instruction uses an address formed by adding ARRAY, BX, and DI
and the second by adding BX, DI.

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Program Memory-Addressing Modes
Program memory-addressing modes, used with the JMP (jump) and CALL instructions, consist
of three distinct forms: direct, relative, and indirect. This section introduces these three addressing
forms, using the JMP instruction to illustrate their operation.
A. Direct Program Memory Addressing
Direct program memory addressing is what many early microprocessors used
for all jumps and calls. Direct program memory addressing is also used in
high-level languages, such as the BASIC language GOTO and
GOSUB instructions. The microprocessor uses this form of
addressing, but not as often as relative and indirect program
memory addressing are used.
Example: Figure 3.1
B. Relative Program Memory Addressing
Relative program memory addressing is not available in all early microprocessors, but it is
available
to this family of microprocessors. The term relative means “relative to the instruction pointer
(IP).”
For example, if a JMP instruction skips the next 2 bytes of memory, the address in relation to the
instruction pointer is a 2 that adds to the instruction pointer. This develops the address of the next
program instruction. An example of the relative JMP instruction is shown in Figure.
C. Indirect Program Memory Addressing
The microprocessor allows several forms of program indirect memory
addressing for the JMP and CALL instructions. Table 3–10 lists some acceptable
program indirect jump instructions, which can use any 16-bit register (AX, BX,
CX, DX, SP, BP, DI, or SI); any relative register ([BP], [BX], [DI], or [SI]); and
any relative register with a displacement. In the 80386 and above, an
extended register can also be used to hold the address or indirect address of a
relative JMP or CALL.
For example, the JMP EAX jumps to the location address by register EAX.

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Stack Memory-Addressing Modes
The stack plays an important role in all microprocessors. It holds data temporarily and stores
the return addresses used by procedures. The stack memory is an LIFO (last-in, first-out)
memory, which describes the way that data are stored and removed from the stack. Data are
placed onto the stack with a PUSH instruction and removed with a POP instruction. The
CALL instruction also uses the stack to hold the return address for procedures and a RET
(return) instruction to remove the return address
from the stack.
(a) PUSH BX places the contents of BX onto the stack;
(b) POP CX removes data from the stack and places
them into CX.
* Both instructions are shown after execution.

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Chapter 4

Instruction set of the 8086/8088 MP

Data transfer instruction
The data transfer instructions are include XCHG, LAHF, SAHF, XLAT, IN, OUT, BSWAP,
MOVSX, MOVZX, and CMOV.
XCHG
 The XCHG (exchange) instruction exchanges the contents of a register with the contents of any
other register or memory location.
 The XCHG instruction cannot exchange segment registers or memory-to-memory data.
 Use any addressing mode, except immediate addressing
 The XCHG instruction, using the 16-bit AX register with another 16-bit register, is the most
efficient exchange.
 This instruction occupies 1 byte of memory. Other XCHG instructions require 2 or more bytes
of memory, depending on the addressing mode selected.
Example
XCHG AL,CL ;Exchanges the contents of AL with CL
LAHF and SAHF
 The LAHF and SAHF instructions are used as bridge instructions.
 The LAHF instruction transfers the rightmost 8 bits of the flag register into the AH register.
 The SAHF instruction transfers the AH register into the rightmost 8 bits of the flag register.
XLAT
 The XLAT (translate) instruction converts the contents of the AL register into a number
stored in a memory table.
 This instruction performs the direct table lookup technique often used to convert one code to
another.
 An XLAT instruction first adds the contents of AL to BX to form a memory address within the
data segment. It then copies the contents of this address into AL. This is the only instruction
that adds an 8-bit number to a l6-bit number.

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 Suppose that a 7-segment LED display lookup table is stored in memory at address
TABLE. The XLAT instruction then uses the lookup table to translate the BCD
number in AL to a 7-segment code in AL.
Example
MOV AL,5 ;load AL with 5 (a test number)
MOV BX,OFFSET TABLE ;address lookup table
XLAT ;convert
;Table
TABLE DB 3FH, 06H, 5BH, 4FH ;lookup table
DB 66H, 6DH, 7DH, 27H
DB 7FH, 6FH

IN and OUT
 IN and OUT instructions, which perform I/O operations.
 Notice: that the contents of AL, AX, or EAX are transferred only between the I/O device and
the microprocessor.
 An IN instruction transfers data from an external I/O device into AL, AX, or EAX;
 An OUT transfers data from AL, AX, or EAX to an external I/O device. (Note that only the
80386 and above contain EAX.)
 Two forms of I/O device (port) addressing exist for IN and OUT: fixed port and variable port.
 Fixed-port addressing allows data transfer between AL, AX, or EAX using an 8-bit I/O port
address.
 A fixed port instruction stored in ROM has its port number permanently fixed because of the
nature of read-only memory.
Example
IN AL,p8 ;8 bits are input to AL from I/O port p8
IN AX,p8 ;16 bits are input to AX from I/O port p8
IN EAX,p8 ;32 bits are input to EAX from I/O port p8
OUT p8,AL 8 bits are output to I/O port p8 from AL
OUT p8,AX 16 bits are output to I/O port p8 from AX
OUT p8,EAX 32 bits are output to I/O port p8 from EAX
 I/O port number (0000H to 00FFH) and I/O port number (0000H to FFFFH) held in register
DX.

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MOVSX and MOVZX

 MOVSX (move and sign-extend) and MOVZX (move and zero-extend).
 These instructions move data, and at the same time either sign- or zero-extend it.
 When a number is zero-extended, the most significant part fills with zeros.
 For example, if an 8-bit 34H is zero-extended into a 16-bit number, it becomes 0034H. Zero
extension is often used to convert unsigned 8- or 16-bit numbers into unsigned 16- or 32-bit
numbers by using the MOVZX instruction.
 A number is sign-extended when its sign-bit is copied into the most significant part.
 For example, if an 8-bit 84H is sign-extended into a 16-bit number, it becomes FF84H. The
sign-bit of an 84H is a 1, which is copied into the most significant part of the sign-extended
result. Sign extension is most often used to convert 8- or 16-bit signed numbers into 16- or 32-
bit signed numbers by using the MOVSX instruction.
BSWAP
 The BSWAP (byte swap) instruction is available only in the 80486–Pentium 4
microprocessors.
 This instruction takes the contents of any 32-bit register and swaps the first byte with the
fourth, and the second with the third.
For example, the BSWAP EAX instruction with
EAX = 00 11 22 33H swaps bytes in EAX, resulting in EAX = 33 22 11 00H
 The order of all 4 bytes is reversed by this instruction. This instruction is used to convert data
between the big- and little-endian forms.
CMOV
 The CMOV (conditional move) class of instruction is new to the Pentium Pro–Core2
instruction sets. There are many variations of the CMOV instruction.
Example
Assembly Lang | Flag(s) | Tested Operation
CMOVB C = 1 ;Move if below
CMOVAE C = 0 ;Move if above or equal
CMOVE or CMOVZ Z = 1 ; Move if equal or move if

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zero
CMOVS S = 1 ;Move if sign (negative)
CMOVNS S = 0 ;Move if no sign (positive)
An arithmetic instruction
 The arithmetic instructions include addition, subtraction, multiplication, division, comparison,
negation, increment, and decrement.
Addition Instruction
 Addition (ADD) appears in many forms in the microprocessor.
 A second form of addition, called add-with-carry, is introduced with the ADC instruction.
Finally, the increment instruction (INC) is presented. Increment is a special type of addition
that adds 1 to a number.
 The only types of addition not allowed are memory-to-memory and segment register.
Example
MOV AL, 3
MOV BL, 5
ADD AL, BL ;AL = AL + BL
 Whenever arithmetic and logic instructions execute, the contents of the flag register change.
Increment Addition.
 Increment addition (INC) adds 1 to a register or a memory location.
 The INC instruction adds 1 to any register or memory location, except a segment register.
 With indirect memory increments, the size of the data must be described by using the PTR,
directives.
 For example, the INC [DI] instruction is a byte-, word-, or doubleword-sized increment.
 INC BYTE PTR [DI] instruction indicates byte sized memory data.
 INC WORD PTR [DI] instruction indicates a word-sized memory data.
 INC DWORD PTR [DI] instruction indicates doubleword-sized data.
 INC QWORD PTR [RSI] instruction indicates quadword-sized data. (In 64-bit mode
operation of the Pentium 4 and Core2 processor)
MOV CL,1
MOV AL,0
ADD AL,CL

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INC CL
ADD AL,CL

Addition-with-Carry
 An addition-with-carry instruction (ADC) adds the bit in the carry flag (C) to the operand
data. This instruction mainly appears in software that adds numbers that are wider than 16
bits in the 8086.
 ADC affects the flags after the addition.
Subtraction
 Forms of subtraction (SUB) appear in the instruction set.
 These forms use any addressing mode with 8-, 16-, or 32-bit data.
 A special form of subtraction (decrement, or DEC) subtracts 1 from any register or memory
location.
 The subtract-with-borrow instruction (SBB) performs this type of subtraction. In the 80486
through the Core2 processors, the instruction set also includes a compare and exchange
instruction.
Register Subtraction
SUB BX,CX
SUB BX,DX.
Immediate Subtraction.
MOV CH,22H
SUB CH,44H
Decrement Subtraction.
 Decrement subtraction (DEC) subtracts 1 from a register or the contents of a memory
location.
 The decrement indirect memory data instructions require BYTE PTR, WORD PTR,
DWORD PTR, or QWORD PTR because the assembler cannot distinguish a byte from a
word.
DEC R14 R14 = R14 – 1 (64-bit mode)
DEC BYTE PTR[DI] Subtracts 1 from the byte contents of the data segment memory
location addressed by DI

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DEC WORD PTR[BP] Subtracts 1 from the word contents of the stack segment memory
location addressed by BP
DEC DWORD PTR[EBX] Subtracts 1 from the doubleword contents of the data segment
memory location addressed by EBX
DEC QWORD PTR[RSI] Subtracts 1 from the quadword contents of the memory location
addressed by RSI (64-bit mode)
Subtraction-with-Borrow.
 A subtraction-with-borrow (SBB) instruction functions as a regular subtraction, except that
the carry flag (C), which holds the borrow, also subtracts from the difference. The most
common use for this instruction is for subtractions that are wider than bits size.
 Wide subtractions require that borrows propagate through the subtraction, just as wide
additions propagate the carry.
Comparison
 The comparison instruction (CMP) is a subtraction that changes only the flag bits.
 The destination operand never changes.
 A comparison is useful for checking the entire contents of a register or a memory location
against another value.
 A CMP is normally followed by a conditional jump instruction, which tests the condition of
the flag bits.
Multiplication
 Multiplied by using a series of shifts and additions or subtractions.
 The product after a multiplication is always a double-width product. If two 8-bit numbers
are multiplied, they generate a 16-bit product.
 (IMUL) for signed integer or (MUL) for unsigned integer.
Example
MOV AL, 02H ;the product stored in AL register
MOV CL, 03H
MUL CL
Division
 Division by using a series of shifts and additions or subtractions.
 (IDIV) numbers are signed or (DIV) unsigned integers.
 The dividend is always a double-width. This means that an 8-bit division divides a 16-bit
number by an 8-bit number; a 16-bit division divides a 32-bit number by a 16-bit number; and
a 32-bit division.
Example

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MOV AL, 07H ; the dividend is 02 store in AL the reminder store in AH
MOV CL, 03H
DIV CL ;07/03

BCD AND ASCII ARITHMETIC

 The microprocessor allows arithmetic manipulation of both BCD (binary-coded decimal) and
ASCII (American Standard Code for Information Interchange) data. This is accomplished by
instructions that adjust the numbers for BCD and ASCII arithmetic.
 Two arithmetic techniques operate with BCD data: addition and subtraction. The instruction set
provides two instructions that correct the result of a BCD addition and a BCD subtraction.
 The DAA (decimal adjust after addition) instruction follows BCD addition.
 The DAS (decimal adjust after subtraction) follows BCD subtraction. Both instructions
correct the result of the addition or subtraction so that it is a BCD number.
The logic instruction
 The logic instructions include AND, OR, Exclusive-OR, NOT, shifts, rotates, and the logical
compare (TEST).
 The logic instructions allow bits to be set, cleared, or complemented.
AND operation
 The AND operation performs logical multiplication, the function generates a logic 1 output
both input are 1.

(a) The truth table for the AND operation and

(b) the logic symbol of an AND gate

OR operation
 The OR operation performs logical addition and is often called the Inclusive-OR function. The
OR function generates a logic 1 output if any inputs are 1.

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(a) The truth table for the OR operation and

(b) the logic symbol of an OR gate

Exclusive-OR
 The Exclusive-OR instruction (XOR) differs from Inclusive-OR (OR). The difference is that a
1,1 condition of the OR function produces a 1; the 1,1 condition of the Exclusive-OR operation
produces a 0.

(a) The truth table for the Exclusive-OR operation and

(b) the logic symbol of an Exclusive-OR gate.

Shift instruction
 Shift instructions position or move numbers to the left or right within a register or memory
location.
 They also perform simple arithmetic such as multiplication by powers of 2+n (left shift) and
division by powers of 2-n (right shift).
 Direction of the shift.

Rotate instruction
Rotate instructions position binary data by rotating the information in a register or memory
location, either from one end to another or through the carry flag.

Microprocessor 8086 Lecture Note 30 | P a g e By Kaledawit E