Tessent Integrated Flow Lab3 Basic Block-Based Bottom-Up DFT Flow Overview
Tessent Integrated Flow Lab3 Basic Block-Based Bottom-Up DFT Flow Overview
Lab3:
Basic Block-based Bottom-up DFT Flow
Overview
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Table of Contents
Before you Begin ...............................................................................................................................2
Notes.................................................................................................................................................8
If this is the first time you are launching this VM (Virtual Machine), you must download and extract
the lab data as described in the "Obtaining Lab Data section below.
Whenever you are using the VM for lab exercises and are finished with your session, please use the
Caution
"Disconnect" feature of the Desktop Viewer before the VM times out to preserve the data from one
session to the next. Failure to do so will remove the VM, and its contents.
If the VM was removed, you will be presented with a new VM requiring you to follow the download
and extract process. This allows you to "refresh" the lab data so you can go through the labs again
with a new database.
If this is the first time you are starting a session for this VM, the flow_data directory will not be in the
home directory and you will need to download and extract it using the following instructions.
1. Double click on the Desktop icon Download_lab_data, . This launches a web browser.
3. In the resultant window, select the Download button, enable the Save File button, then, select the
OK button to download the file.
4. Move the file in the Downloads directory to the home directory. If you are using the terminal
(Applications>Favorites>Terminal) you can use the following command:
mv ./Downloads/tessent_flow_data_v2020.3_20201025.tgz .
5. In a terminal window, extract the files from the compressed tar file using the command:
Basic Block-based Bottom-up DFT Flow Overview 2
Lab Workbook
You should now have a directory named flow_data in your Home directory. That directory contains all
the files you need to perform the exercises, in this learning path.
Lab3:
Basic Block-based Bottom-up DFT Flow
Overview
Objectives
Upon completion of this lab, you should be able to use Tessent Shell to
Usage of design_id
Introduction
In this lab, you will learn the basic building blocks necessary to perform block-based bottom up Design
for Test (DFT) insertion.
Instructions
1. Change to the $FLOW_LABS/Lab3/Exercise1
$ cd $FLOW_LABS/Lab3/Exercise1
o Under the library directory there is standard_cells directory that has verilog and tessent
directories that contain the Verilog simulation library and Tessent Cell Library
respectively.
4. First step is to set the context to load in an RTL design. This being the first Design for Test (DFT)
insertion pass, use –design_id as rtl1
SETUP> set_context dft -rtl -design_id rtl1
5. Second step is to specify the location of the Tessent Shell Data Base (TSDB) directory to be one
level higher up than the current working directory
SETUP> set_tsdb_output_directory ../tsdb_outdir
6. For DFT to be inserted into RTL design, there may not be any Tessent libraries needed, but if it is
then load the necessary library files.
SETUP> read_cell_library \
library/standard_cells/tessent/adk.tcelllib
7. The next step is to load all the RTL design blocks for DFT inserted for this design block using the
read_verilog command. This is an example of entering the command at a session prompt.
SETUP> read_verilog rtl/carrier_nco.v
8. Loading all the verilog files is a tedious typing exercise. A more efficient method is to use a
“dofile”. Open and review the load_rtl.do file, taking note that it contains the following
collection of read_verilog commands for this block of the design.
read_verilog rtl/accumulator.v
read_verilog rtl/code_nco.v
read_verilog rtl/lpm_counter.v
read_verilog rtl/time_base.v
read_verilog rtl/carrier_mixer.v
read_verilog rtl/code_gen.v
read_verilog rtl/epoch_counter.v
read_verilog rtl/lpm_counter_ud.v
read_verilog rtl/lpm_shiftreg.v
read_verilog rtl/tracking_channel.v
read_verilog rtl/gps_baseband.v
9. Execute the dofile, load_rtl.do, to load the remaining RTL modules for the gps_baseband block.
SETUP> dofile load_rtl.do
11. Specify this design level as a physical_block into which the DFT needs to be inserted.
SETUP> set_design_level physical_block
Notes