Appendix A: Verilog Cheat Sheet

Numbers and constants always@(posedge myclock)

Example: 4-bit constant 10 in binary, hex and in cnt = cnt + 1;
decimal: 4’b1010 == 4’ha -- 4’d10
Blocking vs. unblocking assignment <= vs. =
(numbers are unsigned by default)
The <= assignment operator is non-blocking (i.e. if
Concatenation of bits using {} use in an always@(posedge) it will be performed on
every positive edge. If you have many non-blocking
4’b1011 == {2’b10 , 2’b11}
assignments they will all be updated in parallel. The
Constants are declared using parameter: <= operator must be used inside an always block –
parameter myparam = 51 you can’t use it in an assign statement.

Operators The blocking assignment operator = can be used in

either an assign block or an always block. But it
Arithmetic: and (+), subtract (-), multiply (*), divide causes assignments to be performed in sequential
(/) and modulus (%) all provided. order. This tends to result in slower circuits, so
Shift: left (<<), shift right (>>) avoid using it (especially for synthesized circuits)
unless you have to.
Relational ops: equal (==), not-equal (!=), less-than
(<), less-than or equal (<=), greater-than (>), Case and if statements
greater-than or equal (>=). Case and if statements are used inside an always
Bitwise ops: and ( & ), or ( | ), xor ( ˆ ), not ( ˜ ) block to conditionally update state. e.g.:
Logical operators: and (&&) or (||) not (!) note that always @(posedge clock)
these work as in C, e.g. (2 && 1) == 1 if (add1 && add2) r <= r+3;
else if (add2) r <= r+2;
Bit reduction operators: [n] n=bit to extract else if(add1) r <= r+1;
Conditional operator: ? to multiplex result Note that we don’t need to specify what happens
Example: (a==1)? funcif1 : funcif0 when add1 and add2 are both false since the default
behavior is that r will not be updated. Equivalent
The above is equivalent to: function using a case statement:
((a==1) && funcif1) always @(posedge clock)
|| ((a!=1) && funcif0) case({add2,add1})
2’b11 : r <= r+3;
Registers and wires 2’b10 : r <= r+2;
Declaring a 4 bit wire with index starting at 0: 2’b01 : r <= r+1;
default: r <= r;
wire [3:0] w;
endcase
Declaring an 8 bit register:
Module declarations
reg [7:0] r;
Modules pass inputs, outputs as wires by default.
Declaring a 32 element memory 8 bits wide:
module ModName (
reg [7:0] mem [0:31] output reg [3:0] result, // register output
Bit extract example: input [1:0] bitsin, input clk, inout bidirectnl );
… code …
r[5:2] returns 4 bits between pos 2 to 5 inclusive endmodule
Assignment Verilog Simulation / ISIM commands
Assignment to wires uses the assign primitive $display ("a string to display");
outside an always block, e.g.: $monitor ("like printf. Vals: %d %b", decv,bitv);
assign mywire = a & b #100 // wait 100ns or simulation moments
$finish // end simulation
Registers are assigned to inside an always block
which specifies where the clock comes from, e.g.:
 Appendix B: ARM Assembly Language Cheat Sheet

Memory access instructions

LDR Rd, [Rn] ; load 32-bit number at [Rn] to Rd
LDR Rd, [Rn,#off] ; load 32-bit number at [Rn+off] to Rd
STR Rt, [Rn] ; store 32-bit Rt to [Rn]
STR Rt, [Rn,#off] ; store 32-bit Rt to [Rn+off]
PUSH {Rt} ; push 32-bit Rt onto stack
POP {Rd} ; pop 32-bit number from stack into Rd

MOV{S} Rd, <op2> ; set Rd equal to op2

MOV Rd, #im16 ; set Rd equal to im16, im16 is 0 to 65535
MVN{S} Rd, <op2> ; set Rd equal to -op2

Branch instructions
B label ; branch to label Always
BEQ label ; branch if Z == 1 Equal
BNE label ; branch if Z == 0 Not equal
BCS label ; branch if C == 1 Higher or same, unsigned ≥
BHS label ; branch if C == 1 Higher or same, unsigned ≥
BCC label ; branch if C == 0 Lower, unsigned <
BLO label ; branch if C == 0 Lower, unsigned <
BMI label ; branch if N == 1 Negative
BPL label ; branch if N == 0 Positive or zero
BVS label ; branch if V == 1 Overflow
BVC label ; branch if V == 0 No overflow
BHI label ; branch if C==1 and Z==0 Higher, unsigned >
BLS label ; branch if C==0 or Z==1 Lower or same, unsigned ≤
BGE label ; branch if N == V Greater than or equal, signed ≥
BLT label ; branch if N != V Less than, signed <
BGT label ; branch if Z==0 and N==V Greater than, signed >
BLE label ; branch if Z==1 or N!=V Less than or equal, signed ≤
BX Rm ; branch indirect to location specified by Rm
BL label ; branch to subroutine at label
BLX Rm ; branch to subroutine indirect specified by Rm

Logical instructions
AND{S} {Rd,} Rn, <op2> ; Rd=Rn&op2 (op2 is 32 bits)
ORR{S} {Rd,} Rn, <op2> ; Rd=Rn|op2 (op2 is 32 bits)
EOR{S} {Rd,} Rn, <op2> ; Rd=Rn^op2 (op2 is 32 bits)
BIC{S} {Rd,} Rn, <op2> ; Rd=Rn&(~op2) (op2 is 32 bits)
ORN{S} {Rd,} Rn, <op2> ; Rd=Rn|(~op2) (op2 is 32 bits)
LSR{S} Rd, Rm, Rs ; logical shift right Rd=Rm>>Rs (unsigned)
LSR{S} Rd, Rm, #n ; logical shift right Rd=Rm>>n (unsigned)
ASR{S} Rd, Rm, Rs ; arithmetic shift right Rd=Rm>>Rs (signed)
ASR{S} Rd, Rm, #n ; arithmetic shift right Rd=Rm>>n (signed)
LSL{S} Rd, Rm, Rs ; shift left Rd=Rm<<Rs (signed, unsigned)
LSL{S} Rd, Rm, #n ; shift left Rd=Rm<<n (signed, unsigned)

Arithmetic instructions
ADD{S} {Rd,} Rn, <op2> ; Rd = Rn + op2
ADD{S} {Rd,} Rn, #im12 ; Rd = Rn + im12, im12 is 0 to 4095
SUB{S} {Rd,} Rn, <op2> ; Rd = Rn - op2
SUB{S} {Rd,} Rn, #im12 ; Rd = Rn - im12, im12 is 0 to 4095
RSB{S} {Rd,} Rn, <op2> ; Rd = op2 - Rn
RSB{S} {Rd,} Rn, #im12 ; Rd = im12 – Rn
CMP Rn, <op2> ; Rn – op2 sets the NZVC bits
MUL{S} {Rd,} Rn, Rm ; Rd = Rn * Rm signed or unsigned
Notes
Ra Rd Rm Rn Rt represent 32-bit registers
value any 32-bit value: signed, unsigned, or address
{S} if S is present, instruction will set condition codes
#im12 any value from 0 to 4095
#im16 any value from 0 to 65535
{Rd,} if Rd is present Rd is destination, otherwise Rn
#n any value from 0 to 31
#off any value from -255 to 4095
label any address within the ROM of the microcontroller
op2 the value generated by <op2>