Vision: To become a Centre of Excellence in Teaching and Research in the field of Computer

Science and Engineering

Department of Computer Science and Engineering

Computer Architecture and

organization-CSE210

Question Bank

1
Vision: To become a Centre of Excellence in Teaching and Research in the field of Computer
Science and Engineering

Kalasalingam Academy of Research and Education

(Deemed to be University)
Anand Nagar, Krishnan koil - 626126

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

COURSE PLAN – EVEN SEMESTER 2017-2018

Subject with code Computer Architecture and organization

Course B.Tech (CSE)
Semester / Sec IV/A-D
Course Credit 3
Course Coordinator Mr.S.Sankaranarayanan
Module Coordinator Mr.M.Raja
Programme Coordinator Dr.K.Kartheeban

Pre Requisites
 Operating Systems(CSE207)
 Digital Electronics(ECE202)

Course Description

This course aims to provide a strong foundation for students to understand computer system
architecture and to apply these insights and principles to future computer designs. The course is
structured around the three primary building blocks of general-purpose computing systems:
processors, memories, and input/output.

This course includes the organization and architecture of computer systems hardware; instruction
set architectures; addressing modes; register transfer notation; processor design and computer
arithmetic; memory systems; hardware implementations of virtual memory, and input/output
control and devices

Carrier Opportunities

Computers have become a ubiquitous part of modern life, and new applications are introduced
every day. The use of computer technologies is also common place in all types of organizations, in
academia, research, industry, government, private and business organizations. As computers
become even more pervasive, the potential for computer-related careers will continue to grow and
the career paths in computer-related fields will become more diverse.

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Programme Outcomes (POs)

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend

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 and write effective reports and design documentation, make effective presentations, and
give and receive clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of the
Engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary
environments.
12. Life -long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life -long learning in the broadest context of technological
change.
Course Outcomes

CO Description
Understand the functional units of a computers, bus structures and addressing modes
CO1
CO2
Apply the knowledge of algorithms to solve arithmetic problems.
CO3
Demonstrate single bus, multiple bus organization and pipelining concepts
CO4 Analyze RAM, ROM, Cache memory and virtual memory concepts

CO5 Evaluate the various I/O interfaces

PROGRAMME SPECIFIC OUTCOME

PSOs DESCRIPTION
PSO1 Problem-Solving Skills: The ability to apply mathematics, science and computer
engineering knowledge to analyze, design and develop cost effective computing solutions
for complex problems with environmental considerations.
PSO2 Professional Skills: The ability to apply modern tools and strategies in software project
development using modern programming environments to deliver a quality product for
business accomplishment.
PSO3 Communication and Team Skill: The ability to exhibit proficiency in oral and written
communication as individual or as part of a team to work effectively with professional
behaviors and ethics.
PSO4 Successful Career and Entrepreneurship: The ability to create a inventive career path by
applying innovative project management techniques to become a successful software
professional, an entrepreneur or zest for higher studies.

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 MAPPING OF POs and PSOs:

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
PSO1 S S S S
PSO2 S S S M S
PSO3 S M S S S
PSO4 M S M M M S S
CO and PO Mapping

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 S M M M M M
CO2 S S M M
CO3 S S
CO4 M M M
CO5 M M M M S
S- Strong Correlation M- Medium Correlation L – Low Correlation

MAPPING OF COs AND PSOs:

PSO1 PSO2 PSO3 PSO4
CO1 S L
CO2 S L L
CO3 S M L
CO4 S L L
CO5 S S M

Content Delivery Methodologies

 Class Room – Interactive Lectures

 Class Room – PowerPoint Presentations
 Student Seminars
 Guest Lectures
 Workshops

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  Demonstration Sessions - Tools

 Assessment Methodologies

Direct Indirect
 Examinations  Course End Surveys
 Assignments
 Seminars
 Tutorials
 Quiz
Text Book:

T1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, Computer Organization,
McGraw- Hill, 2002, 5th Edition.
Reference books:

R1. William Stallings, Computer Organization and Architecture – Designing

for Performance, Pearson Education, 6th Edition, 2003.

R2. David A.Patterson and John L.Hennessy, Computer Organization and design:
The hardware software interface, Morgan Kaufmann, 2nd Edition, , 2002.

R3. John P.Hayes, Computer Architecture and Organization, McGraw Hill, 3rd
Edition, 1998.

Lesson Plan:
Cumulat Delivery
Topic Topic Name Reference No. Of ive No. method
No Periods Of
periods
UNIT I – BASIC STRUCTURE OF COMPUTERS
1. Functional units - Basic operational 2 2 PPT
T1: 1-9
concepts
2. Bus structures - Software performance 9-17 2 4 PPT
3. Memory locations and addresses 33-36 1 5 PPT
4. Instruction and instruction sequencing 37-47 2 7 PPT
5. Addressing modes 48-56 2 9 PPT
6. Assembly language – Basic I/O 58-64 2 11 Flipped
operations class room
7. Stacks and queues(Student Seminar) 68 1 12 PPT

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 UNIT II – ARITHMETIC UNIT

8. Addition and subtraction of signed 2 13 Black Board

T1: 368-372
numbers, Design of fast adders
9. Multiplication of positive numbers - 376 1 14 Black Board
10. Signed operand multiplication and fast 380-385 2 16 Black Board
multiplication
11. Integer division 390-392 1 17 Black Board
12. Floating point numbers and operations. 393-400 2 19 Flipped
class room
Tutorials 1 20
UNIT III – BASIC PROCESSING UNIT
13. Fundamental concepts – Execution of a 2 22 PPT
T1: 412-422
complete instruction
14. Multiple bus organization 423-424 1 23 PPT
15. Hardwired control 425-428 2 25 PPT
16. Micro programmed control 429-443 2 27 PPT
17. Pipelining – Basic concepts 454-458 1 28 PPT
18. Data hazards – Instruction hazards 461-470 2 30 PPT
19. Influence on Instruction sets(Student 476-478 1 31 PPT
Seminar)
20. Data path and control 479-486 2 33 PPT
consideration – Superscalar operation.

UNIT IV – MEMORY SYSTEM

21. Basic concepts 292-294 1 34 PPT
22. Semiconductor RAMs - ROMs – 295-313 3 37 PPT
Speed - size and cost
23. Cache memories - Performance 314-335 3 40 PPT
consideration
24. Virtual memory 337-339 2 42 Flipped
class room
25. Memory Management requirements 343 1 43 PPT
26. Secondary storage.( Student Seminar) 344-358 2 45 PPT

UNIT V – I/O ORGANIZATION

27. Accessing I/O devices 204-207 1 46 PPT
28. Interrupts 208-220 2 48 PPT
29. Direct Memory Access 234-239 2 50 PPT
30. Buses 240-247 1 51 PPT
31. Interface circuits 248-258 2 53 PPT
32. Standard I/O Interfaces (PCI, SCSI, 259-272 2 55 PPT
USB)(Student Seminar)

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Journals to be referred

1. IEEE Transactions on computer architecture letters

2. http://grouper.ieee.org/groups/754/
3. Computer architecture for machine perception; proceedings.(Brief Article)
(Book Review)

Web Resources

Unit Topic
No Web link

Basic Structure of
computers 1. http://www.cs.mcgill.ca/~mhawke1/cs208/02a-
1 ComputerStructureNotes.pdf
2. http://www.stat.auckland.ac.nz/~dscott/782/Computers.pdf
3. people.bu.edu/bkia/PDF/Computer%20Architecture.pdf

2. Arithmetic Unit: 1. ecl.incheon.ac.kr/courses/ca5/ca00f.pdf

2. www-csag.ucsd.edu/teaching/cse141-
w00/lectures/Introduction.pdf –

3. Basic Processing 1. www.cise.ufl.edu/~prabhat/Teaching/cda5155-

Unit: su09/lecture.html
2. ecl.incheon.ac.kr/courses/ca6/ca00.syllabus.pdf
3. www.site.uottawa.ca/~mbolic/ceg4131/Ch_14_superscal
ar.ppt

4 Memory System: www.ece.eng.wayne.edu/~gchen/ece4680/lecture-

notes/lecture-notes.html
2. www.cs.berkeley.edu/~pattrsn/252S01/index.html
3. 140.113.88.21/course/Computer/handout/Ch0.pdf

5. I/O organization: 1. www.cs.utwente.nl/~co/co213030/sheets/col10.pdf

2. www.ece.eng.wayne.edu/~gchen/ece4680/lecture-
notes/lecture-notes.html -
3. www.cs.utwente.nl/~co/co213030/sheets/col10.pdf
4. www.cs.utexas.edu/~dburger/teaching/cs352-
s07/lectures_07/Lecture_1.pdf

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Portions for sessional examinations

S.No Test No Topics

1. Sessional Examination I 1-11
2. Sessional Examination II 12-22
3. Sessional Examination III 23-32
4. End semester Examination 1-32

MAPPING OF CO TO ASSIGNMENTS and TUTORIALS

CO Assignment I Assignment II Assignment III Tutorial I Tutorial II

CO1 √
CO2 √
CO3 √

CO4 √

CO5 √

Assessment plan for the course

S.No Course outcomes How measured When measured

1. Understand the functional Based on performance in After Sessional I and end

units of a computers, bus sessional I,End semester semester
structures and addressing and assignment I
modes
2. Based on performance in After Sessional
Apply the knowledge of
sessional I,sessional I,Sessional II and end
algorithms to solve
II,End semester and semester
arithmetic problems.
tutorial I
3. Demonstrate about single Based on performance in After Sessional II,End
bus, multiple bus sessional II,End semester semester and end
organization and pipelining and assignment II semester
concepts RAM, ROM, Cache Based on performance in
4. Analyze After Sessional III, End
memory and virtual memory sessional III,End semester semster and tutorial II
concepts and tutorial II
5. Based on performance in After Sessional III, End
Evaluate the various I/O
sessional III,End semester semster and assignment
interfaces
and assignment III III

Content beyond syllabus

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  Multi core architecture
 Parallel processing
 Instruction set architecture

Related Online Courses

Name of the course Web link

University/Org
Computer Architecture NPTEL https://onlinecourses.nptel.ac.in/
noc17_cs16/preview

https://www.coursera.org/learn/
Computer CourseEra comparch
Architecture

Computer System Stanford https://lagunita.stanford.edu/courses/

Architecture Engineering/EE282/Spring2014/about

Practical components

1. Write a program to perform signed operand multiplication using Booth algorithm

2. Write a program to perform signed operand multiplication using bit pair recording of
multiplier
3. Write a program to perform 1101/10 using non restoring division.
4. Write a program to perform 1101/10 using restoring division.

Course Coordinator Module Coordinator

Mr.S.Sankaranarayanan Mr.M.Raja

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 Programme Coordinator HOD/CSE
Dr.K.Kartheeban Dr.R.Ramalakshmi

KALASALINGAM UNIVERSITY
( Kalasalingam Academy of research and Education)
Department of CSE

Name of the subject :Computer Architecture and organization

Year/Sem/Sec : II/IV/A-D

UNIT I- BASIC STRUCTURE OF COMPUTER

1. What are the basic functional units of a computer?

Ans: A computer consists of five functionally independent main parts namely
o Input Unit
oMemory Unit
o Arithmetic and logic Unit
o Output Unit
o ControlUnit

2. Define RAM.
Ans: Memory in which any location can be reached in a short and fixed amount of time
after specifying its address is called random access memory.

3. Define memory access time.

Ans: The time required to access one word is called memory access time.

4. What is instruction register (IR) and program counter (PC) used for ?
Ans: The instruction register (IR) holds the instruction that is currently being
executed .Its output is available to the control circuits which generate the timing signals
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 that control the various processing elements.
The program counter PC) is used to keep track of the execution of the program. It
contains the memory address of the next instruction to be fetched and executed.

5. Compare memory address register(MAR) and memory data register(MDR)?

Ans: The MAR holds the address of the location to be accessed. The MDR contains the
data to be written into or read out of the addressed location.

6. What is an interrupt?

Ans: An interrupt is a request from an I/O device for service by the processor. The
processor provides the requested service by executing an appropriate interrupt service
routine.

7. Explain about Bus.

Ans: Bus is a group of lines that serves as a connecting path for several devices. In
addition to the lines that carry the data , the bus must have the lines for address and
control purposes.

8. What do you mean by multiprogramming or multitasking?

Ans: The operating system manages the concurrent execution of several application
programs to make best possible use of computer resources. This pattern of concurrent
execution is called multiprogramming or multitasking.

9. Give the basic performance equation.

Ans: The basic performance equation is given as

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 T = N *S/ R
T = It is the processor time required to execute a program
N= It is the actual number of instruction executions.
S = It is the average number of basic steps neede to execute one machine instruction.
R = It is the clock rate.

10. Explain the concept of pipelining.

Ans: Pipelining is the means of executing machine instructions concurrently. It is the
effective way of organizing concurrent activity in a computer system. It is a process of
substantial improvement in the performance by overlapping the execution of successive
instructions.

11. What are the two techniques used to increase the clock rate R?
Ans: The two techniques used to increase the clock rate R are:
1. The integrated – circuit (IC) technology can be increased which reduces the time
needed to complete a basic step.
2. We can reduce the amount of processing done in one basic step.

12. What is Big – Endian and Little- Endian representations.

Ans: The Big- endian is used when lower byte addresses are used for the more
significantbytes (The leftmost bytes) of the word.
The little-endian is used for the opposite ordering, where the lower byte addresses are
used for the less significant bytes ( the rightmost bytes) of the word.

13. What is the use of load and store operations

Ans:Load operation transfers the copy of contents of specific memory location to
processor.
Store operation transfers an item of information from processor to specific memory
location.

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14. What is addressing mode?
Ans: The addressing mode is defined as the different ways in which the location of an
operand is specified in an instruction.

15. What are the different types of addressing modes available?

Ans: The different types of addressing modes available are:
1. Immediate addressing mode
2. Register addressing mode
3. Direct or absolute addressing mode
4. Indirect addressing mode
5. Indexed addressing mode
6. Relative addressing mode
7. Autoincrement
8. Autodecrement

16. Write an assembly language for the following instruction.

B=A+6
Ans: Mov A,R0
Add #6,R0
Mov R0,B

17. What is indirect addressing mode?

Ans: The effective address of the operand is the contents of a register or memory
location whose address appears in the instruction

18. What is indexed addressing mode?

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 Ans: The effective address of the operand is generated by adding a constant value to
the contents of a register.

19. Define auto increment mode of addressing?

Ans: The effective address of the operand is the contents of a register specified in the
instruction. After accessing the operand, the contents of this register are automatically
incremented to point to the next item in the list.

20. Define auto decrement mode of addressing?

Ans: The contents of a register specified in the instruction are first automatically
decremented and are then used as the effective address of the operand.

21. What are condition code flags?

Ans: The processor has to keep track of the information about the results of various
operations for the subsequent conditional branch instructions. This is done by recording
required information in individual bits called condition code flags.

22. What are the commonly used flags?

Four commonly used flags are:
N( Negative )
Z(Zero)
V(overflow)
C(Carry)

23. What do you mean by assembler directives?

Ans: These are the instructions which direct the program to be executed. They have no
equivalent so they are called pseudo-opcodes. These instructions are used to

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 define symbols, allocate space for variable, generate fixed tables etc.
Examples : END, NAME

24. What is use of loader?

Ans: Loader is utility program which is stored in the memory. When the loader
program is executed it performs a sequence of input operations needed to transfer the
machine language program from the disk into a specified place in the memory.

25. What do you mean by relative addressing mode?

Ans: The effective address is determined by the index mode using the program counter
in place of the general purpose register Ri.

26. What is meant by zero address instruction

Ans: Location of all the operands are defined explicitly in the instruction.
Ex: Pushdown stack

27. Consider a computer that has byte addressable memory organized in 32 bit words
according to big endian scheme. A program that reads ASCII characters entered
at a keyboard and stores them in successive memory locations starting at locations
1000.Show the contents of two memory words at locations 1000 and1004 after the
name “Johnson” has been entered.

J 0 H N 1000

S O N
1004

28. Consider a computer that has byte addressable memory organized in 32 bit words

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 according to little endian scheme. A program that reads ASCII characters entered
at a keyboard and stores them in successive memory locations starting at locations
1000.Show the contents of two memory words at locations 1000 and1004 after the
name “Johnson” has been entered.

N H O J 1000

N O S 1004

Part B
1. Explain the various functional units of computer.
2. Explain the connection between processor and memory with neat diagram.
3. Explain the various techniques to measure the performance of a computer.
4. Explain the various instruction types with examples.
5. Explain briefly about various addressing modes with examples.
6. Explain briefly about various assembler directives with examples.
7. Explain basic I/O operations.
8. Explain the routine for safe push and safe pop operation in stack.
9. Write a program that can evaluate the expression
E=A*B+C/D
Use single address,two address and three address instruction types.
10. Registers R1 and R2 of a computer contain decimal values 1200 and 4600.
What is the effective address of memory operand in each of the following
instructions?
(a) Load 20(R1),R5
(b) Move #3000,R5
(c) Store R5,20(R1,R2)

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 (d) Add –(R2),R5
(e) Subtract (R1)+,R5

UNIT II
ARITHMETIC UNIT
1. What is half adder?
Ans: A half adder is a logic circuit with two inputs and two outputs, which adds
two bits at a time, producing a sum and a carry.

2. What is full adder?

Ans: A full adder is logic circuit with three inputs and two outputs, which adds three
bits at a time giving a sum and a carry.

3. What is signed binary?

Ans: A system in which the leading bit represents the sign and the remaining bits the
magnitude of the number is called signed binary. This is also known as sign
magnitude.

4. What are the two approaches used to reduce delay in adders?

Ans:
1) The first approach is to use the fastest possible electronic technology in

18
 implementing the ripple-carrylogic design.
2) The second approach is to use an augmented logic gate network structure.

5. What is a carry look-ahead adder?

Ans: The input carry needed by a stage is directly computed from carry signals
obtained from all the preceding stages i-1,i-2,.....0, rather than waiting for normal
carries to supply slowly from stage to stage. An adder that uses this principle isa
called carry look-ahead adder.

6. What are the main features of Booth’s algorithm?

Ans:
1) It handles both positive and negative multipliers uniformly.
2) It achieves some efficiency in the number of addition required when the multiplier
has a few large blocks of 1s.

7.Draw 4 bit ripple carry adder.

8. Draw the addition subtraction binary network

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9. Convert the following pairs of decimal numbers to 4 bit signed 2’s complement
numbers and add them.State whether overflow occurs or not.
-5 and -2
Ans: -5 1011
-2 1110
1001
No overflow.

10. Convert the following pairs of decimal numbers to 4 bit signed 2’s complement
numbers and subtract them.State whether overflow occurs or not.

+6 and +3

Ans: 6 0110 0110

3 0011 2’s com +3 1101
0011
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 No overflow.

11. What is bit pair recoding? Give an example.

Ans: Bit pair recoding halves the maximum number of summands. Group the Booth-
recoded multiplier bits in pairs and observe the following: The pair (+1-1) is equivalent to
to the pair (0+1). That is instead of adding-1times the multiplicand m at shift position I to
+1 ́ X M at position i+1, the same result is obtained by adding +1 X M at position i.
Eg: 11010–Bit Pair recodingvalue is 0-1-2

12. Write the algorithm for restoring division.

Ans: Do the following for n times:
1) Shift A and Q left one binary position.
2) Subtract M and A and place the answer back in A.
3) If the sign of A is 1, set q0 to 0 and add M back to A.
Where A-Accumulator, M-Divisor, Q-Dividend.

13. Write the algorithm for non restoring division.

Ans: Do the following for n times:
Step 1:
Do the following for n times:
1) If the sign of A is 0 , shift A and Q left one bit position and subtract M from
A;otherwise , shift A and Q left and add M to A.
2) Now, if the sign of A is 0,set q0 to 1;otherwise , set q0 to0.

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 Step 2: if the sign of A is 1, add M to A.

14. When can you say that a number is normalized?

Ans: When the decimal point is placed to the right of the first (nonzero) significant
digit, the number is said to be normalized.

15. Explain about the special values in floating point numbers.

Ans:
The end values 0 to 255 of the excess-127 exponent E’ used to represent special
values such as:
a)When E’=0 and the mantissa fraction M is zero the value exact 0 is represented.
b)When E’=255 and M=0, the value ¥ is represented.
c)When E’=0 and M ≠0 , denormal values are represented.
d)When E’=255 and M≠0, the value represented is called Not a number.

16. Write the Add/subtract rule for floating point numbers.

Ans:
1) Choose the number with the smaller exponent and shift its mantissa right a
number of steps equal to the difference in exponents.
2) Set the exponent of the result equal to the larger exponent.
3) Perform addition/subtraction on the mantissa and determine the sign of the result
4) Normalize the resulting value, if necessary.

17. Write the multiply rule for floating point numbers.

Ans:
1) Add the exponent and subtract 127.
2) Multiply the mantissa and determine the sign of the result .
3) Normalize the resulting value , if necessary.

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18. What is guard bit?
Ans: Although the mantissa of initial operands are limited to 24 bits, it is important to
retain extra bits, called as guard bits.
19. What are the ways to truncate the guard bits?
Ans: There are several ways to truncate the guard bits:
1) Chooping
2) Von Neumann rounding
3) Rounding
20. Define carry save addition(CSA) process.
Ans: Instead of letting the carries ripple along the rows, they can be saved and introduced
into the next roe at the correct weighted position. Delay in CSA is less than delay through
the ripple carry adder.

21. What is excess-127 format?

Ans: Instead of the signed exponent E, the value actually stored in the exponent field is
and unsigned integer E’=E+127.This format is called excess-127.

22. What is floating point numbers?

Ans: In some cases, the binary point is variable and is automatically adjusted as
computation proceeds. In such case, the binary point is said to float and the numbers are
called floating point numbers.

23. In floating point numbers when so you say that an underflow or overflow has
occurred?
Ans: In single precision numbers when an exponent is less than-126 then we say that an
underflow has occurred. In single precision numbers when an exponent is less than +127
then we say that an overflow has occurred

24. List out the various exceptions

Ans: Overflow, underflow, divide by zero, invalid, inexact

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25. Represent the flowing number in IEEE single precision format.
+0.0010110…X 29
Number is normalized first normalize the number
+1.0110…X 26

0 10000101 0110

Part B

1. Design fast adder with diagram

2. Explain carry look ahead adder with example.
3. Explain sequential circuit binary multiplier with example.
4. Explain booth algorithm with example.
5. Multiply the following positive numbers using sequential circuit binary multiplier.
Multiplicand=10110
Multiplier=11011
6. Multiply the following pairs of signed 2’s complement numbers using booth
algorithm.
Multiplicand=10110
Multiplier=11011

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 7. Multiply the following pairs of numbers using booth algorithm.
Multiplicand = -13
Multiplier = +6

8. Multiply the following numbers using bit pairing of multipliers

Multiplicand = 11011
Multiplier = 00100
9. Multiply the following numbers using carry save addition
Multiplicand = 011011
Multiplier = 001001
10. Write the algorithm for restoring division and perform the following using
restoring division 1111/0011
11. Write the algorithm for non restoring division and perform the following using non
restoring division 1111/0011.
12. Explain the operation of floating point addition and subtraction.

UNIT III
BASIC PROCESSING UNIT

1. What are the basic steps required to execute an instruction by the processor?

Ans: The basic steps required to execute an instruction by the processor are:
1) Fetch the contents of the memory location pointed to by the PC. They are loaded into
the IR.
IR [[PC]]
2) Assuming that the memory is byte addressable, increment the contents of the PC by 4,

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that is PC [PC} + 4
3) Carry out the action specified by the instruction in the IR.

2. Define datapath in the processor unit.

Ans: The registers, the ALU and the interconnecting bus are collectively referred to as
the datapath.

3. What is processor clock?

Ans: All operations and data transfers within the processor take place within time periods
defined by the processor clock .

4. Write down the control sequence for Move (R1), R2.

Ans: The control sequence is :
(1) R1out, MARin,Read
(2) MDRoutE,WMFC
(3) MDRout,R2 in

5.Define register file .

Ans: A set of general purpose registers are called as register file Each register from register file
R0 is individually addressable.

6. Draw the hardware organization of two-stage pipeline?

Instruction Fetch Unit

Execution Unit
Inter stage buffer

26
7. What is the role of cache memory in pipeline?

Ans: The use of cache memory is to solve the memory access problem. When cache is
included in the processor the access time to the cache is usually the same time needed to
perform other basic operation inside the processor.

8.Name the methods for generating the control signals.

Ans: The methods for generating the control signals are:

1) Hardwired control
2) Microprogrammed control

9. Define hardwired control.

Ans: Hard-wired control can be defined as sequential logic circuit that generates specific
sequences of control signal in response to externally supplied instruction.

10. Define micro programmed control.

Ans: A micro programmed control unit is built around a storage unit is called a control store
where all the control signals are stored in a program like format. The control store stores a set
of micro programs designed to implement the behavior of the given instruction set.

11. Differentiate Micro programmed control from hardwired control.

Hardwired control Micro programmed control

It is the sequential circuit that It is the micro program in control store that
generates control signals. generates control signals
Speed of operation is high Speed of operation is low, because it involves
memory access.

27
Changes in control unit behavior can Changes in control behavior can be implemented
be implemented only by redesigning easily by modifying the microinstruction in the
the entire unit. control store.

.12. Define parallelism in microinstruction.

Ans: The ability to represent maximum number of micro operations in a single
microinstruction is called parallelism in microinstruction.

13. What are the types of microinstructions available?

Ans: 1) Horizontal microinstruction
2) Vertical microinstruction
14. Differentiate horizontal microinstruction from vertical microinstruction.
Horizontal Vertical

Long Formats Short Formats

Ability to express a high degree of Limited ability to express parallel micro

parallelism operation

Little encoding of control information Considerable encoding of control information

19. What is Instruction or control hazard?

Ans: The pipeline may be stalled because of a delay in the availability of an instruction.
For example, this may be a result of a miss in the cache, requiring the instruction to be
fetched from the main memory. Such hazards are often called control hazards or
instruction hazard.
20. Define structural hazards.
Ans: This is the situation when two instruction require the use of a given hardware resource at
28
the same time. The most common case in which this hazard may arise is in access to memory.

21. What is side effect?

Ans: When a location other than one explicitly named in an instruction as a destination
operand is affected, the instruction is said to have a side effect.

22. What do you mean by branch penalty?

Ans: The time lost as a result of a branch instruction is often referred to as branch penalty.

23. What is branch folding?

Ans: When the instruction fetch unit executes the branch instruction concurrently with
the execution of the other instruction, then this technique is called branch folding.

24. What do you mean by delayed branching?

Ans: Delayed branching is used to minimize the penalty incurred as a result of

conditional branch instruction. The location following the branch instruction is called
delay slot. The instructions in the delay slots are always fetched and they are arranged
such that they are fully executed whether or not branch is taken. That is branching takes
place one instruction later than where the branch instruction appears in the instruction
sequence in the memory hence the name delayed branching.

25. What are the two types of branch prediction techniques available?

Ans: The two types of branch prediction techniques are

1) Static branch prediction
2) Dynamic branch prediction
Unit III
Part B

29
 1. Explain the single bus organization with neat diagram.
2. Compare single bus and multiple bus organization.
3. Write the control sequence for the following instruction and explain.
Add(R3),R1
4. Write the control sequence for branching instructions.
5. Write the control sequence for the following instruction using multiple bus
organization and explain.
Sub R1,R2,R3
6. Describe the organization of hardwired control with neat diagrams.
7. Describe the organization of micro programmed control with neat diagram.
8. Design a 4-stage instruction pipeline and show how its performance
is improved over sequential execution.

9. Explain the various types of hazards with suitable examples.

10. Discuss the various techniques to overcome data hazard.
11. Explain the various branch prediction techniques.
12. Explain the super scalar operation with example.

UNIT IV
Part A

1. Define Memory Access Time?

Ans: It is the time taken by the memory to supply the contents of a location, from the
time, it receives “READ”.

30
2. Define memory cycle time.
Ans: It is defined as the minimum time delay required between the initiations of two
successive memory operations.

3. What is RAM?
This storage location can be accessed in any order and access time is independent of
the location being accessed

4. What is cache memory?

Ans: It is a fast memory that is inserted between the larger slower main memory and
the processor. It holds the currently active segments of a program and their data.

5. Explain virtual memory.

Ans: The data is to be stored in physical memory locations that have addresses different
from those specified by the program. The memory control circuitry translates the
address specified by the program into an address that can be used to access the physical
memory.

6. List the various semiconductors RAMs?

i] Static RAM.
ii] Dynamic RAM
7. What do you mean by static memories?
Ans: Memories that consist of circuits capable of retaining their state as long as
power is applied are known as static memories.

8. Define DRAM’s.
Ans: static Rams are fast but their cost is high so we use dynamic RAMs which do
Not retain their state indefinitely but here the information are stored in the form of
charge on a capacitor

31
9. Define DDR SDRAM.
The double data rate SDRAMs are the faster version of SDRAM. It transfers data on
Both edges of the clock.

10. What is ROM?

ROM is by definition Non Volatile Preprogrammed with information permanently
encoded in the chip.

11. What is the mapping procedures adopted in the organization of a Cache

Memory?
i) Associative mapping.
ii) Direct mapping.
iii)Set-associative mapping

12. Give the format for main memory address using direct mapping f unction for
4096 blocks in main memory and 128 blocks in cache with 16 blocks per
cache.
Tag Block Word
5 7 4
13. Give the format for main memory address using associative mapping
Function for 4096 blocks in main memory and 128 blocks in cache with 16
blocks per cache.
Tag Word
12 4

14. Give the format for main memory address using set associative mapping
function for 4096 blocks in main memory and 128 blocks in cache with 16
blocks per cache
Tag Block Word

32
 6 6 4

15. Define Hit and Miss?

The performance of cache memory is frequently measured in terms of a
quantity called hit ratio. When the CPU refers to memory and finds the word in
cache, it is said to produce a hit. If the word is not found in cache, then it is in main
memory and it counts as a miss.

16. Write the formula for the average access time experienced by the processor in
a system with two levels of caches.
Ans: The formula for the average access time experienced by the processor in a
System with two levels of caches is
t ave= h1C1+(1-h1)h2C2+(1-h1)(1-h2)M
h1= hit rate in the L1 cache.
h2= hit rate in the L2 cache.
C1=time to access information in the L1 cache.
C2= time to access information in the L1 cache.
M= time to access information in the main memory.

17. What are the enhancements used in the memory management?

Ans: 1) Write Buffer
2) Pre fetching
3) Look- up Cache.

18. What do you mean by memory management unit?

Ans: The memory management unit is a hardware unit which translates virtual
addresses into physical addresses in the virtual memory techniques.

33
19. Explain main (primary) memory.
Ans: This memory stores programs and data that are active in use. Storage
locations in main memory are addressed directly by the CPU’s load and store
instructions.

20. What do you mean by seek time?

Ans: It is the time required to move the read/write head in the proper track.

21. What is disk controller?

Ans: It provides an interface between the disk drive and the bus that connects it to
the rest of the computer system.

22. What is RAID?

Ans: High performance devices tend to be expensive. So we can achieve very high
performance at a reasonable cost by using a number of low-cost devices oerating
in parallel. This is called RAID( Redundant array of Inexpensive Disks).

23. Define data stripping?

Ans: A single large file is stored in several separate disk units by breaking the file up into a
number of smaller pieces and storing these pieces on different disks. This is called data
stripping.

24. How the data is organized in the disk?

Ans: Each surface is divided into concentric tracks and each track is divided into sectors.
The set of corresponding tracks on all surfaces of a stack of disks forms a logical
cylinder.The data are accessed by using read/write head.

25. Define latency time.

Ans: This is the amount of time that elapses after the head is positioned over the correct

34
track until the starting position of the addressed sector passes under the read/write head.

Part B

1. Explain the internal organization of memory chips.

2. Discuss the internal organization of 2M X 8 dynamic memory chip.
3. Write short notes on Read only memories.
4. Explain the memory hierarchy.
5. Explain the various mapping techniques used in cache memory.
6. How does virtual memory gets translated into physical memory? Explain.
7. Explain the role of translation look aside buffer (TLB) in virtual address translation.
8. Explain the Various performance consideration used in memory.
9. Write short notes on secondary storage devices.

Unit V
Part A
35
1. Compare memory mapped I/O and I/O Mapped I/O

Memory mapped I/O- I/O devices and memory share the same address space
I/O mapped I/O- I/O devices and memory have different address space.
2. What is meant by interrupt

An interrupt is a signal from a device attached to a computer or from a program within

the computer that requires the operating system to stop and figure out what to do next
3. What is interrupt service routine?

A routine executed in response to an interrupt request is called interrupt service routine.

4. Define interrupt latency.

Delay between the time an interrupt request is received and start of execution of
interrupt service routine
5. What is vectored interrupts?

To reduce time involved in polling process a device requesting an interrupt may

identify itself directly to processor. The processor immediately start executing the
interrupt service routine.
6. What is the advantage and disadvantage of polling scheme?

Advantage: Easy to implement

Disadvantage: time spent interrogating the IRQ bits of all devices that may not
requesting any service.
7. Compare interrupt and exception

An interrupt is an event that causes the execution of one program to be suspended and
execution of another program to begin.
Exception is used to refer any event that causes interruption.

36
8. What is the function of DMA controller?

To allow transfer of large block of data directly between an external device and main
memory without continuous intervention by processor.
9. What is meant by cycle stealing?

Processor originates most memory cycles, DMA controller said to steal memory cycles
from processor.
10. List out the two types bus arbitration.

 Centralized bus arbitration

 Distributed bus arbitration

11. What is the function of bus?

The bus is used to provide communication path for the transfer of data.
12. List out the different types of bus lines

Address line
Data line
Control line
13. What is meant by port?

Data path associated with its associated controls to transfer data between the interface
and I/O device.
14. Compare serial port and parallel port.

Parallel port transmits data in the form of number of bits, typically 8 or 16

simultaneously to or from the device
Serial port transmits and receives data one bit at a time.

15. What is SCSI Bus?

37
 SCSI bus is a high speed parallel bus intended for devices such as disk and video
displays.

16. What is USB bus?

USB bus uses serial transmission to suit the needs of equipment ranging from
keyboards to game controls to internet connection.

17. What are the objectives of USB bus?

 Provide simple, low cost and easy to use interconnection system that overcomes
the difficulties due to limited no of I/O ports available on computer.

 Enhance user convenience

 Accommodate wide range of characteristics for I/O devices.

Part B

1. How to access I/O devices? Explain in detail.

2. Write short notes on interrupts.
3. Explain direct memory access with neat block diagram.
4. Explain the various techniques used for bus arbitration.
5. Compare synchronous bus and asynchronous bus.
6. Explain keyboard to processor connection and processor to printer connection.
7. Explain the operation of USB bus.
8. Explain the operation of SCSI bus
9. Explain the operation of PCI bus

38
39
 GATE QUESTIONS AND SOLUTIONS

1. In a k-way set associative cache, the cache is divided into v sets, each of which consists of
k lines. The lines of a set are placed in sequence one after another. The lines in set s are
sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards.
The main memory block numbered j must be mapped to any one of the cache lines from.
a. (j mod v) * k to (j mod v) * k + (k-1)
b. (j mod v) to (j mod v) + (k-1)
c. (j mod k) to (j mod k) + (v-1)
d. (j mod k) * v to (j mod k) * v + (v-1)

2. Consider the following sequence of micro-operations.

MBR ← PC
MAR ← X
PC ← Y
Memory ← MBR
Which one of the following is a possible operation performed by this sequence?
a. Instruction fetch
b. Operand fetch
c. Conditional branch
d. Initiation of interrupt service

3. Consider an instruction pipeline with five stages without any branch prediction: Fetch
Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI)
and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10
ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and
the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, …, I12
is executed in this pipelined processor. Instruction I4 is the only branch instruction and its

40
 branch target is I9. If the branch is taken during the execution of this program, the time (in
ns) needed to complete the program is
a. 132
b. 165
c. 176
d. 328

4. A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4
decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is
a. 4
b. 5
c. 6
d. 7

5. The following code segment is executed on a processor which allows only register
operands in its instructions. Each instruction can have atmost two source operands and one
destination operand. Assume that all variables are dead after this code segment.
c = a + b;
d = c * a;
e = c + a;
x = c * c;
if (x > a) {
y = a * a;
}
else {
d = d * d;
e = e * e;
}
Suppose the instruction set architecture of the processor has only two registers. The only
allowed compiler optimization is code motion, which moves statements from one place to
41
 another while preserving correctness. What is the minimum number of spills to memory in
the compiled code?
a. 0
b. 1
c. 2
d. 3

6. Consider the same data as above question. What is the minimum number of registers
needed in the instruction set architecture of the processor to compile this code segment
without any spill to memory? Do not apply any optimization other than optimizing register
allocation.
a. 3
b. 4
c. 5
d. 6

7. The amount of ROM needed to implement a 4 bit multiplier is

a. 64 bits
b. 128 bits
c. 1 Kbits
d. 2 Kbits

42
8. Register renaming is done in pipelined processors
a. as an alternative to register allocation at compile time
b. for efficient access to function parameters and local variables
c. to handle certain kinds of hazards
d. as part of address translation

9. A computer has a 256 KByte, 4-way set associative, write back data cache with block size
of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag
directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1
replacement bit. The number of bits in the tag field of an address is
a. 11
b. 14
c. 16
d. 27

10. Consider the data given in previous question. The size of the cache tag directory is
a. 160 Kbits
b. 136 bits
c. 40 Kbits
d. 32 bits

43
11. Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which
during execution reads a 32-bit word from memory and stores it in a 32-bit register R1.
The effective address of the memory location is obtained by the addition of a constant 20
and the contents of register R2. Which of the following best reflects the addressing mode
implemented by this instruction for operand in memory?
a. Immediate Addressing
b. Register Addressing
c. Register Indirect Scaled Addressing
d. Base Indexed Addressing

12. On a non-pipelined sequential processor, a program segment, which is a part of the

interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.

Initialize the address register

Initialize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address register
Increment the address register
Decrement the count
If count != 0 go to LOOP

Assume that each statement in this program is equivalent to machine instruction which
takes one clock cycle to execute if it is a non-load/store instruction. The load-store
instructions take two clock cycles to execute. The designer of the system also has an
alternate approach of using DMA controller to implement the same transfer. The DMA
controller requires 20 clock cycles for initialization and other overheads. Each DMA
transfer cycle takes two clock cycles to transfer one byte of data from the device to the
memory. What is the approximate speedup when the DMA controller based design is used
in place of the interrupt driven program based input-output?
a. 3.4
b. 4.4
c. 5.1
d. 6.7

44
13. Consider evaluating the following expression tree on a machine with load-store
architecture in which memory can be accessed only through load and store instructions.
The variables a, b, c, d and e initially stored in memory. The binary operators used in this
expression tree can be evaluate by the machine only when the operands are in registers.
The instructions produce results only in a register. If no intermediate results can be stored
in memory, what is the minimum number of registers needed to evaluate this expression?

a. 2
b. 9
c. 5
d. 3

14. Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with
combinational circuit only. The pipeline registers are required between each stage and at
the end of the last stage. Delays for the stages and for the pipeline registers are as given in

45
 the figure:

What is the approximate speed up of the pipeline in steady state under ideal conditions
when compared to the corresponding non-pipeline implementation?
a. 4.0
b. 2.5
c. 1.1
d. 3.0

15. An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-
bytes. The processor generates 32-bit addresses. The cache controller maintains the tag
information for each cache block comprising of the following. 1 Valid bit 1 Modified bit
As many bits as the minimum needed to identify the memory block mapped in the cache.
What is the total size of memory needed at the cache controller to store meta-data (tags) for
the cache?
a. 4864 bits
b. 6144 bits
c. 6656 bits
d. 5376 bits

46
16. A main memory unit with a capacity of 4 megabytes is built using 1M x 1-bit DRAM
chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for
a single refresh operation is 100 nanoseconds. The time required to perform one refresh
operation on all the cells in the memory unit is
a. 100*210 nanoseconds
b. 100*220 nanoseconds
c. 3200*220 nanoseconds

17. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand
Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and
WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for
ADD and SUB instructions, 3 clock cycles for MUL instruction and 6 clock cycles for DIV
instruction respectively. Operand forwarding is used in the pipeline. What is the number of
clock cycles needed to execute the following sequence of instructions?
Instruction Meaning of instruction
I0 :MUL R2 ,R0 ,R1 R2 ¬ R0 *R1
I1 :DIV R5 ,R3 ,R4 R5 ¬ R3/R4
I2 :ADD R2 ,R5 ,R2 R2 ¬ R5+R2
I3 :SUB R5 ,R2 ,R6 R5 ¬ R2-R6
a. 13
b. 15
c. 17
d. 19

18. The program below uses six temporary variables a, b, c, d, e, f.

a=1
b = 10
c = 20
d=a+b
e=c+d
47
 f=c+e
b=c+e
e=b+f
d=5+e
return d + f
Assuming that all operations take their operands from registers, what is the minimum
number of registers needed to execute this program without spilling?
a. 2
b. 3
c. 4
d. 6

19. A computer system has an L1 cache, an L2 cache, and a main memory unit connected as
shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16
words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds
for L1 cache, L2 cache and main memory unit

respectively. When there is a miss

in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What
is the time taken for this transfer?
a. 2 nanoseconds
b. 20 nanoseconds
c. 22 nanoseconds
d. 88 nanoseconds

48
20. How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
a. 8
b. 32
c. 64
d. 128

21. Consider a 4 stage pipeline processor. The number of cycles needed by the
four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below:
S1 S2 S3 S4

I1 2 1 1 1

I2 1 3 2 2

I3 1 1 1 3

I4 1 2 2 2

What is the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3;
I4}
a. 16
b. 23
c. 28
d. 30

49
22. Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The
main memory consists of 256 blocks and the request for memory blocks is in the following
order: 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92 & 155. Which one of the
following memory block will NOT be in cache if LRU replacement policy is used?
a. 3
b. 8
c. 129
d. 216

23. Which of the following is/are true of the auto-increment addressing mode?
I. It is useful in creating self-relocating code.
II. If it is included in an instruction set architecture, then an additional ALU is required for
effective address calculation.
III. The amount of increment depends on the size of the data item accessed.
Choose the correct option.
a. I only
b. II only
c. III only
d. II and III only

24. Which of the following must be true for the RFE (Return from Exception) instruction on a
general purpose processor?
I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction
Choose the correct option.
a. I only
b. II only
c. I and II only
d. I, II and III
50
25. For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy,
which of the following are necessary?
I. L1 must be a write-through cache
II. L2 must be a write-through cache
III. The associativity of L2 must be greater than that of L1
IV. The L2 cache must be at least as large as the L1 cache
Choose the correct option.
a. IV only
b. I and IV only
c. I, III and IV only
d. I, II, III and IV

26. Which of the following are NOT true in a pipelined processor?

I. Bypassing can handle all RAW hazards.
II. Register renaming can eliminate all register carried WAR hazards
III. Control hazard penalties can be eliminated by dynamic branch prediction
Choose the correct option.
a. I and II only
b. I and III only
c. II and III only
d. I, II and III

27. The use of multiple register windows with overlap causes a reduction in the number of
memory accesses for
I. Function locals and parameters
II. Register saves and restores
III. Instruction fetches
Choose the correct option.
a. I only
b. II only
c. III only
d. I, II and III

28. In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside
Buffer) can be accessed is
a. before effective address calculation has started
b. during effective address calculation
51
 c. after effective address calculation has completed
d. after data cache lookup has completed

29. Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block
size 16 bytes. The cache is managed using 32 bit virtual addresses and the page size is 4
Kbytes. A program to be run on this machine begins as follows:
double ARR[1024][1024];
int i, j;
// Initialize array ARR to 0.0
for(i = 0; i < 1024; i++)
for(j = 0; j < 1024; j++)
ARR[i][j] = 0.0;
The size of double is 8 Bytes. Array ARR is located in memory starting at the beginning of
virtual page 0xFF000 and stored in row major order. The cache is initially empty and no
pre-fetching is done. The only data memory references made by the program are those to
array ARR. The total size of the tags in the cache directory is
a. 32 Kbits
b. 34 Kbits
c. 64 Kbits
d. 68 Kbits

30. The cache hit ratio for this initialization loop is

a. 0%
b. 25%
c. 50%
d. 75%

52
31. Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words.
The CPU generates a 20-bit address of a word in main memory. The number of bits in the
TAG, LINE and WORD fields are respectively:
a. 9,6,5
b. 7,7,6
c. 7,5,8
d. 9,5,6

32. Consider a pipelined processor with the following four stages:

IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The
number of clock cycles for the EX stage depends on the instruction. The ADD and SUB
instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX
stage. Operand forwarding is used in the pipelined processor. What is the number of clock
cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2 <- R0 + R1
MUL R4, R3, R2 R4 <- R3 * R2
SUB R6, R5, R4 R6 <- R5 - R4
a. 7
b. 8
c. 10
d. 14

53
33. Consider the following program segment. Here R1, R2 and R3 are the general purpose
registers.

Assume that the content of memory location 3000 is 10 and the content of the register R3
is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The
program is loaded from the memory location 1000. All the numbers are in decimal.
Assume that the memory is word addressable. The number of memory references for
accessing the data in executing the program completely is:
a. 10
b. 11
c. 20
d. 21

34. Consider the data given in above question. Assume that the memory is word addressable.
After the execution of this program, the content of memory location 2010 is:
a. 100
b. 101
c. 102
d. 110

54
35. Consider the data given in above questions. Assume that the memory is byte addressable
and the word size is 32 bits. If an interrupt occurs during the execution of the instruction
“INC R3”, what return address will be pushed on to the stack?
a. 1005
b. 1020
c. 1024
d. 1040

36. Consider a machine with a byte addressable main memory of 2 16 bytes. Assume that a
direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. A
50 × 50 two-dimensional array of bytes is stored in the main memory starting from
memory location 1100H. Assume that the data cache is initially empty. The complete array
is accessed twice. Assume that the contents of the data cache do not change in between the
two accesses. How many data cache misses will occur in total?
a. 40
b. 50
c. 56
d. 59

37. Consider the data given in above question. Which of the following lines of the data cache
will be replaced by new blocks in accessing the array for the second time?
a. Line 4 to line 11
b. Line 4 to line 12
c. Line 0 to line 7
55
 d. Line 0 to line 8

38. A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of
the following is a legal program counter (all values in decimal)?
a. 400
b. 500
c. 600
d. 700

39. Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume
that there is no cycle-time overhead of pipelining. When an application is executing on this
6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of
the instructions incur 2 pipeline stall cycles is
a. 4
b. 8
c. 6
d. 7

40. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block
size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB.
The number of bits for the TAG field is
a. 5
b. 15
c. 20
d. 25

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41. In designing a computer’s cache system, the cache block (or cache line) size is an
important parameter. Which one of the following statements is correct in this context?
a. A smaller block size implies better spatial locality
b. A smaller block size implies a smaller cache tag and hence lower cache tag overhead
c. A smaller block size implies a larger cache tag and hence lower cache hit time
d. A smaller block size incurs a lower cache miss penalty

42. If the associativity of a processor cache is doubled while keeping the capacity and block
size unchanged, which one of the following is guaranteed to be NOT affected?
a. Width of tag comparator
b. Width of set index decoder
c. Width of way selection multiplexor
d. Width of processor to main memory data bus

43. Consider a main memory system that consists of 8 memory modules attached to the system
bus, which is one word wide. When a write request is made, the bus is occupied for 100
nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for
500 ns thereafter, the addressed memory module executes one cycle accepting and storing
the data. The (internal) operation of different memory modules may overlap in time, but
only one request can be on the bus at any time. The maximum number of stores (of one
word each) that can be initiated in 1 millisecond is
a. 1000
b. 10000
c. 100000
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 d. 100

44. Consider the following processors (ns stands for nanoseconds). Assume that the pipeline
registers have zero latency.
P1: Four-stage pipeline with stage
latencies 1 ns, 2 ns, 2 ns, 1 ns.
P2: Four-stage pipeline with stage
latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
P3: Five-stage pipeline with stage
latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
P4: Five-stage pipeline with stage
latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.
Which processor has the highest peak clock frequency?
a. P1
b. P2
c. P3
d. P4

45. An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode
and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and
register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns,
respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have
decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns.
Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new
design has a total of eight pipeline stages. A program has 20% branch instructions which
execute in the EX stage and produce the next instruction pointer at the end of the EX stage
in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after
fetching a branch instruction until the next instruction pointer is computed. All instructions
other than the branch instruction have an average CPI of one in both the designs. The

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 execution times of this program on the old and the new design are P and Q nanoseconds,
respectively. The value of P/Q is?
a. 1.5
b. 1.4
c. 1.8
d. 2.5

46. A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank
being c bytes wide. Consecutive c − byte chunks are mapped on consecutive banks with
wrap-around. All the k banks can be accessed in parallel, but two accesses to the same
bank must be serialized. A cache block access may involve multiple iterations of parallel
bank accesses depending on the amount of data obtained by accessing all the k banks in
parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and
this takes. k/2 ns The latency of one bank access is 80 ns. If c = 2 and k = 24, the latency of
retrieving a cache block starting at address zero from main memory is:
a. 92 ns
b. 104 ns
c. 172 ns
d. 184 ns

47. A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in
the first stage of the pipeline. A conditional branch instruction computes the target address
and evaluates the condition in the third stage of the pipeline. The processor stops fetching
new instructions following a conditional branch until the branch outcome is known. A
program executes 109 instructions out of which 20% are conditional branches. If each
instruction takes one cycle to complete on average, the total execution time of the program
is?
a. 1.0 second
b. 1.2 seconds
c. 1.4 seconds
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 d. 1.6 seconds

48. Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-
byte block size. The second one is of the same size but direct mapped. The size of an
address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit
comparator has a latency of k/10 ns. The hit latency of the set associative organization is
h1 while that of the direct mapped one is h2. The value of h1 is?
a. 2.4 ns
b. 2.3 ns
c. 1.8 ns
d. 1.7 ns

49. Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-
byte block size. The second one is of the same size but direct mapped. The size of an
address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit
comparator has a latency of k/10 ns. The hit latency of the set associative organization is
h1 while that of the direct mapped one is h2. The value of h2 is?
a. 2.4 ns
b. 2.3 ns
c. 1.8 ns
d. 1.7 ns

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50. A hardwired CPU uses 10 control signals S1 to S10, in various time steps T1 to T5, to
implement 4 instructions I1 to I4 as shown below:

Which of the following pairs of expressions represent the circuit for generating control
signals S5 and S10 respectively? ((Ij+Ik)Tn indicates that the control signal should be
generated in time step Tn if the instruction being executed is Ij or lk)
a. S5=T1+I2⋅T3 and S10=(I1+I3)⋅T4+(I2+I4)⋅T5
b. S5=T1+(I2+I4)⋅T3 and S10=(I1+I3)⋅T4+(I2+I4)⋅T5
c. S5=T1+(I2+I4)⋅T3 and S10=(I2+I3+I4)⋅T2+(I1+I3)⋅T4+(I2+I4)⋅T5
d. S5=T1+(I2+I4)⋅T3 and S10=(I2+I3)⋅T2+I4⋅T3+(I1+I3)⋅T4+(I2+I4)⋅T5

Reference link: http://www.geeksforgeeks.org/computer-organization-and-architecture-gq/

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