Power Factor Correction for a

Bidirectional On-Board Charger for

Electric Vehicles and Plug-in Hybrid
Electric Vehicles
A fundamental study of the bidirectional
totem-pole PFC

Sondre Westby Johannessen

Master of Energy and Environmental Engineering

Submission date: June 2018
Supervisor: Roy Nilsen, IEL
Co-supervisor: Tore Undeland, IEL
Torbjørn Sørsdahl, Valeo Siemens eAutomotive

Norwegian University of Science and Technology

Department of Electric Power Engineering
Abstract

With the beginning implementation of a ”smart grid” in industrialized countries in-

creasing the load flexibility of customers, as well as communication with the grid
operators, a potential market for bidirectional on-board chargers (OBC) is emerg-
ing. The OBC is the electric vehicle charger located within the vehicle, operating
as a link between the DC-voltage battery and the AC grid voltage in electricity
sockets anywhere, thus working at a universal voltage range (85Vrms-265Vrms)
with rated power in the range of 1.9kW to 3.5kW. To maximize the real power
drawn by these OBCs, they are designed with power factor correction (PFC) con-
verters at the AC grid interface, shaping the drawn AC current sinusoidally and
in phase with the AC voltage, to maximize the power factor. Thus, a bidirec-
tional OBC would necessarily require a bidirectional PFC. In this master’s thesis,
a simulation model is developed for a bidirectional totem-pole PFC, attempting
to verify the use of this topology as the mentioned bidirectional OBC PFC. The
work is focused on describing the basic bidirectional operation of the bidirectional
totem-pole PFC, deriving expressions for currents, voltages and losses, as well as
for the gate logic and control system. Average current mode control is used, with
cascaded current and voltage control including PI controllers and Symmetrical op-
timum tuning. To verify the simulation model for the power levels and demands
of an OBC, the main components are dimensioned to achieve 98% efficiency at
230Vrms, 3.5kW and 90kHz switching frequency, implementing GaN eHEMTs in
the fast-switching leg of the totem-pole. At last, simulations are performed, show-
ing that the PFC is able to achieve a power factor of 0.998 and a THD of 5% in
both G2V and V2G, without a DM filter on the AC side.
Sammendrag

Etter hvert som implementeringen av ”smarte nett” er i ferd med å skyte fart i in-
dustrialiserte land, med økt lastfleksibilitet på kundesiden og økt kommunikasjon
mot nettoperatørene, begynner det å åpne seg et marked for bidireksjonelle såkalte
”on-board chargers” (OBC-er). En OBC er elbilladeren som er plasserte inne i
elbilen og fungerer som en link mellom elbilbatteriet - som krever DC-spenning -
og AC-spenningen i strømuttaket, hvilket betyr at den må designes for å operere
ved universell AC-spenning (85Vrms-265Vrms) og nominelle effektnivåer mellom
1.9kW og 3.5kW. For å maksimere den reelle effekten trukket av OBC-en, er de
designet med såkalte ”power factor corretion”-omformere (PFC-er) på AC-siden
ut mot nettet. Denne kontrollerer AC-strømmen som trekkes til å være formet som
en sinus og i fase med AC-spenningen på nettet, for på den måten å maksimere
effektfaktoren. Av den grunn, vil nødvendigvis en bidireksjonell OBC behøve en
bidireksjonell PFC. I denne masteravhandlingen vil det bli utviklet en såkalt bidi-
reksjonell ”totem-pole PFC”, mens det forsøkes å verifisere hvorvidt dennetopolo-
gien egner seg for bruk i en bidireksjonell PFC for en OBC. Hovedfokus for opp-
gaven vil ligge i å beskrive hvordan en bidireksjonell totem-pole PFC fungerer
grunnleggende, mens det vil utledes uttrykk for strømmer, spenninger og tap i om-
formeren, samt gate-logikken og kontrollsystemet. ”Average current mode” brukes
i kontrollsystemet, med dobbel kontrollsløyfe med strøm- og spenningskontroll,
begge to med PI-regulatorer dimensjonert med Symmetrisk optimum. For å ver-
ifisere simuleringsmodellen for de aktuelle spennings- og effektnivåene, dimen-
sjoneres de viktigste komponentene til å opnå 98% virkningsgrad ved 230Vrms,
3,5kW og 90kHz switchefrekvens, med GaN eHEMT-er implementert i det hurtig-
switchende totem-pole-benet. Til slutt ble det utført simuleringer av modellen, og
disse viser at den bidireksjonelle totem-pole PFC-en oppnår en effektfaktor på
0.998 og en THD på 5% både under G2V og V2G, uten filter på AC-siden.
Preface

This master’s thesis is conducted during the spring 2018, and it is the finishing
work of a master’s degree in Energy and Environmental Engineering at the Nor-
wegian University of Science and Technology (NTNU), Department of Electric
Power Engineering. The thesis focuses on power electronics, and it is a continua-
tion of a specialization project performed during the autumn 2017, both of which
have been announced and guided by Valeo Siemens eAutomotive.

I would like to thank my supervisor, Roy Nilsen, for his valuable guidance and sup-
port through numerous guidance sessions throughout the year, and co-supervisor,
Tore M. Undeland, for his expert advice. My sincere gratitude goes to Torbjørn
Sørsdahl at Valeo Siemens for his effort, advice and guidance throughout the year.
Thanks also to the rest of the staff at Valeo Siemens in Drammen who were ready
to answer any of my questions without hesitation, during my stays there through
the year.

Finally, I would like to place a warm thanks to my family for their loving support,
and to my favourite Ingunn for letting me know when it is time to go home for the
night.
Table of Contents

Abstract i

Sammendrag ii

Preface iii

Table of Contents viii

List of Tables ix

List of Figures xiii

Acronyms xiv

1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 The Bidirectional On-Board Charger . . . . . . . . . . . . . . . . 4
1.3 The bidirectional PFC . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Scope of work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Basic operation of the bidirectional totem-pole PFC 13

2.1 G2V operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 V2G operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 Current waveforms and ripple . . . . . . . . . . . . . . . 18

v
 2.3.2 Conduction losses . . . . . . . . . . . . . . . . . . . . . 20
2.4 Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.1 Current waveforms and ripple . . . . . . . . . . . . . . . 22
2.4.2 Conduction losses . . . . . . . . . . . . . . . . . . . . . 25
2.4.3 Switching losses . . . . . . . . . . . . . . . . . . . . . . 27
2.5 DC-link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5.1 Current waveforms and ripple . . . . . . . . . . . . . . . 30
2.5.2 Conduction losses . . . . . . . . . . . . . . . . . . . . . 32

3 Components dimensioning 35
3.1 DC-link capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.1 DC-link rated voltage . . . . . . . . . . . . . . . . . . . . 36
3.1.2 DC-link rated current . . . . . . . . . . . . . . . . . . . . 38
3.1.3 DC-link capacitance value . . . . . . . . . . . . . . . . . 38
3.1.4 Capacitor choice . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.1 Choice of transistor technology . . . . . . . . . . . . . . 41
3.2.2 Guesstimating component loss distribution . . . . . . . . 43
3.2.3 Totem-leg transistors . . . . . . . . . . . . . . . . . . . . 45
3.2.4 Switching frequency . . . . . . . . . . . . . . . . . . . . 47
3.2.5 Comparison to state-of-the-art MOSFETs . . . . . . . . . 48
3.2.6 Rectifier-leg transistors . . . . . . . . . . . . . . . . . . . 49
3.3 Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.1 Boost inductance value . . . . . . . . . . . . . . . . . . . 51
3.3.2 RMS current rating . . . . . . . . . . . . . . . . . . . . . 52
3.3.3 Saturation current rating . . . . . . . . . . . . . . . . . . 52
3.3.4 Choice of inductor . . . . . . . . . . . . . . . . . . . . . 53

4 Drive and control 55

4.1 Gate drive logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.1.1 Rectifier leg . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.1.2 Totem leg . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.1.3 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 Control system . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.1 Control logic . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.2 Current control loop . . . . . . . . . . . . . . . . . . . . 70
 4.2.3 Voltage control loop . . . . . . . . . . . . . . . . . . . . 78

5 System-level simulations 85

6 Feasibility of the bidirectional totem-pole PFC 89

6.1 Model shortcomings . . . . . . . . . . . . . . . . . . . . . . . . 89
6.2 Loss comparison to a regular boost PFC . . . . . . . . . . . . . . 91
6.2.1 Comparison at worst-case operating temperature . . . . . 93
6.2.2 Comparison at normal operating conditions . . . . . . . . 94
6.2.3 Comparison at 120Vrms . . . . . . . . . . . . . . . . . . 95

7 Conclusion and Further Work 97

7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.2 Further Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Bibliography 101

Appendices 109

A Valeo Siemens bidirectional OBC specifications 111

B Literature review on power factor correction converters 121

B.1 Power factor correction AC-DC converter . . . . . . . . . . . . . 121
B.1.1 Conventional PFC . . . . . . . . . . . . . . . . . . . . . 122
B.1.2 Bidirectional PFC . . . . . . . . . . . . . . . . . . . . . 124

C Paper on GaN HEMTs and bidirectional PFCs 129

D 137
D.1 Modulus Optimum in current loop . . . . . . . . . . . . . . . . . 137
D.1.1 PI controller parameters . . . . . . . . . . . . . . . . . . 137
D.1.2 Current measurement filter design with Modulus optimum 138
D.1.3 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . 139

E Implemented Simulink model 141

F MATLAB code 145

F.1 Controller tuning script . . . . . . . . . . . . . . . . . . . . . . . 145
 F.2 Filter graphical solver . . . . . . . . . . . . . . . . . . . . . . . . 149

G System-level simulations 153

List of Tables

1.1 Demands and specifications for the bidirectional universal OBC,

from [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 PFC-specific demands and specifications . . . . . . . . . . . . . . 12

3.1 Key parameters for the relevant electrolytic capacitor used by Va-
leo Siemens today. [1] . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Guesstimated design rule losses distribution in the bidirectional
totem-pole PFC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3 Some key parameters and rated values of the GaN Systems eHEMTs
at Tcase = 25◦ C. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 Calculated conduction losses of the eHEMT models. . . . . . . . 47
3.5 Estimated switching energy, losses and frequency of GS66516. . . 47
3.6 Some key parameters and rated values of MOSFET IPW60R045CPA
at Tcase = 25◦ C. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7 Estimated inductor parameters based on technology used by Valeo
Siemens today.[1] . . . . . . . . . . . . . . . . . . . . . . . . . . 53

ix
List of Figures

1.1 A sketch of the current Valeo Siemens OBC topology [1] . . . . . 4

1.2 The basic bidirectional PFC topology . . . . . . . . . . . . . . . 8

2.1 The basic bidirectional totem-pole topology . . . . . . . . . . . . 13

2.2 The G2V operation of the bidirectional totem-pole PFC. . . . . . 15
2.3 The V2G operation of the bidirectional totem-pole PFC. . . . . . 17
2.4 CCM iL and vL ripple over one switching period . . . . . . . . . . 18
2.5 Boost CCM ∆iL vs duty cycle . . . . . . . . . . . . . . . . . . . . 19
2.6 The inductor current compared to the AC mains voltage through-
out one mains cycle. . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7 The rectifier-leg transistor drain-source currents throughout one
mains cycle during G2V. . . . . . . . . . . . . . . . . . . . . . . 22
2.8 The current ripple of the totem-leg switches during positive mains
half cycle in G2V operation. . . . . . . . . . . . . . . . . . . . . 23
2.9 The totem-leg transistor drain-source currents throughout one mains
cycle during G2V. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.10 Approximation of the switching characteristics of a MOSFET. . . 28
2.11 Illustration of he DC-link capacitor, voltage and currents . . . . . 30
2.12 The current through the DC-link capacitor over one totem-leg switch-
ing period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.13 The DC-side currents throughout one mains cycle during G2V. . . 31

3.1 DC-link voltage design requirements compared to AC mains voltage. 37

xi
3.2 The bidirectional totem pole topology with GaN eHEMTs in the
totem leg and MOSFETs in the rectifier leg. . . . . . . . . . . . . 44

4.1 A screenshot of the PWM system implemented in Simulink. . . . 57

4.2 Illustration of the pulse width modulation used in this . . . . . . . 59
4.3 Duty cycle and gate drive signals over one mains cycle and zoomed
in on a few switching cycles. . . . . . . . . . . . . . . . . . . . . 62
4.4 Current and Voltage control systems implemented in Simulink . . 64
4.5 The fundamental-frequency equivalent totem-pole PFC . . . . . . 65
4.6 Some selected waveforms over one mains cycle in G2V and V2G
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.7 The inner current control loop . . . . . . . . . . . . . . . . . . . 70
4.8 Graphical solution of (4.27) to find T f i,i . . . . . . . . . . . . . . 75
4.9 Simulation of current controller waveforms during one mains period. 76
4.10 A block diagram of the voltage control loop . . . . . . . . . . . . 78
4.11 Grapical solution to (4.36), with ωc = 2π · 500rad/s. . . . . . . . . 81
4.12 Voltage controller step response to a 10V leap in voltage reference. 82

5.1 System-level simulation results at 230Vrms G2V operation. . . . . 87

5.2 System-level simulation results at 230Vrms V2G operation. . . . . 88

B.1 The topology of a conventional boost PFC converter . . . . . . . . 122

B.2 The current waveforms of a boost PFC, as found in [2]. . . . . . . 123
B.3 Bridgeless PFC topologies . . . . . . . . . . . . . . . . . . . . . 125
B.4 The basic bidirectional PFC topology . . . . . . . . . . . . . . . 125
B.5 MOSFET switching dynamics with extended reverse conduction
time, as found in [3]. . . . . . . . . . . . . . . . . . . . . . . . . 127

D.1 Graphical solution of current filter time constant T f i,i with Modu-
lus optimum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
D.2 Current controller waveforms over one mains period with Modulus
optimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

E.1 The complete totem pole converter implemented in Simulink. . . . 142

E.2 The gate drive and totem-pole bridge. . . . . . . . . . . . . . . . 143
E.3 The the totem-pole bridge implemented in Simulink . . . . . . . . 144
G.1 System-level simulation results at 120Vrms G2V operation. . . . . 154
G.2 System-level simulation results at 120Vrms V2G operation. . . . . 155
Abbreviations

AC: Alternating Current

CCM: Continuous Conduction Mode
CrCM: Critical Conduction Mode
DAB: Dual Active Bridge
DC: Direct Current
DCM: Discontinuous Conduction Mode
DM: Direct Mode
DSO: Distribution System Operator
EMI: Electromagnetic Interference
ESR: Equivalent Series Resistance
EV: Electric Vehicle
G2V: Grid-to-Vehicle
GaN: Gallium Nitride
HEMT: High Electron Mobility Transistor
MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor
OBC: On-Board Charger
PCB: Printed Circuit Board
PHEV: Plug-in Hybrid Electric Vehicle
PLL: Phase-Locked Loop
PWM: Pulse Width Modulation
RMS: Root Mean Square
SHBM: Single H-Bridge Modulation
SiC: Silicon Carbide
THD: Total Harmonic Distortion
V2G: Vehicle-to-Grid
V2H: Vehicle-to-Home
ZCS: Zero-Current Switching
ZVS: Zero-Voltage Switching
Chapter 1
Introduction

This master’s thesis is a continuation of a specialization project work performed

on the same topic.[4] For that reason, some of the work described in this thesis is
based on some of the work performed and described in the specialization project
report. The following figures are retrieved from the specialization project report:

• Figure 1.1

• Figure 2.1

• Figure 2.2

• Figure 2.3

Furthermore, the following sections contain large portions of text reproduction

from the abovementioned specialization project report:

• Section 1.1

• Section 1.2

• Section 2.1

• Section 2.2

1
1.1 Motivation

In the quest of securing a more sustainable and renewable electric energy supply in
industrialized countries, the implementation of a ”smart grid” is picking up pace.
The smart grid concept incentivizes more distributed renewable electricity produc-
tion and increased consumption flexibility for the customer.[5] This development
is exemplified by the extensive roll-out of advanced electricity consumption mea-
surement systems for all households in Norway and numerous countries in the Eu-
ropean Union, as well as an increasing amount of distributed solar power built in
e.g. Germany and California. [6, 7, 8, 9] The first tendency introduces a potential
for substantial increase in communication and control at the consumer side of the
electric power grid. The second introduces a possible problem of over-production
at times of day with high solar irradiation, giving stability issues for the utilities
[10]. Combined, these two imply both a possibility and a need for distributed en-
ergy storage in the grid, connecting battery storage units at the consumer end to
even out the big hourly differences in power production.

One part of this distributed energy storage could be the main batteries of elec-
tric vehicles (EVs) and plug-in hybrid electric vehicles (PHEVs) when these are
connected to the electricity supply at home or at work. The number of EVs and
PHEVs on the roads is increasing, and with that comes a big battery capacity that
could be utilized for purposes other than vehicle propulsion. One example of such
utilization is using EV batteries as electricity grid stabilizers through vehicle-to-
grid (V2G) charging. At any time when a big load or generating unit is connected
to or disconnected from the grid, there is an immediate power imbalance which
causes a change in grid frequency. [11, Chapter 9] To ensure that the frequency
stays within the limits of stability, charging or discharging a fleet of cars connected
to the grid could cover some of this immediate power imbalance before the slower
generators reacts after some seconds or minutes to completely cover the whole
imbalance. A potential issue for EVs and PHEVs when enabling bidirectional
charging is that the number of cycles increases. Since the battery degrades with
every cycle, this would help degrade the battery faster.[12, 13] With this sort of
V2G solution, however, utilizing the EV batteries as grid stabilizers, the charg-
ing and discharging would be high-power for a short period of time, meaning the
battery would not fully charge or discharge. Such solutions are being tested these

2
days, where EV owners are paid for having their batteries available for the utility
to draw or inject power whenever needed.[14, 15, 16] Furthermore, if one is to
fully exploit the grid-conditioning potential of the bidirectional OBC, it could also
be modified to be able to deliver and consume reactive power, serving as a reactive
power compensator. [17]

Another possibility is that the battery owners control the power flow themselves,
e.g. to store energy when the electricity price is low, say, when the car is connected
to a power supply at work. Later in the evening the power could be sold back to
the grid at a higher price, earning money from the price difference. Otherwise
it could be supplied to the household when the electricity price is high, saving
money. Moreover, a discussed concept is vehicle-to-home (V2H) charging, which
allows the car battery to serve as an emergency power source, supplying critical
loads during power outages.[18] Yet another possibility for exploiting the EV bat-
tery energy, is using the battery to provide standard grid-voltage AC power within
the car, supplying applications like PC chargers, refrigerators or TVs. Further-
more, when campers today are in need of AC power for various devices, such as
lighting, microwaves, small cooktops or again refrigerators, they use a DC-AC in-
verter connected to a bank of regular 12V car batteries.[19] If an AC power supply
is made available also in the exterior of the EV, then this could replace the need for
such solutions and even increase the available energy compared to the 12V battery
bank.

3
 Figure 1.1: A sketch of the current Valeo Siemens OBC topology [1]

1.2 The Bidirectional On-Board Charger

A key to utilizing PHEV/EV batteries for non-propulsion purposes could be imple-

menting a bidirectional on-board charger (OBC). Being located within the car, the
OBC is an important part of any EV; it is the interface between the DC-voltage EV
battery and standard AC power outlets, such as the wall socket at home or in the
workplace. Since at the moment, vehicles are standing still during large parts of
the day, mostly at home or at work, bidirectional charging should be enabled while
connected at these locations. To avoid making the owners of house and workplace
invest in DC charging stations, the on-board charger could be made with bidirec-
tional power flow capability to enable V2G charging during this time. Moreover,
providing solutions like in-car or exterior grid-voltage AC power supplies would
require the DC-AC conversion to happen within the car. Enabling bidirectional
conduction capability in OBCs could thus indeed be useful, both for V2G charg-
ing and the in-car or exterior solution.

One challenge of a standardized OBC solution is that it has to be able to operate

efficiently in a universal AC-voltage range (85-265Vrms), since the grid voltage
differs between countries and the charger should be able to operate anywhere.[20]
Consequently, the input power will also vary, with maximum power ranging roughly
between 1.4 kW and 3.5kW, depending on the AC voltage.[21] Another challenge
is that since the OBC is located within the car, it has to be small in size and light
in weight, to minimize the physical footprint of the charger and extend the range
of the vehicle.

The OBC most often comprises two stages.[22] This is exemplified by the sketch

4
of the OBC topology used by Valeo Siemens eAutomotive (hereby referred to as
Valeo Siemens) reproduced in figure 1.1. Firstly, there is an AC-DC grid inter-
face rectifier with power factor correction (PFC), sinusoidally shaping the drawn
AC current in phase with the AC supply mains voltage, to maximize the power
factor and remove low-order harmonics, while controlling the voltage ripple at the
DC-link capacitor. The switching frequency of the PFC has to be kept high, in or-
der to minimize the size of the inductor and the AC-side filter. At the same time, a
higher switching frequency causes higher switching losses, reducing the efficiency.
Also, IEC 61000-4-6 defines limits to the emitted EMI in the frequency range of
150kHz to 30MHz, so setting the switching frequency to exceed this lower limit
would mean that all of the harmonics needs to be filtered, increasing the size of
the filter. Cascaded through the DC-link with this PFC is a DC-DC converter with
a high-frequency transformer for galvanic isolation. The DC-DC is controlling
the battery-side voltage to be constant, for optimal performance. High switching
frequency in the isolated DC-DC converter is decisive to minimize the weight and
size of inductors and the transformer, again decreasing the size and weight of the
whole OBC. However, in this case higher switching frequency does of course also
cause higher switching losses. The efficiency has to be kept high, defined by Va-
leo Siemens to be above 94%, to maximize the charging speed.[1] The combined
maximization of efficiency and power density (kW/dm3 ) is always going to be a
trade-off, as explained in [23] with the Pareto front and exemplified with a boost
PFC, where at a certain optimal limit, the increasing one is going to require a com-
plementary decrease in the other. This is the compromise of an OBC, where the
wish is both high efficiency and high power density. Price is also an important
factor, as an OBC would be mass produced and should not lead to a big increase
in vehicle cost.

Up until this point, the majority of commercial OBC solutions have been made
unidirectional, allowing only grid-to-vehicle (G2V) charging. To make the OBC
capable of bidirectional power flow and V2G, there can be no passive diode bridge
rectifiers or standalone freewheeling diodes. Some diodes can be removed, imple-
menting more compact solutions, while some have to be replaced by transistors,
making the whole charger more complex in terms of control. Every transistor
needs its own drive circuit, meaning more transistors can also potentially require
a bigger charger volume. For that reason minimizing the number of transistors is

5
something that has to be considered when developing a bidirectional OBC.

With the smart grid still in its birth, the nature of bidirectional charging is still
not clear, and different potential modes of operation present different demands for
the charger. If operated with the interior power outlet, using it for small TVs,
refrigerators or laptop chargers, the charger would most likely be working at a low
load for a long period of time. On the other hand, if the vehicle is connected to
the grid, working in V2G operation, it could, as mentioned, either be used to sell
the battery power to the utility for a good price at times of high demand, or the
DSO could use the charger capacity for grid stabilizing purposes. The first case
could give an even, high power transfer for hours at a time, while the latter would
provoke power transfers at maximum rated power for seconds or minutes. The
stress on components and operating efficiency would obviously be quite different
in these different cases, and it would be difficult to optimize the charger design for
all modes of operation. For that reason, it will be assumed in this evaluation that the
charger will during V2G most often be under the control of the distribution system
operator (DSO) to regulate stability. Therefore, the relevant PFC topologies will
be evaluated considering operation at maximum load for short periods of time.
The basis of this decision is that this type of operation has already been tested
and considered. The lower efficiency when supplying interior power supply is
considered to be of less importance because the drawn power will be lower, and
thus the stress and power dissipation will be small.

6
1.3 The bidirectional PFC

Having understood the basic composition of an OBC, it is clear that in order to

make a bidirectional OBC it is necessary with a bidirectional PFC. However, to
design a bidirectional PFC, it is also necessary to understand the basic operation
of a unidirectional PFC. A literature review on unidirectional and bidirectional
PFCs was performed in the specialization project, and is attached in appendix B.
This PFC introduction is based on that analysis. As stated there and above, the
PFC is the grid interface of an OBC or another universal power supply, shaping
the drawn AC current sinusoidally and in phase with the AC voltage, and control-
ling the internal DC-link voltage. The conventional boost PFC is structured as in
the OBC topology in figure 1.1, consisting of a passive rectifier cascaded with a
regular boost converter.[24, ch. 7-4] Here, the switching of the boost transistor is
modulated to shape the fundamental inductor current according to the rectified AC
voltage seen from the rectifier.

The PFC operates either in continuous conduction mode (CCM), critical conduc-
tion mode (CrCM) or discontinuous conduction mode (DCM), all of which are ex-
plained in more detail and visualized in appendix B. CCM and CrCM are the most
commonly used, where CCM has the advantage of lower current ripple, apply-
ing less stress on the semiconductors and inductor and requiring a smaller direct-
mode (DM) ac-side current filter, but at the same time yielding hard switching in
both turn-on and turn-off with corresponding higher switching losses. CrCM, on
the other hand, enables zero-current switching (ZCS) and possible zero-voltage
switching (ZVS) due to the current reaching zero every switching cycle, reducing
switching losses but at the same time generatng a large current ripple of twice the
average current, increasing the stress on the components. For higher power ap-
plications it is common to operate in CCM, because the stress on the components
would otherwise get too high.[2]

An obvious disadvantage of the boost PFC with regard to bidirectional conduc-

tion ability is the the presence of passive diodes both in the rectifier bridge and
the freewheeling diode, and so these need to be removed. A first step in that di-
rection is including the operation of the transistor and freewheeling diode into the
rectifier bridge, making it a so-called bridgeless PFC, of which there are many
variations.[25, 26] This integration has advantages with regards to losses, as the

7
 Figure 1.2: The basic bidirectional PFC topology

number of semiconductors in the conduction path is reduced from 3 to 2, reducing

especially the conduction losses. Two simple and compact bridgeless topologies
with regards to number of semiconductors are the basic bridgeless PFC and the
totem-pole PFC, presented in figure B.3 in the appendix. In these topologies, the
transistors are ”taking turns” operating as boost transistor every other half cycle
and remaining turned off (basic bridgeless) or operating as the freewheeling diode
(totem-pole) in the other. Out of the two, the basic bridgeless PFC has previously
been the preferred topology, with the totem-pole PFC disregarded because of large
reverse recovery losses in the MOSFET body diode during CCM operation.[25]
On the other hand, a drawback of the basic bridgeless PFC is increased common
mode (CM) noise due to the DC-link zero-potential floating with respect to the AC
ground. This is explained in more detail in appendix B.

In recent advances, however, the totem-pole PFC has been found increasingly in-
teresting when substituting the rectifier diodes for slow-switching MOSFETs, en-
abling negative current. That creates a bidirectional PFC topology, the bidirec-
tional totem-pole PFC shown in figure 1.2. For lower-power applications, it has
been found that techniques such as triangular current mode (TCM) and CrCM
valley switching, enabling low- or zero-voltage switching by discharging the tran-
sistor parasiic capacitances through short-term negative currents, can increase ef-
ficiency of the totem-pole PFC. This is explained in more detail in appendix B.[3,
27, 28] Interleaving the fast-switching leg, hereby called the totem-leg, i.e. paral-
leling more than one totem-leg, also improves the efficiency and reduces the stress
on the semiconductor components.[27, 29] This is however for lower power lev-

8
els; at the high power levels of an OBC (3.5kWmax) it is still desirable with CCM
operation, to have component stress at a satisfying level. Moreover, given the size
restriction of an OBC and that the DM filter does in fact make up one third of the
OBC volume, it is beneficial that the lower current ripple in CCM implies a smaller
DM filter size.[1]

Beneficially, the most recent advances in wide-bandgap power semiconductor de-

vices show that the Gallium Nitride (GaN) High-Electron-Mobility Transistor
(HEMT) has been shown to give improvements on the performance of totem-pole
PFCs, when used in the fast-switching totem-leg. A literature study has been per-
formed on GaN HEMTs and their application in bidirectional PFCs, and the results
are presented in the paper attached in appendix C. The most notable advantage for
application in the totem-pole PFC is that, unlike the MOSFET, the GaN HEMT
does not contain a reverse body diode, thus solving the problem of reverse re-
covery losses during CCM operation. Moreover, the GaN HEMTs show superior
conduction and switching characteristics all over, due to the combination of high
breakdown field and the low-resistivity 2DEG layer. This is explained in more de-
tail in appendix C. In [30] is presented a 1.5kW, 65kHz CCM-operated totem-pole
PFC, showcasing an efficiency of 99%. Moreover, it is found through the litera-
ture study that currently most 1-phase bidirectional two-stage OBCs proposed in
the scientific literature are using the bidirectional totem-pole PFC shown in figure
2.1 [31, 32, 33]. In fact, most proposed 1-phase bidirectional PFCs overall are
using the bidirectional totem-pole topology [34, 35]. This indicates that it is possi-
ble to design an efficient 3.5kW CCM-operated bidirectional totem-pole PFC. For
that reason, the bidirectional totem-pole PFC will be the topology of choice going
forward in this master’s thesis.

9
1.4 Scope of work

Although a few cases of the bidirectional totem-pole PFC has appeared in the sci-
entific literature, as presented in the previous section, the author has not come
across any verification of the nature its fundamental bidirectional operation. For
that reason, the main objective of this master’s thesis is to fill that hole, by deriv-
ing and developing a fundamental simulation model describing the bidirectional
totem-pole PFC and its bidirectional operation. This simulation model will be im-
plemented in Simulink. To verify the use of the bidirectional totem-pole PFC in
a bidirectional OBC, the simulation model will be implemented with off-the-shelf
components and a control system meeting some demands of a bidirectional OBC
and PFC, shown in tables 1.1 and 1.2. The thesis is written in cooperation with Va-
leo Siemens eAutomotive and is intended to be a building block for further work
on a bidirectional OBC, verifying or dismissing the bidirectional totem-pole PFC
as a technology to take further. In that sense, describing the currents, voltages and
losses in the basic operation of the topology will be important.

The topology will be investigated using MOSFETs and GaN HEMTs as the transis-
tors, disregarding possible solutions with IGBTs. Furthermore, the PFC efficiency
will be optimized for a standard AC voltage of 230Vrms, not designing from the
efficiency at 120Vrms. The design will be aiming to approach the current Valeo
Siemens PFC designs with regards to switching frequency and efficiency, to use
similar components and compare performance. As for the control system and gate
logic design, an emphasis will be put on making a solution which can be adapted to
existing unidirectional boost PFC control systems and gate drives, to create a flex-
ible solution. For the PFC control average current mode control, whith cascaded
current and voltage loops containing PI controllers with Symmetrical optimum
tuning.

In chapter 2, the basic operation of the bidirectional totem-pole PFC is described,

deriving expressions for the currents and losses in the boost inductor, DC-link
capacitor and transistors.

Chapter 3 will cover the design and dimensioning of the components, in particular
the boost inductor, transistors and DC-link capacitor.

In chapter 4 the bidirectional totem-pole control will be developed, deriving the

10
 Table 1.1: Demands and specifications for the bidirectional universal OBC, from [1]

Parameter Value
G2V
Output DC voltage range 200Vdc - 1000Vdc
Max. output DC current 12 Adc
Input AC voltage range 85Vrms - 275Vrms
Max. input AC current 16Arms
Max. input frequency 45Hz - 65Hz
Max. power 3.5kW
Efficiency > 94%
Max. apparent power 3680VA
Lifetime 10 000 hours
V2G
Input DC voltage range 200Vdc - 1000Vdc
Max. input DC current 12 Adc
Output AC voltage range 100Vrms - 250Vrms
Max. output AC current 16Arms
Max. output frequency 45Hz - 65Hz
Max. power 3.5kW
Efficiency > 91%
Max. apparent power 3680VA
THD < 3%
Lifetime (uncertain) 10 000 hours

gate drive and control system logic and tuning controllers and verifying through
simulations.

Chapter 5 shows the results of some system level simulations.

Chapter 6 will discuss the design feasibility by evaluating simulation model short-
comings and comparing performance with existing solutions.

11
 Table 1.2: PFC-specific demands and specifications

Parameter Value
Efficiency G2V >98%
Efficiency V2G >97%
Min. DC-link voltage 340V
Max. DC-link voltage ripple 20V
Max. inductor current ripple 20%

12
Chapter 2
Basic operation of the bidirectional
totem-pole PFC

Based on the reasoning in the introduction, the bidirectional totem-pole PFC was
chosen as the most promising bidirectional PFC topology, and so now the opera-
tion of this topology must be explained in more detail. It is acknowledged that in
order to comply with the current ripple restrictions of 20% (table 1.2), it is neces-
sary to run the bidirectional totem-pole PFC in CCM. This section will consider its
basic CCM operation, covering V2G discharging and G2V charging. Moreover,
current and voltage waveforms will be derived and portrayed for the main com-
ponents of the converter, including the boost inductor, the transistors and the DC-

Figure 2.1: The basic bidirectional totem-pole topology

13
link capacitor. Expressions will be developed for RMS currents and conduction
and switching losses for these components. The relevant bidirectional totem-pole
topology is shown in figure 2.1, and in the following all variables and parameters
will be referred to the notation in this figure.

2.1 G2V operation

In G2V operation, with power flow from AC source to DC link, the totem pole
is operated as a boost converter with PWM switching, to shape the fundamental
waveform of the AC current iAC like a sine in phase with the AC voltage vAC . [24]
The operation is sketched in figure 2.2. During the positive mains half cycle, the
lower totem-leg switch, ST 2 is operated with boost PWM switching (figure 2.2a),
while the upper totem-leg switch ST 1 is operated complementarily; when ST 1 is
on ST 2 is off, and vice versa. SR2 is always on during the positive half cycle.
During the negative mains voltage half cycle, ST 1 is operated as a boost, ST 2 is
complementary and SR1 is conducting. The AC current is governed by (2.1), and
from that controlled by the average vAB , which is again controlled by the time-
varying duty cycle, to be shaped like in figure B.2.

diAC
vL = vAC − vAB = L (2.1)
dt

14
 (a) Mains voltage positive half cycle

(b) Mains voltage negative half cycle

Figure 2.2: The G2V operation of the bidirectional totem-pole PFC.

15
2.2 V2G operation

Conversely, with power flow from DC link to AC side in V2G operation, the totem-
pole is operated as a buck converter, stepping down the voltage from the DC-link
to AC-side [24]. The operation is sketched in figure 2.3. In this case, during
the positive mains voltage half cycle, ST 1 is operated with buck PWM switching,
ST 2 is complementary and SR2 is conducting, as indicated in figure 2.3a. During
negative half cycle, ST 2 is buck PWM controlled, ST 1 is complementary and SR1
is conducting, as indicated in figure 2.3b. With AC current defined positive from
DC-side to AC-side the inductor voltage changes polarity, so that the current is
governed by (2.2).

diAC
vL = vAB − vAC = L (2.2)
dt

Still, this means the current is controlled by the time-varying duty cycle of the
buck-operated switch, controlling vAB , as it is in the boost operation.

16
 (a) Mains voltage positive half cycle

(b) Mains voltage negative half cycle

Figure 2.3: The V2G operation of the bidirectional totem-pole PFC.

17
 Figure 2.4: CCM iL and vL ripple over one switching period

2.3 Boost inductor

For this section, when evaluating inductor currents, iL and IL will be referring to
the instantaneous and RMS currents through the inductors, whereas IAC will be
referring to the RMS AC current drawn from the grid.

2.3.1 Current waveforms and ripple

As explained in section 2.1, the bidirectional totem-pole operates as a boost con-

verter during G2V charging. Thus, the inductor current and voltage waveforms
over one totem-leg switching period during the positive mains half cycle will be
as shown in figure 2.4.[24, ch. 7-4]. During negative half cycle the ripple will be
exactly mirrored over the time axis.

As can be found combining figure 2.4 and (2.1), the inductor current ripple at any
given point in the AC mains cycle can be given as

18
 Figure 2.5: Boost CCM ∆iL vs duty cycle

Z d·Tsw
1
∆iL (t) = vAC (t)dt , (2.3)
L t=0

where d is the duty cycle at this point. Since fsw  fAC , vAC (t) and can be consid-
ered constant over one switching period, giving from (2.3):

Tsw
∆iL (t) = d(t)vAC (t) (2.4)
L

Finally using the boost converter voltage ratio from [24, ch. 7-4],

vDC (t) 1
= , (2.5)
vAC (t) 1 − d(t)

(2.4) can be rewritten as follows:

Tsw vDC (t)

d(t) 1 − d(t) . (2.6)


∆iL (t) =
L

This equation (2.6) is solved graphically in figure 2.5, assuming vDC (t) is approx-
imately constant and equal to vDC (t) ≈ VDC . Figure 2.5 shows that ∆iL (d) has a
parabolic shape, peaking at d = 0.5.

For illustration, the current through the inductor, iAC , during G2V over a whole
mains cycle is shown in figure 2.6. The average inductor current and the AC mains
voltage are shown as well for comparison, and they show that the fundamental AC
current is more or less in phase with the AC voltage.

19
Figure 2.6: The inductor current compared to the AC mains voltage throughout one mains
cycle.

2.3.2 Conduction losses

The inductor conduction losses mainly comprises two parts: copper losses, which
are resistive losses from the resistance in the inductor windings, and core losses,
who are mostly due to eddy current losses end hystheresis losses in the magnetic
core.[24, ch. 30-1] The hysteresis losses are highly dependent on the core material,
but is always given on the following form:

PL,hyst = k · f a · BqAC , (2.7)

where k, a and q are material dependent constants, f is the magnetic flux oscillation
frequency and BAC is the AC magnetic flux density.[24, ch. 30-1-2] Eddy current
losses are also core dependent, given on the form:

q2 ω 2 (BAC + Bavg )2
PL,eddy = , (2.8)
24ρcore

where ω is the angular frequency of the flux oscillations, Bavg is the flux density
constant flux offset and ρcore is the charge density of the core material.[24, ch.
30-1-4] As mentioned, the copper losses are resistive losses due to the winding
resistance, and so they are given by:

20
 PL,copper = RL,copper IL2 , (2.9)

where IL is the RMS inductor current and RL,copper is the inductor winding resis-
tance. Acknowledging that the core flux density B ∝ I by Ampere’s law, as well as
that q often takes a value close to 2,[24, ch. 30-1-2] it can be seen from (2.7), (2.8)
and (2.9) that all of these losses have a nearly proportional relation to to IL2 . Thus,
a simplification will be made going forward, merging all of these losses into one
equivalent resistance at the given frequency, called RL , giving the following loss
equation:

PL ≈ RL IL2 . (2.10)

As mentioned, the inductor current ripple must be less than 20%, and for that
reason it is assumed that

IL ≈ IAC , (2.11)

meaning (2.9) can be rewritten:

2
PL ≈ RL IAC . (2.12)

21
Figure 2.7: The rectifier-leg transistor drain-source currents throughout one mains cycle
during G2V.

2.4 Transistors

2.4.1 Current waveforms and ripple

Rectifier-leg switches

The currents through the transistors will be quite different for the two legs of the
totem pole. Simplest are the rectifier legs, who conduct for a whole mains half-
period each, as shown in sections 2.1 and 2.2. SR1 conducts during negative mains
half cycle, SR2 conducts during the positive. Therefore, the current ripple during
the conducting half-cycle of these rectifier-leg transistors will be shaped like the
inductor current ripple in figure 2.4.

Figure 2.7 illustrates the drain-source currents of the rectifier-leg transistors through-
out the mains cycle during G2V charging. The drain-source currents are evidently
always negative during G2V, confirming the operation description from section
2.1. During V2G the currents will, oppositely, always be positive.

22
 (a) The current through the boost switch at an arbitrary point in the AC
mains cycle.

(b) The totem-pole output current to the DC link at an arbitrary point in

the AC mains cycle.

Figure 2.8: The current ripple of the totem-leg switches during positive mains half cycle
in G2V operation.

23
Totem-leg switches

The current of the two totem-pole transistors depend highly on the duty cycle d
of each of the switches, since the transistors obviously only conducts while they
are on. The modulation is different for the different transistors in each mains half-
cycle, as mentioned in sections 2.1 and 2.2, and so the switching-period current
waveform of each of the transistors will be different as well. To simplify the anal-
ysis, switching-period current waveforms will here be shown for the boost switch
and the boost complementary switch during G2V. During V2G, the boost comple-
mentary switch which will be equivalent to the buck switch, with the same current
waveform, and the boost switch will be equivalent to the buck complementary
switch.

Deriving the switching-period current waveforms from figure 2.4, the boost switch
conducts during dTsw , whereas the boost complementary switch conducts during
(1 − d)Tsw . Hence, the switching-period current waveforms through the boost
switch and the boost complementary switch for an arbitrary duty cycle d can be
given as in figures 2.8a and 2.8b, respectively. The current through the boost com-
plementary switch is the current that is passed from the totem-pole to the DC-link,
and is therefore denoted iDC (t).

Throughout one mains cycle in G2V operation, the currents of the two switches
will be shaped as in figure 2.9. As explained in section 2.1, ST 2 is the boost switch
during positive half-cycle, having the switching-period current waveform drawn
in figure 2.8a, whereas during negative half-cycle it is the complementary switch,
having the switching-period current waveform drawn in figure 2.8b, with negative
polarity. ST 1 is exactly opposite. During V2G, the currents have the same shape,
but with opposite polarity.

24
Figure 2.9: The totem-leg transistor drain-source currents throughout one mains cycle
during G2V.

2.4.2 Conduction losses

In the following it will be assumed that MOSFETs or GaN HEMTs are chosen
for both the rectifier leg and the totem leg. In the case of other relevant transistor
technologies, such as IGBTs, the conduction losses would not be resistive, but
caused by forward voltage and average current through the transistors.

Rectifier-leg switches

To evaluate the conduction losses in the transistors, expressions have to be devel-

oped describing the RMS currents through the transistors. For the rectifier switches
SR1 and SR2 , this is trivial, since they will be conducting for half an AC mains pe-
riod each:

1 1
Z π
2
ISR = i2L (ωt) dωt = IL2 . (2.13)
2π ωt=0 2

Implementing (2.11) in (2.13), we get for each of the rectifier switches:

1
ISR = √ IAC . (2.14)
2

25
Totem-leg switches

In the case of the fast-switching totem-leg switches, ST 1 and ST 2 , the RMS current
through each of the transistors depends on the time-varying duty cycle dST of the
relevant transistor. The discrete-form equation for the RMS current through one of
the totem-leg switches can be given as follows:

fsw / fAC
2 1
IST = ∑ dST [k]i2L [k] , (2.15)
2π k=0

where k represents one single switching period at one point in the AC mains cycle,
fsw is the switching frequency, fAC is the AC mains frequency and d in this case
is the duty cycle of any of the two totem-leg switches. Taking into account that
fsw will be chosen so that fsw  fAC , (2.15) can be approximated as a continuous
integral over the whole AC mains cycle:

Z 2π
2 1
IST = d(ωt)i2L (ωt) dωt . (2.16)
2π ωt=0

Moreover, since ST 1 and ST 2 are switched complementarily, (2.16) can be sim-

plified. Dead time required between turn-off of one transistor and turn-on of the
other to avoid cross-conduction is neglected, since it is assumed very small.[24]
The complementary switching means one of the switches are always conducting,
and as explained in sections 2.1 and 2.2, the roles of the two switches interchange
every half cycle. Thus, based on the current waveforms for the boost and comple-
mentary switch in figures 2.8a and 2.8b, (2.16) can be rewritten as follows:

!
1
Z π Z π
2
IST d(ωt)i2L (ωt) dωt + 1 − d(ωt) i2L (ωt) dωt (2.17)


=
2π ωt=0 ωt=0

1 π
Z
d(ωt) + 1 − d(ωt) i2L (ωt) dωt (2.18)


=
2π ωt=0
1 π 2
Z
= i (ωt) dωt (2.19)
2π ωt=0 L
1
= IL2 (2.20)
2

26
This derivation from (2.17) to (2.20) shows that due to the symmetry of the topol-
ogy, both of the totem-leg switches are conducting in total in half of the AC-mains
voltage cycle. This gives the same RMS current in both of the totem-leg switches
as in the rectifier-leg switches:

1
IST = √ IAC . (2.21)
2

Based on the derived RMS current expressions in (2.14) and (2.21), the conduction
losses in each of the transistors can be determined as follows:

1 2
Pcond = IAC RDS,on . (2.22)
2

2.4.3 Switching losses

Now that the transistor conduction loss expressions have been established, the next
thing needed to estimate the transistor losses is an estimation of the switching
losses. As with the derivation of the conduction losses, the following will assume
MOSFETs or GaN HEMTs as the chosen transistor technology.

Based on the MOSFET switching characteristics described in [24, ch. 22-5-2], the
switching waveforms can be approximated as in figure 2.10. As appears in [36],
the switching characteristics of a GaN HEMT can be estimated in a similar way,
so figure 2.10 and the following derivations are hence considered valid for both
transistor types. The switching energy Esw is given as vDS (t) · iD (t) dt over the
R

switching transient duration, giving the following equation based on figure 2.10:

1
Esw [k] = Eon [k] + Eo f f [k] = (Tr,i + T f ,v + Tr,v + T f ,i )vDC [k]iL [k], (2.23)
2

where vDC and iL are, respectively, the average DC voltage and inductor current
over the switching period.

In order to find a simple expression for the switching power Psw , (2.23) is averaged
over half an AC mains cycle. Current and voltage rise and fall times are obviously
dependent on vDC (t) and iL (t), making it somewhat more complex. However,

27
 (a) Turn-on

(b) Turn-off

Figure 2.10: Approximation of the switching characteristics of a MOSFET.

28
vDC (t) will have a ripple of less than 20%,(table 1.2) meaning it can be assumed to
be approximately constant and equal to VDC , again giving approximately constant
Tr,v and T fv . Since we are mostly interested in a rough estimate of the losses for
transistor dimensioning purposes, it is assumed for simplicity going forward that
also the current rise and fall times do not vary much with time. To clean up the
expression, we set total switching commutation time Tsw,comm = Tr,i + T f ,v + Tr,v +
T f ,i . An expression for the average switching energy is obtained:

1 1
Z π
Esw,avg = Esw (ωt)dωt = Tsw,commVDC IAC,avg , (2.24)
π ωt=0 2

where the average AC current over one half period, IAC,avg , is given as

√
1 2 2
Z π
IAC,avg = iAC,avg (ωt)dωt = IAC . (2.25)
π ωt=0 π

This gives approximate transistor switching power loss:

fsw
Psw = fsw ∗ Esw,avg = Tsw,commVDC IAC,avg . (2.26)
2

29
 Figure 2.11: Illustration of he DC-link capacitor, voltage and currents

2.5 DC-link

Now, having established current waveforms and losses for the other main com-
ponents of the totem-pole PFC, the same can be done for the DC-link capacitor.
The assignment of the DC-link capacitor is to remove as much as possible of the
100Hz and high-frequency ripple in voltage and current from the PFC to the DC-
DC converter feeding the battery. Due to size limitations of this capacitor, it is
practically not possible to remove all of this ripple, leaving a small 100Hz ripple
to be compensated in the DC-DC converter. All variables and parameters in the
following derivations are referred to figure 2.11.

2.5.1 Current waveforms and ripple

From figure 2.11 the DC-link current can be written:

iDC−link = iDC − iDC,avg . (2.27)

The current sent from the PFC to the DC-link, iDC , is the current passed through the
boost complementary switch, with ripple shown in figure 2.8b. Thus, the current
ripple consumed by the DC-link capacitor is equal to this current minus the average
DC current going into the DC-DC converter, as in figure 2.12.

The DC-side currents during a whole mains period are depicted in figure 2.13,
showing a rectified iDC , a small 100Hz ripple on iDC,avg due to the necessary small
DC-voltage ripple and iDC−link as the sum of these in accordance with (2.27).

30
Figure 2.12: The current through the DC-link capacitor over one totem-leg switching
period

Figure 2.13: The DC-side currents throughout one mains cycle during G2V.

31
2.5.2 Conduction losses

Like in the other main components of the totem-pole PFC, there are some losses
in the DC-link capacitor which need to be taken into account in the PFC design.
These are mostly dielectric losses and electrode losses, often simplified as conduc-
tion losses due to an internal equivalent series resistance (ESR) of the capacitor.
[37] A loss expression can be given as

2
PDC−link = IDC−link · ESR , (2.28)

where IDC−link is the RMS current through the DC-link capacitor. With IDC,avg
assumed constant, the DC-link current iDC−link consists of all of the harmonics in
iDC . As explained in [24, ch. 3-2-4-1], using superposition of harmonic signals,
the DC-link RMS current can again be given as follows:

q
IDC−link = 2
IDC,rms 2
− IDC,avg , (2.29)

where IDC,rms is the RMS-value of the current from the totem pole to the DC-side
and IDC,avg is both the RMS and the constant value of the current to the DC-DC
converter. Since iDC is always the current through the complementary boost switch,
and exploiting that iDC is symmetric every half period, the RMS current IDC can be
given from (2.13) over one half period:

1
Z π
2
IDC = dcompl (ωt)i2AC (ωt) dωt , (2.30)
π ωt=0

where dcompl is the duty cycle of the complementary switch. It will be shown later
in section 4.2.1 that the duty cycle dcompl (ωt) ∝ vAB,1 (ωt) = V̂AB sin(ωt + φAB )
from figure 2.1. Hence, (2.30) can be rewritten

1
Z π
2
2
IDC = dˆcompl sin(ωt + φAB ) IˆAC sin(ωt) dωt , (2.31)
π ωt=0

where φAB is the phase angle of vAB (ωt) referred to vAC (ωt). The peak duty dˆcompl
will be, using the basic boost converter properties from [24, ch. 7-4] and that the

32
duty cycle of the complementary switch is given as dcompl = 1 − dboost :

V̂AC
dˆcompl = 1 − dboost,min = . (2.32)
VDC

Implementing (2.32) in (2.31) and solving, the DC RMS current becomes

2 8 V̂AC 2
IDC,rms = I cos(φAB ) . (2.33)
3π VDC AC

Implementing (2.33) in (2.29), the RMS current in the DC-link is given as follows:

s
8 V̂AC 2 2
IDC−link = I cos(φAB ) − IDC,avg , (2.34)
3π VDC AC

which easily gives the conduction losses when implementing in (2.28):

!
8 V̂AC 2 2
PDC−link = I cos(φAB ) − IDC,avg · ESR . (2.35)
3π VDC AC

33
34
Chapter 3
Components dimensioning

Dimensioning the components is obviously important for building a physical em-

bodiment of the PFC, but it is important for building the basic simulation model
as well. Various parameters in the PFC will affect the currents and voltages at
different points in the topology; e.g. loss considerations in boost inductor and
transistors dictating the average DC-link voltage, DC-link capacitor dictating the
DC-link voltage ripple and the boost inductor – along with the DC-link voltage
– dictating the AC current ripple. This chapter will revolve around dimensioning
the key components of the totem-pole PFC: The boost inductor, the transistors and
the DC-link capacitor. The components will be dimensioned assuming maximum
power flow both in G2V and V2G mode. This is justified by the following: During
G2V, the consumer should be able to charge its car at maximum power when re-
quired, and, during V2G, the OBC is likely to operate as a grid stabilizer supplying
the grid at maximum power, as argued in section 1.1. All parameters and variables
will be referred to figure 2.1.

35
3.1 DC-link capacitor

The DC-link capacitor plays an important role in an OBC, suppressing much of

the DC-link voltage ripple to keep the voltage as constant as possible without ex-
ceeding the DC-link capacitor size limitations. This DC-link voltage is controlled
by the PFC, making the DC-link capacitor central in PFC design. The battery on
the DC-side of the OBC requires DC voltage. Thus, a big part of the DC voltage
100Hz ripple must be suppressed in the DC link before DC-DC converter com-
pensates the rest. The DC-DC converter is often less efficient at compensating big
variations in input voltage and current, meaning it is beneficial keeping the ripple
low at its input.[1] Moreover, since the PFC is working in boost operation during
G2V charging and buck during V2G discharging, another key reason for minimiz-
ing the ripple is ensuring that the instantaneous DC-link voltage is always higher
than the instantaneous AC voltage. Moreover, the DC-link capacitor is the most
limiting component to the lifetime of the OBC, and so the current rating should be
chosen as high as possible and the ESR as low as possible to minimize the wear
and tear of the capacitor. [1]

3.1.1 DC-link rated voltage

Valeo Siemens define for this application that the peak-to-peak 100Hz voltage rip-
ple at the DC-link should be held at 20V, as specified in table 1.2. Furthermore,
it is critical for the boost operation in G2V and buck operation in V2G that the
instantaneous DC-link voltage is always higher than the instantaneous magnitude
of vAC (t), as shown in figure 3.1. To allow for some delay in the voltage control, a
certain margin, Vmargin , needs to be added. This margin is for this converter set at

Vmargin ≥ 5V .

As a consequence, with the peak-to-peak ripple of 20V, the average DC-link volt-
age has to be set at
VDC ≥ V̂AC + 15V .

At AC voltages of 230Vrms (325Vpeak) and lower, complying with the above-

mentioned restrictions is not an issue, due to the minimum limit for VDC set at 340

36
 Figure 3.1: DC-link voltage design requirements compared to AC mains voltage.

V (table 1.2). Furthermore, since the switching losses increase with increasing
DC-link voltage, by (2.26), keeping the DC-link voltage as low as possible will
reduce the switching losses. Looking at the PFC in isolation, it would therefore
loss-wise be beneficial to have VDC lower than 340V for VAC lower than 230Vrms,
but this would increase the current from the PFC to the DC-DC, increasing the
conduction losses of the DC-DC converter. This is the reason for the 340V VDC,min
limit, ensuring efficient operation of the DC-DC converter by keeping a narrow
input voltage range. Thus, for every peak voltage lower than 330V, the DC-link
voltage is set at

VDC = VDC,min = 340 when V̂AC ≤ 325V .

For peak AC voltages exceeding 325V, it is exploited that the DC-link voltage is
regulated by the PFC, as will be explained later in the thesis, and therefore can also
be changed according to the AC voltage. The DC-link voltage is set to follow the
mains voltage as closely as possible, given the restriction that vDC (t) should always
be higher than vAC (t) with a DC-link voltage peak-to-peak ripple of 20V. Thus, the
average DC-link voltage VDC is controlled, both in G2V and V2G, according to the
following equation:

VDC = V̂AC + 15V when V̂AC > 325V . (3.1)

37
Based on this the maximum rated DC-link voltage in this design can be found to
be

√
VDC,max = 2 · 275V + 10V = 400V .

3.1.2 DC-link rated current

Finding the minimum DC-link current rating can be done easily using figures 2.12
and 2.13 to recognize that the maximum DC-link current can be given as

IDC−link,max = IˆAC,max − IDC,avg,min , (3.2)

where IDC,avg,min is the minimum DC current at max power, which is given from
the max power and minimum average DC-link voltage:

3500W
IDC,avg,min = = 8.75A ,
400V

and the maximum DC-link current becomes, from (3.2):

√
IDC−link,max = 2 · 16A − 8.75A = 13.87A .

However, as mentioned earlier, the current rating should be chosen higher than this
to minimize the wear and tear of the DC-link capacitor.

3.1.3 DC-link capacitance value

The DC-link capacitance value is chosen in order to filter the 100Hz fundamental
component of the totem-pole DC-side voltage to give the desired DC-link peak-to-
peak voltage ripple of 20V. This is governed by the basic equation for a capacitor:

1
Z
∆vDC,1 (t) = iDC−link,1 (t) dt . (3.3)
C t

38
Table 3.1: Key parameters for the relevant electrolytic capacitor used by Valeo Siemens
today. [1]

Parameter Value
Vrated 450Vdc
Iripple,rated 3.1Arms
Cnominal 360µF

The fundamental component is of course sinusoidal, and so the integral will natu-
rally be biggest over one positive or negative half period of iDC−link,1 . Integrating
over the positive half period, and inserting ωt with dt = dωt/ω, the voltage ripple
becomes:

1 π
Z
∆VDC,1 = IˆDC−link,1 sin(ω1t) dω1t , (3.4)
ω1C ω1t=0
2 ˆ
= IDC−link . (3.5)
ω1C

It becomes clear swapping ω1 with ωn in (3.5) that it is indeed sufficient to design

C from the fundamental current, as ∆VDC,n is then inversely proportional to ωn ,
showing that the fundamental frequency has the biggest voltage ripple.

The capacitance value can now be found solving (3.5) for C and inserting values. A
Fourier analysis performed in Simulink on the signal shown in figure 2.13 reveals
that the fundamental component of iDC−link has amplitude IˆDC−link = 10.81A, equal
to IDC,avg , and a frequency f1 = 100Hz. Using ∆VDC,1 = 20V, the capacitance
becomes:

2IˆDC−link
Cmin = = 1.72mF (3.6)
ω1 ∆VDC,1

3.1.4 Capacitor choice

For the choice of capacitor, it is important to choose a capacitor type with low ESR
and high current rating, since the capacitor is the most limiting component to the
lifetime of the OBC, and high losses and approaching the current rating decreases

39
the lifetime of the capacitors. A good way of solving this is connecting several
capacitors in parallel, reducing the current and losses in each of the capacitors. To
match the lifetime of the current OBC technology at Valeo Siemens, it is chosen to
use the same capacitor. Due to confidenciality the exact model name or datasheet
can not be shown in this thesis, but it is an electrolytic capacitor, and some of its
key parameters are summarized in table 3.1.

With the given Cnominal = 360µF it is apparent that 5 capacitors connected in par-
allel is required to match the required minimum capacitance value in (3.6), giving
total capacitance
C = 5 · 360µF = 1.8mF .

Checking the RMS current through each of the capacitors, the total DC-link RMS
current can first be found from (2.34). Assuming close-to-zero phase angle φAB due
to the low inductance and using minimum DC-link voltage and maximum power
for maximum DC-link current, the DC-link RMS current becomes
r
8 · 325V
IDC−link = (16A)2 − (10.8A)2 = 9.54A .
3π · 340V

Acknowledging that the current in each of the capacitors will be one fifth of the
total DC-link RMS current, the RMS current through each of the capacitors will
be
1
IDC−link,cap = · 9.54A = 1.9A ,
5
which is well below the maximum rated ripple current of the relevant capacitor in
table 3.1.

No ESR is given in the datasheet, but with three capacitors connected in parallel,
and at the same power level, Valeo Siemens experience power losses < 0.5W ,
which is negligible. In this case, with five capacitors connected in parallel, the
losses will be even lower due to lower currents through each of the capacitors. This
lower current stress in each of the capacitors should also imply a longer lifetime
expectancy of the charger.

40
3.2 Transistors

The right choice of transistors is a key part of the design of any switch-mode con-
verter. In this case, the transistors are chosen along with the switching frequency
to comply with the desired efficiency of the whole charger. Moreover, the tran-
sistors have to withstand the expected RMS currents, peak blocking voltages and
peak currents. Aided by a heat sink, the transistors should also be able to handle
its own dissipated heat without melting.

In the following, the design process for choosing and dimensioning the totem-leg
and rectifier-leg transistors will be described chronologically. The reason for this
is that converter design is an iterative process, making assumptions and updating
them based on the results throughout the design process. While dimensioning
the totem-leg transistors, the switching frequency, fsw will also be chosen. This
because the transistors will be designed to match the required efficiency, requiring
the switching losses to be within the allowed losses restriction that follows this
efficiency.

3.2.1 Choice of transistor technology

Totem-leg transistors

When choosing the transistor technology for each of the switches it is important to
first evaluate the requirements of the switch. First of all, figures 2.2 and 2.3 show
that the current should be able to flow in both directions through all of the switches.
Secondly, the totem-leg switches need to be able to handle high-frequency switch-
ing, preferably around 100kHz (appendix A), while also keeping the losses suf-
ficiently low to comply with the efficiency requirement of 98% in G2V and 97%
in V2G. A high switching frequency has several benefits regarding especially the
power density of the OBC; it minimizes the size of magnetic-core components, as
is shown further for the boost inductor in section 3.3, and it minimizes the size of
the AC-side direct mode (DM) filter required to comply with the grid-side current
noise limitations, declared in the design specifications in appendix A.

In this frequency range, and at a required rating of around ∼400V and ∼22.5A,
two transistor technologies stand out as promising solutions: Power MOSFETs

41
and GaN HEMTs. MOSFETs and GaN HEMTs both have bidirectional conduc-
tion capability by nature, due to their symmetrical structure.[38] This is beneficial,
as it would be sufficient the transistor as the only semiconductor component in
each of ST 1 and ST 2 . Furthermore, they are both efficient at high switching levels,
much due to the lack of minority carriers having to be moved in and out of the
transistor during switching, as is the case in many other transistor technologies,
such as IGBTs and BJTs. [24] However, there are differences in the performance
of these two transistor technologies when working as totem-leg switches, owing to
their structural differences highlighted in [38]. This is also explained in more detail
in the paper written on GaN HEMTs in appendix C, and the following argumenta-
tion on GaN HEMTs is based on the contents of this paper. The paper states that
although GaN as a material has higher breakdown field and band gap than SiC and
Si, which initially gives a higher resistivity in the transistor, the two-dimensional
electron gas (2DEG) layer ensures that the GaN HEMT has a lower RDS,on than
MOSFETs for the same breakdown voltage. Moreover, the higher breakdown field
of GaN allows for smaller physical embodiments of the transistors compared to Si
and SiC MOSFETs at the same rated breakdown voltage, again giving smaller par-
asitic capacitances and thus faster switching transients and lower switching losses.
Another significant advantage of the GaN HEMT is that, unlike MOSFETs, it does
not have a reverse body diode. According to [25], the reverse recovery losses of
the MOSFET reverse body diodes during CCM operation of a totem-pole PFC are
severe, and thus the lack of reverse body diodes in GaN HEMTs is beneficial with
regard to losses.

However, one drawback of the GaN HEMT, besides it being a relatively new and
thus not fully developed and commercialized technology, is that it has a relatively
low thermal conductivity compared to Si and SiC MOSFETs. That means it will
have trouble dissipating the heat generated from losses, possibly imposing some
challenges in the heat sink design. On the other hand, the results from [39] sug-
gest that the performance of GaN HEMTs are less affected by the case tempera-
ture, and so the decreased thermal conductivity might not matter anyway. Another
drawback is that the GaN HEMT technology is by nature normally-on, meaning it
is conducting at low gate voltage, as explained in appendix. This is undesirable,
as we want the transistor to be open when the system is not energized. There-
fore, it is compensated by constructing normally-off enhancement-mode HEMTs

42
(eHEMTs), either by changing the structure or by cascading a FET at the gate of
the HEMT. This derates the switching performance of the GaN HEMT some, but
still it is an improvement compared to existing technology in that regard.

All of this taken into account, the GaN eHEMT is chosen as the transistor technol-
ogy for use in the totem-leg switches. This is because it appears most efficient in
high-frequency and high-power application. This decision is backed up by calcu-
lations in section 3.2.5.

Rectifier-leg transistors

As for the rectifier-leg switches, these only really have one requirement, which is
bidirectional conduction ability, due to the reverse direction of the current in V2G
mode shown in figure 2.3. The switching losses are negligible, due to a switching
frequency equal to the mains frequency (45Hz-65Hz), and thus it is desirable to
have transistors with low conduction losses. In that sense, it will be sufficient
to use slow-switching low-RDS,on MOSFETs. Since a more advanced transistor
technology has been used in the totem-leg switches, it also becomes a question
of price, especially since the OBC would be mass-produced. Thus a cheaper and
simpler MOSFET, just complying with the loss and rating demands is preferable
in the rectifier-leg switches.

Corresponding topology

The updated bidirectional totem-pole PFC topology, with GaN eHEMTs in the
totem leg and MOSFETs in the rectifier leg, is shown in figure 3.2. Due to the
absence of eHEMT symbols in the drawing software, eHEMTs are represented as
MOSFETs with no reverse diodes.

3.2.2 Guesstimating component loss distribution

As specified in the bidirectional OBC and PFC specifications in tables 1.1 and 1.2,
the efficiency of an OBC should be designed at 94% in G2V charging mode, with
the efficiency of the PFC being at 98% for the standard voltage levels (230Vrms

43
Figure 3.2: The bidirectional totem pole topology with GaN eHEMTs in the totem leg
and MOSFETs in the rectifier leg.

and 110-120Vrms). [20] In G2V discharging mode, the efficiency of the bidirec-
tional OBC is predetermined to be at least 91%, with the PFC having at least 97%
for the same voltage levels. For the design of this particular totem-pole PFC, it
is decided to design the charger mainly for 230Vrms and the most restrictive ef-
ficiency, ηPFC,G2V = 98%. Due to the conduction losses of the transistors being
independent of the AC voltage, by (2.22), the eHEMTs would have to be paralleled
in order to meet the efficiency demands at 110-120Vrms. This will be discussed
more in the later discussion part, but is rendered out of scope for the totem-pole
model of this master’s work.

The losses will be calculated using worst-case highest drain-source resistances in

the transistors. Thus, it is acceptable to use a worst case efficiency of

ηPFC,worst−case = 97.6% ,

which rounded up becomes 98%. During normal operation, the resistances will be
lower and the efficiency higher. Using this along with rated VAC = 230Vrms and
IAC = 16Arms, the maximum allowed PFC losses can be calculated as follows:

Ploss,PFC,max = (1 − ηPFC,worst−case ) · IAC ·VAC = 0.024 · 16A · 230V = 88.32W .

44
Table 3.2: Guesstimated design rule losses distribution in the bidirectional totem-pole
PFC.

Losses distribution
Totem-leg 31W
Rectifier-leg 31W
Inductor/rest of PFC 26W
Total 88W

To simplify, it is decided that the losses in the PFC should be distributed as pre-
sented in table 3.2. Since the losses will be symmetrically distributed across the
two transistors in each leg, as is determined in section 2.4.2, the total losses in each
of the transistors in the two legs will have to be:

PST = 15.5W, PSR = 15.5W .

3.2.3 Totem-leg transistors

The loss restrictions for PST are now used to determine the transistors used in
the totem-leg switches along with the switching frequency to be applied on this
leg. As mentioned, GaN eHEMTs are preferred over MOSFETs for the totem-leg
switches due to their advantage of not having reverse body diodes. Commercial
GaN eHEMTs are not too many at this moment in time, but a selection has been
found from GaN Systems and these are, for the purpose of this thesis, assumed
representative for the rest of the market. Two models were found to meet both the
current and voltage rating demands (> 22.5A and > 400V) at an assumed worst-
case operating junction temperature of 150◦ C: GS66508 and GS66516. Some key
parameters acquired from the datasheets of GS66508 and GS66516 are shown in
table 3.3.

The switching frequency is chosen based on the switching losses, and later the
transistor model will be chosen based on the desired switching frequency. An
expression for fsw is found rewriting (2.26) as

45
Table 3.3: Some key parameters and rated values of the GaN Systems eHEMTs at Tcase =
25◦ C.

Parameter GS66508 GS66516

RDS,on 50mΩ 25mΩ
RDS,on (@150◦ C) 129mΩ 67mΩ
QG 5.8 nC 12nC
VDS 650V 650V
VGS -10V to +7V -10V to +7V
IDS 30A 60A
IDS (@100◦ C) 25A 47A
Switching energy with VDS = 400V
Eon,rated 47.5µJ (@15A) 134.1µJ (@20A)
Eo f f ,rated 7.5µJ (@15A) 14.7µJ (@20A)

Psw
fsw = . (3.7)
Esw

The switching energy is calculated from the values in table 3.3, while Psw is found
from

Psw = Ptransistor − Pcond , (3.8)

where Ptransistor is given from the design rules, and Pcond is calculated using (2.22).
As with the drain-source current capability, since the RDS,on of MOSFETs and
eHEMTs increase for increasing temperature, the worst-case 150◦ C on-state re-
sistance must be considered when computing the expected conduction losses, as
it will give the biggest losses. Applying the RDS,on at 150◦ C listed in table 3.3
and IAC = 16A to (2.22), the conduction losses of each of the eHEMT models are
calculated as shown in table 3.4. The results show that the conduction losses of
GS66508 have conduction losses that are higher than the permitted totem-leg tran-
sistor losses. That leaves GS66516 as the only real option, and this GaN eHEMT
is chosen for the totem-leg switches.

46
 Table 3.4: Calculated conduction losses of the eHEMT models.

Model Pcond [W]

GS66508 16.51
GS66516 8.32

Table 3.5: Estimated switching energy, losses and frequency of GS66516.

Model Esw,est [µJ] Psw [W] fsw,max [kHz]

GS66516 71.24 7.18 100.79

3.2.4 Switching frequency

To get a good estimation of the switching losses of GS66516, the switching energy
needs to be adjusted from the standard test conditions in the data sheet to fit the
average DC-voltage and inductor current seen by the transistors in the totem-pole
PFC. Using (2.23), where Esw is assumed linearly dependent on VDC and IAC,avg ,
the estimated eHEMT switching energy can be found as follows:

IAC,avg VDC
Esw,est = Esw,rated · · , (3.9)
IDS,test VDS,test

where the average AC current is, from (2.25),

√
2 2
IAC,avg = · 16A = 14.4A .
π

Switching energy, switching power losses and switching frequency can now be cal-
culated using (3.9), (3.8) and (3.7), inserting values from tables 3.3 and 3.4. The
calculation results are shown in table 3.5. Comparing to the present-day switching
frequency of Valeo Siemens OBCs at 90kHz, GS66516 allows higher switching
frequencies than this, at up to 100kHz, while still complying with the losses re-
strictions. Setting fsw = 100kHz could lead to an increase in power density com-
pared to the present-day solution, for the reasons explained above. However, this
increase is assumed to be relatively small for an increase in switching frequency
of 11%. The increase in control speed from 90kHz to 100kHz is also small, as the
requirement is that the current controller bandwidth is at least half a decade lower
than the switching frequency.[40] There are also some insecurities linked to the

47
estimation of switching energy, due to the rough approximation in (2.24), making
it sensible to choose a lower frequency than the maximum of 100kHz. Moreover,
the objective of this master’s thesis is to reveal whether the bidirectional totem-
pole PFC is suiting for a bidirectional OBC, rather than optimizing with respect
to size. Therefore, for simplicity, it is chosen to proceed with the same switch-
ing frequency as in the present-day solutions of Valeo Siemens, assuming that the
increased number of gate drivers required for the totem-pole and the altered re-
quired heat sink design does not propose a big increase in the power density of
the hardware OBC solution. That way, e.g. the same type of DC-link capacitor
and inductor could be used in this solution, since these see the same currents and
voltages for a totem-pole as for a regular boost PFC. The same AC-side DM fil-
ter could also be used, although the filtering is out of scope for this thesis. The
switching frequency is set at

fsw = 90kHz .

3.2.5 Comparison to state-of-the-art MOSFETs

Comparing to the state-of-the-art lowest-RDS,on power MOSFETs on the market

with a rating of at least 400Vdc and 25Adc, such as Infineon’s automotive power
MOSFET IPW60R045CPA, these have a rated RDS,on = 45mΩ. Scaling to a worst-
case on-state resistance at 150◦ C from the data sheet of IPW60R045CPA, this
becomes 110mΩ, which using (2.22) gives conduction losses

1
Pcond,MOS = · (16A)2 · 110mΩ = 14W .
2

An estimation of the MOSFET switching energy using (2.24) and data for switch-
ing times from the data sheet of IPW60R045CPA gives

1
Esw,MOS,noRR = · 30ns · 340V · 14.4A = 73.44µJ ,
2

when not considering the reverse recovery losses of the body diode. That gives a
maximum switching frequency, not considering reverse recovery losses, using the

48
same procedure as for the GaN eHEMTs:

fsw,MOS,max,noRR = 20.42kHz .

If the reverse recovery losses were considered, this switching frequency would be
even lower. In fact, it is found that [30] that the switching losses of a superjunction
CoolMOS has 20 times more switching loss when operated in the totem-leg, due
to the reverse recovery diode. This should make the GaN eHEMT GS66516 a far
superior solution to the IPW60R045CPA.

However, it is worth noting that this analysis is not sufficient for concluding with
absolute certainty that the GaN eHEMT is in fact the best solution, as especially
the estimated switching losses are based on possibly rough approximations from
uncertain parameters in the component data sheets. To get a proper overview of the
losses in each of the transistors, tests should be performed, measuring the losses
in each of the transistors at the relevant current and voltage operating point, e.g.
using thermal measurement equipment. Nonetheless, GaN eHEMTs are, based
on this switching and conduction loss analysis, considered the best solution, and
GS66516 will be the transistor of choice for use in the high-frequency totem leg.

3.2.6 Rectifier-leg transistors

For the rectifier-leg transistors, the switching frequency will be equal to the mains
frequency, meaning switching losses are negligible. Therefore, all that is required
for the rectifier-leg transistors is bidirectional conduction ability and low conduc-
tion losses. A good choice for these transistors would thus be slow-switching
MOSFETs with a low RDS,on . Rearranging (2.22) and setting Pcond,SR,max = PSR =
17W, the span of allowed RDS,on for the rectifier-leg mosfets can be found as fol-
lows:

Pcond,SR,max
RDS,on,SR ≤ 2 2
= 132.8mΩ (3.10)
IAC

Thus, any MOSFET with an RDS,on ≤ 132.8mΩ, voltage rating > 400V and drain-
source current capability > 22.5A would be suiting for this solution. A quick

49
Table 3.6: Some key parameters and rated values of MOSFET IPW60R045CPA at Tcase =
25◦ C.

Parameter Value
RDS,on 45mΩ
RDS,on (@150◦ C) 110mΩ
VDS 600V
VGS -20V to +20V
IDS 60A
IDS (@100◦ C) 38A
VSD (Diode FV) 0.9V

search reveals many possible solutions, but Infineon’s previously analyzed auto-
motive MOSFET IPW60R045CPA is chosen, with key parameters shown in table
3.6.

50
3.3 Boost inductor

Design of magnetic components for power electronics is a research field of its own,
and an overview of the challenges faced can be found in [24, ch. 30]. For the sake
of this master’s thesis, when designing the boost inductor, the magnetic design
itself is regarded out of scope. The design process will revolve around choosing
from existing inductor technologies, considering mainly three factors: Inductance
value, RMS current rating and peak current rating.

3.3.1 Boost inductance value

The boost inductance value L, along with the magnitudes of vAC and Vd , dictates
the slope of the inductor current in every switching interval according to (2.1)
and (2.2). These equations imply that a higher switching frequency would require
a smaller inductance for the same maximum ripple, and likewise with a higher
maximum ripple for the same frequency, as both of these cases would increase the
required slope. For that reason the boost inductance, L, needs to be designed small
enough to allow for the desired switching frequency and large enough limit the
current ripple to its maximum allowed value.

The equations for the inductor ripple is developed in section 2.3.1. It is shown in
(2.6) that the ripple is proportional to the DC-link voltage, meaning the maximum
inductor current ripple occurs at the maximum DC-link voltage. Figure 2.5 also
shows that the maximum inductor current ripple occurs at duty cycle d = 0.5. Us-
ing this information, an expression for maximum inductor current ripple is found
from (2.6):

0.25VDC,max
∆iL,max = . (3.11)
fsw L

Solving (3.11) for L, an expression is developed for the boost inductance value:

0.25VDC,max
L= . (3.12)
fsw ∆iL,max

Defining the AC-side current ripple to be set at 20% of peak AC current accord-

51
ing to the bidirectional PFC specifications presented in table 1.2, the maximum
current ripple becomes ∆iL,max = 0.2 · Iˆac = 4.52 A. The switching frequency has
been chosen at fsw = 90kHz and the maximum DC-link voltage is VDC,max = 400V.
Inserting these data in (3.12), the resulting value of the boost inductance is found
to be:

L ≥ 245.82µH .

3.3.2 RMS current rating

Overly high RMS currents in magnetic core inductors can lead to saturation of
its core material or overheating due to resistive losses in the windings and eddy
current losses in the core.[24, ch. 30] Thus, the inductor needs to be designed
with sufficient RMS current rating. It is found in section 2.3.2 and (2.11) that the
RMS current in the inductor is equal to the AC-grid RMS current. That means
the inductor current rating should comply with the AC current rating described in
table 1.1, giving the following inductor RMS current rating:

IL,rated = 16A .

3.3.3 Saturation current rating

Although continuous currents can cause magnetic core saturation in the inductor,
this is a more adjacent issue with the peak currents, especially in switch-mode
converters, where a current ripple is in fact necessary to control the output and
input currents and voltages. [24, ch. 30] The maximum peak-to-peak current
ripple is defined in table 1.2, to be 20% of the peak current value. Using that, the
minimum peak current rating of the inductor can be defined as follows:

√
IL,sat = (1 + 0.1) 2IAC,max = 24.89A

52
Table 3.7: Estimated inductor parameters based on technology used by Valeo Siemens
today.[1]

Parameter Value
L 245.82µH
RL 10mΩ
Irated 16Arms
Ploss,est (100◦ C) 17W

3.3.4 Choice of inductor

Unlike the capacitor and transistors, who are mostly off-the-shelf components,
the inductor is a more easily customizable component, where performance for an
inductor with a certain core design is dependent on e.g. number of windings thick-
ness of windings.[24] For this application and for the sake of the simulation model
it is chosen to use the same inductor technology as is used by Valeo Siemens to-
day, assuming that windings are chosen to achieve exactly the desired inductance.
The inductor is powder-core, toroid-shaped with copper wires, and reasonable pa-
rameters based on this technology are presented in table 3.7.[1] Saturation current
rating is not mentioned in the data sheet. The data for estimated power losses are
found in data sheets, and comparing it to table 3.7 it is clear that it does not exceed
the estimated losses of the inductor and rest of PFC.

53
54
Chapter 4
Drive and control

In a PFC, as in any other switched-mode converter, the control system and gate
drivers are essential to its operation; they govern the average current through - and
voltage across - the switches, controlling currents and voltages in the rest of the
converter.[24, ch. 28] Control-wise, a PFC has two objectives: It needs to control
the AC current to be sinusoidal and in phase with the AC voltage, and it needs to
control the average value of the DC-side voltage. In the following, the gate driver
logic and the control system will be developed for the ideal proposed bidirectional
totem-pole PFC converter, to build the simulation model and verify the basic op-
eration of this converter. The control system will be built using average current
mode control.[41, 42, 43] Current and voltage control loops will be analyzed sepa-
rately and designed with PI controllers and symmetrical optimum tuning.[44] The
MATLAB scripts used for tuning are shown in appendix F. The practical imple-
mentation of the gate drivers will be neglected for this analysis.

55
4.1 Gate drive logic

Gate drives are the bridge between the desired linear behaviour of the converter
and the highly nonlinear behaviour of the transistors. The gate drives converts
a linear control signal to switch the transistors on and off so that the switching-
period average currents and voltages are behaving as desired. The gate drive logic
for both switching legs implemented in Simulink is shown in figure 4.1. For the
explanation of the controller mechanisms the enable switches can be ignored, as
they are simply there to turn the gate signals on or off. The turn-on delay blocks
can also be ignored for the explanation of the gate drive logic, as they do not
affect the basic theory. They are there to provide a blanking time at the turn-on
of the switches, ensuring that the complementary transistor is properly turned off
before turning on the relevant transistor and hence preventing cross conduction
and possible malfunctioning of the transistors. [24, ch. 28-6-2]

4.1.1 Rectifier leg

Let us first look at the rectifier leg. The rectifier-leg switches change the DC-
voltage polarity seen by the inductor every mains half cycle according to the AC
mains voltage polarity. This ensures that the DC voltage is always of the same
polarity and higher magnitude than the AC voltage, and that the power flows in
the same direction in both half cycles. This is achieved by Comparator SR in
figure 4.1, comparing the measured AC voltage to ground, giving out high voltage
when vAC < 0 and zero when vAC > 0. As explained in sections 2.1 and 2.2, SR1 is
always conducting during negative half cycle and SR2 is always conducting during
the positive. That means the output gate signal of Comparator SR is equal to
the gate voltage of SR1 , vSR1 . In this application it is assumed that the MOSFET
reverse body diode will not be used, but rather that the active part of the MOSFET
is turned on when conducting. Thus, SR2 needs to be switched complementarily
to SR1 , meaning the gate signal needs to be the logical inverse of vSR1 . This is
accomplished by placing the logical NOT operator as shown in figure 4.1. The
gate signals will be distributed as following:

56
Figure 4.1: A screenshot of the PWM system implemented in Simulink.

57
 
0, vAC (t) > 0,
vSR1 (t) =
Vhigh , vAC (t) < 0,
 (4.1)
V , vAC (t) > 0.
high
vSR2 (t) =
0, vAC (t) < 0.

This is the same both in G2V and V2G, as one can see from figures 2.2 and 2.3.

4.1.2 Totem leg

The totem-leg switches are switched at high frequency with boost/buck control to
shape the boost inductor current. In this case two methods are relevant for control-
ling the gate voltage signal to the transistors: Hysteresis and PWM. Hystheresis
control is the faster control alternative, as it requires no computation of the duty
cycle of the switches, but simply switches on/off when the current reaches the
lower and higher ripple peak reference. However, for variation in reference sig-
nals, a varying switching frequency is achieved with hystheresis control. [40, ch.
2.3.1] This gives a great variation in the current ripple frequencies to be filtered
out by the DM filter, creating difficulties in DM filter design. Using PWM, on the
other hand, a constant switching frequency can be achieved in CCM, simplifying
the DM filter design. For that reason, PWM is the gate voltage control method of
choice for this application.

The pulse width modulator operates as the simple DC-DC pulse width modulator
in [24, ch. 7-2], consisting of Comparator ST comparing a strictly positive control
signal, duty cycle d, to a triangular reference signal vtri with amplitude 1, gener-
ating a gate signal vgate , as in figure 4.2. In G2V operation, this is just like in a
regular boost PFC controller; the gate signal is the gate voltage of the boost switch.
The difference in the totem-pole boost PFC is how this gate signal is handled. First
of all, the totem-leg switches are switched complementarily, where one switch acts
as the boost switch while the other imitates the boost diode, as shown in section
2.1. The GaN eHEMT does not contain a reverse body diode and no diode is con-
nected in anti-parallel (figure 3.2), meaning the complementary switch needs to be

58
 Figure 4.2: Illustration of the pulse width modulation used in this

operated actively. This is achieved with the NOT operator, as for the rectifier leg.

Moreover, unlike a regular boost PFC, which has a rectified boost inductor current,
because of the passive rectifier at the AC-side (figure B.1), the boost inductor of the
totem-pole PFC is connected to the AC-side, meaning the boost inductor current
needs to be shaped as a sinusoidal AC signal oscillating from negative to positive.
Still, the control signal is assumed to be the duty cycle d(t) of a regular boost PFC,
which is purely positive. This is compensated as explained in section 2.1, by, for
every other mains half cycle, interchanging which totem-leg switch is operating
as boost switch and which is imitating the diode. The effective duty cycle of the
gate signal of each of the switches throughout the mains cycle can be written as
follows:

59
 
1 − d(t), vAC (t) > 0,
dST 1 (t) =
d(t), vAC (t) < 0,
 (4.2)
d(t), vAC (t) > 0.
dST 2 (t) =
1 − d(t), vAC (t) < 0.

Acknowledging that for high switching frequencies fsw  fAC with gate voltage
amplitudes of Vhigh = 1 in figure 4.2, the duty cycles can be written as follows:

d(t) = vgate,avg (t) , dST 1 (t) = vST 1,avg (t) , dST 2 (t) = vST 2,avg , (4.3)

where vgate,avg , vST 1,avg and vST 2,avg are the floating switching-period averages of
vgate , vST 1 and vST 2 . Applying (4.3) to (4.2), it can be shown that the totem-leg
switches gate voltages can be written as follows:


1 − v (t), vAC (t) > 0,
gate
vST 1 (t) =
vgate (t), vAC (t) < 0,
 (4.4)
v (t), vAC (t) > 0.
gate
vST 2 (t) =
1 − vgate (t), vAC (t) < 0.

The gate voltages are logical signals of true or false, in this case 1 or 0. Thus,
it is clear that the negative-half-cycle gate signals can be achieved by logically
inverting the positive-half-cycle gate signals. To perform this logical inversion, a
handy way of rewriting the gate voltages during negative half cycle can be:

vST 1 (t) = vgate (t) = 1 − |vgate (t) − 1| , vAC (t) < 0 ,

(4.5)
vST 2 (t) = 1 − vgate (t) = |vgate (t) − 1| , vAC (t) < 0 .

The equation (4.5) puts the negative-half-cycle gate signals on the same form,

60
vST 1 = 1 − u and vST 2 = u, as the positive-half-cycle signals in (4.4). Now, all that
needs to be handled is u, which is either vgate or |vgate − 1|, depending on the mains
half cycle. Using (4.5) and recognizing from (4.1), with Vhigh = 1, that vSR1 is 0
for vAC > 0 and 1 for vAC < 0, a simple way of handling u and creating the desired
gate voltages in (4.4) can be the following:

vST 1 (t) = 1 − |vgate (t) − vSR1 (t)| ,

(4.6)
vST 2 (t) = |vgate (t) − vSR1 (t)| .

This is implemented in figure 4.1 with the forward connection from the rectifier-leg
system to the totem-leg system.

V2G

In V2G, the PFC operates as a buck converter from DC-link to grid, in stead of as a
boost converter from grid to DC-link. However, comparing the AC to DC voltage
ratios based on the duty cycle definitions of buck and boost operation, [24, ch. 7]


vAC (t) dbuck (t) for buck operation ,
= (4.7)
VDC 1 − dboost (t) for boost operation ,

it is clear that dbuck = 1 − dboost = 1 − d, i.e. that the boost and buck switching
are complementary to each other. Thus, since the figures 2.2 and 2.3 show that the
buck switch is always the complementary switch to the boost switch, the totem-leg
gate voltages during V2G are also controlled by (4.2) and (4.6). In other words,
the shape and phase of the gate voltages do not change during V2G

4.1.3 Waveforms

For verification of the gate drive operation a simulation is performed, with results
shown in figure 4.3. It shows the duty cycle d, the triangular voltage vtri and the
gate voltages VST 1 , VST 2 , VSR1 and VSR2 in G2V operation, which is the same for

61
 (a) One mains cycle (b) Zoomed

Figure 4.3: Duty cycle and gate drive signals over one mains cycle and zoomed in on a
few switching cycles.

V2G operation. The waveforms throughout one mains cycle in figure 4.3a and
over a few switching cycles in figure 4.3b show that the switches are operated
complementarily according to the control laws described above.

62
4.2 Control system

For the PFC control system, it is necessary with two control loops: the current
control loop and the voltage control loop, since the PFC is assigned to controlling
both the inductor current and th DC-link voltage. The control loops are developed
based on small signal modelling and quasi-steady-state approach, with the non-
linear transistor currents and voltages represented as linearized currents and volt-
ages around their switching-period average.[45, 42] In the current control loop the
switching-period average inductor current is controlled to be shaped sinusoidally
in phase with the mains voltage – or shifted 180 degrees in V2G, while the voltage
control regulates the average DC-link voltage to be equal to a defined DC value.
PI controllers are used in both the current and the voltage loop. The complete PFC
control system, as implemented in Simulink, is depicted in figure 4.4. It is shown
in the figure that the controllers take in measurements of the inductor AC current
iAC , the AC voltage vAC and the instantaneous DC-link voltage vDC , while the out-
put is the boost duty cycle d that is input in the PWM system. It is assumed that
all of the measured currents and voltages can in fact be measured, although the AC
voltage would have to be measured through a transformer, for isolation between the
control system and grid. [46] The following section will develop the current and
voltage controller equations, tune the PI controllers and discuss current and volt-
age measurement filter design, all with reference to the Simulink model in figure
4.4. For the tuning of current and voltage PI controllers, modulus and symmetrical
optimum will be used. It should also be noted that the converter could have been
made to operate with reactive power compensation with some modifications of the
control system to allow phase shifting of the current, but this is considered out of
scope for this analysis and left for further work.

63
 Figure 4.4: Current and Voltage control systems implemented in Simulink

64
 Figure 4.5: The fundamental-frequency equivalent totem-pole PFC

4.2.1 Control logic

As explained in section 4.1, the pulse width modulator is designed assuming a

control signal equal to the duty cycle of the boost converter in a regular boost PFC.
This choice simplifies the control system design, since the control system logic
can then be largely based on existing boost PFC control systems, which is a well-
developed field of research.[45] Some modifications need to be made: bidirec-
tional power flow is enabled through some small modifications and the measured
current and reference current need to be rectified; the inductor current in a regular
boost PFC is rectified, as opposed to the totem-pole PFC inductor current, which is
AC (section 2.3). The latter is implemented by multiplying both the inductor cur-
rent and the measured inductor current with the polarity of the current reference,
as shown in figure 4.4.

The implemented controller is based on the basic current mode boost PFC.[41]
This control technique is beneficial for this high-power application, because it al-
lows the desired CCM operation and constant switching frequency.[45] Normally
in average current mode control, a third current slope compensation loop will be
added, due to poles and zeros changing depending on the duty cycle.[43, 47] This
effect is neglected for this analysis, where the current controller and voltage con-
troller power stages will be analyzed separately, as will be shown in sections 4.2.2
and 4.2.3. The current mode control is implemented as shown in figure 4.4 and
[41], by multiplying the output of the outer voltage control loop, ictrl, with the
reference to the inner current control loop, while the current controller directly
controls the duty cycle.

An expression for the time-varying duty cycle d(t) can be derived using small-
signal modelling and the quasi-static approach, investigating the fundamental cur-

65
rents and voltages; the objective is shaping the fundamental, switching-period
average inductor current in phase with the AC voltage. It is common in small-
signal-modelling analysis of unidirectional PFCs to model the converter and load
as an emulated resistance, ensuring that the drawn power is resistive for maximum
power factor. [45, 42, 46] This approach is, however, not as intuitive in a bidirec-
tional PFC, where the converter seen from the grid will work as a power source
during V2G. Although one could create a fictious negative resistance, another, per-
haps more intuitive solution is modelling the totem-pole converter as a VDC -driven
voltage source. Looking only at the fundamental components, and exploiting that
the boost inductor in a totem-pole PFC in on the AC side, the PFC can be equiv-
alated to the simple two-voltage-source system shown in figure 4.5, based in figure
2.1. Assuming perfect operation and unity power factor, i.e. the AC voltage and
current both having zero phase angle, a phasor form equation can be obtained:

VAC −VAB,1 e jθAB,1

IAC,1 = , where ZL e jθL = RL + jωL . (4.8)
ZL e jθL

The phasor form is useful in this case, because for the sake of the current con-
troller we are only interested in the phase and amplitude of the inductor current.
Investigating figure 2.1, it is clear that the gate voltage vAB will take the following
values:




vDC (t), ST 1 on, vAC (t) > 0 ,

0,

ST 2 on, vAC (t) > 0 ,
vAB (t) = (4.9)


0, ST 1 on, vAC (t) < 0 ,

−vDC (t), ST 2 on, vAC (t) < 0 .



From (4.9) it can be found, based on the duty cycle analysis in section 4.1.2, that
the fundamental gate voltage vAB,1 (t) can be written as follows:


d (t) · v (t) = (1 − d(t)) · v (t) , vAC > 0 ,
ST 1 DC DC
vAB,1 (t) = (4.10)
dST 2 (t) · (−vDC (t)) = (1 − d(t)) · (−vDC (t)) , vAC < 0 .

66
Based on (4.10), a new, equivalent duty cycle function dST,eq (t) can be defined:


d (t) = 1 − d(t) , vAC > 0 ,
ST 1
dST,eq (t) = (4.11)
−dST 2 (t) = d(t) − 1 , vAC < 0 ,

which implemented in (4.10) gives:

vAB,1 (t) = dST,eq (t) · vDC (t) . (4.12)

During PFC operation, the DC-voltage ripple will usually be much smaller than
the average value (in this case 20V versus 340V), which means it can be approxi-
mated as constantly equal to the average DC voltage when considering the current
control. Using that, (4.12) can be approximated as

vAB,1 (t) ≈ VDC · dST,eq (t) = VDC · dˆST,eq sin (ωt + θAB,1 ) . (4.13)

Finally, a expression can be derived for the duty cycle, based on (4.11) and (4.13):

V̂AB,1
d(t) = 1 − |dST,eq (t)| = 1 − | sin (ωt + θAB,1 )| (4.14)
VDC

Comparing (4.14) to (4.8), a key take-away is that since the AC voltage and the
boost inductor impedance are uncontrollable, the inductor fundamental current and
thus power is controlled by the amplitude and phase of the duty cycle. Since ZL is
small, only small variations in duty cycle phase and amplitude will be necessary.
The shape or polarity of the fundamental duty cycle does not change in V2G oper-
ation compared to G2V operation; it is always given by 4.14, as is shown in figure
4.6.

In the implemented current loop in figure 4.4, this is ensured by the logical inverter
on the PI controller output, which is enabled during V2G. When V2G is activated,
the constant source called V2G is set to 1, inverting the polarity of the reference
current and the measured inductor current. This however also inverts the current
error signal entering the PI controller. To fix this, the mentioned logical inverter is

67
 (a) G2V (b) V2G

Figure 4.6: Some selected waveforms over one mains cycle in G2V and V2G operation.

enabled during V2G, correcting the waveform of the output duty cycle so that it is
unchanged compared to G2V.

The inversion of the input signals to maintain the duty cycle signal shown in fig-
ure 4.6 is an advantage, as will be explained now. In the opposite case, if the
reference current and measured inductor current were not inverted, the duty cycle
signal would change shape every half cycle. However, since the duty cycle has
to take a value between 1 and 0, the duty cycle would have to alternate between
1 − vAB,1 (t)/VDC during positive mains half cycle and −vAB,1 (t)/VDC during the
negative half cycle. That requires the duty cycle to drop instantaneously from 1
to 0 in the transition from positive to negative half cycle and leap instantaneously
from 0 to 1 in the transition from negative to positive half cycle. Following this
duty cycle path requires a nearly infinitely fast current controller, which is not pos-
sible to implement, first of all due to a restriction saying that the bandwidth of
the current controller should be at least half a decade lower than the switching fre-
quency, which is at 90kHz.[40] In comparison, the duty cycle achieved through the
proposed control logic (figure 4.6) contains no sudden leaps or drops, improving
stability considerably.

Having established in figure 4.6 that the control system is functioning, it is due
to direct some critique towards the implemented solution. First of all, the con-

68
trol circuitry of the average current mode PFC controller is quite complex, with
a multiplied voltage loop and current loop. This issue could have been addressed
by implementing e.g. linear peak current mode control or other techniques for es-
timating the AC voltage, so that the voltage measurement becomes unnecessary.
[42, 48] On the other hand, the control system could be implemented digitally, in
which case the control circuitry would not be as complex. Another issue is the
necessity of measuring the AC voltage through a voltage transformer, implying a
risk of low energy density. This issue could also be addressed through the men-
tioned AC voltage estimation techniques, not needing to measure the voltage. In
any case, the control structure provides a reference when designing new, improved
control systems for bidirectional PFC converters, using e.g. the techniques men-
tioned above.

69
 Figure 4.7: The inner current control loop

4.2.2 Current control loop

Of the two controllers, the current control loop needs to be the fastest, much due
to the reference signal oscillating sinusoidally with 50Hz. In general control the-
ory, the inner loop needs to be faster than the outer control loop to be able to
provide proper response to the reference signal from the outer loop, meaning that
the current loop needs to be the inner loop. Thus the current control loop will be
developed first.

The general Laplace plane current control loop is chosen as shown in figure 4.7,
where Hpi,i (s), HPW M (s), HPW R (s) and H f i,i (s) represent the transfer functions of
the PI regulator, PWM, power stage and current measurement filter, respectively.
For the PI regulator, the general transfer function is as follows:

!
Ti,i · s + 1
Hpi,i = Kp,i , (4.15)
Ti,i · s

where the Kp,i is the proportional gain and Ti,i is the integrator time constant. This
will be tuned later and is left for now. Moving to the PWM, the transfer function
is dependent on the modulation technique, but is usually modelled as a switching-
frequency dependent time delay. [40, ch. 3.2.5] The delay is due to the gate
voltage pulse widths not being able to update continually within one switching
period. In the PWM system described in section 4.1, natural-sampled triangular
PWM is used, as shown in figure 4.2, which, according to [40, ch. 3.2.5], gives a
time delay Tdelay,PW M = Tsw /3 with a corresponding transfer function:

1 1
HPW M (s) = = 1
. (4.16)
1 + Tdelay,PW M · s 1+ 3 Tsw · s

70
So, to the power stage, which for the current control is approximated as solely the
inductor, since the variable to be controlled is the fundamental-harmonic current
through the inductor. Referring to figure 2.1, the inductor current IAC (s) can be
expressed in Laplace transform as follows:

vAC (s) − vab (s)

iAC (s) = , (4.17)
RL + L · s

where RL is the inductor equivalent resistance. The control variable is the bridge
gate voltage VAB (s), while VAC (s) can be seen as a disturbance from the control
point of view. Thus, from (4.17), the power-stage transfer function can be written

vAC (s) 1 1 1
HPW R (s) = = = . (4.18)
vAB (s) RL + L · s RL 1 + RL · s
L

As for the current measurement filter, the purpose of this is to suppress switching-
frequency and higher-frequency current noise going into the controller, potentially
making the controller generate more harmonics. [40, ch. 3.4] Thus, a simple first-
order low-pass filter is evaluated to be sufficient for this application, with transfer
function:

1
H f i,i (s) = , (4.19)
1 + T f i,i · s

where T f i,i is the current measurement filter time constant. Having established
these transfer functions, the open-loop current controller transfer function becomes

Hol,i (s) = Hpi,i · HPW M (s) · HPW R (s) · H f i,i (s) ,

Kp,i 1 + Ti,i · s (4.20)
= · .
Ti,i RL s · (1 + TPW M · s)(1 + RL · s)(1 + T f i,i · s)
L

To simplify this transfer function, it can be utilized that TL = L/RL is considerably

larger than Ti,i and T f i,i , the two smaller time constant, as an approximation, can
be merged into one time constant Tsum,i = Ti,i + T f i,i in a first-order filter.[40, ch. 3]
The open-loop transfer function (4.20) can be rewritten as

71
 Kp,i 1 + Ti,i · s
Hol,i (s) = · . (4.21)
Ti,i RL s · (1 + Tsum,i · s)(1 + RL · s)
L

Simplifying the system from a fourth-order to a third-order system like this greatly
facilitates the controller tuning that follows, and is a great advantage as such.

PI tuning: Modulus optimum

Now to the PI controller tuning, where expressions for the gain and time constant
of the PI controller must be developed. As stated in the previous, the power stage
time constant is TPW R = L/RL  Tsum . This opens for use of the controller tun-
ing technique called Modulus optimum, which involves cancelling out the slowest
pole with the dominant time constant, if present, by setting Ti,i equal to the dom-
inant time constant. [40] By doing that, the control loop is effectively reduced
to a simpler second-order system. Moreover, since the less dominant time con-
stants correspond to higher cutoff frequencies, a higher crossover frequency can
be achieved for the whole current loop, while maintaining a sufficient phase and
gain margin. [49]

However, an issue with the modulus optimum for this application appears when
the time constant is calculated based on the inductor parameters in section 3.3.
The integrator time constant is chosen:

L 245µH
Ti,i = = = 0.0245s . (4.22)
RL 10mΩ

Taking into account that the reference signal will be a rectified 50Hz sine (figure
4.4), effectively having a frequency of 100Hz, the time period of this signal will
effectively be Tre f = 0.01s. That means the reference signal is faster than the in-
tegrator time constant of the PI controller, and the controller will have difficulties
following the reference signal. Section D.1 in the appendix shows a full derivation
of the modulus optimum tuning parameters along with simulation results confirm-
ing that the controller is not able to follow the reference. Thus, another PI con-
troller tuning technique is attempted, called Symmetrical optimum, which gives
greater freedom in choosing integrator time constant.

72
PI tuning: Symmetrical optimum

The Symmetrical optimum tuning technique, described in [44], involves choosing

the integrator time constant to lift the phase around the crossover frequency of the
control loop, that way increasing the phase margin and gain margin to increase sys-
tem stability. [49] For that reason, poles with large, dominant time constants that
have a cutoff frequency themselves that is far away from the crossover frequency
of the whole control loop can be regarded as free integrators. [44] Applying that to
the current controller open-loop transfer function in (4.21), a new, approximated
transfer function is developed:

Kp,i 1 + Ti,i · s
Hol,i (s) = · . (4.23)
Ti,i L s2 · (1 + Tsum,i · s)

The resulting closed-loop transfer function is:

1 + Ti,i · s
Hcl,i (s) = LTi,i LTi,i Tsum,i . (4.24)
1 + Ti,i · s + K p,i · s2 + K p,i · s3

From that, the PI controller parameters can be chosen based on the following Sym-
metric optimum design equations: [40, ch. 3.2.4]

L 1
Ti,i = βi · Tsum,i , Kp,i = p , ωc,i = p , (4.25)
βi Tsum,i βi Tsum,i

where ωc,i is the crossover frequency and βi is defined from that the phase of
the transfer function is lifted from 1/(βi Tsum,i ) to Tsum,i . The current control loop
needs to be at least half a decade slower than the switching frequency to ensure
that the switches are able to respond to the control signals. Thus, taking into ac-
count that the reference signal is varying with a frequency of 100Hz, the controller
parameters in (4.25) are chosen from a crossover frequency as close as possible to
10−0.5 ∗ ωsw while still keeping a βi within reasonable values.

In order to determine the controller parameters, the current measurement filter

time constant, T f i,i , needs to be determined first. While a filter suppresses certain
frequencies, it is essentially also a delay. Therefore the filter time constant is cho-

73
sen to limit the ripple of the duty cycle, while at the same time maintaining a fast
response by not choosing the time constant too big. A certain amount of switching-
frequency current ripple is inevitable in a PFC, since the boost inductor can not be
chosen infinitely large, and so keeping the ripple of the current measurement at a
low level is important to avoid the controller generating more harmonics. A typical
design rule is keeping the duty cycle ripple amplitude in the range of 0.04 to 0.08,
where a bigger ripple implies a faster response. [40, ch. 3.2.4]

Current filter design using Modulus optimum is performed in section D.1 in the ap-
pendix, and the filter time constant can be found in a similar way with Symmetrical
optimum. Substituting into (D.7) the expression for Kp,i in (4.25), an expression
for the for the duty cycle ripple amplitude is achieved as follows:

L 1 1
dˆripple (ωripple ) = p ·p · ∆IL (ωripple ) . (4.26)
βi Tsum,i 1 + (ωripple T f i,i )2 2

Substituting βi in (4.26) with the expression for ωc,i in (4.25), another expression
is obtained:

1 1
dˆripple (ωripple ) = ωc,i L · p · ∆IL (ωripple ) . (4.27)
1 + (ωripple T f i,i )2 2

In (4.27), there is now two free variables governing the duty cycle ripple: ωc,i and
T f i,i . As mentioned, we wish to choose the crossover frequency as close as possible
to 10−0.5 · ωsw , while keeping βi within reasonable limits. Maximum crossover
frequency is:

ωc,i ≤ 10−0.5 · 2π · 90kHz = 178823rad/s

A reasonable βi is defined in [40] to range from 1 to 25. Choosing a crossover

frequency
ωc = 10−0.8 · ωs w = 89624rad/s ,

(4.27) is solved graphically at the switching frequency, ωripple = ωsw , in figure 4.8.
Prioritizing fast controller response over low control signal ripple, the duty cycle

74
 Figure 4.8: Graphical solution of (4.27) to find T f i,i

ripple amplitude is chosen at dˆripple = 0.08, giving

T f i,i = 2.7 · 10−6 s .

From (4.25) this gives βi = 3.04, which is within the reasonable limits of 1 to 25,
verifying the chosen crossover frequency. Implementing the values for ωc , T f i,i
and βi into (4.25), the controller parameters are found to be

Kp,i = 1.4644 , Ti,i = 19.44 · 10−6 s .

Comparing to the integrator time constant using Modulus optimum, this Ti,i is
more than 4 decades lower, and thus also much lower than the reference signal
time period at 0.01s, which should lead to a better system response.

Simulations

To verify the controller design, simulations are performed with no voltage con-
troller connected, and the current controller tuned with the Symmetrical optimum
parameters described above. The results are shown in figure 4.9, where iref is
the per unit rectified current reference, imeas is the per unit rectified measured
indutcor current, ierr is ire f − imeas and d is the boost-switch duty cycle control

75
 Figure 4.9: Simulation of current controller waveforms during one mains period.

76
signal. These results show that the inductor current following the reference almost
perfectly, and the current error consists mostly of the switching-frequency ripple.
Looking closely, however, there is a small 100Hz error. This is likely due to some
delay in the PWM stage and the measurement filter, and could be compensated by
implementing e.g. a phase-locked loop (PLL), measuring and controlling the phase
of the current. [50] The PLL will, however, not be pursued further in this master’s
thesis, much due to the good phase response of the current loop with symmetrical
optimum, and is left for further work.

77
 Figure 4.10: A block diagram of the voltage control loop

4.2.3 Voltage control loop

The voltage controller governs the average DC-link voltage to be held at the spec-
ified values (section 3.1). It is the outer, slower control loop; the desired average
DC-voltage is set by the controller based on the grid AC voltage, and since any
permanent changes in socket voltage will be small and slow for a strong grid, the
control does not need to be fast.[11] Still, in the event of a sudden, larger drop in
the voltage seen from the grid, e.g. due to a larger nearby load disconnecting, the
slow control ensures that the DC-link voltage does not drop below its minimum
value. In the opposite event, if a sudden larger voltage leap occurs on the AC-side,
e.g. due to a lightning strike, this is solved by a surge diode protection, shorting the
grid voltage to the DC-link capacitor when the grid voltage is higher than the DC-
link voltage.[51] This reduces the voltage leap on the AC side and, if the voltage
change is permanent, helps in charging the DC-link capacitor to the new, higher
average voltage level.

The voltage control loop is modelled as shown in figure 4.10. As in the current
loop, the PI controller can be modelled as follows:

!
Ti,v · s + 1
Hpi,v = Kp,v . (4.28)
Ti,v · s

The voltage measurement filter is there to filter out the 100Hz DC voltage ripple,
which otherwise would generate harmonics in the current loop. Since the voltage
loop is not required to be particularly fast, a simple low-pass filter is chosen here,
as in the current loop, with the following transfer function:

78
 1
H f i,v (s) = . (4.29)
1 + T f i,i · s

Now to the equivalent current loop transfer function Heq,i (s). To simplify the
derivation of controller parameters, it is useful to create an approximate equivalent
first-order transfer function to the current controller closed-loop transfer function.
Assuming that the approximation performed on the second-order voltage-source
converter current loop transfer function in [52] is valid for the third order system
in (4.24), the current controller can be approximated as a simple first-order delay
Teq,i = 2 · Tsum,i . The transfer function becomes:

1 1
Heq,i (s) = = , (4.30)
1 + Teq,i · s 1 + 2 · Tsum,i · s

where Tsum,i is as before: Tsum,i = TPW M + T f i,i .

At last, the voltage controller power stage is the DC-link capacitor. The DC-link
voltage vDC is governed by the DC-link capacitor current iC , which is equal to
iC = iDC − iDC−DC , by iC (t) = C · dvDC /dt. The ESR is negligible in the DC-link
capacitor, thus it can be modelled as a pure capacitance. Using that, the power
stage transfer function can be given as the Laplace form of the capacitor equation:

vDC (s) 1
HPW R,v (s) = = . (4.31)
iC (s) C·s

Looking at figure 2.1, it is evident that the only current that we can control is iDC ;
iDC−DC can be seen as a disturbance and thus be disregarded for the PI controller
design later. Combining (4.28)-(4.31) with figure 4.10, the voltage controller open-
loop transfer function becomes:

Hol,v (s) = Hpi,v · Heq,i (s) · HPW R,v (s) · H f i,v (s) ,
Kp,v 1 + Ti,i · s (4.32)
= · .
Ti,vC s2 · (1 + 2 · Tsum,i · s)(1 + T f i,v · s)

As with the current controller, the two minor time constants can be merged into

79
one as Tsum,v = 2 · Tsum,i + T f i,v , giving new open-loop transfer function:

Kp,v 1 + Ti,i · s
Hol,v (s) = · 2 . (4.33)
Ti,vC s · (1 + Tsum,v · s)

The PI parameters, Kp,v and Ti,v , as well as the filter time constant, T f i,v , are un-
known and need to be tuned. This will be done using the Symmetrical optimum,
as explained in the following:

PI tuning: Symmetrical optimum

As shown in (4.33), there is a double free integrator, which by cancelling out (1 +

Tsum,v · s) by setting Ti,v = Tsum,v using Modulus optimum would result in a phase
of 180◦ , and the system would be on the limit of stability.[49] Thus, Symmetrical
optimum is a better choice for the voltage control loop. The control equations
become, similarly as in (4.25):

L 1
Ti,v = βv · Tsum,v , Kp,v = p , ωc,v = p , (4.34)
βv Tsum,v βv Tsum,v

In this case, the crossover frequency should be chosen at least half a decade slower
than the current loop, i.e.: [40]

ωc,v ≤ 10−0.5 · ωc,i . (4.35)

Moreover, the voltage filter can be designed using the same method as for the
current measurement filter in (4.27), this time with equation:

1 1
Iˆctrl,ripple (ωripple ) = ωc,vC · p · ∆vC (ωripple ) , (4.36)
1 + (ωripple T f i,v )2 2

where Iˆctrl,ripple is the peak ripple of the output control current from the PI con-
troller. As opposed to the current controller, the objective of the voltage mea-
surement filter is not to enable a fast response with high crossover frequency, but
rather minimizing the 100Hz ictrl,ripple , to minimize harmonics generated in the

80
 Figure 4.11: Grapical solution to (4.36), with ωc = 2π · 500rad/s.

current controller. At the same time, choosing the crossover frequency too low
will result in the controller not being able to respond to changes in reference DC
voltage. Solving (4.36) graphically for various ωc,v giving acceptable βv , follow-
ing the standard design rule described earlier, with control signal ripple ranging
from 0.04 to 0.08, it is found through simulations that this ripple range generates
some harmonics in the DC voltage and gives poorer stability performance. This
generation of DC-voltage harmonics is likely due to the low frequency of the con-
trol signal, as the faster current loop is not able to dampen this ripple. It is chosen
to keep Iˆctrl,ripple at approximately 0.01. Choosing ωc = 2π · 500rad/s, the graphi-
cal solution to (4.36) is shown in figure 4.11. The figure shows that Iˆctrl,ripple never
exceeds ∼ 0.01. Thus, Ti,i can be chosen based on (4.34) to give an acceptable βv ,
which is between 1 and 25, as mentioned earlier. The filter time constant is chosen
as follows:

Ti,v = 100µs ,

giving βv = 7.96, which is acceptable according to the abovementioned restric-

tions. Inserting these values in (4.34), the controller parameters become:

81
 Figure 4.12: Voltage controller step response to a 10V leap in voltage reference.

Ti,v = 8.98 · 10−4 s, Kp,v = 0.3763, ωc,v = 2π · 500rad/s . (4.37)

Simulations

A simulation of the DC voltage controller and its response to a 10V leap in refer-
ence voltage is shown in figure 4.12, where the measurements are refferred to the
simulink model in figure 4.4; vmeas is the per unit output of the DC-link voltage
measurement filter, vavg is the floating-100Hz-cycle average of vmeas, vref is the
DC-link voltage reference, verr is vre f −vmeas and ictrl is the control signal to the
current loop. The simulations show that the voltage is able to stabilize at the new

82
reference within ∼ 0.2s, or roughly 20 100Hz cycles. Moreover, there is a signifi-
cant overshoot in the voltage response. However, the leap in DC voltage reference
might be caused by a leap in AC voltage amplitude, in which case an overshoot
is better than a slower response with no overshoot, since it avoids the AC voltage
amplitude being bigger than the DC voltage. This would disturb the boost oper-
ation until the AC voltage drops or the DC-link capacitor is charged through the
surge diode and the necessary balance vDC > vAC is re-achieved. A big reason for
the slow response is the size of capacitance, limiting the possible dvDC /dt slope,
but another is probably the voltage measurement filter. A faster response could
likely have been achieved using a higher-order low-pass filter or a band-stop filter,
or digital filters such as e.g. a digital low pass filter. [53] All of these enable more
precise filtering of the ripple frequency, while passing through more of the other
frequencies, giving faster feedback in the loop. Other smart filtering techniques
could also have been used, such as the voltage measurement filter applied to the
simple PFC in [54], where the ripple is estimated based on current and average
voltage, and then subtracted from the measured signal, leaving just the average
voltage. Still, while the more advanced filter variants might give a faster and more
precise response, figure 4.9 shows that stability is achieved using a low-pass filter
with a good response. Supplementary DC-link voltage control from the DC-DC
converter will normally also be applied, improving the stability even more. [1]

83
84
Chapter 5
System-level simulations

To verify the complete proposed converter, some simulations are performed on

a system level, for maximum-power G2V and V2G operation at two AC voltage
levels: 230Vrms and 120Vrms. Pictures of the complete system implemented in
Simulink can be found in appendix E, except the gate drive logic and control sys-
tem, who are depicted in figures 4.1 and 4.4. Components are implemented with
the values computed in sections 3 and 4. There are however no GaN eHEMT mod-
els in MATLAB, so thiese are implemented as MOSFETs with no reverse recovery
charge or forward voltage in the body diode, and with the same on-state resis-
tance. The MOSFET model used, from the Simscape Power Electronics library in
Simulink, does not present any possibility of including the parasitic capacitances,
and so the gate charge is assumed infinitely small. Another modification is that
during V2G the DC-link capacitor is exchanged for a DC voltage source. This is
done to overcome that no DC-DC converter is connected at the DC-side, meaning
a power source is necessary to deliver power to the grid. Due to the low ripple
of the DC-link voltage at < 20Vp2p, this is approximated here as a DC voltage
source equal to the average DC-link voltage. The simulations are performed with
a discrete solver with constant step size 5 · 10−8 s.

Results of the simulations at 230Vrms G2V and V2G are shown in figures 5.1 and
5.2, respectively. Similar results are found at 120Vrms, and so these simulation
results are attached in appendix G. The results at both voltage levels show that

85
the bidirectional totem-pole PFC is operating properly in both operation modes,
with the current following the voltage in G2V and inverting in V2G, while the
100Hz DC voltage ripple and the switching-frequency current ripple within the
limits defined in table 1.2. The THD of the AC current is computed in Simulink to
be

T HDi = 0.05 ,

and the power angle, i.e. the phase angle of the fundamental AC current is com-
puted as

φi = 2.86◦ .

That gives power factor: [24, ch. 3-2-4]

1
pf = q · cos(φi ) = 0.998 .
1 + T HD2i

This power factor will be further improved by the implementation of a filter on

the AC-side decreasing the THD of the AC current drawn from the grid. Then the
OBC can comply also with the V2G THD restriction described in table 1.1.

86
Figure 5.1: System-level simulation results at 230Vrms G2V operation.

87
 Figure 5.2: System-level simulation results at 230Vrms V2G operation.

88
Chapter 6
Feasibility of the bidirectional
totem-pole PFC

Although the simulations showed that the proposed model is operation properly,
the model is a result of some approximations and simplifications who need to be
taken into account when evaluating the validity of the results and feasibility of
the bidirectional totem-pole PFC. Moreover, the performance of the PFC needs
to be evaluated in a bigger context, comparing it to the existing solutions on the
market. In the following, the feasibility of the proposed bidirectional totem-pole
PFC will be discussed, in light of the shortcomings of the simulation model and
how the performance of the totem-pole PFC compares with existing unidirectional
PFC solutions.

6.1 Model shortcomings

The simulation model developed and tested in the previous chapters is, as men-
tioned, made to derive and demonstrate the fundamental operation of a bidirec-
tional totem-pole PFC. Thus, to limit the scope of work, some effects have been
neglected which might have an effect on the performance of a potential practical
implementation. For one, no parasitic inductances or capacitances, which would
inevitably be present in any PCB embodiment of this bidirectional totem-pole PFC,

89
have been included. Though these are mostly too small to affect the fundamental
waveforms of voltages and currents, e.g. parasitic stray inductances can cause
overvoltages over the transistors during switching, when they experience a rapidly
decreasing current, inducing a negative voltage over the inductance.[24, ch. 27-6]

Another point is that the simulations have not been made with proper GaN eHEMT
simulation models, due to the lack of such a model in Simulink. In stead, they have
been approximated with MOSFETs with no reverse recovery or forward voltage
in the diodes, and negligible gate charge. With the infinitely small gate charges,
the switching transients of the GaN eHEMTs are not included in the simulations,
allowing infinitely fast switching, which is not real. If these transients were in-
cluded, they would e.g. lead to some small delays in the system, which could
potentially affect the stability of the control system.

Moreover, the practical implementation of the gate drives have not been discussed.
GaN eHEMTs impose special requirements in the gate drives, since they require
a quite large negative off-state gate voltage to avoid unwanted turn-on, as shown
in table 3.3. Besides the fact the gate drive circuit imposes a delay itself, a more
complex gate drive circuit might increase that delay, also possibly affecting the
stability of the controllers.

Furthermore, a parasitic effect which has been proven in regular totem-pole PFCs
and has been disregarded here, are current spikes that are discovered to frequently
occur at the zero-crossing.[55] These are found to be caused by stored minority
charges in the slow rectifier diodes, leading the diodes to be forward biased as the
AC voltage switches polarity, creating a very big voltage over the inductor, again
inducing a big current. Such an issue could be present in the body diodes of the
rectifier-leg MOSFETs during G2V operation, when they are forward-biased.

Effects such as these and possible other problems related to parasitic effects will
have to be tested in a practical prototype, in order to fully validate the bidirectional
totem-pole PFC for use in a bidirectional OBC.

90
6.2 Loss comparison to a regular boost PFC

Setting aside the bidirectional conduction ability, which is now proven in the bidi-
rectional totem-pole PFC, the proposed solution should be compared to a conven-
tional boost PFC with respect to performance. If a bidirectional OBC is to be
implemented, it should be able to compete with existing unidirectional PFC solu-
tions, as the primary objective of the bidirectional OBC is still to charge the EV
battery.

To evaluate the efficiency of the proposed bidirectional totem-pole PFC, it is rel-

evant comparing the losses to a regular boost PFC. From the analysis so far it is
found that the losses in the DC-link capacitor are insignificant, while rectifying
the inductor current does not change the RMS and peak currents of the inductor
compared to those found in section 2.3, meaning the losses should be equal. Thus,
the key difference in losses exist in the semiconductor devices. First of all, the
regular boost has more semiconductors in the conduction path (3) than the totem-
pole (2), thus increasing the losses. Another aspect is that diodes and MOSFETs
and HEMTs have different conduction loss characteristics; the conduction losses
of MOSFETs and HEMTs have a dependency on IS,RMS 2 , as shown in (2.22), while
the conduction losses of diodes are dependent on ID,avg to the power of one, as-
suming negligible diode resistance. The conduction losses of a diode are given as
follows: [24, ch. 20-4]

2
Pcond,diode = V f ,diode · Idiode,avg + Ron,diode · Idiode,RMS (6.1)

where V f ,diode is the diode forward voltage and Ron,diode is the diode on-state resis-
tance. The on-state resistance of a diode is usually much smaller than the on-state
resistance of a MOSFET or HEMT. As a consequence, the diode often has lower
conduction losses than the MOSFET and HEMT at high power levels, while it may
have bigger conduction losses at lower power levels, due to the forward voltage.

In the regular boost PFC this can be utilized by another difference between the
two topologies, which becomes evident through the transistor current analysis in
section 2.4. It is shown in (2.21) and (2.14) that the RMS current through the
switches are dependent only on the AC RMS current. This is due to the symmetry
in the totem-pole PFC, where the current has to always pass through either one

91
of the switches in each leg at all times, and the roles are interchanged every half
cycle. This means that to minimize the transistor losses of the bidirectional totem-
pole PFC it is beneficial to choose the DC-link voltage as low as possible, as is
done in section 3.1.1. For a regular boost PFC, on the other hand, the roles of
the transistor and the freewheeling diode do not change every half cycle, meaning
the average and RMS currents through each of these are dependent on the duty
cycle, which again is dependent on the DC-link voltage. It can be shown inserting
dboost = 1 − V̂AC/VDC into 2.31 that the RMS current through the boost switch in a
conventional boost PFC can be expressed as

s
2 − 8 V̂AC 2
Iboost = IAC I cos(φAB ) . (6.2)
3π VDC AC

The RMS current through the freewheeling diode, Idiode,RMS is equal to the RMS
current through the totem-leg complementary switch, described in (2.33), while
the average current through the diode, Idiode,avg , is equal to the average DC-load
current, which can be expressed as follows:

PDC
Idiode,avg = . (6.3)
VDC

The equations (2.33), (6.2) and (6.3) show that the RMS and average currents
through the semiconductors in the conventional boost PFC are dependent on the
DC-link voltage; the boost transistor current increases with increased DC voltage,
while the freewheeling current decreases with increasing DC-voltage. Since it was
established earlier that the diode performs better at high power and the transistor
performs better at low power, it will be beneficial during high power power to
maximize Idiode,avg and minimize Iboost by setting VDC at its lowest permitted level.
In this application this is defined to be 340V. Oppositely, it will be optimal setting
high VDC during low power.

In the diode rectifier bridge, there will always be two diodes conducting, and so the
losses Pcond,bridge can be found from (6.1) with V f ,bridge = 2 · V f ,diode , Ron,bridge =
2 · Ron,diode , Ibridge,avg = IAC,avg (from (2.25)) and Ibridge,RMS = IAC .

92
6.2.1 Comparison at worst-case operating temperature

Since it is assumed in the proposed design that the charger will most often be
operating at maximum power, a quantitative comparison of the conduction losses
in the two topologies is performed at maximum power, at worst-case tempera-
ture and with the same GaN HEMT GS66516 as before operating as boost switch
in the conventional boost PFC. The operating temperature of the diode bridge
is set at Tcase,bridge = 100◦ C to avoid thermal runaway.[56] As there exist fast-
switching diodes, such as Silicon Carbide (SiC) Schottky Barrier diodes, and the
DC-link voltage is equal, the switching losses are assumed to be approximately
equal at approximately the same switching frequency. Assuming Diodes Incorpo-
rated GBJ2506 used for the bridge and ROHM Semiconductors SiC Schottky Bar-
rier diode SCS220AE used for the freewheeling diode, we have V f ,bridge = 1.05V,
Ron,bridge ≈ 0, V f ,diode = 1.50V and Ron,diode ≈ 0. Inserting these values along
with VAC = 230Vrms, VDC,avg = 340 and IAC = 16Arms, the worst-case conduc-
tion losses of the conventional boost PFC is found as follows based on (2.22),
(6.1),(6.2), (6.3) and (2.33):

Pcond,conv,worst−case = Pcond,bridge + Pcond,diode + Pcond,boost = 34.58W (6.4)

In comparison, the total conduction loss of the proposed totem-pole PFC is equal
to the conduction losses of all the transistors, calculated from the worst-case losses
found in section 3.2, with GS66516 in the totem-leg and IPW60R045CPA in the
rectifier-leg:

Pcond,totem,worst−case = 2 · Pcond,ST + 2 · Pcond,SR = 44.80W . (6.5)

The results show that the totem-pole PFC imposes a substantial increase in conduc-
tion losses of 30% at the worst-case case temperature and high power, despite the
decreased number of semiconductors. This is due to the different conduction loss
current dependency of the MOSFETs/eHEMTs and the diodes explained above.
A solution to this problem could be to exchange the rectifier-leg MOSFETs for
IGBTs connected in anti-parallel with low-forward-voltage diodes. Like diodes,
IGBTs are minority carrier devices, with a forward voltage the dominant cause of

93
conduction losses.[24, ch. 25] Thus, the conduction losses current dependency of
the IGBT is going to be equal to that of the diode, meaning the totem-pole con-
duction losses could be reduced by introducing IGBTs anti-paralleled with diodes.
That would however imply two more semiconductors in the design, which would
require e.g. a larger heat sink design. One could of course also substitute the same
low-resistance GaN eHEMTs used in the totem-leg, but GaN eHEMTs are more
expensive than IGBTs and diodes, which are more developed technologies, and so
it would likely increase the total cost of the converter.

6.2.2 Comparison at normal operating conditions

Another reason for the higher conduction losses of the totem-pole PFC at worst-
case temperature is that the MOSFET and eHEMT on-state resistance has a quite
big positive temperature dependency, while the the forward voltage of the diodes
has a much smaller temperature dependency, as is evident in the data sheets of the
chosen semiconductors of this analysis. In other words, the conduction losses of
the MOSFETs and eHEMTs increase at worst-case temperature, while the conduc-
tion losses of the diodes do not change as much. In normal operation, the operating
temperature will be lower than the worst-case temperature, and thus the losses in
normal operation will obviously be different. The operating case temperature will
typically be below 80◦ C, depending on the cooling technique, which would in-
duce much smaller losses in the GaN eHEMTs and MOSFETs than at worst-case
Tcase = 150◦ C.

A new computation is performed at Tcase = 80◦ C, with corresponding on-state

resistances and forward voltages from the data sheets: RDS,on,HEMT = 37.5mΩ,
RDS,on,MOSFET = 60mΩ, V f ,bridge = 1.05V and V f ,diode = 1.40V. Substituting the
new resistances into the calculations in section 3.2 and using (6.4) and (6.5) as
before, the conduction losses during normal operation is computed to be:

Pcond,conv,normal = 33.16W, Pcond,totem,normal = 24.96W .

These calculations show that during normal operation with Tcase = 80◦ C, the bidi-
rectional totem-pole PFC decreases the conduction losses by 25% compared to a
conventional boost PFC. Moreover, the conduction losses of the totem-pole should

94
decrease more for lower load, due to the I 2 dependency, than the conventional PFC.
Thus, although the switching losses are not taken into account and the loss com-
putations might not be completely precise due to inaccuracies in the data sheets,
these computations indicate that the proposed bidirectional totem-pole imposes an
improvement in efficiency compared to conventional boost PFC at 230Vrms and
normal operation.

6.2.3 Comparison at 120Vrms

Having established that the totem-pole PFC is efficient at 230Vrms, a similar com-
parison must be made at 120Vrms to evaluate over its full voltage range. In fact, as
mentioned in section 3.2, a significant disadvantage of the totem-pole PFC emerges
at lower voltage levels; while the power decreases to almost half when the AC volt-
age is changed from 230Vrms to 120Vrms, the switching losses and conduction
losses of the bidirectional totem-pole PFC are unaffected by the AC voltage - only
the AC current and DC voltage. This means the relative losses are almost doubled
at 120Vrms, causing a big decrease in efficiency. Looking at (6.2) and (6.3) it
is evident that the conduction losses of the conventional PFC are indeed depen-
dent on the AC voltage and power. As it turns out, when the AC voltage - and
power - decreases, the current through the boost switch of the conventional PFC
increases while the current through the freewheling diode decreases. Based on the
previous analysis of the current dependency of the conduction losses of diodes and
MOSFET and HEMTs, this should mean an increase in conduction losses in the
conventional PFC at 120Vrms, implying even worse efficiency.

The conduction losses of the conventional PFC at 120Vrms and worst-case oper-
ating conditions can be calculated as follows, using the same procedure as in the
previous analyses:

Pcond,conv,120V = 39.82W ,

which, as expected, is an increase of 15% compared to the worst-case analysis

at 230Vrms. Assuming all the other losses computed in chapter 3 to remain un-
changed, and keeping in mind that these were designed to give more or less exactly
98% efficiency at 230Vrms and 3500kW, it is obvious that the efficiencies of both

95
the conventional boost PFC and the bidirectional totem-pole PFC at 120Vrms and
1.9kW will be less than 98%.

Since the PFC should be able to operate with 98% efficiency at both 120Vrms and
230Vrms, and the efficiency of this bidirectional totem-pole PFC is closer to 96%
at 120Vrms normal conditions, some modifications should be made to increase the
efficiency at low voltage. An example of such a modification could be connecting
extra totem-leg GaN eHEMTs or rectifier-leg MOSFETs in parallel; a halving of
the current through each of these transistors implies a 4-times decrease in conduc-
tion losses in each transistor, by (2.22), thus halving the conduction losses. MOS-
FETs and GaN HEMTs can safely be connected in parallel because of the positive
temperature coefficient of the on-state resistances ensuring an even loss distribu-
tion between the paralleled transistors. There are however some challenges when
connecting transistors in parallel, such as e.g. equalling the impedance of the gate
circuits of both of the paralleled transistors to ensure simultaneous switching. On
the other hand, it has been shown in [29] that interleaving the totem legs can give
positive effects with regards to current ripple, cancelling out harmonics, mean-
ing there are more positive effects to connecting in parallel as well. In any case,
paralleling the transistors would indeed give a more complex system, making it
desireable to avoid if possible. Thus another solution to this problem could be to
decrease and redistribute the estimated losses in table 3.2, to e.g. have approx-
imately the same totem-leg losses, while restricting especially the inductor and
rectifier leg allowed losses. The inductor conduction losses could be decreased by
increasing the core size, and the rectifier legs have no switching losses and could
thus be made with smaller losses than the totem-leg. However, the first would de-
crease the power density, whereas the second would likely require more expensive
transistors.

96
Chapter 7
Conclusion and Further Work

7.1 Conclusion

A fundamental simulation model of a bidirectional totem-pole PFC for bidirec-

tional OBC purposes has been built and implemented in Simulink using off-the-
shelf components while complying with the demands put forward by Valeo Siemens.
General equations have been developed for the description of currents, voltages
and losses in the components throughout the topology, aiding in the dimension-
ing of these components. Importantly, it was discovered that the transistor con-
duction losses in the bidirectional totem-pole are only dependent on the AC cur-
rent, because of the symmetry of the topology forcing the conduction losses to
be equally distributed across both transistors in each leg. The components im-
plemented were a 246µH powder-core, toroid-shaped boost inductor with copper
wires, 5 paralleled 360µF electrolytic DC-link capacitors, GaN eHEMT GS66516
for high-frequency transistors and CoolMOS IPW60R045CPA for slow-switching
rectifier-leg transistors. Combined, they were computed to give an efficiency of
more than 98% at a switching frequency of 90kHz.

Moreover, equations for gate logic and control system with cascaded current and
voltage control have been developed and implemented in Simulink, and verified
through simulations. The current and voltage controllers were implemented with
PI controllers and Symmetrical optimum, giving crossover frequencies of 28kHz

97
and 500Hz, respectively, with good response. The simulations showed that the
charger was able to operate at 120Vrms and 230Vrms max power with a power
factor of 0.998 and a THD of 5% without any DM filter applied on the AC side.
This was not complying with the AC current THD limitations at 3% in V2G, and
thus a DM filter will have to be applied in order to meet these demands.

At last the performance of the proposed bidirectional totem-pole was compared to

a conventional boost PFC at worst-case and normal operating modes at 230Vrms,
and at 120Vrms. This analysis showed that the bidirectional totem-pole PFC pro-
duced higher conduction losses than the conventional boost PFC at worst-case op-
erating conditions with case temperature 150◦ C. This was concluded to be because
the conduction losses of the eHEMTs and MOSFETs being dependent on the cur-
rent squared while for the freewheeling diode of the conventional boost they are
dependent on the current to the power of one, combined with the fact that the
conduction losses of the conventional PFC can be regulated by adjusting the DC-
link voltage to direct more of the current through the diode and less through the
boost MOSFET. However, it was shown that during normal operation, the strong
temperature dependency of the MOSFET and GaN HEMT on-state resistances
decreased the conduction losses to make the bidirectional totem-pole PFC more
efficient than the conventional boost PFC. Still, it was shown at 120Vrms that the
conduction loss - and switching loss - independence from AC voltage of the bidi-
rectional totem-pole PFC causes the efficiency to decrease significantly at lower
voltages, approaching 96% at 120Vrms. This effect is however found to be even
worse in conventional PFCs.

All in all, the bidirectional totem-pole seems a promising topology for use as
a bidirectional PFC, being feasible with existing off-the-shelf components, and
showing good control performance in both G2V and V2G operation. It was ar-
gued in the introduction that the charger would most often be operating at max
power in both G2V and V2G, and at 230Vrms max power the performing at a
good efficiency η > 98%. Moreover, at 230Vrms lower power, the totem-pole is
expected to show even better performance, due to the mentioned I 2 -dependency of
the conduction losses in the transistors. However, at 120Vrms, the efficiency was
found to not meet the demands, and so modifications would need to be made, such
as connecting the high-frequency legs in parallel, in order to achieve a satisfactory
efficiency at lower AC voltages. Also, importantly, the results of this simulation

98
model are not sufficient to verify completely the bidirectional totem-pole, as some
parasitic effects and transients are ignored. A real-life prototype will have to be
made to investigate the performance further.

7.2 Further Work

Picking up on that loose thread, the first suggestion for further work is to build a
prototype of this bidirectional totem-pole PFC for OBC purposes, with the rele-
vant components and with proper gate drive circuits. This way, the real-life per-
formance of the 3.5kW bidirectional can be investigated, studying the effect of
the transient behaviour of the GaN HEMTs and the gate drive circuits on the con-
trol system and the rest of the performance. It would also allow for investigation
of the effect of PCB parasitics on e.g. overvoltages across the transistors during
switching; at this high frequency of 90kHz it is desirable to avoid snubber cir-
cuits at the transistors, since they impose a delay in the switching, and for that
reason it would be valuable to investigate any overvoltages or too high di/dt and
dv/dt during switching, to evaluate the feasibility of the topology. Another tran-
sient effect of importance, is the previously mentioned current spike that is shown
to occur at zero crossing is with unidirectional PFCs, due to rectifier diodes mi-
nority charges.[55] It could be interesting to see if the same effect is present with
the body diodes of the rectifier-leg MOSFETs during G2V, or if implementing a
bidirectional totem-pole removes this problem.

Withal, a suggestion for further work is investigating further the paralleling of GaN
HEMTs in the fast-switching totem-leg, to increase the efficiency of the totem-
pole at lower voltages. As mentioned this imposes stringent requirements to the
gate drivers with regards to equality of gate impedance, and other issues will be
present too. Also, interleaving of the totem-pole fast-switching leg with CrCM and
TCM has been investigated in several papers in the literature,[29, 27] but few have
investigated this interleaving in CCM.

At last, an obvious suggestion for further work is the study of a bidirectional DC-
DC converter, to complete the bidirectional OBC. This will in fact be done in a
master’s thesis at NTNU next spring, also in cooperation with Valeo Siemens.

99
100
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107
108
Appendices

109
Appendix A
Valeo Siemens bidirectional OBC
specifications

111
 Doc. Ref.:
NTNU master project Doc. Rev.: 01
Release Date: -
Bidirectional charger Doc. Classif.: Not restricted
Customer: P3 Product Line: OBC Project Type:
Division: Hardware Platform: - Product: - Project Manager:
Dev./Prod Site(s): Drammen Project Code: - Product Ref.: - Activity Leader: T. Sorsdahl

Schematic and layout review and justification.

SKILL PROJECT NAME PLM

Hardware Bidirectional charger

ABSTRACT / CONCLUSION

ABSTRACT:
General specification && guidelines for design of a bidirectional on board charger for electrical and hybrid vehicles
intended as a starting point / reference for a master project at NTNU.
The bidirectional charger should be designed for J1772/IEC 61851 which describes the charging standard for
electrical vehicles up to level two charging with single phase current up to 32Arms/7680VA. Relevant and extended
requirements are specified in this document.
There is no known standardization for bidirectional chargers at the time of creation of this document.

CIRCULATION LIST (E : E-mail, P : Paper)

Can be released  Communicable with non disclosure commitment  Available on site only  Confidential - unavailable 
C Name Service or Company C Name Service or Company C
E E E

S YES  NO 
R YES  NO 

This document is property of Valeo.

No copy or distribution allowed without authorization. Template Ref: V01 TPL 07 00645
p 1/8 01
Template Rev:
 Doc. Ref.:
NTNU master project Doc. Rev.: 01
Release Date: -
Bidirectional charger Doc. Classif.: Not restricted
Customer: P3 Product Line: OBC Project Type:
Division: Hardware Platform: - Product: - Project Manager:
Dev./Prod Site(s): Drammen Project Code: - Product Ref.: - Activity Leader: T. Sorsdahl

Written by Reviewed by Checked by Approved by

Function Hardware Engineer Referent Engineer HDL Department Manager

Name Torbjørn Sørsdahl

Date

Visa
See Signature Workflow Instruction

This document is property of Valeo.

No copy or distribution allowed without authorization. Template Ref: V01 TPL 07 00645
p 2/8 01
Template Rev:
 Doc. Ref.:
NTNU master project Doc. Rev.: 01
Release Date: -
Bidirectional charger Doc. Classif.: Not restricted
Customer: P3 Product Line: OBC Project Type:
Division: Hardware Platform: - Product: - Project Manager:
Dev./Prod Site(s): Drammen Project Code: - Product Ref.: - Activity Leader: T. Sorsdahl

SUMMARY
CIRCULATION LIST (E : E-MAIL, P : PAPER).................................................................................................. 1
SUMMARY ................................................................................................................................................................. 3
REVISION HISTORY ................................................................................................................................................ 3
1 GLOBAL REQUIREMENTS................................................................................................................. 4
1.1 GENERAL REQUIREMENTS .......................................................................................................................... 4
1.2 SPECIFICATION G2V ................................................................................................................................... 4
1.3 SPECIFICATION V2G ................................................................................................................................... 4
1.4 EMC REQUIREMENTS ................................................................................................................................. 5
2 INTERNAL OBC REQUIREMENTS ................................................................................................... 6
2.1 PFC STAGE OR SIMILAR TOWARD AC GRID ................................................................................................. 6
2.2 DC/DC OR SIMILAR TOWARD BATTERY ....................................................................................................... 7
3 TIPS / FAST CALCULATIONS AS INPUT ......................................................................................... 8

REVISION HISTORY
Revision # Date Modif # Author Modified paragraphs and kind of modification
1 13.12.2017 1 T.Sorsdahl Initial revision

This document is property of Valeo.

No copy or distribution allowed without authorization. Template Ref: V01 TPL 07 00645
p 3/8 01
Template Rev:
 Doc. Ref.:
NTNU master project Doc. Rev.: 01
Release Date: -
Bidirectional charger Doc. Classif.: Not restricted
Customer: P3 Product Line: OBC Project Type:
Division: Hardware Platform: - Product: - Project Manager:
Dev./Prod Site(s): Drammen Project Code: - Product Ref.: - Activity Leader: T. Sorsdahl

1 Global requirements
Rough expectations for performance required for bidirectional on board chargers from standards and other input.
1.1 General requirements
Id Req Description Range

1.1 Galvanic isolation between input and output (transformer) 4kVac

1.2 Encapsulation IP67
1.3 Cooling system by liquid with coolant temperature -40 ~ 85ºC
1.4 Ambient air temperature range -40 ~ 85ºC
15 years
1.5 The charger shall meet the following lifetime (service life): 300 000 km
~ 20.000 hours total V2G && G2V
1.2 Specification G2V
Id Req Description Range

2.1 AC-DC Output voltage range 200 ~ 1000Vdc

2.2. AC-DC Max output current(continuous) 12Adc
2.3 AC-DC Output current ripple 5%
2.4 AC-DC Maximum output power 3500W
2.5 AC-DC Input voltage range 85 ~ 264VAC,rms
2.6 AC-DC Input frequency 45 ~ 65Hz
2.7 AC-DC Maximum input current 16A Max.
2.8 AC-DC Efficiency > 94%.
2.9 AC-DC Max apparent power 3680VA
2.10 10.000 hours
AC-DC Lifetime
(Eq 300.000 km)
2.11 Maximum AC leakage current 1.5mA
1.3 Specification V2G
Id Req Description Range

3.1 DC-AC Output voltage range 85-264Vac

3.2 DC-AC Input voltage range 200VDC~1000VDC
3.3 DC-AC Max power output 3.5kW
3.4 DC-AC Max input current 12Adc Max.
3.5 DC-AC Max output current(rms) 16A Max.
3.6 DC-AC output frequency range 45~65Hz
3.7 DC-AC efficiency > 94%.
3.8 DC-AC THD THD<3%
3.9 10.000 hours
DC-AC Lifetime
(high uncertainty of required lifetime)
3.10 Maximum AC leakage current 1.5mA

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1.4 EMC requirements

Electric vehicle minimum emc requirements for EU : R010r6e (available for free) done at Vehicle level. This
specifies all emc requirements which in the end the charger also need to be according to however component
level requirements are usually stricter.

Id Req Description Standard

3
4.1 Maximum harmonics 50Hz – 2kHz

R010r6e :

IEC 61000-3-2
2
4.2 Supply voltage dips
 Minimum requirement: Voltage reduction of 30 % of
nominal voltage for 10 ms.
 Minimum requirement: Voltage reduction of 50 % of
nominal voltage for 100 ms.
 Minimum requirement: voltage reduction >95 % of
nominal voltage for 5 s.
No loss of charging state allowed reduced power acceptable IEC 61000-4-11
2
4.3 1,2/50 μs surges
 6kV in common mode,
 3 kV in differential mode IEC 61000-4-5
2
4.4 Conducted emission toward ac grid 150kHz-30MHz

IEC 61000-4-6
1
4.5 Radiated emission 30MHz-6GHz R010r6e
4.6 Conducted emission toward battery 150kHz-30MHz

R010r6e
1: Outside any scope for a student task
2: For minor reference regarding switching frequency
3: Why a pfc is required.

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2 Internal obc requirements

Describes recommendations to be able to the global on board charger requirements.

2.1 PFC stage or similar toward ac grid

Id Req Description Value
Reason
 Grid stabilization is usually in the range of seconds
 It is assumed the dc/dc is running in idle mode
PFC startup time to
<1s while awaiting feedback from the grid to only need
Full operation V2G
to start the PFC and not charge the dc link in
addition which is time consuming.
 Total effiency required 94% estimate loss split :
o 40% PFC Min effiency PFC : 97.6%
o 40% DC/DC Min effiency dc/dc : 97.6%
o 20% Other losses Min effiency required :
98.8%
PFC efficiency >97.6%
o Sum 94% efficiency.
 Hard to meet at 85Vrms due to the losses in the
PFC can only be 37% of the value at 230V usually
requring much higher rated component at a higher
cost.
 Core losses for most relevant magnetic materials
increases by the square of the flux density ripple so
100% ripple increases core losses by 25x
PFC choke current ripple < 20% compared to 20%.
 This limits the maximum current ripple which has to
flow in filter capacitors reducing the requirement for
current capability.
 Ac grid legal limits starts at 150kHz and if you are
nd
bellow the 2 harmonic is above legal limits at ~
100kHz < Fsw < 140kHz
Switching frequency 300kHz so the filtering must be designed for
450KHz< Fsw < inf
300kHz while if you are at 150kHz the filter must be
designed for 150kHz leading to a much larger filter.
 Avoids unnecessary component stress
Max dc link voltage ripple < 20V
 Maintains stable input voltage to the dc/dc
 Provides high voltage to the dc/dc stage while
Dc link voltage < 340V
staying bellow nominal grid voltages.
 Legal standards put 8.8uF as maximum x
capacitance between lines for differential mode
Lowest PFC power in V2G >146 Va filtering.
o Energy consumption in 8.8uF = 146Va at
230V

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2.2 Dc/dc or similar toward battery

Id Req Description Value Reason
Dc/dc startup time <1s  Grid stabilization is usually in the range of seconds
 Total effiency required 94% estimate loss split :
o 40% PFC Min effiency PFC : 97.6%
o 40% DC/DC Min effiency dc/dc : 97.6%
o 20% Other losses Min effiency required :
Dc/dc efficiency >97.6%
98.8%
o Sum 94% efficiency.
 Low efficiency also lead to high losses complicating
the cooling system required.
 Ac grid legal limits starts at 150kHz and if you are
nd
bellow the 2 harmonic is above legal limits at ~
100kHz < Fsw < 140kHz
Switching frequency 300kHz so the filtering must be designed for 300kHz
450KHz< Fsw < inf
while if you are at 150kHz the filter must be designed
for 150kHz leading to a much larger filter.
 Three phase dc/dc leads to energy being transferred
rd
Topology Three phase at 3 harmonic reducing magnetic component sizes
and filtering required.

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3 Tips / fast calculations as input

 Power factor correction required for all power levels above 80W
 EMC : Conducted emission fast calculation :
o Assume 400Vpp at the PFC output
 20log(400*10^6) = 172dBuV
 Legal requirement at 150kHz 50dbuV
 If first harmonic is placed at 150kHz filtering required :
 172dBuV-50dBuV = 122dBuV
 122dBuV = 10^(122/20) = 1.25M
 Noise levels need to be reduced 1.25M times between the output of the pfc to the
grid.


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120
Appendix B
Literature review on power factor
correction converters

A literature review has been performed on bidirectional and unidirectional PFCs,

for use in OBCs. The following content, i.e. the whole chapter, is an excerpt from
the specialization project performed in the fall semester. [4]

B.1 Power factor correction AC-DC converter

There are regulations and standards, such as the IEC 61000-3-2 or IEC 61000-6-
3 directives, limiting the permitted current harmonics emissions to the grid from
power supplies and other electric equipment. In OBCs and most other power sup-
plies, this harmonic emission is dealt with by the combination of an AC-side filter,
typically a passive LC filter, and a PFC AC-DC converter. The PFC controls the
drawn AC current to be sinusoidal and in phase with the AC mains voltage, re-
moving the low-frequency harmonics and maximizing the power factor, while the
filter suppresses the high-frequency harmonics from the PFC converter.

121
 Figure B.1: The topology of a conventional boost PFC converter

B.1.1 Conventional PFC

To understand the operation of a bidirectional PFC, the operation of a unidirec-

tional PFC needs to be understood as well. Figure B.1 shows a conventional PFC
converter, similar to that used in the depicted Valeo Siemens OBC topology from
figure 1.1, with a passive rectifier bridge cascaded with a boost converter. The
boost converter sees the rectified positive half wave of the AC voltage, and the
transistor switching is pulse-width modulated to shape the fundamental compo-
nent of inductor current sinusoidally in phase with this voltage. The PFC could be
operated in either continuous conduction mode (CCM), critical conduction mode
(CrCM) or discontinuous conduction mode (DCM), as shown in figures B.2a, B.2b
and B.2c, respectively. Since CrCM is on the boundary of CCM and DCM, with
current shaped like in CCM and becoming zero momentarily once every switching
period, it can be said to be a special case of them both. DCM has no apparent
operational advantages over CrCM, and would cause both more harmonics and a
bigger current ripple for the same average current value due to the period of dis-
continuity [24, Chapter 7]. For that reason DCM is rarely used [2]. CCM has the
advantage that it has a smaller current ripple, and thus also a smaller peak cur-
rent, requiring less current capability in the MOSFETs and a smaller filter on the
AC side. At the same time, there is hard switching both at turn-on and turn-off,
increasing the switching losses. CrCM, on the other hand, achieves zero voltage
switching (ZVS) at turn-on, giving no switching loss when the switches are turned
on, but the peak-to-peak ripple is twice the average current. The ripple in CrCM
implies a bigger current stress on the MOSFET, and it requires a bigger AC filter
to suppress the harmonics.

122
(a) Continuous conduction mode (b) Critical conduction mode

(c) Discontinuous conduction mode

Figure B.2: The current waveforms of a boost PFC, as found in [2].

123
A buck converter could also have been used in stead of a boost, but that would have
required a big capacitor on the output of the rectifier to ensure that the voltage is
always higher than the DC-link voltage, since the buck converter needs to have a
negative voltage gain in order to function [24, Chapter 7-3]. Therefore, boost PFC
is a better option during charging, controlling the DC-link voltage to be higher than
the maximum peak AC voltage (including ripple), so that the charger can operate
at rated voltage during the whole input voltage range from 0 to peak.

B.1.2 Bidirectional PFC

When the boost PFC is to be made bidirectional, it is obvious that both the rectifier
bridge and the freewheeling diode of the boost converter needs to be replaced.
The freewheeling diode can be removed by integrating the PFC switching into the
rectifier bridge, as is done in several bridgeless PFC topologies in [25] and [57].
The forward voltage drop of the diodes cause conduction losses [24, Chapter 2-
2], so minimizing the number of diodes in the conduction path by removing the
freewheeling decreases these losses. Out of these bridgeless topologies, the basic
bridgeless PFC and the totem-pole PFC are standing out with regards to simplicity
and low number of semiconductors. These are depicted in figures B.3a and B.3b.
For both of these topologies, the transistors are controlled such that for positive
AC-voltage half cycle one transistor is in boost PWM switching mode, while the
other transistor is behaving as a rectifier diode, and oppositely in the negative half
cycle.

The totem-pole PFC was previously somewhat disregarded for the benefit of the
basic bridgeless PFC and other bridgeless PFC topologies [25]. This because the
reverse recovery body diode of the MOSFET made CCM (see figure B.2) infea-
sible in this topology, due to the reverse recovery current causing considerable
switching losses in CCM [24, Chapters 19 - 22]. Running it in DCM would require
very high current ratings for higher-power applications, such as an OBC. The basic
bridgeless PFC, on the other hand, does not have these issues, and has been proven
in e.g. [58] to be efficient at power levels up to 3.5 kW. On the negative side,
the basic bridgeless PFC produces significant amounts of common mode noise,
because the zero-potential of the DC-link side is floating compared to AC ground
during negative AC mains half cycle [25, 3]. In more recent scientific works, the

124
 (a) Basic bridgeless PFC

(b) Totem-pole PFC

Figure B.3: Bridgeless PFC topologies

Figure B.4: The basic bidirectional PFC topology

125
totem-pole has been given renewed attention; there has been proposed some mod-
ulation schemes where by replacing the diodes with low-frequency MOSFETs and
allowing negative current before turn-on, operating at the boundary of CCM and
DCM, ZVS can be achieved through large parts of the input voltage range. This
because the brief negative current helps discharge the drain-source capacitance of
the blocking high-frequency MOSFET, lowering the drain-source voltage before
turn-on [24, Chapter 22]. The resulting topology is the basic bidirectional H-bridge
AC-DC converter, as shown in figure B.4, with one high-frequency switching leg,
the totem-leg, and one rectifier leg operating at synchronous frequency. This topol-
ogy obviously allows for bidirectional power flow.

One of the proposed modulation schemes is called valley filling, or valley switch-
ing [28]. The current and voltage dynamics in the MOSFETs at switching is shown
in figure B.5a. In this technique the resonance between the parasitic capacitances
of the high-frequency MOSFETs and the boost inductor is exploited by delaying
the MOSFET turn-on until the drain-source voltage of the blocking MOSFET res-
onates down to a ”valley” or to zero, significantly reducing the turn-on switching
losses. It is found i [28] that ZVS is achieved while |vAC | < VDC /2. The other mod-
ulation scheme is named triangular current mode (TCM) [3, 29, 27]. The switching
dynamics are shown in figure B.5b. Here, instead of utilizing the resonance after
MOSFET turn-off, the conducting MOSFET is kept on while the current becomes
negative. The hitherto conducting switch is turned off and the complementary
switch turned on when the drain-source voltage of the blocking MOSFET becomes
zero, achieving ZVS throughout the mains voltage period. Withal, this technique
does also require complex control due to the non-linearity of the MOSFET output
capacitances making the switching timing difficult; the average current needs to
be computed over every switching cycle [3]. Additionally, with the average cur-
rent being dependent on the grid voltage and the drawn power, including negative
current in every switching cycle gives a higher peak current ripple, sharpening
the demands to MOSFET current ratings and requiring bigger AC filter current
capability.

In the totem-pole topology, the high-frequency totem-legs can easily be inter-

leaved, by operating several legs in parallel, with switching schemes phase-shifted
between each leg, as has been done in [3] and [27]. This is a big advantage, as for
the same charging power one could significantly reduce the current stress on each

126
 (a) Valley switching (b) Triangular current mode (TCM)

Figure B.5: MOSFET switching dynamics with extended reverse conduction time, as
found in [3].

of the totem-leg switches. The peak current stress was, as mentioned, previously
the limiting factor for the totem-pole PFC, so interleaving has been a big factor
for bringing the totem-pole PFC back in the discussion. In [3] there are three in-
terleaved legs, which has benefits also regarding cancellation of first and second
harmonics in the inductor current, while in [27] there are two interleaved legs. Us-
ing three interleaved legs, one could actually double the input power while at the
same time reducing the stress on each of the totem-leg switches. The drawback of
the interleaving strategy is however that the control becomes more complex [3],
and obviously it would also require larger drive circuits. Interleaving is also pos-
sible with the basic bridgeless PFC, but it would require a more complex topology
with more semiconductor components, as in [59].

Furthermore, recent research in wide-bandgap power semiconductor devices have

shown that gallium nitride (GaN) high-electron-mobility transistors (HEMTs) can
significantly improve the performance of the bidirectional totem-pole PFC, replac-
ing the high-frequency MOSFETs [35, 60]. The GaN HEMT has a very low on-
state resistance while at the same time providing a higher breakdown voltage than
regular silicon MOSFETs [38, 61]. Additionally, as opposed to the MOSFET,
the HEMT has no reverse body diode, and it has lower gate charge and smaller
and less non-linear output capacitances than the MOSFET [62]. Also the various
normally-off GaN arrangements, such as the cascode HEMT and E-mode HEMTs,
have very low turn-off losses, making them ideal for boundary CCM/DCM oper-
ation with ZVS turn-on, giving virtually no switching losses and efficiencies up

127
to 99% at 1MHz [27, 60]. Moreover, the lack of reverse body diode, lower gate
charge and smaller output capacitances reduce switching losses to such extent that
a CCM-operated totem-pole becomes feasible. This is evident in [30], where a
65kHz 1.5kW CCM-operated bidirectional totem-pole PFC is proven to achieve
an efficiency of 99%. The normally-off GaN HEMTs are however still a tech-
nology in development, and few commercially available solutions exist as of now,
especially at the power level of an OBC (3.5kW), but the technology in this field
is rapidly evolving.

128
Appendix C
Paper on GaN HEMTs and
bidirectional PFCs

129
 GaN HEMTs and Bidirectional Power Factor
Correctors - A Review Paper

Sondre Johannessen
Department of Electric Power Engineering
Faculty of Information Technology and Electrical Engineering
Norwegian University of Science and Technology (NTNU)
Trondheim, Norway
Email: [email protected]

Abstract—Gallium Nitride power devices is widely considered

as an appealing technology within power supplies. At the same
time, bidirectional power supplies is finding a growing interest,
especially within distributed renewable energy and battery en-
ergy storages, presenting a need for bidirectional power factor
correctors (PFCs). This paper discusses and evaluates the state-of-
the-art within GaN power transistors and bidirectional PFCs, and
the joint potential and present use of these technologies. Totem-
pole PFCs is found to be the leading bidirectional topology in
the present, and shows goods attributes together with cascode
GaN HEMTs. Other promising technologies are the already
commercialized gate-injection-transistors. GaN transistors are
found to have a big potential for both increasing PFC efficiency Fig. 1: Conventional boost PFC, as found in [2].
and decreasing size due with high frequency.
Keywords—GaN, Bidirectional PFC, GaN E-HEMT, GIT, DAB,
dual active bridge

I. I NTRODUCTION
These days there is an increasing focus on distributed
battery energy storage connected to e.g. intermittent renewable
energy production. By its nature, such solutions will have
bidirectional power flow, so a necessary effect is a growing
need for bidirectional active power factor correctors (PFCs).
PFCs are an important part of any electronic power supply; a
PFC drastically improves the power quality of the AC power
drawn by the electronic load by controlling the shape of the
drawn AC current waveform. First of all it is keeping the input (a) Continuous conduction mode
AC current in phase with the input AC voltage to improve the
power factor and secondly it is controlling the harmonics of
the drawn current by shaping it sinusoidally. High-frequency
harmonics lead to unnecessary loss, heat up the components
and may cause harm on electronic equipment [1]. For that
reason, there are regulations limiting the permitted emission of
harmonics from grid-connected power supplies and standards,
such as the european IEC/EN 61000-3-2 directive, which have
to be obeyed by the combination of PFCs and harmonic filters.

A. PFC converters
Traditional, conventional boost PFCs consist of a rectifier
bridge and a dc-dc boost converter, as shown in figure 1[2]. (b) Critical conduction mode
When using a boost converter the DC side is able to operate at
its rated voltage over the whole mains voltage period without Fig. 2: The current waveforms of a boost PFC, as found in
having a big DC link cap on the output of the rectifier bridge. [3].
The passive rectifier bridge rectifies the voltage to the wave-
form of the absolute value of a sine, and the current is ruled
by the voltage over the inductor according to L diL /dt = vL .
The current waveform is then shaped like a sine (figure 2) by
controlling the duty cycle of the MOSFET, keeping it in phase
with the voltage. The converter can either be ran in continuous
conuction mode (CCM) (figure 2a) or critical conduction mode
(CrCM) (figure 2b); the first gives smaller current ripple but
harder switching in the MOSFET, the latter gives soft turn-
on of the MOSFET, but a bigger current ripple. The boost
converter is rarely operated in discontinuous conduction mode
(DCM), as DCM has no apparent operational advantages over
CrCM and produces more harmonics due to the discontinuous (a) The basic bridgeless PFC
current [4, Chapter 7]. With the average AC mains current
shaped like a sine, the harmonics are limited to the switching-
frequency ripple, which can be compensated by a passive filter
on the AC side.
The basic boost PFC converter does its duty, but has
some drawbacks. Most notable is the number of semiconductor
devices in the conduction path from grid to load; during
charging of inductor there are two diodes and a MOSFET,
while during discharge of the inductor there are three diodes.
This means a lot of conduction and switching losses, and
so there has been developed bridgeless PFCs, such as those
presented in [2], [5] and [6], to minimize the number of
semiconductor devices in the conduction path. The most simple (b) The totem pole PFC
are the basic bridgeless PFC and the totem-pole PFC, shown
in figures 3a and 3b. These converters are operated such that Fig. 3: The simplest bridgeless PFC topologies, as found in
for the positive half of the AC mains voltage period one of [2].
the MOSFETs is conducting, either through the body diode or
through the MOSFET itself if it is turned on, while the other is
doing the PFC switching. During the negative half period the
roles are swapped. The diodes still aid with rectification. This has no reverse body diode, making it symmetrical and thus
way the number of semiconductor devices in the conduction advantageous for bidirectional purposes, and it has a lower
path is reduced from three to two, reducing the losses[5]. on-state resistance. This will be explained in more detail in
section II.
From bridgeless PFCs the way is short to bidirectional
PFCs. Looking at figures 3a and 3b it is easy to see that by
C. Scope of work
replacing the diodes with MOSFETs, the converter enables
bidirectional power flow. This substitution even improves This review will present and investigate the state of the art
the efficiency of the converter, as is shown in [7], [8] and in bidirectional PFC topologies, and the use of GaN HEMTs
[9]. These are totem-pole PFCs where the diodes have been in these topologies. Section II will present the concept of
replaced by slow-switching MOSFETs to remove the forward GaN HEMTs, with emphasis on the electrical performance
voltage loss of the diodes and thus reduce the losses. of the transistor. Section III will evaluate the state-of-the art
bidirectional PFCs and the present and potential use of GaN
B. GaN HEMTs HEMTs in these.
To this date Si superjunction MOSFETs have been the most II. G A N HEMT S
used transistor in front-end PFCs[10]. However, recently wide-
band-gap (WBG) semiconductors such as silicon carbide (SiC) A. Structure
and gallium nitride (GaN) have gained momentum in power The basic structure of a GaN HEMT is shown in figure
electronic components, especially for higher voltages >400V 4[14]. Its foundation consists of bottom-layer semiconductor
due to their higher breakdown voltage[11], [12]. To this date substrate (often silicon, due to low price [11]). The main GaN
SiC is the WBG semiconductor which has seen the most structure consists of AlGaN layer grown on top of a GaN
progress because of its temperature stability, both allowing for channel, forming a highly conductive two-dimensional electron
smaller heat sinks through higher operating temperature and gas (2DEG) layer in between. Between the substrate and the
enabling use in environments with big variations in ambient GaN structure is a high-resistivity buffer layer to ensure high
temperature [13]. However, for high very high switching breakdown voltage of the transistor. A dielectric is isolating
frequencies (MHz range) the Si SiC MOSFETs are having the gate contact from the AlGaN-layer to prevent gate leakage
difficulties achieving soft switching due to the high reverse current[15] and current collapse[16].
recovery charge [9]. Therefore, lately the GaN high-electron-
mobility transistors (HEMTs), also called heterostructure field- One of the key positive attributes of the GaN HEMT lies
effect transistors (HFETs), have become very interesting, with in the 2DEG layer; GaN has a higher breakdown voltage than
a very low recovery charge. Furthermore, the GaN HEMT SiC (and much higher than Si, see figure 5[17]), which means
 Fig. 6: The circuit diagram and resulting symbol of a cascode
GaN HEMT, as found in [18].

body diode in the MOSFET, so this means that that the HEMT
does not contain a reverse body diode. Thus the GaN HEMT
Fig. 4: The basic structure of a GaN HEMT, as found in [14] is completely symmetrical from drain to source, making it
a bidirectional in switching operation. This is a feature that
comes in handy for some bidirectional converter purposes, and
will be discussed further in section III.
Although seeming superior to other semiconductor materi-
als up until this point, there is of course a drawback to GaN as
well; as highlighted in figure 5, GaN has relatively lower ther-
mal conductivity compared to both SiC and Si. Consequently,
GaN transistors are not as capable of transferring dissipated
heat to the environment, resulting in an increased temperature
inside the transistor. This increases the risk of melting and
cracking inside the transistor package. To avoid these effects, it
is important to keep the losses at a low level, and since the on-
state resistance is already very low, that means minimizing the
switching losses. Otherwise this would have to be compensated
by a bigger heat sink, increasing the converter size and weight.

B. Normally-off GaN HEMTs

The 2DEG layer does, despite its positive effects, introduce
some issues. Since this layer is present without any voltage on
the gate, the GaN HEMT is by nature normally on, i.e. it
is conducting without an applied gate voltage. The HEMT is
instead blocking when voltage is applied on the gate. In power
electronics it is demanded to have normally-off transistors, so
modifications have to be made in order to make a normally-off
GaN HEMT-based transistor [18].
The simplest of these modifications is cascading the HEMT
with a low-voltage normally-off Si FET, to form what is called
Fig. 5: Five relative material attributes of GaN versus SiC and a cascode GaN HEMT, as in [11], [18], [19], [20]. However,
Si, as found in [17] while simple in theory, such an arrangement should be made
single-chip in order to reduce the inductance in bond wires
and PCB traces, which is not so simple from a mechanical
point of view. The circuit diagram and symbol of cascode GaN
the material itself has a higher resistivity. However the low- HEMT is shown in figure 6. Here the gate of the HEMT is
resistivity 2DEG layer in the GaN HEMT makes the on-state connected to the source of the low-voltage FET, so that when
resistance lower than for a SiC MOSFET. Thus the conduction there is no voltage applied to the gate of the FET there is
losses of a GaN HEMT is lower than that of a SiC MOSFET. a voltage at the gate of the HEMT, meaning the HEMT is
Furthermore, both the gate charge and output capacitance of blocking. Oppositely, when the FET gate voltage is high, the
the HEMT is smaller than for a Si and SiC MOSFETs[18]. HEMT gate is at HEMT source potential, meaning the HEMT
is conducting. This sort of cascade connection will necessarily
A feature which is apparent looking at the structure of make the gate charge of the HEMT slightly higher, since both
the GaN HEMT in figure 4 is that there is no PN junction the gate charge and the output capacitance of the FET will
between source and drain in the off-state, as is present in a delay the gate voltage of the HEMT, not allowing for as fast
MOSFET. The body PN junction is what creates the reverse switching as for the HEMT alone. Huang, X. et. al. (2014)
Fig. 7: The basic structure of a p-GaN hybrid drain GIT, as
found in [20].
Fig. 8: A MOSFET-based bidirectional totem-pole PFC, as
found in [7].
have shown that due to especially the parasitic capacitances
of the low-voltage FET, the switching losses of the cascode
GaN HEMT during hard turn-on are very high [21]. The same
article does however reveal a mechanism that assures the hard- The totem-pole PFC was previously discarded for the
switched turn-off losses to be minimal. For that reason, the benefit of the basic bridgeless PFC (figure 3a), due to the
cascode HEMT should always be operated with soft-switched combination of switch arrangement and too high reverse
turn-on, while it can easily be operated with hard-switched recovery charge in the body-diodes of the high-frequency
turn-off. MOSFETS making CCM unfeasible[5]. The converter can
only operate in DCM or on the boundary of CCM/DCM,
Chowdhury, S. (2015) and Chen, K. et. al. (2017) are where it generates a lot of high-frequency noise with a peak-
presenting some other solutions for a normally-off GaN HEMT to-peak of twice the current amplitude, as can be seen in
without external FETs or other components, called E-mode figure 2b. This again would require a large DM noise filter
GaN transistors [18], [20]. These are all in development, and on the AC side. In addition, the peak current through the
have mostly not been commercialized. One type that has MOSFETs is twice of that at CCM, requiring a higher current
been commercialized, however, is the p-GaN gate injection rating of the MOSFET, and the switching losses at hard turn-
transistor (GIT), brought up by Efficient Power Conversion. off are higher. There are however drawbacks to the basic
In this technology a p-type GaN layer inserted between the bridgeless PFC as well; it generates a lot of common-mode
gate channel and the AlGaN layer. Given the right thickness (CM) EMI noise due to a floating zero potential on the
and doping, this p-GaN layer could attract enough negative DC side, relative to AC ground[26]. This common mode
charges to empty the 2DEG layer[20]. This way there is no noise is difficult to compensate and requires large CM filters,
conduction channel when there is no gate voltage, and the and it is a problem connected to the arrangement of the
HEMT is normally off. To solve current collapse issues, an bridgeless PFC. Partly for that reason, the totem-pole has
additional p-GaN layer is connected between the drain and been given renewed attention, since it does not have that
the AlGaN. Such a variation to the GIT is called hybrid problem. Bidirectional front-end PFCs for power supplies that
drain GIT and is depicted in figure 7. Using these sort of E- are proposed in these days are almost invariably using the
mode GaN transistors it is possible to achieve faster switching bidirectional totem-pole topology [8], [9], [25], [27]. Some
transients and lower switching losses compared to the cascode use an interleaved variation where the PFC switching stress is
GaN HEMT solution, since the gate charge and the parasitic distributed across more than one parallel switching leg[7], [24],
capacitances of the FET are avoided. Besides, the solution is [9], [23]. Operated properly, the interleaved legs can cancel
compact, avoiding any wire inductances. The downside is that out second and third harmonics, and otherwise significantly
these solutions are more complex and thus more expensive and decrease the current ripple[23]. The topology of an interleaved
they are, as mentioned, still in development. bidirectional totem-pole PFC is shown in figure 9. Modulation
schemes called triangular current mode (TCM) have been
proposed that ensure ZVS turn-on over the whole input voltage
III. B IDIRECTIONAL PFC S range by operating around CrCM and extending the current
A. Topologies waveform to becoming negative at turn-on, so that the input
capacitances of the MOSFETs are fully discharged before turn-
The topology of a simple bidirectional totem-pole PFC on of the switches[7], [28], [23]. This modulation scheme
is shown in figure 8. This exact topology is proposed in makes bidirectional totem-pole PFCs more feasible. Be that as
[7], but is completely based on the totem-pole PFC (see it may, it has some issues, with perhaps the most significant
figure 3b), which has been discussed in plenty of research being how the negative current cause a ”dead time” in the
already [5], [22], [23], [24]. Other newer studies are also input current, making the shape less sinusoidal, generating
looking at the bidirectional totem-pole PFC [8], [9], [25]. The more harmonics. This is however partly solved in [9] using
bidirectional power flow capability is in [7] actually a positive variable time control. This leads over to the next issue: the
side effect of the substitution of diodes with MOSFETs to control using this modulation scheme is very complex; the
reduce conduction losses by removing diode forward voltage average current needs to be computed accurately for each
drop. The totem-pole leg MOSFETs S11 and S12 are switching switching period, and the non-linear parasitic capacitances in
at high frequency (several tens of kHz), while the rectifier leg the MOSFETs are hindering accurate analytic estimation of the
MOSFETs operate at mains frequency. timing parameters, thus making this computation difficult[7].
 (2015) was able to achieve a peak efficiency of 99% using that
technique with cascode GaN HEMTs in two interleaved totem-
pole legs and TCM[9]. The operating frequncy was 1 MHz.
In general GaN has smaller parasitic capacitances, smaller
gate charge and no reverse body diode, which yields faster
switching transients, again giving smaller losses. This permits
a higher switching frequency. Higher frequency ripple allows
for smaller EMI filter and smaller magnetic components,
such as inductors and high-frequency transformers (galvanic
Fig. 9: A MOSFET-based interleaved bidirectional totem-pole isolation) in the power supply, which is confirmed in [9], where
PFC, as found in [7]. an ten-times increase in switching frequency from 100kHz
to 1 MHz led to a 50% reduction in DM EMI filter size.
Ripple magnitude of the totem-poe PFC is still large, but
increasing the frequency many-fold makes the ripple easier to
filter out. In this specific case the issue is still the complexity
of control using TCM, although the mentioned less significant
non-linearity of the HEMTs might somewhat facilitate the
timing in the control. More complex control requires more
advanced MCUs, requiring larger control circuits. However,
Fig. 10: The topology of an AC-DC DAB, as found in [31]. it is also shown in [9] that even using regular CrCM with
valley switching, a peak efficiency of over 98% was achieved
at 1MHz switching and 1.2 kW power.
Xue, L. et. al. has made a bidirectional totem-pole PFC
Other modulation schemes, including e.g. ”valley switching”, using GaN e-HEMTs in the totem-pole leg, operating in
or ”valley filling”, give simpler control, but only gives ZVS CCM[8]. In this study, focus is put on the current behaviour
turn-on when vs < 1/2Vout , giving more hard switching over around the voltage zero crossing. This study finds that there
the mains voltage period, thus giving slighty more losses[29]. is a current spike at this zero-crossing, owing to dead-time of
Power factor correction can also be achieved without the the low-frequency rectifier leg. It finds that with big difference
dedicated AC-DC PFC. Although most power supplies are in switching frequency between the two legs of the totem-pole
two-step with an AC-DC PFC converter in series with an PFC, there is an increased current spike at the zero crossing.
isolated DC-DC converter, there is an interest for the single- This issue is mainly related to the control, and adds to the
stage AC-DC dual active bridge (DAB) solution, especially as complexity of control of totem-pole PFC. It does however
grid interfaces for renewable energy sources and bidirectional show that using GaN e-HEMTs, the totem-pole PFC can be ran
automotive charging[30], [31], [32], [33]. The topology of an in CCM, minimizing current ripple. The reference design GaN
AC-DC DAB converter is depicted in 10. The DAB interfaces E-HEMT-based bidirectional totem-pole PFC made by GaN
in [31] and [32] achieve open-loop PFC by pulse-width modu- Systems also operates in CCM, enabled by the fast switching
lating the DC bridge to keep the AC current in phase with the transients of the GaN HEMTs[34]. It achieves a peak efficiency
AC mains voltage. The converter also achieves ZVS in the DC of 99% and a power factor close to 1, operating at a switching
bridge and ZCS in the AC bridge, it provides galvanic isolation frequency of 65kHz and power of 1.5 kW.
and it has simple current control through controlling only the The GaN E-HEMT could also give improvement to the
phase shift. It does however not achieve ZVS across the whole AC-DC DAB topology. The bidirectional MOSFET switch in
AC mains voltage period, as the MOSFET capacitances are not the AC-bridge is causing conduction losses due to the current
able to fully charge and discharge at low current and voltage flowing through two of the reverse body diodes at all times (see
levels. Furthermore there is a need for bidirectional switches figure 10). As previously mentioned, the GaN E-HEMT is by
since the input voltage switches polarity, and the MOSFET- nature bidirectional, with no reverse body diode. Swapping the
based bidirectional switches are causing losses due to the bidirectional MOSFET switches with GaN E-HEMTs would
forward voltages of the body diodes or external diodes. give a simpler structure, with only one gate at each switch,
and the conduction losses would be substantially reduced
B. The use of GaN in bidirectional PFCs due to the low on-state resistance. Furthermore, swapping
all the switches to GaN E-HEMTS, the switching frequency
And so to where GaN comes into the picture in bidirec- could be increased, decreasing the size of the high-frequency
tional PFCs. GaN HEMTs or e-HEMTs have the potential transformer and inductor. Xue, L. et. al. (2015) made a DC-DC
to improve the bidirectional PFCs, e.g. solving some of the DAB with a peak efficiency of 98.2% when operating at 1 kW
issues mentioned with the PFCs and otherwise compressing and 500MHz. Regular MOSFET-based DABs are operating
the physical executions of these converters. One example is around 100kHz, so this would mean a substantial decrease in
how the switching nature of the cascode HEMT make them the size of transformer, inductor and filter.
ideal for the totem-pole PFC when operating in TCM; the
turn-off losses of the cascode GaN HEMT are minimal and IV. C ONCLUSION
the converter achieves ZVS turn-on. Combining that with a
very low on-state resistance of the GaN HEMT and the losses This paper has discussed and evaluated GaN technologies
of the converter become astonishingly small. Liu, Z. et.al. and bidirectional PFCs, and their joint potential and present
use. The cascode GaN HEMT is looking the simplest solution [15] W. Saito, M. Kuraguchi, Y. Takada, K. Tsuda, I. Omura, and T. Ogura.
to a GaN transistor, but with difficulties affiliated to com- Influence of Surface Defect Charge at AlGaNGaN-HEMT Upon Schot-
pactness and high turn-on losses. However due to the ZVS tky Gate Leakage Current and Breakdown Voltage. IEEE Transactions
on Electron Devices, 52(2):159–164, feb 2005.
turn-on of the bidirectional totem-pole, this seems a promising
[16] T. Mizutani, Y. Ohno, M. Akita, S. Kishimoto, and K. Maezawa. A
combination. Other GaN transistor technologies, such as the study on current collapse in AlGaN/GaN HEMTs induced by bias stress.
GIT E-HEMTs has seen commercialization and are looking IEEE Transactions on Electron Devices, 50(10):2015–2020, oct 2003.
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electronics context, and because of that the prices are high and GaN-based power transistors for renewable energy applications. In 2012
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Appendix D
D.1 Modulus Optimum in current loop

D.1.1 PI controller parameters

Choosing Ti,i = L/RL and implementing to (4.21), the open-loop transfer function
can be reduced to:

Kp,i 1
Hol,i (s) = · , (D.1)
L s · (1 + Tsum,i · s)

giving the following closed-loop transfer function:

iAC (s) 1
Hcl,i (s) = = . (D.2)
iAC,re f (s) 1 + K · s + LT
L
K p,i · s
sum 2
p,i

Comparing (D.2) to the standard equation for a second-order system, which is

1
H2.order (s) = , (D.3)
s 2
1 + 2ζ ωs0 +


ω0

expressions for the relative damping ζ and the resonant frequency ω0 can be found
as

137
 s s
1 L Kp,i
ζ= , ω0 = . (D.4)
2 Kp,i · Tsum,i L · Tsum,i

√
In modulus optimum, it is common setting ζ = 1/ 2. [40, ch. 3.2.3] Implement-
ing that to (D.4), an expression for the proportional gain can be found, giving the
following controller parameters:

L L
Kp,i = , Ti,i = . (D.5)
2 · Tsum,i RL

D.1.2 Current measurement filter design with Modulus optimum

As explained in section 4.2.2, the integrator time constant limits the ripple of the
control signal, in this case d. The control signal ripple is caused by the proportional
gain on the measured ripple. Acknowledging this and neglecting the integrator
part of the PI as well as the reference current, which has no ripple, the following
expression can be obtained based on figure 4.7 and (4.15): [40, ch. 3.4.1]

dripple (s) 1
= Kp,i · . (D.6)
iAC,ripple (s) 1 + T f i,i · s

Based on D.6, the amplitude of the ripple can be expressed as follows:

1 1
dˆripple (ωripple ) = Kp,i · p · ∆IL (ωripple ) . (D.7)
1 + (ωripple T f i,i )2 2

Substituting the expression for Kp,i in D.5 into (??), an expression for the duty
cycle ripple can be given as follows:

L 1 1
dˆripple (ωripple ) = ·p · ∆IL (ωripple ) . (D.8)
2 · Tsum,i 1 + (ωripple T f i,i ) 2
2

It is stated in [40, 3.4.1] that the control voltage ripple amplitude, in this case
dˆr ipple, should be kept at values between 0.04 and 0.08, to avoid the controller
itself generating harmonics while still limiting the delay of the filter. Solving (D.8)

138
Figure D.1: Graphical solution of current filter time constant T f i,i with Modulus optimum.

graphically at switching frequency ωripple = 2π fsw and choosing dˆripple = 0.08 for
fast response, as shown in figure D.1, the filter time constant is found to be:

T f i,i = 2.4µs .

D.1.3 Simulations

Implementing the deduced parameters to the PI controller and the current filter,
simulations could be performed for the current controller. Figure D.2 shows the
waveforms through the current controller throughout one mains cycle. The figure
shows that the rectified actual current imeas is not able to follow the reference
rectified current iref, with measurement error ierr varying from 0 to 0.6.

139
Figure D.2: Current controller waveforms over one mains period with Modulus optimum

140
Appendix E
Implemented Simulink model

141
 Figure E.1: The complete totem pole converter implemented in Simulink.

142
Figure E.2: The gate drive and totem-pole bridge.

143
 Figure E.3: The the totem-pole bridge implemented in Simulink

144
 Appendix F
MATLAB code

F.1 Controller tuning script

2 % Chosen p a r a m e t e r s
3

4 Vac = 2 3 0 ; %V
5 Vacpeak = s q r t ( 2 ) ∗Vac ; %V
6 Vdc = 3 4 0 ; %V
7 Vdcmax = 4 0 0 ; %V
8 I a c = 1 6 ; %A
9 I a c p e a k = s q r t ( 2 ) ∗ I a c ; %A
10 Pac = Vac∗ I a c ; %W
11 fsw = 90 e + 0 3 ; %Hz
12 wsw = 2∗ p i ∗ fsw ; %Hz
13 f g r i d = 5 0 ; %Hz
14

15 K i r i p p l e = 0 . 2 ; % peak−t o −p e a k c u r r e n t r i p p l e f a c t o r
[%/100%]
16 K v r i p p l e = 0 . 1 ; % peak−t o −p e a k s w i t c h i n g f r e q u e n c y
v o l t a g e r i p p l e [%/100%]

145
17 I L p e a k 2 p e a k = K i r i p p l e ∗ I a c p e a k ; %A
18 VCpeak2peak = 2 0 ; %V
19 Kvdc = VCpeak2peak / Vdc ;
20

21

22 %Base v a l u e s
23

24 Vbase = Vdc ;
25 I b a s e = 16∗ s q r t ( 2 ) ;
26 Rbase = Vbase / I b a s e ;
27

28

29 % Component d i m e n s i o n i n g
30

31 L = 0 . 2 5 ∗ Vdcmax / ( I L p e a k 2 p e a k ∗ fsw ) ; %H
32 C = 1 . 8 e −3; %F
33

34

35

36

37 %% CURRENT CONTROLLER d e s i g n u s i n g P I and SYMMETRICAL

OPTIMUM
38

39 %Base values
40 Vbase = Vdc ;
41 Ibase = 16∗ s q r t ( 2 ) ;
42 Rbase = Vbase / I b a s e ;
43

44 %PU p a r a m e t e r s
45 Lpu = L / Rbase ;
46

47 %Time c o n s t a n t s and g a i n s
48 Tpwm = 1 / ( 3 ∗ fsw ) ;
49 f c i = 1 0 ˆ ( − 0 . 8 ) ∗ fsw ;
50 Kfi = 1;

146
51 Kregi = 1;
52 T f i = 2 . 7 e −6;
53 Tsum i = T f i +Tpwm ;
54

55 %S y m m e t r i c a l optimum
56 b e t a i = 1 / ( 2 ∗ p i ∗ f c i ∗ Tsum i ) ˆ 2 ;
57 T i i = b e t a i ∗ Tsum i ;
58 Kpi = Lpu∗ K r e g i / ( K f i ∗ s q r t ( b e t a i ) ∗ Tsum i ) ;
59

60 display ( Tii )
61 d i s p l a y ( Kpi )
62

63

64 %Bode p l o t
65 H o l i = t f ( Kpi / ( L∗ T i i ) ∗ [ T i i 1 ] , [ Tsum i 1 0 0 ] ) ;
66 % bode ( H o l i )
67

68

69

70 %% CURRRENT CONTROLLER d e s i g n u s i n g P I and MODULUS

OPTIMUM
71

72 Rl = 10 e −03; %P a r a s i t i c r e s i s t a n c e o f
73

74 %Base values
75 Vbase = Vdc ;
76 Ibase = 16∗ s q r t ( 2 ) ;
77 Rbase = Vbase / I b a s e ;
78

79 %PU p a r a m e t e r s
80 Lpu = L / Rbase ;
81 Rlpu = Rl / Rbase ;
82

83 %Time c o n s t a n t s and g a i n s
84 T l = L / Rl ;

147
 85 Tpwm = 1 / ( 3 ∗ fsw ) ;
86 T f i = 2 . 4 e −6;
87 Tsum i = Tpwm+ T f i ;
88

89 f 0 i = 1 / ( 2 ∗ p i ∗ s q r t ( 2 ) ∗ Tsum i ) ;
90

91 %Modulus optimum
92 T i i = Tl ;
93 Ks = 1 ;
94 Kpi = Lpu / ( 2 ∗ Ks∗ Tsum i ) ;
95

96 display ( Tii )
97 d i s p l a y ( Kpi )
98

99 %C r o s s o v e r f r e q u e n c y ( c u t −o f f f r e q u e n c y )
100 wc2 = −1/(2∗ Tsum i ˆ 2 ) + s q r t ( 1 / ( 4 ∗ Tsum i ˆ 4 ) + ( Kpi ∗Ks / ( Lpu
∗ Tsum i ) ) ˆ 2 ) ;
101 wc = s q r t ( wc2 ) ;
102 f c = wc / ( 2 ∗ p i ) ;
103

104

105 Bode p l o t
106 H o l i = t f ( Kpi / L , [ Tsum i 1 0 ] ) ;
107

108 bode ( H o l i )
109

110

111 %% V o l t a g e c o n t r o l l e r d e s i g n u s i n g s y m m e t r i c a l optimum
112

113 %PU p a r a m e t e r s
114 Cpu = C / Rbase ;
115

116 %Time c o n s t a n t s and g a i n s

117 f f i v = 2 0 ; %F i l t e r c u t −o f f f r e q u e n c y
118 T f i v = 1 ∗ 1 0 ˆ ( − 4 ) ;%1 / f f i v ; %Time c o n s t a n t

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119 Tsum v = T f i v +2∗ Tsum i ; %Sum o f d e l a y s
120

121 f c v = 5 0 0 ;%1 0 ˆ ( − 0 . 7 ) ∗ f c i ; %V o l t a g e l o o p c u t o f f
frequency
122 Kfiv = 1;
123 Kregv = 1 ;
124

125 %S y m m e t r i c a l optimum
126 b e t a v = 1 / ( 2 ∗ p i ∗ f c v ∗ Tsum v ) ˆ 2 ;
127 T i v = b e t a v ∗ Tsum v ;
128 Kpv = Cpu∗ Kregv / ( K f i v ∗ s q r t ( b e t a v ) ∗ Tsum v ) ;
129

130

131 d i s p l a y ( Tiv ) ;
132 d i s p l a y ( Kpv ) ;

F.2 Filter graphical solver

1 %−−> F i l t e r t i m e c o n s t a n t ( B e l o n g s t o
T o t e m p o l e s c r i p t . m, which n e e d s t o be r u n f i r s t )
2

3 %% C u r r e n t c o n t r o l l e r w i t h Modulus optimum
4

5 T f i s t e p = 1 e −10;
6 Tfimax = 1 e −03;
7 T f i v e c t o r = 0 : T f i s t e p : Tfimax ;
8 m a ripple = zeros (1 , length ( Tfivector ) ) ;
9

10 for i = 1: length ( Tfivector )

11 m a r i p p l e ( i ) = 1 / 2 ∗ K i r i p p l e ∗Lpu / ( 2 ∗ ( Tpwm+ T f i v e c t o r
( i ) ) ∗ s q r t ( 1 + ( T f i v e c t o r ( i ) ∗2∗ p i ∗ fsw ) ˆ 2 ) ) ;
12 end
13

14 close all
15 figure

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16 loglog ( Tfivector , m a ripple )
17 t i t l e ( ’T { fi , i } graphical solver ’ )
18 xlabel ( ’T { fi , i } [ s ] ’ )
19 ylabel ( ’d { ripple } ’ )
20 s e t ( gca , ’ f o n t s i z e ’ , 1 8 )
21

22

23 %% C u r r e n t c o n t r o l l e r w i t h S y m m e t r i c a l optimum
24

25 wci = 2∗ p i ∗ f c i ;
26

27 T f i s t e p = 1 e −10;
28 Tfimax = 1 e −03;
29 T f i v e c t o r = 0 : T f i s t e p : Tfimax ;
30 m a ripple = zeros (1 , length ( Tfivector ) ) ;
31

32 for i = 1: length ( Tfivector )

33 m a r i p p l e ( i ) = 1 / 2 ∗ K i r i p p l e ∗Lpu∗ wci / s q r t ( 1 + (
T f i v e c t o r ( i ) ∗2∗ p i ∗ fsw ) ˆ 2 ) ;
34 end
35

36 close all
37 figure
38 loglog ( Tfivector , m a ripple )
39 t i t l e ( ’T { fi , i } graphical solver ’ )
40 xlabel ( ’T { fi , i } [ s ] ’ )
41 ylabel ( ’d { ripple } ’ )
42 s e t ( gca , ’ f o n t s i z e ’ , 1 8 )
43

44

45 %% V o l t a g e c o n t r o l l e r w i t h s y m m e t r i c a l optimum
46

47 wcv = 2∗ p i ∗ 5 0 0 ;
48

49 T f v s t e p = 1 e −8;

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50 Tfvmax = 1 e −02;
51 T f v v e c t o r = 1 e −6: T f v s t e p : Tfvmax ;
52 i c t r l r i p p l e = zeros (1 , length ( Tfvvector ) ) ;
53

54 for i = 1: length ( Tfvvector )

55 i c t r l r i p p l e ( i ) = 1 / 2 ∗ Kvdc∗Cpu∗wcv / s q r t ( 1 + (
T f v v e c t o r ( i ) ∗2∗ p i ∗2∗ f g r i d ) ˆ 2 ) ;
56 end
57

58 close all
59 figure
60 loglog ( Tfvvector , i c t r l r i p p l e )
61 t i t l e ( ’ T { f i , v} g r a p h i c a l s o l v e r ’ )
62 x l a b e l ( ’ T { f i , v} [ s ] ’ )
63 ylabel ( ’ i { ctrl , ripple } ’ )
64 s e t ( gca , ’ f o n t s i z e ’ , 1 8 )

151
152
Appendix G
System-level simulations

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 Figure G.1: System-level simulation results at 120Vrms G2V operation.

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Figure G.2: System-level simulation results at 120Vrms V2G operation.

155