0% found this document useful (0 votes)
85 views128 pagesMicroprocessor
PU Microprocessor Note
Uploaded by
Saurav ChaulagainCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
0% found this document useful (0 votes)
85 views128 pagesMicroprocessor
PU Microprocessor Note
Uploaded by
Saurav ChaulagainCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 128
1
| Micxprcessov 3-1-2
——_course_obgectives: Seeeaseeeaaeee a
A) The architecture and oxganization of a Micropmressor ( 2085/e0e6)
=, The basic operations, pmgsamming cmd applica of
3:| The interfacing T/o devices with the _Micrprocetor
4 _Goneept oft The foundation forthe micoprocesser based system clesign
icroprocenor_
_ Chapter’. Brtnduction do Microprocessors:
i _Micnpocersor ts an electinnic chip, that Performs func
_ central Preceding uit (CPU) of @ Computer:
‘The word Micaoprocevior comes fromm the Combination of Ini
__antd _paceasor’ _ sponges ay
> Where micio means small in size and pwceyor is q devite
| thot Perform pret or manipulate numbers, speciticalty binary
—Oumberz (0's and 1's). According to ne _ instwuction_(pregzam)
| Stored in the memory.
—_Micenprocesioys_Centoing_both Combinational tpgic amd sequential
Aigitel Logic
Std. Segiothyn:
___ “Microprceuor_ts a multipurpose, prgrammaple, clock dmiven,
—_|_egister_loaged, cligital integrated circuit that accepts kangny _
=| dlata_cu input, pmceses it accorling to inshuctiong stored
Lip its _memny ood _provicles retutt ay outmt”
an | pavqrammable : __ r _ os __
Perform Liffezont set of operation eo) the _clata dopending-
—100_sthe _ Sequence of iospuctions Supplied by the pgrammer.
| Clock Odeve drives: wiive soya) 0 os
__._iceopmreuor_iz co _ device _which_executer jostuctons in_sequmtial
order. To order to correctly execuke the pregtam instructions,
—|_micrmproceuty__folbws certain steps: Fetch, cade clerwode, £ execute
—| And__inovder_to correctly Follows these _steps , microprocevoy_
Scanned with CamScanner _| Register Based > Storage bued
| needs to “activate _ cliffetent. Components _tn_clifferent
| me. And how cloes_-microprcceyor__ Knoro_when te clo__
what? St Wes Glock:
- Application: teh) tthe
Mobile_phine,
|TV emote Conbo 80835 0
Micmwave oven
Washing machine os OT ee ae
Consumer _clectonic goods _4
Calculators. _
a clustrial_ceotellerz
Computers _ _
“traffic Signal Confoul_ Systems
Speed Contsls Of motors
Electronic & Clecinical_prorects
2 9t advance pplication are Radar, safettites etc-
“Advantage
Prvcesing speed is high — :
Tofelligence has_beeo brought to systems
Flexible
Compact size = — ae
Say malntengace oe ee =
Complex _mathamattes. : ee
Scanned with CamScanner Sisncwortage:
Overheating occurs clue +o oversye
Performance _clepesds 0) sixe of cata
Large _ board size than _micncanbo|lers a
| Most _micsopaoceyor —ch_oot_support Floating point operations.
Compulers Cenleal_proceuiog_unit (crv) built ona single. toteqraled
_cinut( te) 1S_catled q microproceyor —_
The _mlcrpseceyor _ cx
optaing millions ef Hy _companestz_Like |
L — | Tnnsicoss, registers, and clisdes that nase togeiner
/ The MP isthe “brain of the micevcomputty’
Ord Addauing: Ae Feats
_ Given M_Worell CAocation to acceu), how many bits tare
Tequireds to aobrey them?
- A= 409m —
—&: 10 addres came, we wed
A= Leh, (642% 2") = Ang, (2542! 99) =
Concept of Bin &Hex_ =
0000 ° OH” 0000 _00H > ©6000 0000
O00 1 4n ool : .
dec Hex wre Bin ae y “Babs
—Tritk_ e4og 7
0010
FEW Sn
Ete =
ate its
oo) tele
"OOOOH Steir ana 000
foot
~— ERR HSinitmnny
wo Beara FH ee |
16 Com Abits Nibble = Gait
Scanned with CamScanner | gs2 30
Power oF Qo
grat :
oss
gre
Bz 8
ez 16
64
2x2 a
ghx gl? =
lex gl0 = LK x AK
axgre = 2M
2 exere = 4M
1G
2
dl
gy 28 = acxtg = iT
a 2 a xo%? (227 -
— = ee ‘= iP iii
a = axa? = 20 +
Scanned with CamScanner _ Read sigma {waite operatic? ;
| Te Croho iz reading)
{ y
Hue
ASM pit
LLL/ME /obs /Bin_ ¥ & Assembler
ott compter_
converted) 10 Machine language
a Com er progr 40 _Convorteel_ to Machine language,” iE the there i$ an
_evnv_ it Cap not be temple so tt throws fer ern
Scanned with CamScanner so
: _ a
ry instruction has its own” “op
shyly cycle!
__|_ Fetch - Sle
© | Becedte”: uoderstanding ef opcode
execute ne -
ee Memory
Ceroceuor) |e 2
uP cet
— ASM,
App
[sve a Pc
| a MUL
~T Div =
Scanned with CamScanner 1 BS a fe
CUAL “tohncuction to Miceprocessor
i {4 4:1. Evolution of Micxnproces gov
2 Transistor war Invented Ip 194@ (23 dec, 1947 in n Gell lab)
2 te Was Thveoted to 1958 (Fairchild semiconductor2) Gy Texas
Inshunents J Kilby. _
We Can calogerixe “the AP according _ to the _ _geoerationg |
Or asconsing tothe Sixe of. the wp.
{| The eat emo ae wat infduced in 1971 by Intel corp:
_St_Wwas named Intel For each instruction,
this cycle zepeat omd hence need two cycle to complet
|_ ap _instuction- ac |
is _vrelatively older aad nos !
| weplace by Howard Architecture:
ie - 1 ]Mfral Procesing unit
: Cophl voit |
| vo) Neumann Architecture. j
J] Memmy unit]
Scanned with CamScanner ‘The CPU ie the aa naire rpansine Seren
the fostuchons of a Cormpubey prograny ——————
St is Sometimes gweferred to gy the mycvponeyor or - proceyor -
The CPU combatns the ALU, CU and_o variety of registexx-
Corl unit cew:
2 “eonhl unit Console. “the operation of +e computer's =
ALU; Memory onc input output levies) te ing. then, hows to _
meIpomd +o the progvam inshuchons it has yust react aod _
| lnterpreted from the memoy unit:
"The Contwl unit ato pawides the timing amel coxtl sig
|. -wequined by the cormpuler-componets:
Actthaett amd_logic_vnrt ie LU)!
i The Ate ALU _abows arithmetic (add, subtract etc) aod
Not etc) operating te be carried out:
Registers: -
L Register are hjgh Speed Storage a areas ip) the ceu-- Al| data must be
Stored in a _wegister before it cap be sprocessect.
2\ The variow models of u
_| MemunyAAddrey Register CMAQ): 91. Storer the Jocatitas ef inginucitor
_that need tr be fetched from memory er stored int) memory. _
27 Holds the meimery location of dota thet geeds to be acceyed-
_| Memory Guster Register (MBR): Helde=eatetite Ot Storer
=Loshuctions fetched. fromm memory or any. clata that ie to be _
transfered _t0,.00d_stored in, memory. te
Holds hata thou 4 belng- transformed” oof fmm_memmry.—
Ls
Tpshucto see CR): Cosytaiins the ~Seereat Jockin tog
ian — — fo
Scanned with CamScanner pPUYram Counter (PC): contains the addrey tthe Oe
losbuctton to be executed
by ALU-
|
}
|
| Accumladr (Ag)! Stores the rejuths of calculations rade +
fh q
| t
Toshuctin Buster Register CVO): _,pnarA
Used to ‘Temporary hold the “inshuchoo from the Word
|
J
iy memory -
— Memory verbs
ThE Memby unit Consists ef RAM, sor
Primary _ or main memory
2 _Uplike a hard daive (
_ addres and its combemts Looth in bingry form) - _
The addrey voll] uniquely identify every _Location_in the
memoye
Loading clata Foon pesnanent_memey_ thard drive), into
the faster and direct accenible temporary memory RAl
___| Ieput/oviput devices:
4
|
|
. | allows the CPU to operate much quicker. ;
4
|
program or data is wead into main memoy — form the input
olevice - 07 Secondary sterage under the contol of cpp input
inshuction- Olpuy_clevices are wed to _oupu the informed
fron. Computer. 9F Some results are evaluated by 4.
Computer and ibis shored “iy the: computer , then roth
“te help of output devices, we can present. it +p the.
Scanned with CamScanner originated from ‘Hayvard Mark 1’ @ relay _
basect old cormputers: _ anes Paneer eal a Sak Penne
| Harvaed Architecture ig the computer gechitectyre that cagtaias |
Separate Sterage amd separate lower for tostruction_aad_data-_
34 was _asicatty oleveloped to _ovextome the bottleneck of
-1 Von. Neumang. architecture, wi
ia The Main adventage-of having separate busel for. inctmehioo
994 cata is that CPU cae) acceu_instuctons_amd_read/rrite|
_data_at the same time: __ es
Addreg,_ nn Prt Memey Addrey Gus
Sse Os SSG |
Saka Nemsy Addres Gus
REBT unit | [ALU] [Hartearl | Aare
— _ [ewnhot ote lel
Progsam Meme Baha Bus
“abe MUX
Ee Ada Memoy Saia_6us a
$ig- Harvard Architecture . -
There ore -+wy data god twp addrey byes multiplexed fox
—daka bis and _addrey bus. Hence, there ore tWD blocks of RAM
chips: oe for. peogram merry oad _ayether for. -data_memory |
addretes. ee 7 2 - a
Th_Conbnl unit _Contwls the "sequane- ef cperatins.
| central ALU consists of ALU, wultiplier, accumulator 299d _Scabing-
| chief register:
: | The pc_is wed to addrey_program-.memon and always centaing
the _addrey of next instuchina +o be. exeathed.. -
Here, cata and contml bine are bidivectisnal qed actives buy js
UnidirecHonal - i
Scanned with CamScanner Harvard Architecture
gt this name _is originated fro
‘Harvard Mark 1’ a relay based
old Computer 9
ries FOr
| theiy_ instruction. programy) an;
| data. -
| Qitperemce between Harvard and Von -Neuman
|
1 Anchitecture:
von Neuman Architecture
oF ts named aster the
| mathematician and ealy Compute
_| Scientist .Toho_von_Neumann-—_
based on store prograry compulss onc
i) Harvard architecture is vequired
3] _Proceuer cap complete _|
__| aa -tnstouction_in_one_cych
“Clvp| -Satian of Hayward Architecture _|
__lis complicated.
| Sepqrate bu fey _instuckn and |
dota. = it
(Gi) Von- Neumann architecture 1s
| required only one lous tor inshucti
land lata.
om procelior_ deeds two clock
| cycles to Complete _aa_instuct
bin Seiign for of Ye Von: Neuns
itecture__ig_simple-
VW) Low performance a4 compare
Cy | Easter to. Pipeline , so hi
____| pexformance can be _achieve-| to Hayward Architecture. 4
— _ :
wh Comparatively. high cost (vi) St ig cheaper |
(vi | Used). in Laptop, personal (Vil) Used ig_micicontrnller and _—
1
Computer_and_Work steHon
Signal _procening
| Tho sets of mmomby aod
bwes_megn__daka can be_|
Vili) Speed is gimited: wher
| Compared to Harvard clue te
handled more: quickly which
only having one memory _
_decreming | location and Set of. louses-—
aa
4
Scanned with CamScanner x) Use esc proceuoy,
_| (Reduced tnchnckton set Gompuies)
More Space is required jin.
Harvard Architecture
Geo use cisc_ proceuor
(Gompley Soshuctin Set Comp ute)
[2 bea Space ig requir
Von Neumann. archifecture-
. — progam] | [|
memory |
ei ot Hef cs |_| procenor
__| Proceuor ine
J_sata_|
rf K——>} memory
L L | = Some
‘Ceohal Piece oi a ~ AW. -
i [compol uit [|| A {>
Tar Ll [art ar a a
ay [Asithiette /ai Pek Confoo! Unik KY
Tio | :
te
fig. Harvard Model
T Memoy Unit
Lve Von Neumm Architecture
Scanned with CamScanner £3. 3+| Micanproreuor, aod Microcontroller > - ———
7 7 Microproceucr _ " wiaweanholley.
Apelicalin | ot lased where infensive
| Processing 14 aqeauired: 9+ is
ued io persona Cormpulers, _
Laptops, mobiles , video games etc.
Shieture |: 9b hay only the cpu _lo-the | Memory, Tip port and att thes
_____|_ chip other ctevices tke __| ceh_a22 Copnected)_on “the St
Tyo port, memoy, timer is Single chip.
_| comected_externatly- —
: The shucture of up is flexible The stwucture ig fixed once i
| Uses can_clecide the amount | 14 eltsigned the wee cannct_chan
| the peripheral _clevices:
! The Clock Speed of the |: The cl Cleck speed of mi microtontnl
| wei UP is high: 9b is in Htzms| ig les. 9b is in teams of “the Mit
Of the GHz- 4 ra0ges St ranges between dMHz to S00 MH
| between 4G@Hzto “GHz. |
— j
RAM =| The volatile memoy (RAM) for_|: The volatile ile memory (RAM) fo
|+the up is in the ramge of the, UC jothe wange of 2K to 25¢h
542MB to 32G8-
hThe hard ative or flash memory lf
____| be. changed. for cUffernt |
_ | applicaHtone. The programming
_| of the YP 18 olifeicult Compared |
+o the UC
Scanned with CamScanner 64 bit and ag-bit - nn
cost © The cosh of Up is high compared |. 9+ is cheaper _
tothe ue
Power The | Power Consumption Hel
‘a 4p high |
| size: _The_ovetal ‘size of the system]
| is barge
Small
Have power Saving modes Like
Power |: 80 aot “have power Saving |:
ae | Fecuturey, ” Idle mode and power Savigg mode.
ues . Thisheles to reduce power Consumer
Jonly]__ \Read-ws even Further-
7 Tienes | Mensey
| r
: —— _
[ attcroppncene = ihe Microcenhalle| Read only |Read vorite
a L Memory Memory |
[rimer Xo | timer__| To port "| serial »
[ Pov . a I ]
F1g: Block diagram ef UP Figi Block cagran oF MC
Scanned with CamScanner — 14 A Toternal architecture of @ bit micropeocoyor SOBs _
1 The archibecture of Bors up iz shown below
Microprocessors ‘chapter 2: Programming with 8085 Microprocessor
Chapter-2
Programming with 8085 microprocessor
chitecture of 8 bit microprocessor and its registers:
'® complete 8 bit parallel central processing main components of
085A ae array of registers, the arhmetic loge unit, the encoder/decoder, and Ying and
‘Onteo circuits linked by an internal data bus. The block dlagram is shown below:
som ™Ther 39 99) so 800.
AT iif
weet Comal Seid ¥0 cane
: Gi ‘a3
7 a 7 7 5
roi | De Ss
= Ea Seah a
a : aE
mn eaee
ese eae | | peta.
cn ee atte iN
y ray |
mo ES TT LESS
Somers
eee L ‘nao a
: eee
LTT EE
Fig The £0854 icroprocssor Functional Blk Diagram nln elt on
Scanned with CamScanner Gil) tofernal hata bus
w Registers : 4
do Arithmetic & Logtc usit ALU __
Gi) Timing & comtrol_circuitey
Won Instuction decoder_and machine cycle encoder -—--
aw
@) Serial r/o_ conta) _ ——
WiD Addreu Butter and _ Addzeis (ata kufere
__ © Registers: :
| @_ Accumulator ‘os Register A: x
| S085 up is geiccurmutater based pevceuoy-
21 OF 1K om B-bit programmable register which tg Wed to..
accumulate the ficou result of any ALU operations-
JF ik one of the +wo operands of ALU amd ig as) _
implicit ope. |
27 Any dota input /outpur to /favrm the Jap fakes place via the
1. accumulator
in|
TL _St ls genemuly wed fer temporay storage of data aod for
| the placencot of final wecult of azithmetic/ logic cperations-
& Temporary Register Clo aad z):
ia Ther ane 3% temporary vegister ay operand of ALUCT) and wez-
register. atin
i] These vefisters are wot available to ne | programmer, _ bet
1 Wes them internally to held temporary lata _ luring: execution
Of Some costes
wo "Genera purpose wegisters
the gemeral purpose registers are 8,C,D,E, Hand ue
They gre all @-bit’ register but Cao alto be Used a3 16-
~~ Scanned with CamScanner ‘register, poles = BC, DE amd HL
Prgrammable vegisters -
TEAC register gre Wed tn Programming. sa camect
back, | Pointer csp! sea »
B+ 1B the 16-bit wegister Hat holds “the add re55
the top location of +he stack: _
The Stack }4° 0D -area of Q/w Memory in Which
| temporary Informahon ig stored n= Firstly tast out
Cor Last in First out) basis
25h incremented /clecremental during Push aed PUP
operation
| on eve PUSH SP get decremented « on every PUP
| sp get incrememb 4
| Pavgsam Counter CPC):
St js _Q 16-bit wegister that holdg the adden
Of “the _mext _loshuchn te be executed: 4
| As the _pepceuor executes instructions ope _ after _ainthet,
“He. PC is incremented —"Hhe Humber _by which
| +e PC__ineremants dopemds on -the - nature _of “the
tosbuction __
‘for a L-byte inshuction PC is incremented
by L a for_.q_3- byte inchuction, the pmceuo™,
| incsements PC by 3 addreu \natioos. _ = |
i
Register BEES
a OL 1h Gn __@-bit wegistey_in_whith five bit positioes
Lcontain the Status of five Condit Flagg which
are Xero Z), Si9nls) , canyter)., en \e) aad
_puxilasy carry CAC)-
| Each of these five flags ic q 4 Abit Eze
The flag -wegister format ts — shown
Scanned with CamScanner : [> De_ Ds Dy Ds Do Dy Do
= 1s Z[- [AC ~ iP ei [er]
wT. Flags ae Set or west according + to+
@ Apshuction Register (te) | _
= Shia 16-bit - WStey that holds the addrey of the next _|
inshuction +0 be executed:
_ St 16 wot _acceuille to >the programmer.
7 St _meceives the operation codes. of .inshuchon frm interoal |
lata lous and paties tothe in shuction. decoder which
{ deades So that UP Knows Which sai operation _
| ig tebe fetched.
= ee
@) increment /decremest addrey latch register:
‘| This 46-bit wegister_increment/devements +h contents
_of Pc or sp Wohen ingtuctions gelahed te therm are
! executed:
CW) Arithmetic & Logic unit CALU)!
“| The ALU perfoomg -the actual numerical and Logical cperatinn
| Such as add’, ‘subtract’, ‘AND’, ‘oR’, etc
ot Alu_coosists of accumulator, Flag zegister_and temporary resist.
Ti aetna came mmamnay ond fun sacctdat 40 pester —
—ithe awithmantc 2 fogic_operativns and always stores the 74
Of the mpervaton in accurmulater. HN
HD) Tiroing and control unit:
271 The cootn| unit generates signals voithin up 46 cory out-tty
L_toshyction which ha been decoded.
| 39 reality, It Causes certain connections between dock of
the MUP +o be opened or closed, so thal “the sata goch
Where it is required and the ALU. operations occur.
Scanned with CamScanner _ Addreu. buster and Sala/addres buster: _
=| These _vegisters _hyld the addres |loda, received fron
-| Wohermal_ dasa bug and then loaal toe external adel
Cate buseg.» = SES se
These _segisters actually bo behave a the buggers 1
betwen the _MP_- and external system buses: —
Internal Saka buy (#-bit) i
| St Th wed forthe inter comection of different operat
Unite of UP. ie the proceuor uses “this bus for transfervi
la data from _one_segister to another register, A
—_|4o_register etc _within-the UP
Serial To Contr! ! a
|_ serial 1 T/o__Contry| provides “tno Vines. 4_sop and SID- > for
| Sextal Communicat oo: B=
| The Serial output data Lsop) line is wed +o se A
|_clata sevially amd__sextat_input_. dlocka tine. Usp) i
to __wecetve cata Serially:
: | Interrupt. control oa
| Qt & an obstacle ¢ ye to
St sent ly chiffexent devices to take cpu sime fo
| Particllan device -
:1 The interrupt” Signay aw #InTe, RST S5, RSTE-5, BETAS
ai has pa
Some __time _to_pexform_a specific task +5 Of that
a
TRAP od oe ackxowWledge sigoal_ INTA
| flods
a
Tnshucton decoder & Machine cycle Encoder: 4
The TR sends the machine code +o this unit a
Thly_upit, as ts name suggests , decades the opcode _and— A
et hshat i to be “done _in response _of the
| Coming opcode and. how | many Machine cycles ar. a
required +o execute thig inshuchon
Scanned with CamScanner |
45 #| concept of fetch, decode and execution! Iostructoo cycle)
—The.._.Sequerxe_of_steps__in_which iostrushiong are
loaded fmm memo & executed ig cated instruction cy
This cycle describes +he proces of execution. _0f _an_inshruckis:
| boithio the computer:
Lone wound of steps pam getting an ‘nstruction back _
to_getting the _mext instruction is catted inctction cycle: _
Get a5 lnchuctiop frm main memory _ Z
xanslate_it into computer commands,
* Execube- Actually process, the Command
»_-peried 40 complete inctrichion
Fetching, decoding, and_executiy cyche om the basis of
Clock speed - Such time period _'4. cabled ‘instruction cycle’.
ime _wequired +o complete execution of an instruction.
Shpz, dewde Tnghuctione toto Compubes steps: Execute Commands
seo _-Acotl uit | [Atv ster:
Feich Seessegelissaemery
inshuchy | Main Memoy fa!
Fer memoy amstauction —_
FQ: a cycle.
Fetching!
___1 |The cpu veads the value PC_and the inshuction ig Gapied
into the inshuction vegisteY CLR) -Thig pxycou igvolves Following
Steps:
4: Copy the contents of PC into MAR
2: Copy +he data fmm the memory to MBR
3: WStuchon 4 copied into IR ;
Ashes ampleting +he above steps -the valuo of Pc is
——incremented _and_it Porats the adden of next \nchuchen-
ail
Scanned with CamScanner Decoding: = : i
decoding means +0 activate. the apprpriate clreuit 40 eeu!
she lostuchtons me
After completing: “the Rekch. papress the cu decodes -
loshucion by andy xing the opcode _of the. Inshuckion -
—__| Ste Instruction -
_i | Cu allo weads +he_value of operands. Specified in the 1
Execution 4 2 Storage:
{| The process. of Restoring Anstey onthe decoded
—|_inshucton_ jg called execution —_
After clecodi CPU_exetubes the instruction ler
Wing the activaked circuit.
Lape execution the 1 regults are. “copied ints’ the _
regi stex_and_ memory:
le Sete
CECE Por
“Fetch cycle |
i yg EXECUtON cycle
anetnetion < eycle
| __fig_ Tostuctinn cycle _
Scanned with CamScanner at Flags in Goes
{A ¢lag ig a giipplop. -
che indicates Some comditiong prpclyced by the execution
OF am instuchon P :
a The Flag wegister of Sogs UP consists OF 5 Flage
:{ The Flag register is connected to ALU
2) Whan_on_operadion ig _pesformed by ALU the result ig
| transformer transferred on data lous cmd Status of
| Pesut _boill be stored in _ Flip Flope - a
_They_ave_catled Xerox) , Carry’cy), Signts), Parity CP) aod
|auxillagy camy CAC) Flags bh taal -
The UP Uses these flags to Set aad test data conditiong-
The flag wegister format is shaon in fi :
| Dy De Ds Dy Da Do Dy Do
fo 25, x | x Tac x |? [x Te)
| __ fig. Fag aegister io goes
<1 The flags ave Stored ip the sit register So that the _
1 Psogrammer Can examine these Flags _by accessing the
wegister through dn _inshyction-
ign Flag (Ss): - _ _ ee
Sigo_flag_lodicates _rohether the _-wesult of a mathematical
Operation ig negaHve or positive:
Sf the MsB orDzbit of the senult of ap operation is 4, this
|_ flag ig Set, Otherwise it is ese}. ie Jf D=1, S=4 CNegative)
oF tegical _
_| operation ig zero or no} a
GF the recult of the current. operation ig zero, then this flog will
be_ set, otherwise veset 0 ae
Scanned with CamScanner | Auritlny _cany CAG Flag!
11 96 there ts 9 camy out of bit 3 and intobit 4 resulting.
| $20m_the _execution_of ao__arbthmetic operation itis Set
otbenvise reset-_ Cyt tt tad
= ey at
Dy De Ds Dy ‘Do De Di Do
cte programmer
an even numbers of 4S amd reset otherwise _
This Slag 4 wed for Bcd operahwn and is not free a
j
=
This__¢lag_is_Set when -the result of an operation comlainé. A
ae |
Carry (cy) flag: is
___| then this Hag is set, cthenise reset
€g: Awe |
11 Qf am_insthuchon results _in_Q_carry (tor addition operation)
|or. borrova_( for Subtraction or comparison) Our of bit Da .
3
asd 9 vegister B hag 44H Ged accumulator ha, 5% H- Theo
fb. at = oto
Al Before Addition) 54H ¢ ofo4
\LAFter Addition) 38H (= toot 100 °
Since Dz is 1, Signo flag ts set le sot
—_|__ Result 18_om zerp_, zero flag is reset ie Z=0.
ie Ac=O
SO
Scanned with CamScanner
___There \_no carry from By into Dg, Acculary flag ip ves —|There ig odd number of {’s in wesult, parity flag is eecet te pzo
——|There_1s_90__carry or borrow out of bit Da , Cary flag is reset,
be Cy=o0
Scanned with CamScanner —— Performed by on _iostuction
Sd mbolicatly , ao_ioshuction_tooke like.
a
2 This the struct
CH-2 Assembly Language Programmi ng
Inshuchon Formats lopcodes, mnemonics and operands)
Sts a symbolic or a weprdentadion of _ any
loghuchons -
J AD lostuction consists of an. een code, an opsode)
ad the address ef the clata (called operand) , on Which
ithe opcode operates.
0n Which an, instmuctoo te based. _
The opcode _ specifies the mature of the task te_be
____[preratin code | Addvesy opaaia 7
|
__|_hex code,
|_Pruceszor What Should be done.
opcode (SFerand -
£035 can hasdle atthe rmasivoum_of 256 (= 2%) lnstruchions;
however. only 246 inshuctions are wed in goxs- 7
The Sheet Which contains all these instructions with theiy_
Mnemonic’, decryptions ard functions is cated an instruchion
sheet.
Opcode: opcode ts _Q Part of instruction that tells. the,
{Sr
OPevaed: operand ix a part ¢ of the instruction - “that contains _
| the data_+p be acted on,
ing wregister.
63: MVI A,B
ox the memory location of the data
here lostructon Myr. ig an » opcode. A&B are eee
ADD RaRo
ner _acrooym/ abbreviation, for operation
9b 16 used in ingimicton code_+to make easy and. Suttable
_ Coding
Scanned with CamScanner 9: The mnemnice are R wed for the register, a
A Fox the accumulator, z fo. xexo slags,
Arp for addition etc:
e_.inshuchion format. ‘can be “classified “into the? catego
W 4 Byle _rostuction : FS
“ie Jo 4 Byte | inghuctiie, ‘the. opcode and. the “operand
-| Qre._in the same byte ie
- opcode /operand |
& ADD B, Mov A,B
iy 2- Byte _Tstruction:
i> 99 2- Byte Ingtuction, the. first byte will “be. opcode
__| and_ second byte will be 2 the operand ox data/ addres
- ‘[orcede operand
69: _MVT C, OFH
A
_3- Byte Tostructin:
= 90 3-@yte instruction, the First byte will be opcode
Second byte willbe Low ower byte of address, and
third byte will. be High order byte of address
_ [opcode Caw order eyte of [High order byte oF]
LXE B, 2050H
1 Specifies What. operativ tobe fertormed
cities bohere “to Pe&form the operat
—_———
rere
Scanned with CamScanner 2A SoRXs Istucpion sete:
4
rn
a1
Iv
v|_ stack, Tyo amd machine. contol group
AY Instruction i a command given +o the microcemprtes
WD Pefom a specific -hask wy functon on a given data:
Am insbuction set is a collecton of instouctions hat
the micvpocersor is Aesignectt +o perforn:
| Fanstionally, the tnstuchions can be clawigied tobe five
gRCUns:
Sata Transfer Ccopy) Group
Avithmetic Group 7
Logical Group _
Branch Grup
Sata Transfer (copy) Group:
This _lpshuction copies clala firm one location _catled
~Source +0 another location catled Aestinahion without
Modifying the comtest of the Source. _ a
The ‘transfer of lata may be between the vegisters or |
between register and memory os bety
ANd _accumylator: J toe
None Of -+hese _tnghyctiong changes _- the flag: _
The lvshuction of these group
|_ Mov MR (Move +
i L- byte inshuction
Mov eae Re (Mov
L- byte instruction
Copies the Confemts of the Source register, +0_destination — eal
Ra &Rs may be A,B GI,E,H and L
Eg. MovA,8 ) A<6
ry fe0m Register)
Copies the contenls of the. _Specitied register - FO memory -
_|: Here memory is the locodion specigied by the content of HL Regisker pair
/Eg Mov @,8
Scanned with CamScanner “Mov RM _ (Move to Register. From Meno)
14> byte logtuchon
‘Copies the coments of memory jocabion a specitied by HL
| register pair to a Register aeettpistett t
Eq, Mov 8,M_ 7
VIR, g-bitdata 7
_ 2- byte inshuction _
F * loads the 9-bit data_ into te pet igi
4 R may be AB, 6 DEH and Lb
Eg Mvr @,54H 5 B< StH
&® “VT. M, 8- ~bit data © Load Memorey_
: Qebyte instruction
loads the g-bit clafa_ to “tne mpernary location dubo.
| _cdldress 13 speci¢ied by the contents of HL register pall
LHUIS 35H
iv
LEg. MVIM,35H }
LXI Rp, 16-bit data (Load Register Pal with Immediate Sala)
1 S- byte jiostuchon
: load immediate 16-bit cata _to_register pair.
: Register _paly_may be Bc, DE HL and SP
iFirst it \oads lower g-bit clata into lower orcler register
aod then loads higher g-bit data into higher order
G
vegister: 7 at
Lg LXI 6, 4532H 5 645, c <-32H
| LDA 16-bit address
3- byte _instuction
Loadz the contents Of memory lowtion whnse address.
ig Specified by 16-bit adolress -
| €g WDA 40354 , AS Wo35hI
Choad. Accumulator Sirect)
7 Scanned with CamScanner er See
|
@ LAX Rp LLoad Accumulator Indirect)
a1 | d= byte jostuction . By -
Loads the comlets of memory location potted by +he
coments of register pair te accumulate. 9 —
=g_Lpax 6; TAI <— Ue
- __STA 16-bit address (Store Accumulator Content Olrect)
i | B-byte instuchon _ aoe seen
: Storez the contents of accumulator to. Specified address
_ i) &g. STA FAOOH ; [FAoo] — LAI
_ Uo) STAX. Ro (store Accumulator Content Inclivec)
= = byte Jnstuction I a sh RS —
Pee the Contents _ “of _accumulater to. -to_memory. ocation. _
Specified by the contents of register pair.
Eg-_STAx 8; [Bc] <—- A
QD) Lat> 46-it address Coad HL palr Sirect)-
i) B-byte instuction aa
loads the contents of specitied memory location +0 “L-vegiste
99d _ contents of Oext higher location to H- _wregist
4: LHLD 5000H_ 5 H= 03, L= 02
4 byte
Instruction
and contents of Hq— Register to ext higher memmy locaioe
Eg. SHLD 20004 ; ovoj=05,Roots= oq [Boece 05
Scanned with CamScanner XCHG _LEXchange Ht pair with DE Pair)
i- byte insbuctoo at
Exchange DE pair with HL Pay a
(een
UE A; F500n
UxE D>; Sbo0n
—= is ii
Reads sata fem the input port addey specifred ip the
Second byte _qad_loads__data_into the accumulator ie, _ —
lgpur port +o accumulator: 2
ae
a
| Sy IN 4on_ y A < Toon
OUT+ S-bit pert addres Lowpuh data to output port)
2-byte lostruction.
copies the comtents of the accumulator to the output.
Port addeeu specified in-the Secomd byte ie accumulator
to output post-
&. OUT 40H ; L4oy eA
Vl ial. Bh
