Noida Institute of Engineering and

Technology, Greater Noida

Introduction to Microprocessor
(ACSE0405)

Unit: 1

Microprocessor
Karan Singh
Assistant Professor
B.Tech 4th Semester
ECE

Karan Singh Microprocessor UNIT- 1

1
2/2/2024
 Evaluation Scheme

2/2/2024 Karan Singh Microprocessor UNIT- 1 2

 Subject Syllabus

2/2/2024 Karan Singh Microprocessor UNIT- 1 3

 Branch Wise Application

• Microprocessor, any of a type of miniature electronic device

that contains the arithmetic, logic, and control circuitry
necessary to perform the functions of a
digital computer’s central processing unit.
• This kind of integrated circuit can interpret and
execute program instructions as well as handle arithmetic
operations.

2/2/2024 Karan Singh Microprocessor UNIT- 1 4

 Course Objective

• The objective of this course is to understand basic concepts of

Microprocessor based systems and able to do programming in
Assembly Language of 8085. They will be able to learn and
program Peripheral IC’s.

2/2/2024 Karan Singh Microprocessor UNIT- 1 5

 Course Outcome

At the end of this course students will able to:

• Apply a basic concept of digital fundamentals to
Microprocessor based personal computer system.
• Analyze a detailed s/w & h/w structure of the Microprocessor.
• Illustrate how the different peripherals (8085/8086) are
interfaced with Microprocessor.
• Analyze the properties of Microprocessors (8085/8086).
• Evaluate the data transfer information through serial & parallel
ports.

2/2/2024 Karan Singh Microprocessor UNIT- 1 6

 Program Outcomes
• Program Outcomes are narrow statements that describe what the students
are expected to know and would be able to do upon the graduation.

• These relate to the skills, knowledge, and behavior that students acquire
through the programmed.

1. Engineering knowledge 9. Individual and team work

2. Problem analysis 10. Communication
3. Design/development of solutions 11. Project management and
4. Conduct investigations of complex finance
problems 12. Life-long learning
5. Modern tool usage
6. The engineer and society
7. Environment and sustainability
8. Ethics

2/2/2024 Karan Singh Microprocessor UNIT- 1 7

 CO-PO Mapping

Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Outcome

ACSE0405.1 3 1 2 1 - - - - - - 3

3 1 - 1 - - - - - - 2
ACSE0405.2
3 1 3 1 - - - - - - 2
ACSE0405.3
3 1 - 1 - - - - - - 2
ACSE0405.4
3 1 2 1 - - - - - - 2
ACSE0405.5
3 1 2.3 1 - - - - - - 2.1
Average

2/2/2024 Karan Singh Microprocessor UNIT- 1 8

 PSOs Mapping

Course
Sr. No. Outcome PSO1 PSO2 PSO3

1 ACSE0405.1 3 2 1

2 ACSE0405.2 3 2 1

3 ACSE0405.3 3 2 1

4 ACSE0405.4 3 2 1

5 ACSE0405.5 3 2 2

Average 3 2 1.2

2/2/2024 Karan Singh Microprocessor UNIT- 1 9

 End Semester Question Paper Template
B.Tech (Semester IV Theory Examination 2021-22) Total Marks : 100
Note: Attempt all sections. If require any missing data, then choose suitably. Time: 3 hours
Section A
1. Attempt all questions in brief. 2 X 10 = 20
Q. No. Question Marks CO
a. to j 2
Section B
2. Attempt any three of the following 3 X 10 = 30
Q. No. Question Marks CO
a to e 10
Section C
Question no. 3,4,5,6,7. Attempt any one of the following 1 X 10 = 10
a 10
b 10

2/2/2024 Karan Singh Microprocessor UNIT- 1 10

 Prerequisites

• Basic knowledge of digital logic gates

• Knowledge of Boolean Algebra
• Basic concept of Flip-Flops

2/2/2024 Karan Singh Microprocessor UNIT- 1 11

 Unit Content
• Course Objective • Example of an 8085 based
• Unit Objective computer
• Course Outcome • Instruction and data flow
• CO and PO Mapping • Timer and timing diagram
• Topic Objective • Interrupt and Machine Cycle
• Prerequisite • Addressing modes
• Introduction to Microprocessor • Daily quiz & MCQs
• Microprocessor evolution and types • Old Question Papers
• Microprocessor architecture and its • Recap
operations • Video Links
• Logic devices for interfacing • Weekly Assignments
• Pin Diagram • References
• Internal architecture of 8085
Microprocessor

2/2/2024 Karan Singh Microprocessor UNIT- 1 12

 Unit Objective

1. To study the Introduction of microprocessors.

2. To understand Memory and I/O devices.
3. To learn microprocessor 8085 architecture.
4. To discuss concept of Timing Diagram.
5. To acquire the knowledge of Addressing Modes.

2/2/2024 Karan Singh Microprocessor UNIT- 1 13

 Topic-1 Objective

Name of the Topic Objective of the topic Mapping with CO

Introduction to To understand the concept
Microprocessor of microprocessor. CO1

2/2/2024 Karan Singh Microprocessor UNIT- 1 14

 Introduction to Microprocessor
Block Diagram of a Basic Computer
A computer is a programmable machine that receives input, stores and
manipulates data/information, and provides output in a useful format.
Basic computer system consist of a Central processing unit (CPU), memory
(RAM and ROM), input/output (I/O) unit.

Address bus

ROM RAM I/O I/O

Proce interface devices
ssor

Data bus Control bus

2/2/2024 Karan Singh Microprocessor UNIT- 1 15

 Introduction to Microprocessor
A microprocessor is a controlling unit of a micro-computer, fabricated on a small chip
capable of performing Arithmetic Logical Unit (ALU) operations and communicating with
the other devices connected to it.
Block Diagram of a Basic Microcomputer

2/2/2024 Karan Singh Microprocessor UNIT- 1 16

 Cont..

1. CPU - Central Processing Unit

• The portion of a computer system that carries out the instructions of a
computer program
• The primary element carrying out the computer's functions. It is the unit
that reads and executes program instructions.
• The data in the instruction tells the processor what to do.
2. Memory
• Physical devices used to store data or programs.
• Computer main memory comes in two principal varieties: random-access
memory (RAM) and read-only memory (ROM).
• RAM can be read and written to anytime the CPU commands it, but ROM
is pre-loaded with data and software that never changes, so the CPU can
only read from it.
• ROM is typically used to store the computer's initial start-up instructions.
In general, the contents of RAM are erased when the power to the computer is
turned off, but ROM retains its data indefinitely.

Karan Singh Microprocessor UNIT- 1 17

2/2/2024
 KARNAUGHMAP (K-MAP)
Cont.. REPRESENTATION

3. I/O Unit
• Input/output (I/O), refers to the communication between an
information processing system (such as a computer), and the outside
world possibly a human, or another information processing system.
• Inputs are the signals or data received by the system, and outputs are the
signals or data sent from it
• Devices that provide input or output to the computer are called
peripherals.
• On a typical personal computer, peripherals include input devices like
the keyboard and mouse, and output devices such as the display and
printer. Hard disk drives, floppy disk drives and optical disc drives serve
as both input and output devices. Computer networking is another form
of I/O.

2/2/2024 Karan Singh Microprocessor UNIT- 1 18

 Cont..
Data Size
Nibble 4 bit

Byte 8 bit

Word 16 bit

Long word 32 bit

2/2/2024 Karan Singh Microprocessor UNIT- 1 19

 Cont..
Internal structure and basic operation of microprocessor

Address bus
ALU Register
Section
Data bus

Control and timing

section Control bus

Block diagram of a microprocessor

Arithmetic and logic unit (ALU):
• The component that performs the arithmetic and logical operations
• The most important components in a microprocessor, and is typically the part
of the processor that is designed first.
• Able to perform the basic logical operations (AND, OR), including the addition
operation.
2/2/2024 Karan Singh Microprocessor UNIT- 1 20
 Cont..
Control unit:
• The circuitry that controls the flow of information through the processor, and
coordinates the activities of the other units within it.
• In a way, it is the "brain within the brain", as it controls what happens inside the
processor, which in turn controls the rest of the PC.
On a regular processor, the control unit performs the tasks of fetching, decoding,
managing execution and then storing results.
Register sets:
• The register section/array consists completely of circuitry used to temporarily
store data or program codes until they are sent to the ALU or to the control
section or to memory.
• The number of registers are different for any particular CPU and the more
register a CPU have will result in easier programming tasks.
Registers are normally measured by the number of bits they can hold, for example,
an "8-bit register" or a "32-bit register".

2/2/2024 Karan Singh Microprocessor UNIT- 1 21

 Daily Quiz
Problems
1. Convert (25)10 to binary number.
2. Convert (128)10 to octal number.
3. Convert 12810 to hex.
4. Convert (1101)2 into decimal number.
5. Convert 228 to decimal number.
6. Convert 12116 to decimal number.
7. Convert (89)16 into a binary number.
8. Convert (214)8 into a binary number.

Karan Singh Microprocessor UNIT- 1 22

2/2/2024
 Daily Quiz

Answers
1. (25)10 = (11001)2
2. 2008
3. 8016
4. (1101)2 = (13)10
5. 228 = 1810
6. 12116 = 28910
7. (89)16 = (10001001)2
8. (214)8 = (010001100)2

2/2/2024 Karan Singh Microprocessor UNIT- 1 23

 Weekly Assignment
➢ Addition of two hexadecimal
number.
1. 2345H+9854H
2. 4A6H + 1B3H
3. 182ABH + 5FCAA H
4. A6CCH+ 4AC7H ➢ Subtraction of two
5. 90A6H + DF91H hexadecimal number.
6. 1712H + 4753H 1. 923H – 257H
7. AFC2H+ 4ACCH 2. 4A6H - 1B3H
3. 180BFH – FFDFH
4. 7E6CH - 5DFAH
5. 15DA2H - 884FH
6. 1C582H - E706H

2/2/2024 Karan Singh Microprocessor UNIT- 1 24

 Topic Links
https://www.youtube.com/watch?v=Xl2nWDcy0To

https://slideplayer.com/slide/3944912/

https://www.bu.edu.eg/portal/uploads/Engineering,%20Shoubra/Electrical%20Engineering
/3515/crs-14315/Files/Lec%201%20Intro%20to%20mp.ppt

2/2/2024 Karan Singh Microprocessor UNIT- 1 25

 Topic-2 Objectives

Name of the Topic Objective of the topic Mapping with CO

Microprocessor To understand the
Evolution and concept of CO1
Types microprocessor & its
architecture.

2/2/2024 Karan Singh Microprocessor UNIT- 1 26

 Microprocessor Evolution
Intel 4004
Year of introduction 1971
• 4-bit microprocessor
• 4 KB main memory
• 45 instructions
• PMOS technology
• as first programmable device which was used in calculators

Intel 8008
Year of introduction 1972
• 8-bit version of 4004
• 16 KB main memory
• 48 instructions
• PMOS technology

2/2/2024 Karan Singh Microprocessor UNIT- 1 27

 Cont..
Intel 8080
Year of introduction 1973
• 8-bit microprocessor, 64 KB main memory
• 2 microseconds clock cycle time
• 500,000 instructions/sec
• 10X faster than 8008
• NMOS technology
• Drawback was that it needed three power supplies.
• Small computers (Microcomputers) were designed in mid 1970’s using 8080 as
CPU
Intel 8085
Year of introduction 1975
• 8-bit microprocessor-upgraded version of 8080
• 64 KB main memory
• 1.3 microseconds clock cycle time
• 246 instructions
• Intel sold 100 million copies of this 8-bit microprocessor
• uses only one +5V power supply.
2/2/2024 28
Karan Singh Microprocessor UNIT- 1
 Cont..
Intel 8086/8088
Year of introduction 1978 for 8086 and 1979 for 8088
• 16-bit microprocessors
• Data bus width of 8086 is 16 bit and 8 bit for 8088
• 1 MB main memory
• 400 nanoseconds clock cycle time
• 6 byte instruction cache for 8086 and 4 byte for 8088
• Other improvements included more registers and additional instructions
• In 1981 IBM decided to use 8088 in its personal computer

Intel 80386
• Year of introduction 1986
• Intel’s first practical 32-bit microprocessor
• 4 GB main memory
• Improvements include page handling in virtual environment
• Includes hardware circuitry for memory management and memory assignment
• Memory paging and enhanced I/O permissions

2/2/2024 Karan Singh Microprocessor UNIT- 1 29

 Cont..
Pentium
Year of introduction 1993
• 32-bit microprocessor, 32/64-bit data bus and 32-bit address bus
• 4 GB main memory, Double clocked 120 and 133MHz versions
• Fastest version is the 233MHz, Dual integer processor
• 16 KB L1 cache (split instruction and data: 8 KB each)

2/2/2024 Karan Singh Microprocessor UNIT- 1 30

 Microprocessor Types
A microprocessor can be classified into three categories:

RISC Processor
RISC stands for Reduced Instruction Set Computer. It is designed to reduce the execution
time by simplifying the instruction set of the computer. Using RISC processors, each
instruction requires only one clock cycle to execute results in uniform execution time. This
reduces the efficiency as there are more lines of code, hence more RAM is needed to store
the instructions. The compiler also has to work more to convert high-level language
instructions into machine code.
Some of the RISC processors are:
• Power PC: 601, 604, 615, 620
• DEC Alpha: 210642, 211066, 21068, 21164
• MIPS: TS (R10000) RISC Processor
• PA-RISC: HP 7100LC
2/2/2024 31
Karan Singh Microprocessor UNIT- 1
 Cont..
Characteristics of RISC
The major characteristics of a RISC processor are as follows:
• It consists of simple instructions.
• It supports various data-type formats.
• It utilizes simple addressing modes and fixed length instructions for
pipelining.
• It supports register to use in any context.
• One cycle execution time.
• “LOAD” and “STORE” instructions are used to access the memory location.
• It consists of larger number of registers.
• It consists of less number of transistors.
CISC Processor
CISC stands for Complex Instruction Set Computer. It is designed to minimize the
number of instructions per program, ignoring the number of cycles per instruction.
The compiler has to do very little work to translate a high-level language into assembly
level language/machine code because the length of the code is relatively short, so very little
RAM is required to store the instructions.
Some of the CISC Processors are: IBM 370/168, VAX 11/780, Intel 80486
2/2/2024 Karan Singh Microprocessor UNIT- 1 33
 Cont..

Characteristics of CISC
• Variety of addressing modes.
• Larger number of instructions available.
• Variable length of instruction formats.
• Several cycles may be required to execute one instruction.
• Instruction-decoding logic is complex.
• One instruction is required to support multiple addressing modes.

2/2/2024 Karan Singh Microprocessor UNIT- 1 35

 Cont..
Special Processors
These are the processors which are designed for some special purposes. Few of the
special processors are briefly discussed:
Coprocessor:
A coprocessor is a specially designed microprocessor, which can handle its
particular function many times faster than the ordinary microprocessor.
For example: Math Coprocessor.
Some Intel math-coprocessors are:
• 8087-used with 8086
• 80287-used with 80286
• 80387-used with 80386
Input/Output Processor:
It is a specially designed microprocessor having a local memory of its own, which is
used to control I/O devices with minimum CPU involvement.
For example:
• DMA (direct Memory Access) controller
• Keyboard/mouse controller
• Graphic display controller
2/2/2024 Karan Singh Microprocessor UNIT- 1 36
 Cont..
DSP (Digital Signal Processor):
This processor is specially designed to process the analog signals into a digital
form. This is done by sampling the voltage level at regular time intervals and
converting the voltage at that instant into a digital form. This process is performed
by a circuit called an analogue to digital converter, A to D converter or ADC.
Its applications are:
• Sound and music synthesis, Audio and video compression, Video signal
processing, 2D and 3d graphics acceleration.
For example: Texas Instrument’s TMS 320 series, e.g., TMS 320C40.

2/2/2024 Karan Singh Microprocessor UNIT- 1 37

 Daily Quiz
• Which of the following is a type of microprocessor?
a) CISC
b) RISC
c) EPIC
d) All of the mentioned
• Which of the following technology was used by Intel to design its first 8-bit
microprocessor?
a) NMOS
b) HMOS
c) PMOS
d) TTL
• Which of the following is true about microprocessors?
a) It has an internal memory
b) It has interfacing circuits
c) It contains ALU, CU, and registers
d) It uses Harvard architecture

2/2/2024 Karan Singh Microprocessor UNIT- 1 38

 Daily Quiz
• What is Microprocessor?
a) A multipurpose PLD that accepts binary data as input
b) A multipurpose PLD that accepts an integer as input
c) A multipurpose PLD that accepts whole numbers as input
d) A multipurpose PLD that accepts prime numbers as input

• Which of the following is not true about 8085 microprocessor?

a) It is an 8-bit microprocessor
b) It is a 40 pin DIP chip
c) It is manufactured using PMOS technology
d) It has 16 address lines

2/2/2024 Karan Singh Microprocessor UNIT- 1 39

 Weekly Assignment

1. What is Microprocessor?
2. What are the different types of Microprocessor?
3. Explain the evolution of Microprocessor.
4. How many generation of Microprocessors are there?
5. Which is the fastest speed of microprocessor?

2/2/2024 Karan Singh Microprocessor UNIT- 1 40

 Topic Links
https://www.youtube.com/watch?v=cylTOKGdFJI

https://www.youtube.com/watch?v=mU7wpeThu7A

2/2/2024 Karan Singh Microprocessor UNIT- 1 41

 Topic-3 Objective

Name of the Topic Objective of the topic Mapping with

CO
Microprocessor To understand the concept
architecture and its of microprocessor & its CO1
operations architecture.

2/2/2024 Karan Singh Microprocessor UNIT- 1 42

 Microprocessor Architecture
The microprocessor is a programmable logic device, designed with registers, flip-
flops. The microprocessor has a set of instructions designed internally, to
manipulate data and communicate with peripherals. This process of data
manipulation and communication is determined by the logic design of the
microprocessor, called the architecture.
Von Neumann Architecture
• In 1945, John von Neumann, who was a mathematician at the time, had delved
into the study that, a computer could have a fixed simple structure and still be
able to execute any kind of computation without hardware modification. This is
providing that the computer is properly programmed with proper instructions, in
which it is able to execute them.
• The von Neumann architecture describes a design model for a stored program
digital computer that incorporates only one single processing unit and one
single separate storage structure, which will hold both instructions and data.
• The von Neumann architecture refers to one that keeps the data as well as the
programmed instructions in read-write RAM (Random Access Memory).

2/2/2024 Karan Singh Microprocessor UNIT- 1 43

 Cont..

Von Neumann Architecture

2/2/2024 Karan Singh Microprocessor UNIT- 1 45

 Cont..
Harvard Architecture
• Harvard architecture is named after the “Harvard Mark I” relay-based
computer, which was an IBM computer in the University of Harvard.
• The computer-stored instructions on “punched tape” (24 bits wide),
furthermore the data was stored in electro mechanical counters.
• The CPU of these early computer systems contained the data storage entirely,
and it provided no access to the instruction storage as data.
• Harvard architecture is a type of architecture, which stores the data and
instructions separately, therefore splitting the memory unit.
• The CPU in a Harvard architecture system is enabled to fetch data and
instructions simultaneously, due to the architecture having separate buses for
data transfers and instruction fetches.

2/2/2024 Karan Singh Microprocessor UNIT- 1 46

 Cont..
Difference between Harvard Architecture & Von Neumann Architecture
Von Neumann
Basis for Comparison Harvard Architecture
Architecture
Basic Data and instructions Data and instruction are
reside within a single provided 2 different
memory unit. memory units.
Based on Stored program computer Harvard Mark I relay based
concept model
Memory system Single Dual
Required space Less Comparatively more
Set of address/ data bus One Two
Development cost Low Comparatively more
Efficiency Less More
Execution speed Slow Comparatively fast
2/2/2024 Karan Singh Microprocessor UNIT- 1 47
 Cont..
Difference between Harvard Architecture & Von Neumann Architecture
Von Neumann
Basis for Comparison Harvard Architecture
Architecture
Operation Simple Complex
Performance offered Low Comparatively high

Clock cycle Single instruction is executed Single instruction is executed

in minimum two clock cycles. in one clock cycle.

Feature Data transfer and instruction Data transfer and instruction

fetching do not occur fetch take place at the same
simultaneously. time.

Space utilization Good Not so good

Applications PCs, workstations, notebooks, Microcontrollers, digital signal
etc. processing, etc.

2/2/2024 Karan Singh Microprocessor UNIT- 1 48

 Operations
3. Peripheral or Externally-Initiated Operations
• These are operations initiated by external devices.
• These are usually :
• Reset
• Interrupt
• Ready
• Hold

2/2/2024 Karan Singh Microprocessor UNIT- 1 50

 Daily Quiz
1. There are _______ general purpose registers in 8085 processor
a) 5
b) 6
c) 7
d) 8
2. Flag register is an 8-bit register having __________ 1-bit flip-flops.
a) 3
b) 4
c) 5
d) 6
3. What is true about Program counter?
a) It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.
b) When an instruction is fetched from memory then it is stored in the program
counter.
c) It provides timing and control signal to the microprocessor
d) It is a 16-bit register used to store the memory address location of the next
instruction to be executed.

2/2/2024 Karan Singh Microprocessor UNIT- 1 51

 Daily Quiz
4. The microprocessor ___________ the instructions from the memory.
A. Fetch
B. Decode
C. Execute
D. None of the above
5. An 8-bit microprocessor can process _____ data at a time.
A. 4-bit
B. 8-bit
C. 16-bit
D. All of the above
6. There are primarily two types of register:
A. general purpose register
B. dedicated register
C. A and B
D. none of these

2/2/2024 Karan Singh Microprocessor UNIT- 1 52

 Weekly Assignment

1. Differentiate Von Neuman and Harvard Architecture.

2. Which architecture is used in microprocessor and explain it.
3. What are the different types of Flags in 8085?
4. Explain Microprocessor and its operations.
5. What is the length of stack pointer in 8085 microprocessor? And what is its use?

2/2/2024 Karan Singh Microprocessor UNIT- 1 53

 Topic Links
https://www.slideshare.net/RamaPrabha24/8085-microprocessor-architecture-and-its-
operations

https://www.javatpoint.com/microprocessor-architecture

2/2/2024 Karan Singh Microprocessor UNIT- 1 54

 Topic-4 Objectives

Name of the Topic Objective of the topic Mapping with CO

Logic devices for To understand the
interfacing concept of interfacing CO1
with 8085
microprocessor.

2/2/2024 Karan Singh Microprocessor UNIT- 1 55

 Logic Devices for Interfacing

Logic Devices consists of :

• Tri-State devices
• Buffer
• Bidirectional Buffer
• Decoder
• Encoder
• D Flip Flop : Latch and Clocked

2/2/2024 Karan Singh Microprocessor UNIT- 1 56

 Cont..
Tri-State devices:
Tri-state logic devices have three states:
1. Logic 1 or High
2. Logic 0 or Low
3. High impedance
• A tri-state logic device has a extra input line called Enable.
• When this line is active (Enabled), a tri-state device functions in the same way
as ordinary logic devices.
• When this line is not active (disabled), the logic device goes into a high
impedance state, as if it is disconnected from the system and practically no
current is drawn from the system.

2/2/2024 Karan Singh Microprocessor UNIT- 1 57

 Cont..
Buffer
• A Digital Buffer is a single input device that does not invert or perform any
type of logical operation on its input signal.
• In other words, the logic level of the output is same as that of the input.
• The buffer is a logic circuit that amplifies the current or power.
• The buffer is used primarily to increase the driving capability of a logic
circuit.
• It is also known as driver.

2/2/2024 Karan Singh Microprocessor UNIT- 1 58

 Cont..

Tri-state Buffer
• A Tri-state Buffer can be thought of as an input controlled switch which has an
output that can be electronically turned "ON" or "OFF" by means of an
external "Enable" signal input.
• This Enable signal can be either a logic "0" or a logic "1" type signal.
• When Enable line is high (logic “1‟), the circuit functions as a buffer.

2/2/2024 Karan Singh Microprocessor UNIT- 1 59

 Cont..
• There are two different types of Tri-state Buffer, one whose output is controlled
by an "Active-HIGH" Enable signal and the other which is controlled by an
"Active-LOW" Enable signal, as shown below

Active "HIGH" Tri-state Buffer

2/2/2024 Karan Singh Microprocessor UNIT- 1 60

 Cont..

Active "LOW" Tri-state Buffer

2/2/2024 Karan Singh Microprocessor UNIT- 1 61

 Cont..

Encoder
• The encoder is a logic circuit that provides the appropriate code (binary, BCD,
etc.) as output for each input signal.

Binary Encoder
• A binary encoder, is a multi-input combinational logic circuit that converts the
logic level "1" data at its inputs into an equivalent binary code at its output.
• Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes
depending upon the number of data input lines.
• An "n-bit" binary encoder has 2n input lines and n-bit output lines with common
types that include 4-to-2, 8-to-3 and 16-to-4 line configurations.
• The output lines of a digital encoder generate the binary equivalent of the input
line whose value is equal to "1" and are available to encode either a decimal or
hexadecimal input pattern to typically a binary or B.C.D. output code.

2/2/2024 Karan Singh Microprocessor UNIT- 1 62

 Cont..
4-to-2 Bit Binary Encoder:

Disadvantages of standard digital encoders

• They can generate the wrong output code when there is more than one input
present at logic level "1".

2/2/2024 Karan Singh Microprocessor UNIT- 1 63

 Cont..

Priority Encoder
• The Priority Encoder solves the problems mentioned above by allocating a
priority level to each input.
• The priority encoders output corresponds to the currently active input which has
the highest priority.
• So when an input with a higher priority is present, all other inputs with a lower
priority will be ignored.
• The priority encoder comes in many different forms with an example of an 8-
input priority encoder along with its truth table shown below.

2/2/2024 Karan Singh Microprocessor UNIT- 1 64

 Cont..

8-to-3 Bit Priority Encoder:

2/2/2024 Karan Singh Microprocessor UNIT- 1 65

 Cont..
Decoder: A Decoder is the exact opposite to that of an "Encoder". It is basically,
a combinational type logic circuit that converts the binary code data at its input into
an equivalent decimal code at its output. Binary Decoders have inputs of 2-bit, 3-
bit or 4-bit codes depending upon the number of data input lines, and a n-bit
decoder has 2n output lines. Therefore, if it receives n inputs (usually grouped as a
binary or Boolean number) it activates one and only one of its 2n outputs based on
that input with all other outputs deactivated. A decoders output code normally has
more bits than its input code and practical binary decoder circuits include, 2-to-4, 3-
to-8 and 4-to-16 line configurations.
2-to-4 Binary Decoder :

2/2/2024 Karan Singh Microprocessor UNIT- 1 66

 Cont..
In this simple example of a 2-to-4 line binary decoder, the binary inputs A and B
determine which output line from D0 to D3 is "HIGH" at logic level "1" while the
remaining outputs are held "LOW" at logic "0" so only one output can be active
(HIGH) at any one time. Therefore, whichever output line is "HIGH" identifies the
binary code present at the input, in other words it "de-codes" the binary input and
these types of binary decoders are commonly used as Address Decoders in
microprocessor memory applications.
The D flip-flop:
The D flip-flop is by far the most important of the clocked flip-flops as it ensures
that inputs S and R are never equal to one at the same time. D-type flip-flops are
constructed from a gated SR flip-flop with an inverter added between the S and the
R inputs to allow for a single D (data) input. This single data input D is used in
place of the "set" signal, and the inverter is used to generate the complementary
"reset" input thereby making a level-sensitive D-type flip-flop from a level-sensitive
RS-latch as now S = D and R = not D as shown.

2/2/2024 Karan Singh Microprocessor UNIT- 1 67

 Cont..

A simple SR flip-flop requires two inputs, one to "SET" the output and one to "RESET" the
output. By connecting NOT gate to the SR flip-flop one can "SET" and "RESET" the flip-
flop using just one input as now the two input signals are complements of each other. This
complement avoids “forbidden state” in the SR latch when both inputs are LOW, since that
state is no longer possible.
Thus the single input is called the "DATA" input. If this data input is HIGH the flip-flop
would be "SET" and when it is LOW the flip-flop would be "RESET". However, this would
be rather pointless since the flip-flop's output would always change on every data input. To
avoid this an additional input called the "CLOCK" or "ENABLE" input is used to isolate the
data input from the flip-flop after the desired data has been stored. The effect is that D is only
copied to the output Q when the clock is active. This forms the basis of a D flip-flop.
2/2/2024 Karan Singh Microprocessor UNIT- 1 68
 Cont..
The D flip-flop will store and output whatever logic level is applied to its data
terminal so long as the clock input is HIGH. Once the clock input goes LOW the
"set" and "reset" inputs of the flip-flop are both held at logic level "1" so it will
not change state and store whatever data was present on its output before the
clock transition occurred. In other words the output is "latched" at either logic "0"
or logic "1".
Truth Table for the D Flip-flop:

Note: ↓ and ↑ indicates direction of clock pulse as it is assumed D flip-flops

are edge triggered

2/2/2024 Karan Singh Microprocessor UNIT- 1 69

 Daily Quiz
• To avoid loading during read operation, the device used is
a) latch
b) flip flop
c) buffer
d) tristate buffer
• The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
• Which is not the control bus signal:
A. READ
B. WRITE
C. RESET
D. None of these

2/2/2024 Karan Singh Microprocessor UNIT- 1 70

 Daily Quiz
• PROM stands for:
A. Programmable read-only memory
B. Programmable read write memory
C. Programmer read and write memory
D. None of these

• The method of connecting a driving device to a loading device is known as

___________
a) Compatibility
b) Interface
c) Sourcing
d) Sinking

2/2/2024 Karan Singh Microprocessor UNIT- 1 71

 Weekly Assignment
1. What do you mean by tri-state devices?
2. With the help of a neat symbol explain tri-state buffer.
3. State function of buffer.
4. Explain different types of encoder.
5. With the help of neat block diagram explain 4 to 2 encoder.
6. What do you mean by priority encoder?
7. With the help of neat block diagram explain 8 to 3 encoder.
8. Explain decoder in detail.
9. With the help of neat block diagram explain 3 to 8 decoder.
10. Explain the working of D flipflop.

2/2/2024 Karan Singh Microprocessor UNIT- 1 72

 Topic Links

https://www.youtube.com/watch?v=_EJDoLnJ5BM

https://www.youtube.com/watch?v=bXOpC0z-8o8

2/2/2024 Karan Singh Microprocessor UNIT- 1 73

 Topic-5 Objectives

Name of the Topic Objective of the topic Mapping with CO

Pin Diagram and To understand the
Internal concept of Architecture CO1
Architecture of and Pin configuration of
8085 8085.

2/2/2024 Karan Singh Microprocessor UNIT- 1 74

 PIN Diagram

2/2/2024 Karan Singh Microprocessor UNIT- 1 75

 PIN Diagram

• The pins on the chip can be grouped into 6 groups:

1. Address Bus.
2. Data Bus.
3. Control and Status Signals.
4. Power supply and frequency.
5. Externally Initiated Signals.
6. Serial I/O ports.

2/2/2024 Karan Singh Microprocessor UNIT- 1 76

 PIN Diagram
Frequency Control Signals (X1 & X2) Pin 1 and Pin 2 (Input)

• There are 3 important pins in the

frequency control group.
• X0 and X1 are the inputs from the
crystal or clock generating circuit.
• The frequency is internally divided by
2.
• So, to run the microprocessor at 3.072
MHz, a clock running at 6.144 MHz
should be connected to the X0 and X1
pins.
• CLK (OUT) Pin 37: An output clock
pin to drive the clock of the rest of the
system.

2/2/2024 Karan Singh Microprocessor UNIT- 1 77

 Pins and signals
RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)

RESET IN
• It is used to reset the microprocessor.
• It is active low signal.
• When the signal on this pin is low
For at least 3 clocking cycles, it
forces the microprocessor to reset itself.
– Resetting the microprocessor means:
1) Clearing the PC and IR.
2) Disabling all interrupts(except TRAP).
3) Disabling the SOD pin.
4) Gives HIGH output to RESET OUT pin

2/2/2024 Karan Singh Microprocessor UNIT- 1 78

 Pins and signals
RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
RESET OUT
• It is used to reset the peripheral devices and other ICs on the
circuit.
• It is an active high signal.
• The output on this pin goes high
• whenever RESET IN is given low signal.

2/2/2024 Karan Singh Microprocessor UNIT- 1 79

 Pins and signals
SID and SOD Pin 4 (Input) and Pin 5 (Output)

SID (Serial Input Data)

• It takes 1 bit input from serial port of 8085.

• Stores the bit at the 8th position (MSB) of the
Accumulator.
• RIM (Read Interrupt Mask) instruction is used
to transfer the bit.

2/2/2024 Karan Singh Microprocessor UNIT- 1 80

 Pins and signals
SID and SOD Pin 4 (Input) and Pin 5 (Output)

SOD (Serial Output Data)

• It takes 1 bit from Accumulator to serial port

of 8085.

• Takes the bit from the 8th position (MSB) of

the Accumulator.

• SIM (Set Interrupt Mask) instruction is used

to transfer the bit.

2/2/2024 Karan Singh Microprocessor UNIT- 1 81

 Pins and signals

Interrupt Pin 6 to Pin 10

2/2/2024 Karan Singh Microprocessor UNIT- 1 82

 Pins and signals
INTA Pin 11 (Output)
• It stands for interrupt acknowledge.

• It is an active low signal.

• Low output on this pin indicates that

microprocessor has acknowledged the
INTR request.

2/2/2024 Karan Singh Microprocessor UNIT- 1 83

 Pins and signals
AD0 – AD7 [Pin 19-12 (Bidirectional)]

• These pins serve the dual purpose of

transmitting lower order address and
data byte.
• During 1st clock cycle, these pins act
as lower half of address.
• In remaining clock cycles, these pins
act as data bus.
• The separation of lower order address
and data is done by address latch
Enable (ALE).

2/2/2024 Karan Singh Microprocessor UNIT- 1 84

 Pins and signals
A8 – A15 [Pin 21-28 (Unidirectional)]

• These pins carry the higher order of address

bus.

• The address is sent from microprocessor to

memory.

2/2/2024 Karan Singh Microprocessor UNIT- 1 85

 Pins and signals
ALE [Pin 30 (Output)]

• It is used to enable Address Latch.

• If ALE = 1 then
Bus functions as address bus.
• If ALE = 0 then
Bus functions as data bus.

2/2/2024 Karan Singh Microprocessor UNIT- 1 86

 Pins and signals
S0 and S1 [Pin 29 (Output) and Pin 33 (Output)]

• S0 and S1 are called Status Pins.

• They tell the current operation which is in
progress in 8085.

S1 S0 Operation
0 0 Halt
0 1 Write
1 0 Read
1 1 Opcode Fetch

2/2/2024 Karan Singh Microprocessor UNIT- 1 87

 Pins and signals
IO/M [Pin 34 (Output)]

• This pin tells whether I/O or memory

operation is being performed.
• If IO/M = 1 then
• I/O operation is being performed.
• If IO/M = 0 then
• Memory operation is being
• performed.

2/2/2024 Karan Singh Microprocessor UNIT- 1 88

 Pins and signals

Table Showing IO/M, S0, S1 and Corresponding Operations

Operations IO/M S1 S0
Opcode Fetch 0 1 1
Memory Read 0 1 0
Memory Write 0 0 1
I/O Read 1 1 0
I/O Write 1 0 1
Interrupt Ack. 1 1 1
Halt High Impedance 0 0

2/2/2024 Karan Singh Microprocessor UNIT- 1 89

 Pins and signals

WR Pin 31 (Output)

• WR stands for write.

• It is an active low signal.

• It is a control signal used for Write

operation either into memory or into
output device.

2/2/2024 Karan Singh Microprocessor UNIT- 1 90

 Pins and signals

RD Pin 32 (Output)

• RD stands for Read.

• It is an active low signal.

• It is a control signal used for Read

operation either from memory or from
Input device.

2/2/2024 Karan Singh Microprocessor UNIT- 1 91

 Pins and signals

READY Pin 35 (Input)

• This pin is used to synchronize slower

peripheral devices with fast
microprocessor.

• A low value causes the microprocessor

to enter into wait state.

• The microprocessor remains in wait

state until the input at this pin goes high.

2/2/2024 Karan Singh Microprocessor UNIT- 1 92

 Pins and signals

HOLD [ Pin 38 (Input) ]

• HOLD pin is used to request the

microprocessor for DMA transfer.
• A high signal on this pin is a request to
microprocessor to relinquish the hold on
buses.
• This request is sent by DMA controller.
• Intel 8257 and Intel 8237 are two DMA
controllers.

2/2/2024 Karan Singh Microprocessor UNIT- 1 93

 Pins and signals
HLDA [Pin 39 (Output)]

• HLDA stands for Hold Acknowledge.

• The microprocessor uses this pin to
acknowledge the receipt of HOLD signal.
• When HLDA signal goes high, address
bus, data bus, RD, WR, IO/M pins are
tri-stated.
• This means they are cut-off from external
environment.

2/2/2024 Karan Singh Microprocessor UNIT- 1 94

 Pins and signals
HLDA [Pin 39 (Output)]

• The control of these buses goes to DMA

Controller.
• Control remains at DMA Controller until
HOLD is held high.
• When HOLD goes low, HLDA also goes
low and the microprocessor takes control
of the buses.

2/2/2024 Karan Singh Microprocessor UNIT- 1 95

 Pins and signals
Vss andVcc [Pin 20 (Input) and Pin 40 (Input)]

• +5V power supply is connected to VCC.

• Ground signal is connected to VSS.

2/2/2024 Karan Singh Microprocessor UNIT- 1 96

 8085 Microprocessor Architecture

2/2/2024 Karan Singh Microprocessor UNIT- 1 97

 8085 Microprocessor Architecture

2/2/2024 Karan Singh Microprocessor UNIT- 1 98

 8085 Microprocessor Architecture
• The 8085 uses three separate busses to perform its operations:
• Address bus.
• Data bus.
• Control bus.
16 bits wide (A0 A1…A15) Address bus:
• Therefore, the 8085 can access locations with numbers
from 0 to 65,535. Or, the 8085 can access a total of 64K
addresses.
• “Unidirectional”.
• Information flows out of the microprocessor and into the
memory or peripherals.
• When the 8085 wants to access a peripheral or a memory
location, it places the 16-bit address on the address bus and
then sends the appropriate control signals.

2/2/2024 Karan Singh Microprocessor UNIT- 1 100

 8085 Microprocessor Architecture

The Data Bus

• 8 bits wide (D0 D1…D7)

• “Bi-directional”.
• Information flows both ways between the
microprocessor and memory or I/O.
• The 8085 uses the data bus to transfer the binary
information.
• Since the data bus has 8-bits only, then the 8085 can
manipulate data 8 bits at-a-time only.

2/2/2024 Karan Singh Microprocessor UNIT- 1 101

 8085 Microprocessor Architecture
The Control Bus
• The control bus is made up of a number of single bit control
signals.
Registers
• Six general purpose registers used to store 8-bit data during a
program execution.
• The registers are identified as B, C, D, E, H, and L.
• They can be combined as register pairs: BC, DE, and HL to
perform 16-bit operations.

2/2/2024 Karan Singh Microprocessor UNIT- 1 102

 8085 Microprocessor Architecture
Program Counter (PC) [16]
• This is used to control the sequencing of the execution of
instructions.
• This register always holds the address of the next instruction.
Stack pointer [16]
• It is used to point into memory (stack).
• The stack is an area of memory used to hold data that will be
retreived soon.
• The stack is usually accessed in a Last In First Out (LIFO) fashion.
Accumulator [8]
• 8-bit register that is part of the ALU.
• Used to store 8-bit data and in performing 8-bit arithmetic and
logical operations, and in storing the results of operations.

2/2/2024 Karan Singh Microprocessor UNIT- 1 103

 8085 Microprocessor Architecture
FLAGS OF 8085

2/2/2024 Karan Singh Microprocessor UNIT- 1 104

 8085 Microprocessor Architecture
Interrupts Control Unit

• Interrupt is a signal sent by a peripheral interface or a software

program to microprocessor to perform a particular task or work.
• Intel 8085 Microprocessor has 5 hardware interrupts and 8 software
interrupts.

• Hardware interrupts in the descending order of their priority :

TRAP (RST 4.5) , RST 7.5 , RST 6.5 , RST 5.5 , INTR
• Software interrupts :
RST 0 , RST 1 , RST 2, RST 3, RST 4 , RST 5 , RST 6 , RST 7.

2/2/2024 Karan Singh Microprocessor UNIT- 1 105

 8085 Microprocessor Architecture
Timing & Control Unit
• This unit synchronizes all the microprocessors operation with the
clock & generates the control signal necessary for communication
between the microprocessors & peripherals.
• The RD & WR signals are indicating the availability of the data on
the data bus.
Instruction Register & Decoder
• This is a part of ALU.
• When an instruction is fetched from memory, it is loaded in the
instruction register.
• The decoder decodes the instruction & establishes the sequence of
events to follow.

2/2/2024 Karan Singh Microprocessor UNIT- 1 106

 Example of an 8085 based Computer

2/2/2024 Karan Singh Microprocessor UNIT- 1 107

 Instruction and Data Flow

• The instruction code 0100 1111 (4FH) is stored in memory location

2005H. Illustrate the data flow and list the sequence of events when
the instruction code is fetched by the MPU.

2/2/2024 Karan Singh Microprocessor UNIT- 1 108

 Instruction and Data Flow

2/2/2024 Karan Singh Microprocessor UNIT- 1 109

 Timer and Timing Diagram
MACHINE CYCLES AND THEIR TIMING OF 8085

Instruction Cycle

M1 M2 M3

M = Machine Cycle
T = T States
T1 T2 T3

2/2/2024 Karan Singh Microprocessor UNIT- 1 110

 Timing Diagrams
MACHINE CYCLES AND THEIR TIMING OF 8085
• Timing Diagram is a graphical representation. It represents the
execution time taken by each instruction.
T- State:
Microprocessor performs an operation in specific time period i.e clock
cycles. Each clock cycles is called T-State.
Machine Cycle:
The time required to complete one operation of accessing memory, I/O, or
acknowledging an external request. This cycle may consist of 3 to 6 T-
states.
Instruction Cycle:
The time required to complete the execution of an instruction. In the 8085,
an instruction cycle may consist of 1 to 6 machine cycles.

2/2/2024 Karan Singh Microprocessor UNIT- 1 111

 Timing Diagrams
MACHINE CYCLES AND THEIR TIMING OF 8085
Fetch Cycle:
In this cycle, the CPU fetches opcode of the instruction of the memory.
Execute Cycle:
• In this cycle, the data acquired from the memory & complete the
operation.
• Total time taken to execute an instruction = FC + EC.

2/2/2024 Karan Singh Microprocessor UNIT- 1 112

 Timing Diagrams

The 8085 microprocessor has 5 basic machine cycles.

1. Opcode fetch cycle (4T)
2. Memory write cycle (3 T)
3. Memory read cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)

2/2/2024 Karan Singh Microprocessor UNIT- 1 113

 Timing Diagrams
Clock Signal
• The 8085 divides the clock frequency provided at x1 and x2 inputs
by 2 which is called operating frequency.

2/2/2024 Karan Singh Microprocessor UNIT- 1 114

 Timing Diagrams

Single Signal

• Single signal status is represented by a line. It may have status either

logic 0 or logic 1 or tri-state.

2/2/2024 Karan Singh Microprocessor UNIT- 1 115

 Timing Diagrams
Group of signals
• Group of signals is also called a bus.
Eg: Address bus, data bus

2/2/2024 Karan Singh Microprocessor UNIT- 1 116

 Timing Diagrams
Instruction

Instruction

Opcode Operand

Example
MOV A, B

MVI B, 64H

2/2/2024 Karan Singh Microprocessor UNIT- 1 117

 Opcode Fetch Machine Cycle (4T or 6T)

• The first step of executing any instruction is the Opcode fetch cycle.
• In this cycle, the microprocessor brings in the instruction’s Opcode
from memory.
1) T1
Microprocessor uses IO/M , S0, S1 to instruct processor to fetch opcode,
16 bit address & ALE signal.

2) T2
Uses read signal & make data ready from that memory location to read
the opcode & PC is incremented by one. And also check READY signal.
If READY signal = 0: wait state between T2 & T3.

2/2/2024 Karan Singh Microprocessor UNIT- 1 118

 Opcode Fetch Machine Cycle (4T or 6T)

3) T3
Microprocessor reads opcode & store into the instruction register to
decode it further.
4) T4
Microprocessor performs internal operation.
1) Decoding opcode (T5 or T6 is required or not)
2) Providing necessary action

2/2/2024 Karan Singh Microprocessor UNIT- 1 119

 Timing Diagrams
Opcode Fetch Machine Cycle (4T or 6T)
• Instructions having opcode fetch machine cycle is of 6T states.
• INX & DCX
• Ccondtional, Rconditional & CALL
• PCHL & SPHL
• RSTn
• PUSH
• Rest of instructions required 4T states to execute opcode fetch
machine cycle.

2/2/2024 Karan Singh Microprocessor UNIT- 1 120

 Timing Diagrams
Timing Diagram for Opcode Fetch Machine Cycle

2/2/2024 Karan Singh Microprocessor UNIT- 1 121

 Timing Diagrams

Memory Read Machine Cycle

• The memory read machine cycle is exactly the same as the
opcode fetch except:
• It only has 3 T-states.
• The s0 signal is set to 0 instead.
• The memory read machine cycle is executed by the processor to
read a data byte from memory.
• The processor takes 3T states to execute this cycle.
• The instructions which have more than one byte word size will
use the machine cycle after the opcode fetch machine cycle.

2/2/2024 Karan Singh Microprocessor UNIT- 1 122

 Timing Diagrams

Memory Read Machine Cycle

• To understand the memory read machine cycle, let’s study the
execution of the following instruction:
MVI A, 32H
In memory, this instruction looks like:
• The first byte 3EH represents the opcode for loading a byte into
the accumulator (MVI A), the second byte is the data to be
loaded.
• The 8085 needs to read these two bytes from memory before it
can execute the instruction. Therefore, it will need at least two
machine cycles.
• The first machine cycle is the opcode fetch discussed earlier.
• The second machine cycle is the Memory Read Cycle.

2/2/2024 Karan Singh Microprocessor UNIT- 1 123

 Timing Diagrams

Memory Read Machine Cycle

2/2/2024 Karan Singh Microprocessor UNIT- 1 124

 Timing Diagrams

Memory Write Machine Cycle

• The memory write machine cycle is executed by the processor to
write a data byte in a memory location.
• The processor takes, 3T states to execute this machine cycle.
• In a memory write operation:
• The 8085 places the address (2065H) on the address bus
Identifies the operation as a memory write (IO/M=0, s1=0,
s0=1).
• Places the contents of the accumulator on the data bus and
asserts the signal WR.
• During the last T-state, the contents of the data bus are saved
into the memory location.

2/2/2024 Karan Singh Microprocessor UNIT- 1 125

 Timing Diagrams

Timing Diagram for Memory Write Machine Cycle

2/2/2024 Karan Singh Microprocessor UNIT- 1 126

 Timing Diagrams
MOV A,B , ANA B , ORA B , XRA B
ADD B , ADC B , SUB B , SBB B
RAL , RAR , RLC , RRC
RIM , SIM , EI , DI
NOP , CMA , CMC , STC
INR B , DCR B , CMP B , XCHG
DAA
OPCODE FETCH
CLK
T1 T2 T3 T4

A15 - A8 PCH Unspecified

AD7 - AD0 PCL OPCODE

Tri-states

ALE

RD

IO/ M

S1

S0

2/2/2024 Karan Singh Microprocessor UNIT- 1 127

 Timing Diagrams
MVI A,40H , ADI 80H , ACI 30H , SUI 40H , SBI 20H
ANI 30H , ORI 40H , XRI 75H , CPI 90H

OPCODE FETCH READ

CLK
T1 T2 T3 T4 T5 T6 T7

A15 - A8 PCH Unspecified PCH

AD7 - AD0 PCL OPCODE PCL + 1 Data = 40H

ALE

RD

IO/ M

S1

S0

2/2/2024 Karan Singh Microprocessor UNIT- 1 128

 Timing Diagrams
MOV A,M , ADD M , ADC M , SUB M , SBB M
ANA M , ORA M , XRA M , CMP M

OPCODE FETCH READ

CLK
T1 T2 T3 T4 T5 T6 T7

A15 - A8 PCH Unspecified H

AD7 - AD0 PCL OPCODE L data

ALE

RD

IO/ M

S1

S0

2/2/2024 Karan Singh Microprocessor UNIT- 1 129

 Timing Diagrams
MOV M,A

OPCODE FETCH WRITE

CLK
T1 T2 T3 T4 T5 T6 T7

A15 - A8 PCH Unspecified H

AD7 - AD0 PCL OPCODE L data

ALE

RD

WR

IO/ M

S1

S0

2/2/2024 Karan Singh Microprocessor UNIT- 1 130

 Timing Diagrams
MVI M,55H

OPCODE FETCH READ WRITE

CLK
T1 T2 T3 T4 T5 T6 T7 T5 T6 T7

A15 - A8 PCH Unspecified PCH H

AD7 - AD0 PCL OPCODE PCL + 1 Data = 55H L Data = 55H

ALE

RD

WR

IO/ M

S1

S0

2/2/2024 Karan Singh Microprocessor UNIT- 1 131

 Timing Diagrams

INR M
OPCODE FETCH READ WRITE
CLK
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

A15 - A8 PCH Unspecified H H

AD7 - AD0 PCL OPCODE L M L M

= data = data + 1

ALE

RD

WR

IO/ M

S1

S0

2/2/2024 Karan Singh Microprocessor UNIT- 1 132

 Timing Diagrams
LXI H,4030H

OPCODE FETCH READ READ

CLK
T1 T2 T3 T4 T5 T6 T7 T5 T6 T7

A15 - A8 PCH Unspecified PCH PCH

AD7 - AD0 PCL OPCODE PCL + 1 Data = 30H PCL + 2 Data = 40H

ALE

RD

IO/ M

S1

S0

2/2/2024 Karan Singh Microprocessor UNIT- 1 133

 Topic-8 Objectives

Name of the Topic Objective of the topic Mapping with CO

To understand the
Interrupt Interrupt function of CO1
8085.

2/2/2024 Karan Singh Microprocessor UNIT- 1 134

 Interrupt
• Interrupts are signals send by an external device to the processor, to
request the processor to perform a particular task or work.
• Mainly in the microprocessor based system the interrupts are used for
data transfer between the peripheral and the microprocessor.
• The processor will check the interrupts always at the 2nd T-state of last
machine cycle.
• If there is any interrupt it accept the interrupt and send the INTA
(active low) signal to the peripheral.
• The vectored address of particular interrupt is stored in program
counter.
• The processor executes an interrupt service routine (ISR) addressed in
program counter.
• It returned to main program by RET instruction.

2/2/2024 Karan Singh Microprocessor UNIT- 1 135

 Interrupt

Types of Interrupts: It supports two types of interrupts.

1. Hardware interrupts
2. Software interrupts

• Hardware interrupts in the descending order of their priority :

TRAP (RST 4.5) , RST 7.5 , RST 6.5 , RST 5.5 , INTR

• Software interrupts :
RST 0 , RST 1 , RST 2, RST 3, RST 4 , RST 5 , RST 6 , RST 7

2/2/2024 Karan Singh Microprocessor UNIT- 1 136

 Types of Interrupt
Based on address:
• Vectored Interrupt: In this type of interrupt, the interrupt address is
known to the processor. For example: RST7.5, RST6.5, RST5.5,
TRAP.
• Non Vectored Interrupt: In this type of interrupt, the interrupt address
is not known to the processor so, the interrupt address needs to be sent
externally by the device to perform interrupts. For example: INTR.

Based on execution:
• Maskable interrupt − In this type of interrupt, we can disable the
interrupt by writing some instructions into the program.
For example: RST7.5, RST6.5, RST5.5.
• Non-Maskable interrupt − In this type of interrupt, we cannot disable
the interrupt by writing some instructions into the program.
For example: TRAP.

2/2/2024 Karan Singh Microprocessor UNIT- 1 137

 Interrupts

Calculation of vector address

Vector Address = 8 * no of interrupt

Example

RST 5 = 8 * 5= 4010 = 28 16

2/2/2024 Karan Singh Microprocessor UNIT- 1 138

 Cont..
Software interrupts: The software interrupts are program instructions. These
instructions are inserted at desired locations in a program.
• The 8085 has eight software interrupts from RST 0 to RST 7. The vector
address for these interrupts can be calculated as follows.
The Table shows the vector addresses of all interrupts.

2/2/2024 Karan Singh Microprocessor UNIT- 1 139

 Cont..
Hardware interrupts:
• An external device initiates the hardware interrupts and placing an appropriate
signal at the interrupt pin of the processor.
• If the interrupt is accepted then the processor executes an interrupt service
routine.
The 8085 has five hardware interrupts:
(1) TRAP (2) RST 7.5 (3) RST 6.5 4) RST 5.5 5) INTR

2/2/2024 Karan Singh Microprocessor UNIT- 1 140

 Cont..
TRAP:
• This interrupt is a non-maskable interrupt. It is unaffected by any mask or
interrupt enable.
• TRAP has the highest priority and vectored interrupt.
• TRAP interrupt is edge and level triggered. This means that the TRAP
must go high and remain high until it is acknowledged.

2/2/2024 Karan Singh Microprocessor UNIT- 1 141

 Cont..
RST 7.5:
• The RST 7.5 interrupt is a maskable interrupt.
• It has the second highest priority.
• It is edge sensitive. ie. Input goes to high and no need to maintain high state
until it recognized.
• Maskable interrupt. It is disabled by,
1. DI, SIM instruction
2. System or processor reset.
3. After reorganization of interrupt with high priority .
• Enabled by EI instruction.

2/2/2024 Karan Singh Microprocessor UNIT- 1 142

 Cont..
RST 6.5 and 5.5:
• The RST 6.5 and RST 5.5 both are level triggered. ie. Inputs goes to high
and stay high until it recognized.
• Maskable interrupt. It is disabled by,
1. DI, SIM instruction
2. System or processor reset.
3. after reorganization of interrupt with high priority.
• Enabled by EI instruction.
• The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

2/2/2024 Karan Singh Microprocessor UNIT- 1 143

 Cont..
INTR:
• INTR is a maskable interrupt. It is disabled by,
1. DI, SIM instruction
2. System or processor reset.
3. After reorganization of interrupt with high priority .
• Enabled by EI instruction.
• Non- vectored interrupt
• It has lowest priority.
• It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain
high state until it recognized.
.

2/2/2024 Karan Singh Microprocessor UNIT- 1 144

 Daily Quiz

• The INTR interrupt may be masked using the flag

a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
• NMI stands for
a) non-maskable interrupt
b) non-multiple interrupt
c) non-movable interrupt
d) none of the mentioned
• The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request

2/2/2024 Karan Singh Microprocessor UNIT- 1 145

 Daily Quiz
• An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
• If any interrupt request given to an input pin cannot be disabled by any means
then the input pin is called
a) maskable interrupt
b) non-maskable interrupt
c) maskable interrupt and non-maskable interrupt
d) none of the mentioned
• The INTR interrupt may be
a) maskable
b) non-maskable
c) maskable and non-maskable
d) none of the mentioned

2/2/2024 Karan Singh Microprocessor UNIT- 1 146

 Weekly Assignment
1. The 8085 microprocessor is executing a program given below:
2000: MVI A, 10 H
MVI B, 04 H
LOOP: ADD B
RLC
RLC
DCR B
JNZ LOOP
HLT
How many times ADD B operation takes place and final result of Accumulator?
2. An 8085 is executing the following program:
2000: LXI H 4325H
LXI SP 3000H
MOV A, H
ADD L
PUSH PSW
HLT
At the end of the program execution, what will be the contents of the PSW with stack
location.

2/2/2024 Karan Singh Microprocessor UNIT- 1 147

 Weekly Assignment

3. Read the following program and answer the questions

2000 LXI SP, 2100H DELAY: 2064 PUSH H
2003 LXI B,0000H 2065 PUSH B
2006 PUSH B 2066 LXI B,80FFH
2007 POP PSW LOOP: 2069 DCX B
2008 LXI H,200BH 206A MOV A,B
200B CALL 2064H 206B ORA C
200E OUT 01H 206C JNZ LOOP
2010 HLT 206F POP B
2070 RET
a). What is the status of the flags and the contents of the accumulator after the
execution of the POP instruction located at 2007H?
b). What are the contents of the stack pointer and program counter registers after
the execution of the CALL instruction?

2/2/2024 Karan Singh Microprocessor UNIT- 1 148

 Topic Links

https://www.youtube.com/watch?v=79icCUmqyPc

https://www.youtube.com/watch?v=1aG3aFEKxyA

2/2/2024 Karan Singh Microprocessor UNIT- 1 149

 Topic-9 Objective

Name of the Topic Objective of the topic Mapping with CO

To understand the role of
Addressing Modes Addressing Modes in CO1
8085 microprocessor.

2/2/2024 Karan Singh Microprocessor UNIT- 1 150

 Addressing Modes

• The method by which the address of source of data or the address of

destination of result is given in the instruction is called Addressing
Modes.

• The term addressing mode refers to the way in which the operand
of the instruction is specified.

Addressing modes in 8085 is classified into 5 groups −

1. Immediate addressing mode
2. Register addressing mode
3. Direct addressing mode
4. Indirect addressing mode
5. Implied addressing mode
2/2/2024 Karan Singh Microprocessor UNIT- 1 151
 Cont..

1. Immediate Addressing Mode:

In immediate addressing mode the source operand is always data. If the data is 8-
bit, then the instruction will be of 2 bytes, if the data is of 16-bit then the
instruction will be of 3 bytes.
Examples:
MVI B,45 (move the data 45H immediately to register B)
LXI H,3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)

2. Register Addressing Mode:

In register addressing mode, the data to be operated is available inside the
register(s) and register(s) is(are) operands. Therefore the operation is performed
within various registers of the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)
2/2/2024 Karan Singh Microprocessor UNIT- 1 152
 Cont..
3. Direct Addressing Mode:
In direct addressing mode, the data to be operated is available inside a memory
location and that memory location is directly specified as an operand. The
operand is directly available in the instruction itself.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register
pair)
IN 35 (read the data from port whose address is 35)

4. Register Indirect Addressing Mode:

In register indirect addressing mode, the data to be operated is available inside a
memory location and that memory location is indirectly specified by a register
pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L
pair to the accumulator)
LDAX B (move contents of B-C register to the accumulator)
2/2/2024 Karan Singh Microprocessor UNIT- 1 153
 Cont..
5. Implied/Implicit Addressing Mode:
In implied/implicit addressing mode the operand is hidden and the data to be
operated is available in the instruction itself.
Examples:
CMA (finds and stores the 1’s complement of the contents of accumulator A
in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)

2/2/2024 Karan Singh Microprocessor UNIT- 1 154

 Daily Quiz
• The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
• Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more
operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the
stack
d) None of the mentioned
• The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
2/2/2024 Karan Singh Microprocessor UNIT- 1 155
 Daily Quiz
In the following indexed addressing mode instruction, MOV 5(R1), LOC the
effective address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]
The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative
The addressing mode/s, which uses the PC instead of a general purpose register
is ______
a) Indexed with offset
b) Relative
c) Direct
d) Both Indexed with offset and direct
2/2/2024 Karan Singh Microprocessor UNIT- 1 156
 Topic Links
https://www.youtube.com/watch?v=1m-jgtGetl4

https://www.youtube.com/watch?v=VK3wnxEbaqI

2/2/2024 Karan Singh Microprocessor UNIT- 1 157

 Daily Quiz
• This signal is used as the system clock for devices connected with the
microprocessor.
A. X1, X2
B. CLK OUT
C. CLK IN
D. IO/M
• Which of the following is true about Control and status signals?
A. These signals are used to identify the nature of operation.
B. There are 3 control signal and 3 status signals.
C. Three status signals are IO/M, S0 & S1.
D. All of the above
• How many pins of 8085 microprocessor includes?
A. 39
B. 40
C. 20
D. 25

2/2/2024 Karan Singh Microprocessor UNIT- 1 158

 Daily Quiz
• The 8085A has interrupt pins:-
a) TRAP, RST7.5
b) RST6.5, RST5.5
c) TNTR (pin 10)
d) All of the above.
• In the 8085A microprocessor, the data size is 8-bit and the address size is
16-bit.
a) B-C pair
b) D-E pair
c) H-L pair
d) All of the above.
• A microprocessor to execute a program, the CPU has to do the following
operations:
a) Fetch the opcode
b) Read a memory location for the data.
c) Perform the required operation
d) All of the above.

2/2/2024 Karan Singh Microprocessor UNIT- 1 159

 Weekly Assignment

1. Explain general architecture of microprocessor.

2. Sketch the internal architecture of 8085 microprocessor.
3. How many signal groups are in 8085 pin.
4. What is the function of CLK OUT pin of 8085.

2/2/2024 Karan Singh Microprocessor UNIT- 1 160

 Topic Links

https://www.youtube.com/watch?v=STnM8a4hUII

https://www.youtube.com/watch?v=4PemFcazH_A

https://www.youtube.com/watch?v=UWekjor55pc

2/2/2024 Karan Singh Microprocessor UNIT- 1 161

 MCQ
• In static memory, the upper 8-bit bank of an available 16-bit memory chip is
called
a) upper address memory bank
b) even address memory bank
c) static upper memory
d) odd address memory bank
• To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are
arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
• To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
2/2/2024 Karan Singh Microprocessor UNIT- 1 162
 MCQ
• The CPU sends out a ____ signal to indicate that valid data is available on the
data bus:
A. Read
B. Write
C. Both A and B
D. None of these
• A microprocessor retries instructions from :
A. Control memory
B. Cache memory
C. Main memory
D. Virtual memory
• EU STAND FOR:
A. Execution unit
B. Execute unit
C. Exchange unit
D. None of these

2/2/2024 Karan Singh Microprocessor UNIT- 1 163

 MCQ
• The CPU removes the ___ signal to complete the memory write operation:
A. Read
B. Write
C. Both A and B
D. None of these
• Which RAM is created using MOS transistors:
A. Dynamic RAM
B. Static RAM
C. Permanent RAM
D. SD RAM
• The RAM which is created using bipolar transistors is called:
A. Dynamic RAM
B. Static RAM
C. Permanent RAM
D. DDR RAM

2/2/2024 Karan Singh Microprocessor UNIT- 1 164

 MCQ
• Which one of the following is not a vectored interrupt?
a. TRAP
b. INTR
c. RST 7.5
d. RST 3
• In 8085 microprocessor, the RST6 instruction transfer programme execution to
following location
a. 0030H
b. 0024H
c. 0048H
d. 0060H
• HLT opcode means
a. load data to accumulator.
b. store result in memory.
c. load accumulator with contents of register.
d. end of program.

2/2/2024 Karan Singh Microprocessor UNIT- 1 165

 MCQ

• In 8085 name/names of the 16 bit registers is/are

a. stack pointer.
b. program counter.
c. both A and B
d. None of the above
• What is SIM?
a. Select interrupt mask.
b. Sorting interrupt mask.
c. Set interrupt mask.
d. None of these.
• The ROM programmed during manufacturing process itself is called
a. MROM
b. PROM
c. EPROM
d. EEPROM

2/2/2024 Karan Singh Microprocessor UNIT- 1 166

 MCQ

• A mask programmed ROM is

a. programmed at the time of fabrication
b. programmed by the user
c. erasable and programmable
d. erasable electrically
• The program counter in a 8085 micro-processor is a 16-bit register, because
a. It counts 16-bits at a time
b. There are 16 address lines
c. It facilitates the user storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time
• A microprocessor is ALU
a. and control unit on a single chip.
b. and memory on a single chip.
c. register unit and I/O device on a single chip.
d. register unit and control unit on a single chip.

2/2/2024 Karan Singh Microprocessor UNIT- 1 167

 Glossary Questions
Fill in the blanks with correct options:
Options: a) 1951, b) 1960, c) 1940, d) 1971

1. The first digital electronic computer was built in ________.

(1940)
2. The Texas institute invented IC in _________.
(1960)
3. Microprocessor was invented in ________.
(1971)

2/2/2024 Karan Singh Microprocessor UNIT- 1 168

 Old Question Papers (Sessional &University)

• Not Available

2/2/2024 Karan Singh Microprocessor UNIT- 1 169

 Expected Questions

1. With the help of neat diagram explain the architecture of 8085

microprocessor in detail.
2. Explain the sequence of events during the execution of the CALL
instruction by 8085 processor with the help of neat timing diagram.
3. Write an assembly language program with comment lines. An 8-bit
number is stored in memory location C100H. Count number of ones (i.e.
1) in this byte and store this count in memory location C200H.
4. Draw and explain the timing diagram of memory write cycle with
example.
5. Draw and explain the timing diagram of opcode fetch cycle.
6. Explain Functions of PIN configuration of 8085 microprocessor.

2/2/2024 Karan Singh Microprocessor UNIT- 1 170

 Recap of Unit

• 8085 microprocessor internal architecture, PIN Diagram, Timing Diagram,

Addressing Modes, Interrupts are discussed.
• Various logic devices are discussed in detail for interfacing with 8085
microprocessor.

2/2/2024 Karan Singh Microprocessor UNIT- 1 171

 Thank You!

2/2/2024 Karan Singh Microprocessor UNIT- 1 172