UNIT-I: INTRODUCTION

What is Boolean algebra? How it is differ from Elementary algebra.

In mathematics and mathematical logic, Boolean algebra is a branch of algebra. It differs from elementary
algebra in two ways. First, the values of the variables are the truth values true and false, usually denoted 1
and 0, whereas in elementary algebra the values of the variables are numbers. Second, Boolean algebra
uses logical operators such as conjunction (AND) denoted as ∧ or dot symbol, disjunction (OR) denoted
as ∨ or Plus symbol, and the negation (NOT) denoted as ¬ or horizontal line above the symbol. Elementary
algebra, on the other hand, uses arithmetic operators such as addition, multiplication, subtraction and
division. Boolean algebra is therefore a formal way of describing logical operations, in the same way that
elementary algebra describes numerical operations.

 Boolean algebra is used for representing logical operations like AND (Conjunction), OR
(Disjunction) and NOT (Negation).
 Elementary algebra is used to represent elementary operations like addition, multiplication,
subtraction and division.

Why Boolean algebra?

Boolean algebra has been fundamental part in the development of digital electronics.

Boolean Logic:
 Boolean logic is a type of algebra in which results are calculated as either TRUE or FALSE (known
as truth values or truth variables). Instead of using arithmetic operators like addition, subtraction,
and multiplication, Boolean logic utilizes three basic logical operators: AND, OR, and NOT.
 Behind Boolean logic are two very simple words: TRUE and FALSE.
 Today’s digital devices are made up of Integrated circuits. Integrated circuits contains several small
circuits which performs small operations, for Eg. Any digital calculator contains several small units
which can perform different arithmetic operations like binary addition operation. So, combination
of several small digital units help in making an integrated circuits.
 These small digitals units are made using several ways. Boolean algebra is one of the basic way of
designing digital circuits.

Basic of Boolean algebra is Boolean logic. Boolean logic is divided into two types.

Binary Logic

Basic Derived

Basic Boolean Logic: There are 3 basic Boolean logic

1. AND
2. OR
3. NOT

Derived Boolean Logic: There are mainly 4 derived Boolean logic

1. NAND
 2. NOR
3. XOR
4. XNOR
Boolean/Binary Variables: Any variable which stores only two values either 0 or 1 is called as Boolean
variable.

Boolean AND operation: If both inputs are 1 then the output is 1 and in rest all other cases the
output is 0
TRUTH TABLE:
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

Logic Symbol of AND gate:

Boolean Expression of AND gate:

Y=AB
Boolean OR operation: If both inputs are 0 then the output is 0 and in rest all other cases the
output is 1.
TRUTH TABLE:
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

Logic symbol of OR gate:

Boolean Expression of OR gate:

Y=A+B

Boolean NOT operation: NOT operation is 1’s complement of the input. It reverses the logic
state. If the input is 1, then the output is 0. If the input is 0, then the output is 1.
TRUTH TABLE:

A Y=X’
0 1
1 0

Logic symbol of NOT gate:

Boolean expression of NOT gate:

Y= Ā

Derived Boolean Logic:

The NAND gate and NOR gate are called Universal gates because they can perform all the three basic
functions of AND, OR, and NOT gates.
Boolean NAND operation: NAND is opposite case of the AND gate. The NAND gate operates as an
AND gate followed by a NOT gate. It acts in the manner of the logical operation "AND" followed by
negation. The output is 0 if both inputs are 1 and in rest all other cases the output is 1.
TRUTH TABLE:
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

Logic symbol of NAND gate:

Boolean Expression of NAND gate:

Boolean NOR operation: The NOR gate is the union of the NOT and the OR gate. The output state
of the NOR gate will be high only when all of the inputs are low. Simply, this gate delivers the
complement result of the OR gate.
TRUTH TABLE:

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Logic symbol of OR gate:

Boolean expression of OR gate:

Boolean XOR operation: The Exclusive OR Gate, which is usually written as XOR Gate or EX-OR
Gate, is a two-input logic gate that performs an exclusive OR operation on its inputs. The output of
XOR Gate is 1 if the inputs are dissimilar i.e. if one input is 1 and the other input is 0. If both the inputs
are the same i.e., both are 1 or both are 0, then the output of XOR Gate is 0.
TRUTH TABLE:
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Logic symbol of XOR gate:

Boolean expression of XOR gate:

Boolean XNOR operation: The XNOR gate is the complement of the XOR gate. It is a hybrid gate.
Simply, it is the combination of the XOR gate and NOT gate. The output level of the XNOR gate is
high only when both of its inputs are the same, either 0 or 1. The symbol of the XNOR gate is the same
as XOR, only complement sign is added.
TRUTH TABLE:

A B Y
0 0 1
0 1 0
1 0 0
1 1 1

Logic symbol of XNOR gate:

Boolean expression of XNOR gate:

Combinational and Sequential Circuits:

Combinational Circuits:
A combinational circuit is one whose output at any time is based only on the present combination of
inputs at that point of time. Since it does not use past output so it does not contain any memory element.
A combinational logic circuit consists of NAND, NOR, and NOT logic gates. These logic gates are the
basic building blocks of the circuitry of a combinational circuit.

Figure: Illustrates Combinational Circuits

Examples of Combinational circuits:

 Multiplexer
 De-multiplexer
 Encoder
 Decoder

Multiplexer: A multiplexer (MUX) is a combinational circuits which have many inputs and single
output depending upon select lines. Multiplexer is also called as many-to-one circuit, data selector and
parallel to serial converter

If select lines = n, Inputs= 2n and Output=1

 Figure: Illustrates 4*1 Multiplexer
De-multiplexer (DeMux): A multiplexer (MUX) is a combinational circuits which has single input
and many outputs depending upon select lines. De-multiplexer is exactly opposite of the Multiplexer
and is also called as many-to-one circuit, data distributor.

Fig: Illustrates 1*4 Multiplexer

If selects line = n, and Input =1 output=2n

Encoder and Decoder: Both encoder and decoder are multiple input and multiple output devices.
Decoder is combinational circuit that converts n lines of input into 2n lines of output. On the other hand
encoder is also a combinational circuit which takes 2n inputs and produces n output.

Fig: Illustrates block diagram of Encoder

Fig: Illustrates block diagram of Decoder

Sequential Circuits:
A sequential circuit is a type of digital logic circuit whose output not only relies on the current input
but also depends on the previous/past output. Hence, a sequential circuit is basically a set of
combinational circuits and memory elements connected in a feedback path.
 Fig: Illustrates Sequential Circuits
Examples for Sequential circuit:

 Flip-Flop
 Registers
 Counters
Flip flop: Flip flop is a memory element containing only 1 bit of information. Flip always produces two
outputs, one is normal output and other is complement (Inverted) output.

Fig: Block diagram of Flip-Flop

Types of Flip flops:

 S-R Flip flop (Set-Reset Flip Flop)
 J-K Flip flop (Jack-Kilby Flip flop)
 D Flip flop (Delay Flip flop)
 T Flip flop (Toggling Flip flop)
Latches: Latches is defined as a logical circuit that is used for storing single binary digit.
Latch stores data using a feedback loop that helps memory elements to store binary
information.

 The feedback loops are created in circuit diagrams so that output values depend on
themselves indirectly.
 Input of a latch works as an electronic switch to control the state of device. Latch
circuits have two output stable states, LOW & HIGH.
 Therefore, latch is also called as bistable-multivibrator.
A latch’s output depends on its current and previous inputs, and its state can change at
any time when input changes.
Registers: A register is a collection of flip-flop used to store n-bit of information. Normally
flip-flop stores only 1 bit information so, to store more than 1 bit of information registers are
used.

Functional Components of Computer: Computer contain mainly three components

and they are.
1. CPU
2. Memory
3. I/O devices

1. CPU: CPU contains two subparts and they are Control Unit (CU) and Arithmetic and Logic
Unit (ALU)

i) Control Unit: Control unit controls the whole system by sending control signals.
ii) ALU: ALU is responsible for performing arithmetic and logical operations.

2. Memory: This unit can store instructions, data, and intermediate results. This unit supplies
information to other units of the computer when needed. It is also known as an internal storage
unit or the main memory or the primary storage or Random Access Memory (RAM).

Primary memory (RAM and ROM) and secondary memory (HDD and SSD) are two types of
memories in the computer.

3. I/O devices: An input/output device, often known as an IO device, is any hardware that
allows a human operator or other systems to interface with a computer. Input/output devices,
as the name implies, are capable of delivering data (output) to and receiving data from a
computer (input). An input/output (I/O) device is a piece of hardware that can take, output, or
process data.

Input devices are the devices that are used to send signals to the computer for performing tasks.

Some of the classification of input devices are:

 Keyboard devices
 Mouse, Joystick, Track ball, Light pen etc.
 Game Controller
 Audio Input devices
 Scanner
 Mouse

Output Devices are the devices that show us the result after giving the input to a computer
system. Output can be of many different forms like image, graphic audio, video, etc. Some of
the output devices are described below.
  Monitor
 Printer
 Speakers
 Projectors
 Plotter

Other Components of Computer Systems

1. System bus
2. Registers

1. System bus: Collection of communication lines between components of computer is called

as system bus. One communication line is responsible for sending 1-bit of information. So, if
we need to transfer or receive n-bit of information then collection of communication lines are
used and is called as system bus.

There are 3-types of buses:

i) Address bus
ii) Data bus
iii) Control bus

Fig: Illustrates types of buses:

In the above figure first unidirectional line from CPU to Memory and I/O devices indicate
address bus. It is unidirectional because address can only flow from CPU to memory and I/O
devices and vice-versa is not possible.

Both data bus and control bus are bi-directional because data and control signals can flow from
CPU to memory and I/O devices and vice-versa is also possible.

Registers: Small storages inside the CPU are called as registers. Registers are memory element
used to store n-bit of information. Based on what information the registers contains, there are
mainly two types of registers.
i) General purpose registers
ii) Special purpose registers
i) General purpose registers: Used store general purpose information like operand value,
intermediate results etc. General purpose registers are normally represented as R0, R1, R2, R3
…..Rn.
ii) Special Purpose registers: Used to store special information. Every special registers are
used store a specific information. At any given point of time these registers will not store any
other information other than the one which is dedicatedly designed for.

Following Special types of registers are used to store some specific information. They are,

1. Accumulator (AC)
2. Program Counter (PC)
3. Instruction Register (IR)
4. Stack Pointer (SP)
5. Flag Register /Status Register / Program Status Word (PSW)
6. Address Register (AR) / Memory Address Register (MAR)
7. Data Register (DR) / Memory Data Register (MDR)

1. Accumulator (AC): Used to store result of ALU and sometimes to store one of the operand
for ALU too.

2. Program Counter (PC): Used to store address of next instructions to be executed.

3. Instruction Register (IR): Used to store current instruction going for execution.
4. Stack Pointer (SP): Used to store address of Top-of-the stack
5. Flag Register / Status Register / Program Status Word (PSW): Used to store the status of
ALU result. If ALU is performing arithmetic operations the result may generates a carry, or
result may be a zero or it may produce positive or negative number based on that flag register
contains the status as shown in below figure.

6. Address Register (AR) / Memory Address Register (MAR): Used to send address to
memory. Before sending the address to memory for any read/write operation, the address is
stored in a register called as Memory Address Register (MAR).
7. Data Register (DR) / Memory Data Register (MDR):
Used to:
i) Send data to memory (during memory write operation)
ii) To receive data from memory (during memory read operation)
 UNIT-II: Instruction Set Architecture of a CPU

What is instruction?: A group of bits which instructs computer to perform specific operation.
Instruction contains two information (Syntax of Instruction):
Opcode Operand Information

8-Bits (For 8-bit instruction architecture)

Opcode (3-bits): Determines what operation needs to be performed.

Operand information (5-bits): This filed gives information about the operand on which
operation needs to be performed.
Conversion of High level programming into machine language (Binary code):

High Level Language Binary Language

(Instructions)

Register Transfer Language (RTL):

Register: Register is small storage used to store n-bit of information. Registers are represented
in different ways as shown below.
Fig: a) Represents register R1 b) Represents content of register c) Represents bits numbering
of 16-bit PC register d) Represents register PC divided into 2-parts lower bits (0-7) and
higher bits (8-15)

Micro-operations: Basic operations performed on content of the registers is called as micro-

operations. Micro-operations are divided into 3-types.
i) Arithmetic micro-operations
ii) Logic micro-operations
iii) Shift micro-operations

Some of the arithmetic micro-operations are:

Register Transfer: Transferring content of one register to another register is called as register
transfer.

Register transfer takes place only when register receives a transfer control signals, which is
indicated as follows.

If (p=1) R1R2: When P=1 there is control signal and hence register transfer takes place from
R2 to R1), which can also be written as, P: R1R2

Register Transfer Language (RTL): Refers to symbolic notations which specifies register
transfer micro-operations.
Notations used in RTL:

Apart from above notations few other notations are:

1. If data is coming into the register, for example data is receiving into the MDR register
then it is represented as MDRin.
2. Id data is going out of the register, for example data is going out of the MDR register
then it is represented as MDRout.

Example of RTL: Fetch the data from memory to R0 register:

1. MARin, Read
2. MDRin
3. MDRout, R0in

Addressing Mode: Every instructions contains two information first one is OPCODE and
second one is OPERAND INFORMATION. Addressing mode refers to how operand
information is specified in the instruction.

Basic Requisites to understand Addressing mode:

1. MOV R0, R1: Here R0 is destination operand and R2 is source operand.

2. General Purpose registers in 8086 machine architecture:
 3. Physical address can be calculated as,
Physical address= Segment Address*10H + offset.
Here, offset contains three parts: 1. Displacement 2. Base register content 3. Index
register content.

Based on how the operand information is specified in the instructions, we have following types
of addressing modes (In 8086 Machine Architecture).

1. Immediate addressing mode.

2. Direct Addressing mode.
3. Register Addressing mode.
4. Register-indirect addressing mode.
5. Indexed addressing mode.
6. Register-relative addressing mode.
7. Based-Indexed addressing mode.
8. Relative-Base-Indexed addressing mode.

1. Immediate addressing mode: Here, the source operand contains the required data
itself.
Eg: MOV AX, 0010H
Here, 0010H is the required data in HEX format.

2. Direct addressing mode: Here, the source operand contains address of the required
data.
Eg: MOV AX, [4896H]

Here, [4896H] is the offset address. Using offset address we can calculate Physical
address. Content from that physical address is moved to AX register.

3. Register addressing mode: Here, the source operand is a register and contains the
required data.
Eg: MOV AX, BX

4. Register-indirect addressing mode: Here, the offset address of the data is in either of
one of the BP, BX, SI and DI register.
Eg: 1. MOV AX, [BX]
2. MOV AX, [SI]

5. Indexed Addressing mode: Here, the offset address of the data is specified by the sum
of contents of the SI/DI registers and 8bit/16bit displacement.
Eg: MOV DX, 08H [SI]

6. Register-relative addressing mode: Here, the effective address is formed by adding

an 8bit/16bit displacement with the content of any one of the registers BX, BP, SI and
DI in the default segment of DS or ES segment.
Eg: MOV AX, 30H [BX]
 7. Based-Indexed addressing mode: In this addressing mode, the effective address of
the data is formed by adding content of base register (BX or BP) to the content of the
index register (SI or DI).
Eg: MOV AX, [BX] [SI]

8. Relative-Based-Indexed addressing mode: In this addressing mode, the effective

address of the data is formed by adding 8bit/16bit displacement with content of base
register (BX or BP) and content of the index register (SI or DI).
Eg: MOV AX, 30H [BX] [SI]

Instruction Set of 8086 machine architecture:

8086 machine architecture contains more than 20000 instructions in it. These instructions are
broadly classified into 9-types as follows.

1. Data transfer/Data copy instructions

2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Loop instructions
6. Machine/processor controlled instructions
7. Flag manipulation instructions
8. Shift and rotate instructions
9. String manipulation instructions

1. Data Transfer/Data Copy Instructions: The data transfer instructions move data between
memory and the general-purpose and segment registers, and perform operations such as
conditional moves, stack access, and data conversion. Data transfer instructions does not affect
carry flag or overflow flag. Few data transfer instructions are listed as below

 MOV (MOVE operation)

 XCHG (Exchange operation)
 LEA (Load effective address)
 LDS (Load data segment register)
 LES (Load extra segment register)
 PUSH
 POP

MOV: Syntax of MOV instruction is,

MOV Destination operand, Source Operand

MOV instructions move data from source operand to the destination operand.
Eg: 1) MOV AX, BX 2) MOV AX, [4895H]
XCHG: Syntax of XCHG instruction is,

XCHG Destination Operand, Source Operand

XCHG instructions exchange the content of destination operand and source operand
Eg: 1) XCHG AX, BX 2) XCHG AX, [4895H]

LEA: Syntax of LEA instruction is,

LEA Register, Source operand

LEA instruction loads effective address mentioned in the source operand into the register
(Destination Operand).
Eg: LEA AX, [4895H]

LDS: Syntax of LDS instruction is,

LDS Register, Memory address of the first word of Data Segment

LDS instructions loads starting address of data segment/ address of the first word in data
segment into the register (Destination operand).
Eg: LDS AX, [4896H]

LES: Syntax of LES register is,

LES Register, Memory address of the first word of Extra Segment

LES instructions loads starting address of extra segment/ address of the first word in extra
segment into the register (Destination operand).
Eg: LES BX, [6000H]

PUSH: Syntax of the PUSH instruction is,

PUSH Register

PUSH instruction pushes the content of the register (Destination operand) into the top of the
stack in stack segment.
Eg: PUSH AX

POP: Syntax of POP instruction is,

POP Register

POP instructions loads the content of top of the stack into the register (Destination Operand)
2. Arithmetic instructions: Arithmetic Instructions are the instructions which perform basic
arithmetic operations such as addition, subtraction and a few more. Unlike in 8085
microprocessor, in 8086 microprocessor the destination operand need not be the accumulator.
Arithmetic instructions does not affect carry flag or overflow flag. Few of the arithmetic
instructions are,

 ADD (Addition)
 ADC (Addition with carry)
 SUB (Subtraction)
 SBB (Subtraction with borrow)
 MUL (Multiplication)
 INC (Increment)
 DEC (Decrement)

ADD: Syntax of ADD instruction is,

ADD Destination operand, Source Operand

ADD instruction adds the content of destination operand and source operand and stores the
result in the destination operand only.
Eg: 1) ADD AX, BX 2) ADD AX, [5609H]

ADC: Syntax of ADC instruction is,

ADC Destination operand, Source Operand

ADC instruction adds the content of source operand plus the status of the carry flag with
destination operand
Eg: ADC AX, BX

SUB: Syntax of SUB instruction is,

SUB Destination operand, Source Operand

SUB instruction subtracts the content of source operand and destination operand and stores the
result in the destination operand only.
Eg: SUB AX, BX

SBB: Syntax of SBB instruction is,

SBB Destination operand, Source Operand

SBB instruction subtracts the content of destination operand with source operand plus the status
of the carry flag.
Eg: SBB AX, BX
MUL: Syntax of MUL instruction is,

MUL Source operand

Here, by default the destination operand is always ACCUMULATOR register so it is not

necessary to mention destination operand explicitly. MUL instruction performs multiplication
operation with source operand and default accumulator register and the result is stored in
accumulator register only.
Eg: MUL BX

INC: Syntax of INC operand is,

INC Destination operand

INC instruction increments the value of destination operand by 1.

Eg: INC AX

DEC: Syntax of INC operand is,

DEC Destination operand

DEC instruction decrements the value of destination operand by 1.

Eg: DEC AX

3. Logical instructions: Logical instructions in the 8086 microprocessor are instructions that
perform logical operations on data stored in registers or memory locations. These instructions
can manipulate bits within a byte, set or clear individual bits, or perform Boolean operations
such as AND, OR, XOR, NOT and NEG. Logical instructions does not affect carry flag or
overflow flag. Few of the logical instructions are listed as below.

 AND
 OR
 XOR
 NOT
 NEG

AND: Syntax of AND instruction is,

AND Destination operand, Source Operand

AND instruction performs a bitwise logical AND operation between destination and source
operands and stores the result in the destination operand.
Eg: AND AX, BX
OR: Syntax of OR instruction is,

OR Destination operand, Source Operand

OR instruction performs a bitwise logical OR operation between destination and source

operands and stores the result in the destination operand.
Eg: OR AX, BX

XOR: Syntax of XOR instruction is,

XOR Destination operand, Source Operand

XOR instruction performs a bitwise logical XOR operation between destination and source
operands and stores the result in the destination operand.
Eg: XOR AX, BX

NOT: Syntax of NOT instruction is,

NOT Destination operand

NOT instruction performs a bitwise logical NOT (negation/1’s complement) operation on the
destination operand and stores the result in the destination operand only.
Eg: NOT AX

NEG: Syntax of NEG instruction is,

NEG Destination operand

NEG instruction performs a bitwise logical NEG (2’s complement+1) operation on the
destination operand and stores the result in the destination operand only.
Eg: NEG AX

4. Branch Instructions: Branch instructions transfer the flow of execution of the program to
a new address specified in the instruction directly or indirectly. Branch instructions does not
affect carry flag or overflow flag. Few of the conditional branch instructions are as below.

 JC (Jump if carry)
 JNC (Jump if no carry)
 JZ (Jump if zero)
 JNZ (Jump if not zero)
 JPE (Jump if parity bit is even)
 JPO (Jump if parity bit is odd)

JC: Syntax of JC instruction is,

JC Address
JC instruction checks whether the carry flag is set or not. If yes, then jump takes place, that
is: If CF = 1, then jump.
Eg: JC NEXT

JNC: Syntax of JNC instruction is,

JNC Address

JNC checks whether the carry flag is reset or not. If yes, then jump takes place, that is: If CF =
0, then jump.
Eg: JNC NEXT

JZ: Syntax of JZ instruction is,

JZ Address

JZ checks whether the zero flag is set or not. If yes, then jump takes place, that is: If ZF = 1,
then jump.
Eg: JZ NEXT

JNZ: Syntax of JNZ instruction is,

JNZ Address

JNZ checks whether the zero flag is set or not. If no, then jump takes place, that is: If ZF = 0,
then jump.
Eg: JNZ NEXT

JPE: Syntax of JPE instruction is,

JPE Address

JPE checks whether the parity flag contains even number or odd. If even, then jump takes place.
Eg: JPE NEXT

JPO: Syntax of JPO instruction is,

JPO Address

JPO checks whether the parity flag contains even number or odd. If odd, then jump takes place.
Eg: JPO NEXT

5. Shift and Rotate instructions: These instructions are used to perform logical or arithmetic
shift and rotate operations where a bit of data is involved. Shift and Rotate instructions affect
carry flag or overflow flag. Few of the shift and rotate instructions are as below.
  SHR (Shift Right)
 SAR (Shift Arithmetic Right)
 SHL (Shift Left)
 SAL (Shift Arithmetic Left)
 ROL (Rotate Left)
 ROR (Rotate Right)

SHR: Syntax of SHR instructions is,

SHR Register, Number of bits to be shifted

SHR instruction simply shifts the mentioned bits in the register to the right side one by one by
inserting the same number (bits that are being shifted) of zeroes from the left end. The rightmost
bit that is being shifted is stored in the Carry Flag (CF).
Eg: SHR AX, 2

SAR: Syntax of SAR instructions is,

SAR Register, Number of bits to be shifted

This instruction shifts the mentioned bits in the register to the right side one by one, but instead
of inserting the zeroes from the left end, the MSB is restored. The rightmost bit that is being
shifted is stored in the Carry Flag (CF).
Eg: SAR BX, 5

SHL: Syntax of SHL instructions is,

SHL Register, Number of bits to be shifted

This instruction simply shifts the mentioned bits in the register to the left side one by one by
inserting the same number (bits that are being shifted) of zeroes from the right end. The leftmost
bit that is being shifted is stored in the Carry Flag (CF).
Eg: SHL AX, 2

SAL: Syntax of SAL instructions is,

SAL Register, Number of bits to be shifted

This instruction is the same as SHL.

Eg: SAL AX, 3

ROL: Syntax of ROL instructions is,

ROL Register, Number of bits to be shifted

This instruction rotates the mentioned bits in the register to the left side one by one such that
leftmost bit that is being rotated is again stored as the rightmost bit in the register, and it is also
stored in the Carry Flag (CF).
Eg: ROL AH, 3

ROR: Syntax of ROL instructions is,

ROR Register, Number of bits to be shifted

This instruction rotates the mentioned bits in the register to the right side one by one such that
rightmost bit that is being rotated is again stored as the leftmost bit in the register, and it is also
stored in the Carry Flag (CF).
Eg: ROR AH, 2

6. Machine Control Instructions: Machine control instructions are a type of instruction that
control machine functions such as Halt, Interrupt, or do nothing. These instructions does not
alter carry flag or overflow flag. Few machine control instructions as follows.

 NOP (No-operation)
 HLT (Halt)

NOP: Syntax of NOP instructions is,

NOP

NOP is used when no operation is performed. It is commonly used to fill in time delay or to
delete and insert instructions while troubleshooting.

HLT: Syntax of HLT instructions is,

HLT

HLT is used to stop the execution of the program temporarily. The microprocessor finishes
executing the current instruction and halts any further execution. The contents of the registers
are unaffected during the HLT state. HLT can be used to enter a wait state in which the
microprocessor waits for a specific event to occur before resuming execution. Processor gets
out of halt state upon an interrupt signal (INTR and NMI) or reset signal (RESET)

7. Flag manipulation instructions: The Flag manipulation instructions directly modify some
of the Flags of 8086. Few flag manipulation instructions are as follows.

 CLC (Clear Carry Flag)

 CMC (Complement Carry Flag)
 STC (Set Carry Flag)
 CLD (Clear Direction Flag)
 STD (Set Direction Flag)
  CLI (Clear Interrupt Flag)
 STI (Set Interrupt Flag)

8. String manipulation instructions: The 8086 supports a set of more powerful instructions
for string manipulations for referring to a string, two parameters are required. Few of the string
manipulation instructions are.

 REP (Repeat instruction prefix)

 REPE/REPZ (Repeat instruction while equal/zero)
 MOVSB/MOVSW (Move string byte or string word)
 CMPS (Compare string byte or string word)

REP: This instruction is used as a prefix to other instructions, the instruction to which the REP
prefix is provided, is executed repeatedly until the CX register becomes zero (at each iteration
CX is automatically decremented by one).

REPE/REPZ: Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.

MOVSB/MOVSW: Used to move the byte/word from one string to another.

CMPS: Used to compare two string bytes/words.