Chapter 3 : Addressing mode of the 8086 microprocessor

Table of contents for chapter 3

1 Memory Management ..................................................................................................................................22
2 Addressing Modes .........................................................................................................................................23
2.1 Immediate Addressing:..........................................................................................................................23
2.2 Register Addressing: ..............................................................................................................................24
2.3 Direct Addressing: .................................................................................................................................24
2.4 Indirect Addressing ................................................................................................................................24
2.4.1 Indexed Addressing .......................................................................................................................24
2.4.2 Base Addressing.............................................................................................................................26
2.4.3 Indirect Addressing with Displacement .........................................................................................26
2.4.4 Base and Indexed Addressing with Displacement .........................................................................26
3 Load Address Instructions .............................................................................................................................27
4 Data Transfer Instructions .............................................................................................................................27
5 Tutorial exercises No 3 ..................................................................................................................................29
6 Correction of Tutorial exercises No 3 ............................................................................................................31

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Chapter 3 : Addressing mode of the 8086 microprocessor

Chapter 3 : Addressing mode of the 8086 microprocessor

1 Memory Management
The addressable memory space of the 8086 is 1 MB, which equals 2 20 bytes (with a 20-bit address bus). This
memory is divided into four logical segments, each of 64K bytes (or 2 16 bytes). The 8086's registers are 16-bit
registers, which means they cannot cover the entire memory space directly. To address memory locations, two
registers are used to specify an address to the processor.
The pair (CS:IP) points to the address of an instruction in memory. A segment is a memory area defined by its
starting address, where the 4 least significant bits are set to zero.
To specify a memory location among the 216 (or 64K) locations contained within a segment, a 16-bit value is
sufficient. This is how the 8086 identifies a memory location.

Logical address, also referred to as the Effective Address (EA) or Offset, is contained within the 16-bit registers
IP, BP, SP, BX, SI, or DI.
Note that the range of logical addresses spans from 0000H to FFFFH.

Figure 3.1. Memory Segmentation.

A pair of (segment, offset) defines a logical address, represented in the form segment:offset.
- Physical address (PA) is an address presented as a 20-bit value (5 hexadecimal digits) because it corresponds
to the actual value sent on the address bus A0 to A19.
Note: The range of physical addresses spans from 00000H to FFFFFH.
The mapping between the logical address and the physical address is depicted in the following figure:

Figure 3.2. Calculating the 20-bit Physical Address

A 20-bit instruction address is computed using the operation (CS x 16) + IP.
Therefore, the physical address is calculated by the expression :

Physical address = (segment register × 16) + offset

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Chapter 3 : Addressing mode of the 8086 microprocessor

Because injecting four zeros in the least significant bits of the segment address (in binary) is equivalent to
performing a left shift of 4 positions (4 bits), which is essentially a multiplication by 24 = 16.

Example:
Consider the instruction MOV BL, [SI].
Assuming the DS register contains the value 2400H and the SI register contains 0410H, the physical address of
the source operand pointed to by the SI register in the data segment is given by:
phys_addr = DS x 10H + SI = 2400H x 10H + 0410H = 24410H.
If the CS register contains the value 2367H and the IP register contains the value 5563H, the physical address
of the instruction is given by:
phys_addr = CS x 10H + IP = 2367H x 10H + 5563H = 28BD3H.
Example:
Consider the instruction MOV BL, ES:[SI].
Assuming the DS register contains the value 2400H, the SI register contains 0410H, and ES contains 5000H, the
physical address of the source operand pointed to by the SI register in the Extra segment is given by:
phys_addr = ES x 10H + SI = 5000H x 10H + 0410H = 50410H.

2 Addressing Modes
Data transfer instructions allow for moving data from a source to a destination, including:
Register to memory.
Register to register.
Memory to register.
Note: The 8086 does not permit memory-to-memory transfers; to achieve this, you must go through an
intermediate register.
Syntax: MOV destination, source
Note: MOV is an abbreviation of the verb "to move," signifying the action of moving.
There are various ways to specify the address of a memory location within an instruction, and these are known
as addressing modes.

2.1 Immediate Addressing:

constante.
The operand appears in the instruction, and the operand is a constant value.
Example: MOV AL, 12H; The instruction loads the AL register with the value 12H.
MOV [1100H], 40H; The instruction stores the value 40H in the memory location with the address
1100H.
Note: In this mode, it is necessary to specify the data format: byte or word (2 bytes), as the 8086 microprocessor
can handle data in either 8-bit or 16-bit formats. To do this, a format specifier must be used:
MOV byte ptr [1100H], 65H: Transfers the value 65H (as an 8-bit byte) to the memory location at offset 1100H.
MOV word ptr [1100H], 65H: Transfers the value 65H (as a 16-bit word) to the memory locations at offsets
1100H and 1101H.

Figure 3.3. Immediate Addressing

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Chapter 3 : Addressing mode of the 8086 microprocessor

2.2 Register Addressing:

The transfer occurs from one register to another. In this mode, the size of both registers must be the same.
Example: MOV AX, BX
The instruction loads the contents of the BX register into the AX register.
2.3 Direct Addressing:
The transfer occurs between a register and a memory location, or between a memory location and a register.
Example: MOV AL, [2400H]
The value 2400H represents the offset of the memory location within the data segment (DS). The instruction
loads the contents of the memory location at address 2400H into the AL register.

Figure 3.4. Direct Addressing

You can use a different segment, but to do so, you need to specify the desired segment in the instruction.
Example: MOV AL, ES:[1200H]
Here, ES is used as a segment prefix in the instruction to specify the segment in which the transfer will be
performed. The instruction loads the contents of the memory location at address 1200H in the Extra Segment
into the AL register.

Figure 3.5 Direct Addressing from the Extra Segment

2.4 Indirect Addressing
In this addressing mode, the content of the DS register is combined with the effective address to obtain the
physical address. The address of the operand is stored in a register that needs to be loaded with the correct
address beforehand. The address of the operand will be stored in a base register (BX or BP) or an index register
(SI or DI).

2.4.1 Indexed Addressing

In this addressing mode, the memory operand's address is determined by the content of the SI (source index)
or DI (destination index) register. The DS register is assumed by default.

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Chapter 3 : Addressing mode of the 8086 microprocessor

Exemple 1 :
Consider the instruction: MOV AL, [SI]

Figure 3.6. Example of Indexed Addressing

If the content of the SI register is 2400H, it means transferring the content of the memory location at offset
[2400H] located in the data segment into the AL register.

Example 2:
Consider the following two examples:
a) MOV BL, [SI]
b) MOV CL, [DI]

These instructions show that the data located in the memory locations pointed to by the SI and DI index
registers are transferred to the BL and CL registers, respectively. The physical address (PA) of the desired
memory location is given by:
PA1 = DS × 10H + SI (for the instruction: MOV BL, [SI])
PA2 = DS × 10H + DI (for the instruction: MOV CL, [DI])
If the DS register contains the value 0500H, and the SI and DI registers contain the values 0082H and 0092H,
respectively, the physical addresses of the memory operands corresponding to the above instructions are as
follows:
PA1 = 0500H × 10H + 0082H = 5082H.
PA2 = 0500H × 10H + 0092H = 5092H.

Example 3:
In this example, indexed addressing is used to access elements of a memory array named TABLE.
TABLE represents the offset of the first element (a memory word) of the array, and the SI register serves as the
array index:
MOV SI, 0 ; SI points to the first element of the 'TABLE' array
MOV word ptr TABLE[SI], 1234H
MOV SI, 2
MOV word ptr TABLE[SI], 5678H

Figure 3.7. Example of Accessing an Element in a Memory Array

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Chapter 3 : Addressing mode of the 8086 microprocessor

2.4.2 Base Addressing

Similar to indexed addressing, except that the offset is contained in the BX index register, which is by default
associated with the data segment.
Similar to indexed addressing, except that the offset is contained in the BX index register, which is by default
associated with the data segment.
Example: MOV AL, [BX], this instruction transfers the data whose offset is contained in the base register BX to
the AL register. The segment associated by default with the BX register is the data segment; this is referred to
as base addressing.
Consider the following two examples:
a) MOV AL, [BP]
b) MOV CL, [BX]
To calculate the physical address of the two instructions above, the following formulas are used:
PA = SS × 10H + BP (SS: Stack Segment register, and BP: base pointer register)
PA = DS × 10H + BX (DS: Data Segment register, and BX: base register)
Example: MOV AL, [BP]: the default segment associated with the base register BP is the stack segment (SS). In
this case, the addressing is based on SS.

Figure 3.8. Example of Base Addressing

2.4.3 Indirect Addressing with Displacement
In this addressing mode, a constant value can be added to the base or index registers to obtain the offset.
Indexed Addressing with Displacement
Example: MOV [SI+100H], AL; 100H is the displacement, which can also be written as MOV [SI][100H], AL or
even MOV 100H[SI], AL.
Base Addressing with Displacement
It is similar to indexed addressing.
Example: MOV [BX+100H], AL

2.4.4 Base and Indexed Addressing with Displacement

In this addressing mode, the memory operand's offset is obtained by summing a base register, an index register,
and a constant value.
Example: MOV AH, [BX][SI+100H]
This addressing mode allows for addressing complex data structures, such as arrays, records, etc.
Example:
MOV BX, 10
MOV SI, 15
MOV byte ptr MATRIX[BX][SI], 12H
In this example, BX and SI serve as row and column indices in the matrix.
Base or indexed addressing modes enable the manipulation of arrays stored in memory.
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Chapter 3 : Addressing mode of the 8086 microprocessor

3 Load Address Instructions

The table below describes the instructions that allow for loading the addresses of memory locations.
Table 3.1. Load Address Instructions
Tableau 3.1. Load Address Instructions
Instruction Operands Description of the instruction
Load Effective Address : loading the offset of the 'mem' operand into the destination register 'reg'.
LEA op1, op2 Reg, Mém
Load memory double word into word register and ES : This instruction copying a 32-bit memory
LES op1, op2 Reg, Mém address into the segment register pair ES and a specified offset register 'reg'.
Load memory double word into word register and DS : This instruction copying a 32-bit memory
LDS op1, op2 Reg, Mém address into the segment register pair DS and a specified offset register 'reg'.
Load byte at DS:[SI] into AL. Update SI : loading the content of the memory address DS:SI into the
LODSB accumulator register and increments/decrements the SI register by 1 based on the direction flag (DF)
Sans
(Without an state.
operand)
opérande
Si DF = 0 alors SI = SI + 1 Sinon SI = SI 1.
Load word at DS:[SI] into AX. Update SI : loading the content of the memory address DS:SI into the
Sans accumulator register and increments/decrements the SI register by 2 based on the state of the
LODSW
opérande direction flag (DF)..

Si DF = 0 alors SI = SI + 2 Sinon SI = SI 2.
Remarque : Ces instructions n nt pas les indicateurs

4 Data Transfer Instructions

The table below describes the instructions that allow data loading.
Table 3.2. Data Transfer Instructions
Instruction Operands Description of the instruction
Copy byte at DS:[SI] to ES:[DI]. Update SI and DI. This instruction copies a byte from the address
DS:[SI] to the address ES:[DI] and increments/decrements the DI and SI registers by 1 based on the
Sans direction flag (DF) state.
MOVSB
opérande
Si DF = 0 alors SI = SI + 1 et DI = DI + 1
Sinon SI = SI 1 et DI = DI 1
Sans Copy word at DS:[SI] to ES:[DI]. Update SI and DI. This instruction copies a word from the address
opérande DS:[SI] to the address ES:[DI] and increments/decrements the DI and SI registers by 2 based on the
state of the direction flag (DF).
MOVSW
Si DF = 0 alors SI = SI + 2 et DI = DI + 2
Sinon SI = SI 2 et DI = DI 2
Sans Store byte in AL into ES:[DI]. Update DI.
STOSB opérande - ES:[DI] = AL
- if DF = 0 then DI = DI + 1 else DI = DI - 1
Sans Store word in AX into ES:[DI]. Update DI.
STOSW opérande - ES:[DI] = AX
- if DF = 0 then DI = DI + 2 else DI = DI - 2
Reg, Mém
Exchange values of two operands : Exchanging the values of two operands. The operands can be
XCHG op1, op2 Mém, Reg
two registers, a register and a memory location, or a memory location and a register.
Reg, Reg
Translate byte from table. Copy value of memory byte at DS:[BX + AL] to AL register. This
Sans
XLATB instruction replacing the content of the AL register with a byte from the "source table.
opérande
DS:[BX + AL]

Note: These instructions do not affect the flags

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Chapter 3 : Addressing mode of the 8086 microprocessor

Instruction Description of the instruction Affected flags

Repeat the following instructions MOVSB, MOVSW, LODSB, LODSW, STOSB, STOSW CX
REP times.
ZF
(Without an While CX <> 0, do the following.
operand) Executer instruction
CX = CX - 1

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Chapter 3 : Addressing mode of the 8086 microprocessor

5 Tutorial exercises No 3
Exercise 01 :
Evaluate the following instructions, are they correct (yes/no)? (Then provide your justification)
TEMP1 and TEMP2 are two memory bytes.
a) MOV TEMP1, TEMP2
b) MOV AL, BX
c) MOV BX, AL
d) MOV TEMP1, AX
e) MOV 55H, AL
f) MOV AL, [4000H]
g) MOV AL, [SI]
h) MOV AL, SI
i) MOV BX, [2000H]
j) MOV byte ptr [1100H], 6500H
k) PUSH BL
l) PUSH BX
Exercise 02 :
Choose the correct answer
1. The range of effective addresses (EA) spanning from
a) 0000H à FFFFH.
b) 00000H à FFFFFH.
2. The range of physical addresses (PA: Physical Address) ranging from
a) 0000H à FFFFH.
b) 00000H à FFFFFH.
3. In indexed addressing, the address of the operand is stored in
a) le registre SI ou DI.
b) le registre BX ou BP.
c) Les registres SI et BX.

4. In indirect addressing mode, the physical address of the operand is obtained by combining the content of the
DS register:
a) with an immediate value.
b) with one or more general registers.

Exercise 03:
1. If the physical address of the instruction MOV AL, [BX+SI] is 46F32H and the content of the IP register is
6F02H, determine the content of the CS register.
2. Determine the Physical Address of the Source Operand (PASO) for the instruction, knowing that BX = 0430H,
DS = 2300H, SI = 320H, and AL = 33H.
3. Rewrite the instruction using direct addressing.

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Chapter 3 : Addressing mode of the 8086 microprocessor

Exercise 04:
1. If the physical address of an instruction is 46F32H and the content of the code segment register CS is
42F3H, determine the value contained in the instruction pointer register IP.
2. Determine the physical address (PA) of the memory location pointed to by SI in the instruction: MOV BL,
[SI]. Knowing that the content of SI = 0410H and that of DS = 2400H.
3.
a) Determine the physical address of the operand in the instruction: MOV AL, [SI][BX], knowing that the
content of SI = 0220H, BX = 0140H, and DS = 3000H.
b) What type of addressing is used in this instruction?
c) Can this instruction be written in another form? If yes, rewrite it.
d) Determine the physical address of the operand in the instruction MOV AL, [SI][BX+200H]. What type of
addressing is used in the last instruction?

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