ECE 341

Lecture # 3
Instructor: Zeshan Chishti
[email protected]

October 6, 2014

Portland State University

 Lecture Topics
• Registers
• Counters
• Finite State Machines

• Reference: Appendix A of the textbook, sections A.7, A.8, A.13.

 Registers
• A flip-flop stores one bit of information
• When a set of n flip-flops is used together to store n bits of data,
it is referred to as a n-bit register
• All flip-flops in a register are synchronized by a common clock
– Data loaded and stored into all flip-flops at the same time
• Common register usage:
– Temporary storage of data output from an arithmetic circuit
D0 D1 Dn-1

D Q D Q D Q
……………………
Clk

Write operation in a n-bit register

 Shift Register
• A register whose contents may be shifted one bit position at a time
– To the right or left or possibly both
• Example: Shift Right Register
– At each positive clock edge, contents of Fi are shifted to Fi+1 (right shift)
– Gated latch unsuitable for a shift register, no control over # bit shifts per clock
F1 F2 F3 F4

Shift Right Register

 Example: Shift Right Register
• Example: Data 1001 needs to be written to a 4-bit shift right register

Before the first

+ve clock edge F1 F2 F3 F4

1 x x x x

Shift Right Register

 Example: Shift Right Register
• Example: Data 1001 needs to be written to a 4-bit shift right register

After first +ve

clock edge F1 F2 F3 F4

0 1 x x x

Shift Right Register

 Example: Shift Right Register
• Example: Data 1001 needs to be written to a 4-bit shift right register

After second +ve

clock edge F1 F2 F3 F4

0 0 1 x x

Shift Right Register

 Example: Shift Right Register
• Example: Data 1001 needs to be written to a 4-bit shift right register

After third +ve

clock edge F1 F2 F3 F4

1 0 0 1 x

Shift Right Register

 Example: Shift Right Register
• Example: Data 1001 needs to be written to a 4-bit shift right register

After fourth +ve

clock edge F1 F2 F3 F4

1 0 0 1

Shift Right Register

 Parallel Access Shift Register
• Data transfer in computer systems is of two types:
– If the transfer is 1-bit at a time, it is said to be serial
– If the transfer is n-bits (n > 1) at a time, it is said to be parallel
• To read/write a register in serial fashion, data is read/written bit-
by-bit and is shifted by one bit position each cycle
• To read/write a register in parallel fashion, all the n-bits are
read/written during the same clock cycle
Parallel Access Shift Register
 Parallel Access Shift Register

Assume
:Shift / Load  1

Behavior:
Parallel Access

0 1` 0 1 0 1 0 1
 Parallel Access Shift Register

Assume
:Shift / Load  0

Behavior:
Serial Access

1 0 1 0 1 0 1 0
 Counters
• Counters are arithmetic circuits used for the purpose of counting
– Can increment or decrement by 1 each cycle
• Counters often implemented with T flip-flops
– Toggle feature naturally suited for counting operation
• Applications of counters
– Count occurrences of certain events, for example, no. of add instructions
– Track elapsed time between events
– Generate control and timing signals, for example, to produce signals whose
frequencies are multiples of original clock frequency
 A 3-bit Up-counter
Counter x2 x1 x0
Consider a 3-bit counter Value
x2x1x0 shown in table. 0 0 0 0
•The least significant bit x0 1 0 0 1
toggles at every increment
of counter 2 0 1 0
• x1 toggles on 1->0 3 0 1 1
transitions of x0 (half the
4 1 0 0
rate of toggling of x0)
• x2 toggles on 1->0 5 1 0 1
transitions of x1 (half the 6 1 1 0
rate of toggling of x1)
7 1 1 1
A 3-bit Up-counter
 Practice Exercise
• Design a 3-bit down counter with T flip-flops. How does
the down counter circuit differ from the up-counter
circuit?
 A 3-bit Down-counter
Counter x2 x1 x0
•The least significant bit x0 Value
toggles at every decrement 7 1 1 1
of counter 6 1 1 0
• x1 toggles on 0->1
transitions of x0 5 1 0 1
• x2 toggles on 0->1 4 1 0 0
transitions of x1
3 0 1 1
2 0 1 0
1 0 0 1
0 0 0 0
 Practice Exercise Solution
• Design a 3-bit down counter with T flip-flops. How
does the down counter circuit differ from the up-
counter circuit?
• Solution:
– Two ways to convert the up-counter to a down-counter:
1. Either, replace the +ve edge-triggered T flip-flops with –ve edge-
triggered T flip-flops
2. Or, connect the Q outputs (instead of NOT(Q) outputs) from previous
flip-flops to clock inputs of next flip-flops
 Asynchronous Counters
• The previous counter is an example of asynchronous counters.
Also called ripple counters
– Input clock only connected to one flip flop
– Clocks for other flip-flops are derived from outputs of previous flip-flops
• Asynchronous counters are slow because of cascaded clocking
– The input clock pulse ripples from stage to stage
– Propagation delay of individual flip-flops limit speed of operation
• Solution: Synchronous sequential circuits (finite state machines)
 Finite State Machines
• Recall that in a sequential circuit:
– Outputs depend both on present inputs and the sequence of previous inputs
• The state of a sequential circuit determines its behavior when various
input patterns are applied
• A finite state machine model formally describes a sequential circuit

Inputs Outputs
Combinational
Logic

Present Next
State State

Delay Elements
(Flip-flops)
 Synthesis of Finite State Machines
Synthesis of FSM involves the following steps:
• Step 1: Develop a state diagram or state table
– Depict how state transitions occur in response to input patterns
• Step 2: Determine # and types of needed flip flops
• Step 3: Determine state assignment (flip-flop values for each state)
• Step 4: Determine the state-assigned state table
• Step 5: Derive the logic expressions for next-state logic and outputs
• Step 6: Use the derived expressions to implement the circuit
 Example: Up/Down Counter with D flip-flops
Problem Statement: Design a mod-4 counter which counts up or down
depending on an input and has an output of 1 if the count is equal to 2

• States: 4 states (S0, S1, S2 and S3) corresponding to 4 count values

• Input: Variable x. Count up if x=0, down if x=1
• Output: Variable z. If present state is S2, then z=1, otherwise z=0;
 State Diagram

x=0

S0/0 S1/0

x=1

x=0 x=1 x=1 x=0

x=1

S3/0 S2/1

x=0
 State Table

Present State Next State Output z

x=0 x=1

S0 S1 S3 0

S1 S2 S0 0

S2 S3 S1 1

S3 S0 S2 0

Need 2 state variables to represent 4 states => use 2 D flip-flops

 State-Assigned State Table
• State variables y1 and y2 used to express each state as a 2-bit number y2y1
• We choose the following state assignment S0=00, S1=01, S2=10, S3=11

Present State Next State Output z

x=0 x=1
y2y1 Y2Y1 Y2Y1
00 01 11 0
01 10 00 0
10 11 01 1
11 00 10 0

Next state Y 2  y 2  y1  x Y1  y1
Logic
Expressions Output z  y 2y1
 Logic Circuit

Y 2  y 2  y1  x Y1  y1
Logic Next state
Expressions Output z  y 2y1