RV College of

Engineering

Unit 5
Microprocessor Based System Design
1
 Unit 5
Clock generator(8284), Memory Devices, Address Decoding, Interfacing Memory,
I/O sub System: Busy wait, DMA, Interrupt Driven, Memory Maps, I/O Port address
decoding, Introduction to 8255, Interfacing 8255 with 8086, Interrupt Based IO
Design.

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 8086 Pin Out:
Revisited

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  BHE /S7: Byte High Enable, Active low signal
- Used to enable most significant data bus bits (D15-
D8) during read or write operation.
- Generated during first part of machine cycle.

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  BHE & A0 pin together indicate various data transfer as
indicated below.
Operation A0 Data Pins used
BHE
Write/Read a word 0 0 AD15-AD0
at Even Address
Write/Read a byte 1 0 AD7-AD0
at even address
Write/ Read a byte 0 1 AD15-AD0
at an odd address
Write/Read a word 0 1 AD15-AD0
at odd Address Read least
significant byte
1 0 AD7-AD0
Read Most
significant byte

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Clock generators

• F/C’: Frequency/ Crystal input choses the clocking source for 8284.
Held low for crystal input
6 • Refer Bary B Brey for more details.
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 8282 Latch
 This is latch with 3 state output
buffers.
 STB(strobe)=1, latches the bit
applied to input data lines.
 OE=0 ,enables output lathes
 OE=1, Forces output to high
impedance state.

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8286 octal bus transceiver

 OE is to enable data transmission.

 T is used control direction

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Minimum mode system
 Bus(multiplexed)
Latching

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 Data Bus
Buffering

Transceiver

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 Selection logic

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 Write Cycle- Bus timings

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 Read cycle-Bus timings

A19– S7 – S3

D15 – D0 D15 – D0

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 Memory Devices

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 Memory Devices: Examples
 2716 2K x 8 (2 KB) EPROM: Pinout, Pin names, Mode selection

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 Memory Devices: Examples
 62256 32K x 8 SRAM: Pin out, Pin names

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 Question 1: Interfacing memory
 Interface two 4k x 8 EPROMS and two 4k x 8 RAM chips to 8086 in minimum
mode. Select suitable memory maps.
Solution:
- After reset, the IP & CS is initialized to 0000h & FFFFH to form physical
address FFFF0H.
- This address must lie in EPROM (Program Memory)
- RAM (data memory) address can be selected any where in 1Mb of memory.

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 Question 1…..
Odd & Even Banks

 8 K bytes
No address lines =13: (213= 8K)

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RAM Memory Map generation
Address Bank
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Lines Selection
1 1 1 1 1 1 1 1 1 1 1 1 1 Odd
1 1 1 1 1 1 1 1 1 1 1 1 0 Even
. . . . . . . . . . . . .
0 0 0 0 0 0 0 0 0 0 1 1 1 Odd
RAM 0 0 0 0 0 0 0 0 0 0 1 1 0 Even
0 0 0 0 0 0 0 0 0 0 1 0 1 Odd
8Kb 0 0 0 0 0 0 0 0 0 0 1 0 0 Even
0 0 0 0 0 0 0 0 0 0 0 1 1 Odd
0 0 0 0 0 0 0 0 0 0 0 1 0 Even
0 0 0 0 0 0 0 0 0 0 0 0 1 Odd
0 0 0 0 0 0 0 0 0 0 0 0 0 Even

Location Selection Even Bank

selection
Chip Select
signal

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 Question 1…..
Memory Map generation: RAM & ROM

 RAM & ROM chip size :4 K bytes

No of address lines :12 (A12-A1)
A0 is used to select Even bank
 ROM address map should include RESET address

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 Question 1…..
Memory Map

 A0 is chip select signal for even bank.

 A1-A12 Address lines
 A13-A19 Chip Select signal for RAM & ROM

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 Generating Control signals

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 ROM interfacing

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 RAM Interfacing

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 Memory Chip Selection: Function Table

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 Question 2
 Design an interface between 8086 CPU and two chips of 16 x 8 EPROM and two
chips of 32k x 8 RAM. Select the starting address of EPROM suitably. The RAM
address must start at 00000H.
Solution:
No. of address lines ROM: 15 (215= 32k x 8)
No. of address lines RAM : 16(216=64k x 8)
Reset address:FFFF0H
Memory Map:

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 Interfacing diagram Question 2…..

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 Question 2….

Control Signals

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 Question 3
Design an interface between 8086 CPU and four chips of 8 K x 8 EPROM and two
chips of 32k x 8 RAM. Select the starting address of EPROM suitably. The RAM
address must start at 20000H.
Memory Map Generation:
Address A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
FFFFFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPROM (First 2 chips) 16K x 8
FC000H 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FBFFFH 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
EPROM (Next 2 chips) 16K x 8
F8000H 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2FFFFH 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RAM 64K x 8
20000H 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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 Question 3..
 Write interfacing diagram:

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IO Subsystem
 Embedded system are interfaced with different IOs to communicate and control
external world.
 Data transfer to and from the peripherals to CPU may be done in any of the three
possible ways:
 Busy wait IO or Programmed IO or Polling.
 Interrupt Driven IO.
 Direct Memory Access( DMA) based IO.
 Memory-mapped IO allows IO registers to be accessed as memory locations. As a
result, these registers can be accessed using only LOAD and STORE instructions.
 IO mapped IO allows IO to be accessed using separate instructions IN and OUT
provided by ISAs.

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 IO Subsystem….
Busy wait IO
 Each IO access is initiated by an instruction in the program.
 It requires constant monitoring by the CPU of the peripheral devices.
 A transfer from IO device to memory requires the execution of several
instructions by the CPU, including an input instruction to transfer the data from
device to the CPU and store instruction to transfer the data from CPU to
memory.
 The CPU stays in the program loop until the IO unit indicates that it is ready for
data transfer.
 Due to the time needed to poll if IO device is ready, the processor cannot often perform
useful computation.

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 Busy wait IO..
Example: ADC 0809 Interface to 8051 MCU.
Polling loop: Pseudo Code
void main(void)
{
/* MCU & ADC Initialization
while(1)
{

/*Send Start of Conversion

//wait for End of Conversion(EoC)
//from ADC
while(eoc==0);
 EOC is connected to GPIO pin configured as
/* Read digital data on port 0
input. }
}

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 IO Subsystem….

Interrupt Driven IO
 By using interrupt facility and special interface to issue an interrupt
request signal whenever data is available from IO device.
 In the meantime, the CPU can proceed for any other program execution.
 Whenever it is determined that the IO device is ready for data transfer, the
interface(device itself) initiates an interrupt request signal to the computer.
 The CPU stops momentarily the task that it was already performing, branches
to the Interrupt Service Routine(ISR) to process the IO transfer, and
then return to the task it was originally performing.

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 Interrupt Driven IO..
Example: ADC 0809 Interface to 8051 MCU. Interrupt Driven IO: Pseudo Code
void main(void)
{
/* MCU & ADC Initialization
/* Interrupt Initialization
while(1)
{

/*Send Start of Conversion

//CPU is doing any other operation
 EOC is connected to Interrupt input of MCU. //No operation, can be kept in sleep modes
 Response time involves context switching }
overhead. }
void isr_ADC (void)interrupt 0
{
//Read digital data
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 DMA based IO
IO Subsystem….
 For fast, bulk data transfer between memory and IO devices is DMA is used.
 The DMA eliminates CPU intervention between IO devices and memory in data
transfer.
 During DMA the CPU is idle and it has no control over the memory buses.
 The DMA controller takes over the buses to manage the transfer directly between
the I/O devices and the memory unit.
DMA is not operational DMA is operational

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 DMA IO..
 Bus Request (HOLD): It is used by the DMA controller to request the CPU to
relinquish the control of the buses.
 Bus Grant (HLDA): It is activated by the CPU to Inform the external DMA controller
that, the buses are in high impedance state and the requesting DMA can take control of the
buses.
 Burst Transfer :In which, a block sequence consisting of memory words is transferred in
a continuous burst where the DMA controller is the master of the memory buses.
 Cyclic Stealing : In this, DMA controller transfers one word at a time after which it
must return the control of the buses to the CPU. The CPU merely delays its operation for
one memory cycle to allow the direct memory IO transfer to “steal” one memory cycle.

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 Interfacing I/O devices
Two methods:
1. I/O mapped I/O
2. Memory Mapped I/O
- In 8086, the memory mapped I/O is seldom used.
- An I/O mapped I/O device requires the use of IN & OUT instructions.
Example: IN AL,80h (8 bit address)
OUT DX,AL (16 bit address)

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 I/P & O/P Port
 Latch(O/P 8 bit Port):8282 Transceiver(I/P port):8286

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Question 4
 Design a system to interface 8 LEDs to 8086. Write a program to toggle the LEDs at the
rate of 100ms.
Solution:
- Use Latch to connect LEDs.

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 Question 4:Solution
-Assign address to latch: FFFFH (16 bit: Use DX to hold address)
-Generate suitable decoding circuit to enable chip

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 Question 4:Solution
-Generation of delay 100 ms (Assume CPU Clock frequency:5 MHz)

- No. of cycles for execution of loop:19

- Time taken:19 x 0.2 µ =3.8 µSec
- For 100 msec: COUNT=100 m/3.8 µ =26,315=66CBH
- Software method of generating delay

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 Question 4:Complete system

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Program: Busy wait(Polled Loop) Question 4:Solution

066CBH

 Note that, system is assumed to be interfaced with memory for code and data
segment
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Question 5
 Write a program to read status of switches SW1 to SW8. The switches, when shorted
input a ‘1’ else input ‘0’ to the microprocessor system. Store result in register BL. The
address of the port is FFFFH.
Solution:
-Use octal transceiver (8286) connect switch.
- T=0 (Direction Control)

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 Question 5: Complete
system

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 Question 5:Solution
Program Statements:
 MOV DX,0FFFFH
 IN AL,DX
 MOV BL,AL

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 Question 6
 The diagram below shows interface card with eight DIP switches with status indicating
LEDs D1 & D8. The card also features 8 LEDs (D9-D16) controlled by external devices.
Design a suitable scheme to interface card to 8086.Write a program to read the status of
switches & display the same on LEDs D9-D16. Demonstrate polled method of IO.

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 8255- Programmable peripheral Interface
 Low cost interfacing component used in many applications.
 These devices can be used to input parallel data to microprocessor &
output parallel data from microprocessor.
 This device can be used to interface any TTL compatible I/O devices
to microprocessor.
Features of 8255:
1. It is designed to perform various input/output function by
configuring 8 bits in the internal register called control word
register. The programmer can access the CW by its address.
2. It has three 8 bit ports: Port A(8 bits), Port B(8 bits), Port C(4 PCU
+4 PCL).
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 3. The 24 I/O pins are arranged in group of 12 pins GROUP A(Port A+PCU) & GROUP
B(Port B+PCL).
4. Each port has an unique address and data can be written or read to a port.
5. 3 Operating modes:
Mode 0: Port A & Port B & Port C in simple I/O
Mode 1: Port A & Port B can be programmed as 8 bit input or output.
-Port C pins (6) are used for as handshaking pins for Port A & Port B
Mode 2: Only Port A in mode 2.
- Port C 5 pins are used as handshaking signals for Port A
- Port B in either mode 0 or mode 1

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 Connection between 8086 & 8255

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 8255 Pin diagram

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 8255 functional diagram

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 Function table

 Reset : High on this pin, clears the control register and all ports are set to the
input mode by default.

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Control word
format

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 Mode 0 (Basic Input / Output)
 This functional configuration provides simple input and
output operations for each of the three ports.
 No “handshaking” is required, data is simply written to or
read from a specified port.

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 Mode 0:Interfacing
Port A Address: FFFCH
Port B Address: FFFDH
Port C Address: FFFEH
CW Address: FFFFH

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 Question 7
 Design 8086 system to realize 2 digit BCD counting operation. Use 8255 to realize
port operations. Generate the suitable delay to observe count value. Interface
suitable display to observe count value and button to start counting operation. Write
interfacing diagram & Program.

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 Bit Set/Reset Mode (BSR)
• BSR mode is selected only when D7 = 0 of the Control Word Register (CWR).
• Applicable for only for bits of port C.
• Individual bits of Port C can either be Set or Reset.
• At a time, only a single bit of port C can be Set or Reset.
• BSR control word doesn’t affect ports A and B functioning.
• In the BSR mode, individual bits of port C can be used for applications such as
on/off switch.

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 Question 8
Write a BSR control word to set bits PC7 and PC0 and to reset them after 1 second
delay. Address of control word is 83H.
Solution:
MOV AL, 0FH ;(AL loaded with 0FH to set PC7 bit of Port C)
OUT 83H, AL ;(This sets PC7 bit of Port C)
MOV AL, 01H ;(AL loaded with 01H to set PC0 bit of Port C)
OUT 83H, AL ;(This sets PC0 bit of Port C)
CALL DELAY ;(Assume the DELAY is for 1 second)
MOV AL, 00H ;(Accumulator loaded with 00H to reset PC0 bit of Port C)
OUT 83H, AL ; (This resets PC0 bit of Port C)
MOV AL, 0EH ;(Accumulator loaded with 0EH to reset PC7 bit of Port C)
OUT 83H, AL ; (This resets PC7 bit of Port C)

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 Question 9
 Program PC4 of the 8255 in the following figure to generate a square
wave of time period 50 ms with 50% duty cycle.

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 Question 10:Interrupt driven IO
 Design 8086 system to interface ADC 0809 to convert analog voltage in the range
0-5 V into digital value in the range 00H- FFH. Display the digital value in the first
row of 2x 16 LCD. Use EOC signal of ADC to cause interrupt on INTR pin of
8086 and write ISR for type 32 interrupt to read digital value and displaying on
LCD.

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 Question 11:
Write 8086 program to
read a key value and display on
Seven segment interface.The
Schematics of the system in shown
in figure.

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