Unit 3

Application of microprocessor
Contents
• Interfacing of A/D converters, Interfacing of D/A converters,
Waveform generators, Multiplexed seven segment LED display
systems, Measurement of frequency, phase angle and power
factor, Traffic light controller, Stepper motor control
Counter and Time delay in 8085
• Counters are used to keep track of events.
• Time delays are important in setting up reasonably accurate
timing between two events.
Counters
• A Counter is designed simply by
loading an appropriate number
into one of the registers and
using the INR (Increment by
one) or the DCR (Decrement by
one) instructions.
• A loop is established to update
the count, and each count is
checked to determine whether it
has reached the final number; if
not, the loop is repeated.
Time delays
• The procedure used to design a
specific delay is similar to that
used to set up a counter.
• A register is loaded with a number,
depending on the time delay
required, and then the register is
decremented until it reaches zero
by setting up a loop with a
conditional jump instruction.
• The loop causes the delay,
depending upon the clock period of
the system.
Calculating time delays
• Each instruction passes through different combinations of Opcode
Fetch, Memory Read, and Memory Write cycles.
• Knowing the combinations of cycles, one can calculate how long
such an instruction would require to complete.
• Number of Bytes
• Number of Machine Cycles
• Number of T-State.
Calculating time delays …
• Knowing how many T-States an instruction requires, and keeping
in mind that a T-State is one clock cycle long, we can calculate the
time delay using the following formula:
Time Delay = No. of T-States * Clock Period
• For example,
• MVI instruction uses 7 T-States.
• Therefore, if the Microprocessor is running at 2 MHz, the
instruction would require 3.5 µS to complete.
Time delay design techniques
• Using One Register.
• Using a Register Pair.
• Using a Loop with in a Loop
Time delay design techniques …
• Using one register
• A count is loaded in a register, and We can use a loop to produce a
certain amount of time delay in a program.
• The following is an example of a delay using one register:
MVI C, FFH ;7 T-States
LOOP: DCR C ;4 T-States
JNZ LOOP ;10 T-States
• The first instruction initializes the loop counter and is executed only
once requiring only 7 T-States.
• The following two instructions form a loop that requires 14 T-States to
execute and is repeated 255 times until C becomes 0.
Time delay design techniques …
• Using one register …
• We need to keep in mind though that in the last iteration of the
loop, the JNZ instruction will fail and require only 7 T-States
rather than the 10.
• Therefore, we must deduct 3 T-States from the total delay to get
an accurate delay calculation.
Time delay design techniques …
• Using one register …
• To calculate the delay, we use the following formula:
Tdelay = TO + TL
Tdelay = Total delay
TO = delay outside the loop
TL = delay of the loop
TO is the sum of all delays outside the loop.
TL is calculated using the formula
TL = T * Loop T-States * N (no. of iterations)
Time delay design techniques …
• Using one register …
• Using these formulas, we can calculate the time delay for the
MVI C, FFH ;7 T-States
LOOP: DCR C ;4 T-States
JNZ LOOP ;10 T-States
• Assuming f = 2 MHz
• TO = 7 T-States (Delay of the MVI instruction)
• TL = (14 X 255) - 3 = 3567 T-States
• 14 T-States for the 2 instructions repeated 255 times
• FF16 = 25510 reduced by the 3 T-States for the final JNZ.)
Time delay design techniques …
• Using one register …
• TDelay = [(TO + TL ) / f]
= (7 + 3567) / 2MHz
= (3574) X 0.5 mSec
= 1.787 mSec
Time delay design techniques …
• Using a register pair
• Using a single register, one can repeat a loop for a maximum
count of 255 times.
• It is possible to increase this count by using a register pair for
the loop counter instead of the single register.
• A minor problem arises in how to test for the final count since
DCX and INX do not modify the flags.
• However, if the loop is looking for when the count becomes
zero, we can use a small trick by ORing the two registers in the
pair and then checking the zero flag.
Time delay design techniques …
• Using a register pair
• The following is an example of a delay loop set up with a
register pair as the loop counter.

LXI B, 1000H 10 T-States

LOOP: DCX B 6 T-States
MOV A, C 4 T-States
ORA B 4 T-States
JNZ LOOP 10 T-States
Time delay design techniques …
• Using a register pair
• The following is an example of a delay loop set up with a
register pair as the loop counter.
• TO = 10 T-States
• (The delay for the LXI instruction)
• TL = (24 X 4096) - 3 = 98301 T- States
• (24 T-States for the 4 instructions in the loop repeated 4096
times (100016 = 409610) reduced by the 3 T-States for the
JNZ in the last iteration.)
• TDelay = (10 + 98301) X 0.5 mSec = 49.155 mSec
Time delay design techniques …
Initialize loop 2

• Using a Loop with in a Loop Body of loop 2

• Nested loops can be easily Initialize loop 1

setup in Assembly Language Body of loop 1

by using two registers for Update the count1

the two loop counters and Is this

No
updating the right register Final
Count?

in the right loop. Yes

Update the count 2

No Is this
Final
Count?

Yes

Flowchart for time delay with two loops

Time delay design techniques …
• Using a Loop with in a Loop …
• Instead (or in conjunction with) Register Pairs, a nested loop
structure can be used to increase the total delay produced.
MVI B, 10H 7 T-States
LOOP2 MVI C, FFH 7 T-States
LOOP1 DCR C 4 T-States
JNZ LOOP1 10 T-States
DCR B 4 T-States
JNZ LOOP2 10 T-States
Time delay design techniques …
• Using a Loop with in a Loop …
• The calculation remains the same except that the formula must be
applied recursively to each loop.
• Start with the inner loop, then plug that delay in the calculation of
the outer loop.
Time delay design techniques …
• Using a Loop with in a Loop …
• Delay of inner loop,
• TO1 = 7 T-States
• (MVI C, FFH instruction)
• TL1 = (255 X 14) - 3 = 3567 T-States
• (14 T-States for the DCR C and JNZ instructions repeated 255
times (FF16 = 25510) minus 3 for the final JNZ.)
• TLOOP1 = 7 + 3567 = 3574 T-States
Time delay design techniques …
• Using a Loop with in a Loop …
• Delay of outer loop
• TO2 = 7 T-States
• (MVI B, 10H instruction)
• TL1 = (16 X (14 + 3574)) - 3 = 57405 T-States
• (14 T-States for the DCR B and JNZ instructions and 3574 T-States
for loop1 repeated 16 times (1016 = 1610) minus 3 for the final JNZ.)
• TDelay = 7 + 57405 = 57412 T-States
• Total Delay
• TDelay = 57412 X 0.5 µSec = 28.706 mSec
Time delay design techniques …
• Increasing the Time Delay
• The Delay can be further increased by using register pairs for
each of the loop counters in the nested loops setup.
• It can also be increased by adding dummy instructions (like
NOP) in the body of the loop.
Time delay design techniques …
• Counter Design with Time Delay

Initialize Counter
Load Delay Register

Display
Body of loop
Time Delay

Update Count
Is this
Final
Is Count?
No Count No
Complete?
Yes

Yes
Time delay design techniques …
• Counter Design with Time Delay
Initialize Counter

Initialize Counter
Display Count

Display Update Count

Time Delay Is Yes

Count
Update Count Complete?

Is No
No Count Time Delay
Complete?
Go back
Yes
End
End

Variations Of Counter Flowchart

Illustrative program 1
• Hexa-decimal counter.
• Write a program to count continuously in hexa-decimal from
FFH to 00H in a system with a 0.5 micro sec clock period. Use
register C to set up a one Millisecond delay between each count
and display the numbers at one of the output ports.
Illustrative program 1 …
• This problem has two parts; the first is to set up a continuous
down-counter, and the second is to design a given delay between
two counts.
1. The hexadecimal counter is set up by loading a register with
an appropriate starting number and decrementing it until it
becomes zero. After zero count, the register goes back to FF
because decrementing zero results in a (-1), which is FF in
2’s complement.
2. The 1 ms delay between each count is set up by using delay
techniques.
Illustrative program 1 …

MVI B,00H
NEXT: DCR B
MVI C,COUNT
DELAY: DCR C
JNZ DELAY
MOV A,B
OUT PORT#
JMP NEXT
Illustrative program 1 …
• Delay loop includes two instructions:
• DCR C and JNZ with 14 T-states.
• Therefore the time delay TL in the loop (without accounting
for the fact that JNZ requires 7 T-States in the last cycle,
because count will remain same even if the calculations take
into account the difference of 3 T-States) is:
TL = 14 T-states x T (Clock period) x Count
= 14 x (0.5 x 10-6) x Count
= (7.0 x 10-6) x Count
Illustrative program 1 …
• The Delay outside the loop includes the following instructions:
Illustrative program 2 …
• Modulo TEN counter (0-9)
• Write a program to count from 0 – 9 with a one - second delay
between each count. At count of 9, the counter should reset
itself to 0 and repeat the sequence continuously. Use register
pair H-L to set up the delay, and display each count at one of
the output ports. Assume the clock frequency of the micro
computer is 1 MHz.
Illustrative program 2 …
START: MVI B,00H 7
MOV A,B 4
DISPLAY: OUT PORT# 10
LXI H,16-Bit 10
LOOP: DCX H 6
MOV A,L 4
ORA H 4
JNZ LOOP 10/7
INR B 4
MOV A,B 4
CPI 0AH 7
JNZ DISPLAY 10/7
JZ START 10/7
Illustrative program 2 …
• Time Delay Calculation
• The major delay between two counts is provided by the 16-bit
number in the delay register HL(inner loop in flow chart).
• This delay is set up by using a register pair.
Loop Delay TL= 24 T-states *T * Count 1
second= 24*1.0 *10-6 *Count
Count= 1 = 41666 = A2C2H
24 x 10-6
• A2C2H would provide approx 1 sec delay between two counts.
To achieve higher accuracy in the delay, the instructions
outside the loop must be accounted for delay calculation. (will
be 41665).
Illustrative program 3 …
• Generating Pulse waveforms
• Write a program to generate a continuous square wave with the
period of 500 micro sec. Assume the system clock period is
325 ns, and use bit D0 to output the square wave.
Illustrative program 3 …
MVI D,AA 7T
ROTATE: MOV A,D 4T
RLC 4T
MOV D,A 4T
ANI 01H 7T //mask MSB 7 Bits
OUT PORT1 10T
MVI B,COUNT
DELAY: DCR B 4T
JNZ DELAY 10/7 T
JMP ROTATE 10T

A 10101010
After RLC 01010101
A AND 01H 00000001

COUNT= 52.410 = 34H

Debugging counter & time- delay programs
1. Errors in counting T-States in a delay loop. Typically, the first
instruction–to load a delay register–is mistakenly included in the loop.
2. Errors in recognizing how many times a loop is repeated.
3. Failure to convert a delay count from a decimal number into its
hexadecimal equivalent.
4. Conversion error in converting a delay count from decimal to
hexadecimal number or vice versa.
5. Specifying a wrong jump location.
6. Failure to set a flag, especially with 16-bit
decrement/increment instructions.
7. Using a wrong jump instruction.
8. Failure to display either the first or the last count.
9. Failure to provide a delay between the last and the last-but-one count.
ADC0800: 8-Bit A/D Converter
• The ADC0800 is an 8-bit monolithic A/D converter using P-channel
ion-implanted MOS technology.
• It contains a high input impedance comparator, 256 series resistors and
analog switches, control logic and output latches.
• Conversion is performed using a successive approximation technique
where the unknown analog voltage is compared to the resistor tie
points using analog switches.
• When the appropriate tie point voltage matches the unknown voltage,
conversion is complete and the digital outputs contain an 8-bit
complementary binary word corresponding to the unknown.
• The binary output is TRI-STATE® to permit bussing on common data
lines.
ADC0800: 8-Bit A/D Converter …
• Features
• Low cost
• ±5V, 10V input ranges
• Ratiometric conversion
• TRI-STATE outputs
• Fast: TC=50 μs
• Contains output latches
• TTL compatible
• Supply voltages: 5 VDC and −12 VDC
• Resolution : 8 bits
• Conversion speed: 40 clock periods
• Clock range: 50 to 800 kHz
ADC0800: 8-Bit A/D Converter …
• Block Diagram
ADC0800: 8-Bit A/D Converter …
• Timing Diagram
ADC 0808/0809: 8-Bit A/D Converter
• The ADC 0808/0809 is an 8-bit analog to digital converter.
• It has 8 channel multiplexer to interface with the microprocessor.
• This chip is popular and widely used ADC.
• ADC 0808/0809 is a monolithic CMOS device.
• This device uses successive approximation technique to convert
analog signal to digital form.
• One of the main advantage of this chip is that it does not require
any external zero and full scale adjustment, only +5V DC supply
is sufficient.
ADC 0808/0809: 8-Bit A/D Converter …
• Features of ADC 0808/0809
• The conversion speed is much higher
• The accuracy is also high
• It has minimal temperature dependence
• Excellent long term accuracy and repeatability
• Less power consumption
ADC 0808/0809: 8-Bit A/D Converter …
• Pin diagram of ADC 0808/0809
ADC 0808/0809: 8-Bit A/D Converter …
• Functional block diagram of ADC 0808/0809
Interfacing ADC with 8085 Microprocessor
• To interface the ADC with 8085, 8255 Programmable Peripheral Interface
chip is required with it.
• The circuit diagram of connecting 8085, 8255 and the ADC converter is
shown in fig.
Program
MVI A, 98H ; Set Port A and Cupper as input, PCL
as output
OUT 03H ; Write control word 8255 to CWR
XRA A ; Clear the accumulator
OUT 02H ; Send the content of Acc to PCL to
select IN0
MVI A, 08H ; Load the accumulator with 08H
OUT 02H ; ALE and SOC will be 0
XRA A ; Clear the accumulator
OUT 02H ; ALE and SOC will be low.
Program …
READ: IN 02H ; Read from EOC (PC7)
RAL ; Rotate left to check C7 is 1.
JNC READ ; If C7 is not 1, go to READ
IN 00H ; Read digital output of ADC
STA 8000H ; Save result at 8000H
HLT ; Stop the program
Interfacing DAC with 8085 Microprocessor
• DAC 0800 Features
• To convert the digital signal to analog signal a Digital-to-Analog
Converter (DAC) has to be employed.
• The DAC will accept a digital (binary) input and convert to analog
voltage or current.
• Every DAC will have "n" input lines and an analog output.
• The DAC require a reference analog voltage (Vref) or current (Iref)
source.
• The smallest possible analog value that can be represented by the n-bit
binary code is called resolution.
• The resolution of DAC with n-bit binary input is 1/2n of reference analog
value.
Interfacing DAC with 8085 Microprocessor
• The DAC0800 is an 8-bit, high speed, current output DAC
with a typical settling time (conversion time) of 100 ns.
• It produces complementary current output, which can be
converted to voltage by using simple resistor load.
• The DAC0800 require a positive and a negative supply
voltage in the range of ± 5V to ±18V.
Interfacing DAC with 8085 Microprocessor
• It can be directly interfaced with TTL, CMOS, PMOS and other
logic families.
• For TTL input, the threshold pin should be tied to ground (VLC =
0V).
• The reference voltage and the digital input will decide the analog
output current, which can be converted to a voltage by simply
connecting a resistor to output terminal or by using an op-amp I to
V converter.
• The DAC0800 is available as a 16-pin IC in DIP.
Interfacing DAC with 8085 Microprocessor
Interfacing DAC with 8085 Microprocessor
Interfacing DAC with 8085 Microprocessor
Square Wave Generation Using DAC
Sawtooth Wave Generation Using DAC
• Positive Ramp
Sawtooth Wave Generation Using DAC …
• Positive Ramp
Sawtooth Wave Generation Using DAC
• Negative Ramp
Sawtooth Wave Generation Using DAC …
• Negative Ramp
Triangular Wave Generation Using DAC
Triangular Wave Generation Using DAC …
Sine Wave Generation Using DAC
• To generate sine wave we have to output digital equivalent values
which will represent sine wave as shown in figure.

• Digital data 00H represents -2.5V.

• The 84H represents 0V and
• FFH represents +2.5V.
Sine Wave Generation Using DAC …
• The digital equivalent for sine wave can be calculated as follows.
• We know that sin 0°=0 and sin 90°=1.
• The range in 0° to 90° is distributed over digital range of 7FH to FFH
i.e.,(FFH to 7FH) 128 decimal steps.
• Therefore taking 128 as a offset we can write digital equivalent value for
sin θ =(128+128×sin α).
• Where ɑ is an angle in degrees which varies from -90° to +90° with a
period of 5°.
• By changing the value of ɑ to less than 5°, you can get more accurate sine
wave.
• Now you have to enter DATA(approximate hex code) in corresponding
memory location as shown in the table below
 Sine Wave Generation Using DAC …
Angle Degree Hex Angle Degree Hex Angle Degree Hex
Address Address Address
(θ) (α) Code (θ) (α) Code (θ) (α) Code
2500 -90 0 00 250D -25 73.90 54 250A 40 210.27 D8
2501 -85 0.48 01 250E -20 84.22 5E 250B 45 218.50 E0
2502 -80 1.94 02 250F -15 94.87 69 250C 50 226.05 EA
2503 -75 4.36 04 2510 -10 105.77 74 250D 55 232.85 ED
2504 -70 7.71 08 2511 -05 116.84 7F 250E 60 238.85 EF
2505 -65 11.99 11 2512 00 128.00 84 250F 65 244.00 F2
2506 -60 17.14 17 2513 05 139.15 95 2520 70 248.28 F9
2507 -55 23.14 1E 2514 10 150.20 9F 2521 75 251.63 FC
2508 -50 29.94 25 2515 15 161.12 AF 2522 80 254.05 FD
2509 -45 37.49 2D 2516 20 171.77 B4 2523 85 255.51 FF
250A -40 45.72 36 2517 25 182.09 C0 2524 90 256.00 00
250B -35 54.58 40 2518 30 192.00 C8
250C -30 64.00 49 2519 35 201.42 D0
Sine Wave Generation Using DAC …
Machine
address Label Mnemonic Comments
code
Initializing the ports of the PPI 8255 as O/P ports
2000 MVI A,80H 3E, 80 by writing the control word as 80H.

Control word specify the I/O function for each

2002 0UT CWR D3, CWR ports of 8255.
2004 START MVI C,24H 0E, 24
2006 LXI H,2500H 21, 00, 25
2009 POS MOV A,M 7E
200A OUT PORT A D3, PORT A [[H-L]] is outputted through portA

200C INX H 23
Sine Wave Generation Using DAC …
address Label Mnemonic Machine code Comments
200D DCR C 0D
200E JNZ POS C2, 09, 20
2011 MVI A,24H 0E, 24
2013 NEG DCX H 2B
2014 MOV A,M 7E
2015 OUT 00H D3, PORT A [[H-L]] is outputted through portA.

2017 DCR C 0D
2018 JNZ NEG C2, 13, 20
201B JMP START C3, 04, 20
Measurement of frequency
Measurement of frequency …
Measurement of frequency …
Traffic light controller
Traffic light controller …
• Port A is used to control lights on N-S road and Port B is used to
control lights on W-E road.
Traffic light controller …
Traffic light controller …
Traffic light controller …
Traffic light controller …
MVI A, 80H : Initialize 8255, port A and port B
OUT 83H (CR) : in output mode
START: MVI A, 09H
OUT 80H (PA) : Send data on PA to glow R1 and R2
MVI A, 24H
OUT 81H (PB) : Send data on PB to glow G3 and G4
MVI C, 28H : Load multiplier count (40D) for delay
CALL DELAY : Call delay subroutine
MVI A, 12H
OUT 80H : Send data on Port A to glow Y1 and Y2
OUT 81H : Send data on port B to glow Y3 and Y
Traffic light controller …
MVI C, 0AH : Load multiplier count (10D) for delay
CALL DELAY : Call delay subroutine
MVI A, 24H
OUT 80H : Send data on port A to glow G1 and G2
MVI A, 09H
OUT 81H : Send data on port B to glow R3 and R4
MVI C, 28H : Load multiplier count (40D) for delay
CALL DELAY : Call delay subroutine
MVI A, 12H
OUT 80H : Send data on port A to glow Y1 and Y2
OUT 81H : Send data on port B to glow Y3 and Y4
Traffic light controller …
MVI C, 0AH : Load multiplier count (10D) for delay
CALL DELAY : Call delay subroutine
JMP START

Delay Subroutine:
DELAY: LXI D, Count : Load count to give 0.5 sec delay
BACK: DCX D : Decrement counter
MOV A, D
ORA E : Check whether count is 0
JNZ BACK : If not zero, repeat
DCR C : Check if multiplier zero, otherwise repeat
JNZ DELAY
RET : Return to main program
Traffic light controller …
Stepper motor controller …
• A stepper motor is a digital motor.
• It can be driven by digital signal.
Stepper motor controller …
• Motor shown in the circuit has two phases, with center-tap
winding.
• The center taps of these windings are connected to the 12V
supply.
• Due to this, motor can be excited by grounding four terminals of
the two windings.
• Motor can be rotated in steps by giving proper excitation sequence
to these windings.
• The lower nibble of port A of the 8255 is used to generate
excitation signals in the proper sequence.
Stepper motor controller …
• These excitation signals are buffered using driver transistors.
• The transistors are selected such that they can source rated current
for the windings.
• Motor is rotated by 1.80 per excitation.
Stepper motor controller …
Source Program
Stepper motor controller …
Stepper motor subroutine
Stepper motor controller …
Delay subroutine
Stepper motor controller …
As port A is used as an output port, control word for 8255 is 80H.
Stepper Motor Control Program:
2500H Excite code DB 03H, 06H, 09H, OCH : This is the code sequence for clockwise
rotation
Subroutine to rotate a stepper motor clockwise by 360° - Set the counts:
MVI C, 32H : Set repetition count to 50ıο
START: MVI B, 04H : Counts excitation sequence
LXI H, 2500H : Initialize pointer
BACK1: MOV A, M : Get the Excite code
OUT PORTA : Send Excite code
CALL DELAY : Wait
INX H : Increment pointer
Stepper motor controller …
DCR B : Repeat 4 times
JNZ BACK l
DCR C
JNZ START : Repeat 50 times
RET
Stepper motor controller …

Delay subroutine:
Delay: LXI D, Count
Back: DCX D
MOV A, D
ORA E
JNZ Back
RET