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Uvm

The document provides an overview of UVM concepts including objects, components, factory registration, and phases. It explains that: 1) Objects can be created and destroyed during simulation while components exist for the entire simulation. 2) Factory registration is used for objects and components. Objects use `uvm_object_utils while components use `uvm_component_utils. 3) Components have phases like build, connect, run etc. while objects do not have phases.

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0% found this document useful (0 votes)
164 views18 pages

Uvm

The document provides an overview of UVM concepts including objects, components, factory registration, and phases. It explains that: 1) Objects can be created and destroyed during simulation while components exist for the entire simulation. 2) Factory registration is used for objects and components. Objects use `uvm_object_utils while components use `uvm_component_utils. 3) Components have phases like build, connect, run etc. while objects do not have phases.

Uploaded by

choradiyaankita
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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Non Technical Way of Understanding :

Sequence_item:It will generate the single set of the decimal i/p


Sequence :it will generate the multiple set of the decimal i/p
Seqeuncer :it will send the decimal set of i/p 1 by 1 . I.e Like a security
Guard
Driver :It will convert decimal to binary
Monitor :It will convert binaryy to decimal
Scoreboarad :it will take the decimal o/p and compare and check the o/p and give a
result as Pass/Fail

Technical: decimal->Transcation binary->Pinwiggle

Sequence_item:It will generate the single set of the Transcation i/p


Sequence :it will generate the multiple set of the Transcation i/p
Seqeuncer :it will send the Transcation set of i/p 1 by 1 . I.e
Arbitration(Process) and Arbiter(Component)
Driver :It will convert Transcation to Pinwiggle
Monitor :It will convert Pinwiggle to Transcation
Scoreboarad :it will take the Transcation o/p and compare and check the o/p and
give a result as Pass/Fail

object :object is one which we create and we can destroy whenever we want it will
not be their till end of the simulation
component :Component is one which we create and we can't destroy whenever we want
it will be their till end of the simulation

Note:we use for Sequence and Sequence_item both with field only with field also
* Factory Registration for the object with field ->Sequence_item
and Sequence

Uvm Coding :
1)Factory Registration:Object and Component

o Factory Registration for the object


* Factory Registration for the object w/o field ->Sequence
* Factory Registration for the object with field ->Sequence_item

o Factory Registration for the Component


* Factory Registration for the Component w/o field

2)Constructor:object and Component


* Constructor for the object (have 1 field(argument) i.e Name)
* Constructor for the Component (have 2 field(argument) i.e Name and
Parent)

Note: In Build Phase if their is a create for them we do instatiate

3)Phases :Only Component

object(NO Phases):NA
Component:
1.Build Phase
2.connect Phase
3.end of elobaration Phase
4.start of simulation Phase
5.Run Phase
6.Extrac Phase
7.check Phase
8.Report Phase
9.Final Phase

###################################################################################
#################
###################################################################################
#################
Object || Component
FR || FR
Constructor || Constructor
instatiate || Institiate
NA || Phase
Eg:Sequence_item,Seqeunce ||
Sequencer,Driver,Monitor,Scoreboarad,Agent,Env,Test

Factory Registration:
#####################

Object:Sequence_item and Sequence


w/o field :

class apb_sequence_item extends uvm_sequence_item


`uvm_object_utils(apb_sequence_item)

Component:Seqeuncer
w/o field :

class apb_sequencer extends uvm_sequencer


`uvm_component_utils(apb_sequencer)

UVM_TB_Architectur:
Tb_top |------------------------------------->uvm will be applicable for
this only
Test
Sequence ?c
Sequence_item
Env
Scoreboard
Agent
Seqeuncer
Driver
Monitor
interface
Dut
FR For Component:
Test:
class apb_test extends uvm_test
`uvm_component_utils(apb_test)

Env:
class apb_env extends uvm_env
`uvm_component_utils(apb_env)

Scoreboard:
class apb_scoreboard extends uvm_scoreboard
`uvm_component_utils(apb_scoreboard)

Agent:
class apb_agent extends uvm_agent
`uvm_component_utils(apb_agent)

Sequencer:
class apb_sequencer extends uvm_sequencer
`uvm_component_utils(apb_sequencer)

Driver:
class apb_driver extends uvm_driver
`uvm_component_utils(apb_driver)

Monitor:
class apb_monitor extends uvm_monitor
`uvm_component_utils(apb_monitor)

Object:
Sequence_item:
class apb_sequence_item extends uvm_sequence_item
`uvm_object_utils(apb_sequence_item)

Constructor:
Component:
Test,Env,Scoreboard,Agent,Sequencer,Driver,Monitor:
function new(string name,uvm_component parent="Null")
super.new(name,parent)
endfunction

Object:
Sequence_item,Seqeuence:

function new(string name)


super.new(name)
endfunction

Build_Phase:
Test:
//instance
mem_env env_h;
mem_sequence sequence_h;

//Build_Phase
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = mem_env::type_id::create("env", this);
seq = mem_sequence::type_id::create("seq");
endfunction : build_phase

Env:
mem_agent agent_h;
mem_scoreboard scoreboard_h;

virtual function void build_phase(uvm_phase phase);


super.build_phase(phase);
agent_h = mem_agent::type_id::create("agent_h", this);
scoreboard_h = mem_scoreboard::type_id::create("scoreboard_h",this);
endfunction : build_phase

Agent:
mem_sequencer sequencer_h;
mem_driver driver_h;
mem_monitor monitor_h;

virtual function void build_phase(uvm_phase phase);


super.build_phase(phase);
seqeuncer_h = mem_sequencer::type_id::create("sequencer_h", this);
driver_h = mem_driver::type_id::create("driver_h",this);
monitor_h = mem_monitor::type_id::create("monitor_h",this);
endfunction : build_phase

----------------------------------
Build Phase :
test (env,seq)
env (sb,agent)
agent (sqr,drv,mon)

before build we need to institate.

test.sv
//instatiate
mem_env env_h;
mem_sequence sequence_h;

//build
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = mem_model_env::type_id::create("env", this);
sequence_h = mem_sequence::type_id::create("sequence_h");
endfunction : build_phase

env.sv (agnt,scb)

//instatiate
mem_scb scb_h;
mem_agent agent_h;

//build
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
scb_h = mem_scb::type_id::create("scb_h", this);
agent_h = mem_agent::type_id::create("agent_h",this);
endfunction : build_phase

agent.sv
//instatiate
mem_sqr sqr_h;
mem_drv drv_h;
mem_mon mon_h;

//build
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
sqr_h = mem_sqr::type_id::create("sqr_h", this);
drv_h = mem_drv::type_id::create("drv_h",this);
mon_h = mem_mon::type_id::create("mon_h",this);
endfunction : build_phase

connect.sv :
Sequencer-driver uvm rules followed (connect)
driver-interface no uvm rules followed coz of interface (no connect)
interface-dut no uvm rules followed coz of interface and dut (no connect)
dut-interface no uvm rules followed coz of interface and dut (no connect)
interface-Monitor no uvm rules folloed coz of interface (no connect)
monitor-scb uvm rules followed (connect)

sequncer-driver connect in agent.sv


monitor-scb connect in env.sv

########################
verilog:
########################
TB_TOP
Test/TB
DUT

#########################
System_Verilog
#########################
TB_TOP
Test
Env
Scb
Gen
Tx
Bfm
MOn
Interface
Dut
#########################
UVM
#########################
TB_Top
Test
Seq
Sequence_item
Env
Scb
Agnt
SQR
DRV
MON
Interface
Dut

//print
paddr
pwdata
prdata
pwrite
pselx
pready
pslaveerror
penable
..
100000
//code-1(System verilog)
//$display("%d",paddr);
$display("%x",pwdata);
$display("%d",prdata);
$display("%d",pwrite);
$display("%d",pselx);
$display("%d",penable);
$display("%d",pslaveerror);
$display("%d",pready);

//code-2:(uvm)
tx.print();
---------------------------------------------------
copy
tx1 and tx2

tx2.addr=tx1.addr
tx2.wd=tx1.addr
tx2.addr=tx1.addr
tx2.addr=tx1.addr
tx2.addr=tx1.addr
tx2.addr=tx1.addr

1)Only Few signals i want to print eg:8 signals out of 10 signals ?


2)I want few signals to be in hex , few dec ,few in bin ?
3)i want to compare only partial signals eg:8 signals out of 10 signals
4)i want to copy only partial signals eg:8 signals out of 10 signals

//sv
//$display("%d",paddr);
//$display("%d",pwdata);
$display("%d",prdata);
$display("%d",pwrite);
$display("%d",pselx);
$display("%d",penable);
$display("%d",pslaveerror);
$display("%d",pready);

//uvm
tx.print();

class apb_sequence extends uvm_sequence;


`uvm_object_utils(apb_sequence)//copy compare print record clone pack unpack create

class apb_sequencer extends uvm_sequencer;


`uvm_component_utils(apb_sequencer)//
phases,heirachy,reporting,tx_recording,factory,reporting(severity and
verbosity),do_hooks(copy,compare,print,pack,unpack,record,clone)

class
Property(Data Type Declartion)
Method (Data Type Usage)

Task (Non Zero Time/Delay)


Function(Zero Time/No Delay)

Normal Function(Function Name!=new()) -->Function


Constructor (Function Name==new())

Implicit Constructor (function new defination will be


default/hidden)
Explicit Constructor (function new defination user
need to write)

property is for declartion and method for the usage .


class abc;
//property (legal)
int a;
int b;
int c;

c=a+b;//nor property and method so it will give error (illegal)

//Method (legal)
function add();
c=a+b;
#2 c=a+b;(illegal coz we cannot have delay in function)
endfunction

task add();
c=a+b;(legal)
wait(a)
#2 c=a+b;
endtask

Note:
Inside function :only non delay can come ,delay statment cannot come
Inside Task :Both delay and non delay statment can come

endclass

class abc;
int a;

function new();
endfunction

endclass

abc a1;
a1=new();

//code-1:function defination is missing and function calling is present


class abc;
//function new defination is hidden->Implicit constructor
endclass

abc a1;
a1=new();

//code-2
class abc;
//function new defination is user written->Explicit constructor
function new();
endfunction
endclass

abc a1;
a1=new();
//function defination
function add(int a,int b);
c=a+b;
endfunction

//function calling
add(2,3)

class abc;
endclass

abc a1;//instance or instatiate or instatiation (datatype declaration)


a1=new();//object creation

abc a1;//abc-userdefined datatype , a1-variable


int a1;//int-built-in datatype , a1-variable

float(c)==real(v)

int a1;
real a1;
bit a1;

abc a1;

class student;
int roll_no;
string student_name;
endclass

student s1;//student(userdefined Datatype),s1(variable)


s1.roll_no=1;
s1.student_name="Raju"

int a1;

class abc;
int a;
bit b;
//#################HIDDEN Constructor###############################
//function new();
//1)create a blank memory
//2)Extract the variable of the class
//3)Assigned the defualt value
//4)Assign the handle to the memory
//endfunction
//#################HIDDEN Constructor###############################

endclass

abc a1;
a1=new();

class abc;
//Property
int a=10;
bit b=0;

//method
function hello();
$display("%d %b",a,b);
endfunction

endclass

abc a1;
a1=new();
//accessing the Property
a1.a=40;
a1.b=1;

//accessing the method


a1.hello();

. dot operator we will access the property and method

Implicit constructor :

class abc;
//#################HIDDEN Constructor###############################
//function new();
//1)create a blank memory
//2)Extract the variable of the class
//3)Assigned the defualt value
//4)Assign the handle to the memory
//endfunction
//#################HIDDEN Constructor###############################
endclass

abc a1;
a1=new();
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
$$$$$$$$$$$$$
Explicit constructor :

class abc;
int a;
int b;

function new(int a1,int b1);


a=a1;
b=b1;
endfunction

endclass

abc a1;
a1=new(10,20)

Explicit constructor:
//function new();
//1)create a blank memory
//2)Extract the variable of the class
//3)Assigned the userdefined value
//4)Assign the handle to the memory
//endfunction

UVM_VOID
|
UVM_OBJECT
|
UVM_REPORT_OBJECT
|
UVM_COMPONENT
|
UVM_TEST

class uvm_void;
endclass

class uvm_object extends uvm_void;


uvm_void v1;
v1=new();
endclass

class uvm_report_object extends uvm_object;


uvm_object o1;
o1=new();
endclass

class uvm_component extends uvm_report_object;


uvm_report_object r1;
r1=new();
endclass

class uvm_test extends uvm_component;


uvm_component c1;
c1=new();
endclass

###################################################################################
#######
class uvm_void;
endclass

class uvm_object extends uvm_void;

function new();
super.new();
endfunction

endclass

class uvm_report_object extends uvm_object;


function new();
super.new();
endfunction
endclass

class uvm_component extends uvm_report_object;


function new();
super.new();
endfunction
endclass

class uvm_test extends uvm_component;


function new();
super.new();
endfunction
endclass

uvm_test t1;
t1=new();
Note:For every class we need to create a memory

class abc;
abc a1;
a1=new();
endclass

class abc;
endclass

class def;
abc a1;
a1=new();
endclass

class abc;
//property
int a;

//method
function hello();
endfunction

endclass

###################################################################################
#################
###################################################################################
#################
###################################################################################
#################
###################################################################################
#################
//Non_Heriachy
class abc;
endclass
class def;
abc a1;//instance

a1=new();//object creation in sv
or
a1=abc::type_id::create("a1",this);//object creation in uvm

endclass
--------------------------------------------------------------
//Heirachy
class abc;
endclass

class def extends abc;

function new();
super.new();
endfunction
endclass

uvm_void
|
uvm_object
|
uvm_report_object
|
uvm_component
|
uvm_test uvm_env uvm_agent uvm_scoreboard uvm_seqeuncer
uvm_driver uvm_monitor
| | | | | |
|
apb_test apb_env apb_agent apb_scoreboard apb_seqeuncer
apb_driver apb_monitor

test
env
sb
agent
sqr
drv
mon

run_test->test->env->agent,scb->sqr,drv,mon->respective_uvm_parent->uvm_component-
>uvm_report_object->uvm_object->uvm_void

class uvm_object extends uvm_void;


function new();
super.new();
endfunction
endclass

class uvm_report_object extends uvm_object;


function new();
super.new();
endfunction
endclass

class uvm_component extends uvm_report_object;


function new();
super.new();
endfunction
endclass

class
uvm_test,uvm_env,uvm_agent,uvm_scoreboard,uvm_sequencer,uvm_driver,uvm_monitor
extends uvm_component;
function new();
super.new();
endfunction
endclass
-----------------------------------------------------------------------------------
-------Till above those coding are part of lib
class apb_test extends uvm_test;

//apb_test-uvm_test
function new();
super.new()
endfunction

//apb_test-apb_env
apb_env apb_env_h;
apb_env_h=new();//sv-no need
or
apb_env_h=apb_env::type_id::create("apb_env_h",this);//uvm

endclass

class apb_env extends uvm_env;


//apb_env-uvm_env
function new();
super.new()
endfunction

//apb_env-apb_agent,apb_scoreboard
apb_agent apb_agent_h;
apb_scoreboard apb_scoreboard_h;

//sv code (not needed)


apb_scoreboard_h=new();
apb_agent_h =new();

//uvm code
apb_scoreboard_h=apb_scoreboard::type_id::create("apb_scoreboard_h",this)
apb_agent_h =apb_agent ::type_id::create("apb_agent_h",this)

endclass

class apb_scoreboard extends uvm_scoreboard;


//apb_scoreboard-uvm_scoreboard

function new();
super.new()
endfunction

endclass

class apb_agent extends uvm_agent;


//apb_agent-uvm_agent
function new();
super.new()
endfunction

//apb_agent-apb_seqeuncer,apb_driver,apb_monitor

apb_sequencer apb_sequencer_h;
apb_driver apb_driver_h;
apb_monitor apb_monitor_h;

//sv -this lines are not needed as it as uvm code ,for sv we go for this code
apb_sequencer_h=new();
apb_driver_h =new();
apb_monitor_h =new();

//uvm
apb_sequencer_h=apb_sequencer::type_id::create("apb_sequencer_h",this)
apb_driver_h =apb_driver ::type_id::create("apb_driver_h" ,this)
apb_monitor_h =apb_monitor ::type_id::create("apb_monitor_h" ,this)

endclass

class apb_sequencer extends uvm_sequencer;


//apb_sequencer-uvm_sequencer
function new();
super.new()
endfunction
endclass

class apb_driver extends uvm_driver;


//apb_driver-uvm_driver
function new();
super.new()
endfunction
endclass

class apb_monitor extends uvm_monitor;


//apb_monitor-uvm_monitor
function new();
super.new()
endfunction
endclass

//sv
class abc;
endclass

class def;
abc a1;
a1=new();//sv
a1=abc::type_id::create("a1")//uvm
create=new+factory_override

endclass

//uvm
class abc;
endclass

class def;
abc a1;
a1=abc::type_id::create("a1")
endclass

###################################################################################
#################
###################################################################################
#################
04/08/2023
###################################################################################
#################
###################################################################################
#################
0)create a text format file
tb_top.sv
test.sv
seq.sv
seq_item.sv
env.sv
scb.sv
agent.sv
sqr.sv
drv.sv
mon.sv
interface.sv
dut.sv
1)Factory Registration test,env,scb,agent,sqr,drv,mon,seq,sequence_item
2)Constructor code test,env,scb,agent,sqr,drv,mon,seq,Sequence_item
3)instance test,env,scb,agent,sqr,drv,mon,seq,Sequence_item
4)create/new done i.e build_phase

class abc;
function new(string name);
endfunction
endclass

class def;
abc a1;
a1=new("a1",this);
a1=abc::type_id::create("a1")
endclass

class def extends abc;


function new(9,10);
super.new();
endfunction
endclass

function add(int a,int b,int c)


endfunction

add(2,3,4)

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