Uvm
Uvm
object :object is one which we create and we can destroy whenever we want it will
not be their till end of the simulation
component :Component is one which we create and we can't destroy whenever we want
it will be their till end of the simulation
Note:we use for Sequence and Sequence_item both with field only with field also
* Factory Registration for the object with field ->Sequence_item
and Sequence
Uvm Coding :
1)Factory Registration:Object and Component
object(NO Phases):NA
Component:
1.Build Phase
2.connect Phase
3.end of elobaration Phase
4.start of simulation Phase
5.Run Phase
6.Extrac Phase
7.check Phase
8.Report Phase
9.Final Phase
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Object || Component
FR || FR
Constructor || Constructor
instatiate || Institiate
NA || Phase
Eg:Sequence_item,Seqeunce ||
Sequencer,Driver,Monitor,Scoreboarad,Agent,Env,Test
Factory Registration:
#####################
Component:Seqeuncer
w/o field :
UVM_TB_Architectur:
Tb_top |------------------------------------->uvm will be applicable for
this only
Test
Sequence ?c
Sequence_item
Env
Scoreboard
Agent
Seqeuncer
Driver
Monitor
interface
Dut
FR For Component:
Test:
class apb_test extends uvm_test
`uvm_component_utils(apb_test)
Env:
class apb_env extends uvm_env
`uvm_component_utils(apb_env)
Scoreboard:
class apb_scoreboard extends uvm_scoreboard
`uvm_component_utils(apb_scoreboard)
Agent:
class apb_agent extends uvm_agent
`uvm_component_utils(apb_agent)
Sequencer:
class apb_sequencer extends uvm_sequencer
`uvm_component_utils(apb_sequencer)
Driver:
class apb_driver extends uvm_driver
`uvm_component_utils(apb_driver)
Monitor:
class apb_monitor extends uvm_monitor
`uvm_component_utils(apb_monitor)
Object:
Sequence_item:
class apb_sequence_item extends uvm_sequence_item
`uvm_object_utils(apb_sequence_item)
Constructor:
Component:
Test,Env,Scoreboard,Agent,Sequencer,Driver,Monitor:
function new(string name,uvm_component parent="Null")
super.new(name,parent)
endfunction
Object:
Sequence_item,Seqeuence:
Build_Phase:
Test:
//instance
mem_env env_h;
mem_sequence sequence_h;
//Build_Phase
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = mem_env::type_id::create("env", this);
seq = mem_sequence::type_id::create("seq");
endfunction : build_phase
Env:
mem_agent agent_h;
mem_scoreboard scoreboard_h;
Agent:
mem_sequencer sequencer_h;
mem_driver driver_h;
mem_monitor monitor_h;
----------------------------------
Build Phase :
test (env,seq)
env (sb,agent)
agent (sqr,drv,mon)
test.sv
//instatiate
mem_env env_h;
mem_sequence sequence_h;
//build
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = mem_model_env::type_id::create("env", this);
sequence_h = mem_sequence::type_id::create("sequence_h");
endfunction : build_phase
env.sv (agnt,scb)
//instatiate
mem_scb scb_h;
mem_agent agent_h;
//build
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
scb_h = mem_scb::type_id::create("scb_h", this);
agent_h = mem_agent::type_id::create("agent_h",this);
endfunction : build_phase
agent.sv
//instatiate
mem_sqr sqr_h;
mem_drv drv_h;
mem_mon mon_h;
//build
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
sqr_h = mem_sqr::type_id::create("sqr_h", this);
drv_h = mem_drv::type_id::create("drv_h",this);
mon_h = mem_mon::type_id::create("mon_h",this);
endfunction : build_phase
connect.sv :
Sequencer-driver uvm rules followed (connect)
driver-interface no uvm rules followed coz of interface (no connect)
interface-dut no uvm rules followed coz of interface and dut (no connect)
dut-interface no uvm rules followed coz of interface and dut (no connect)
interface-Monitor no uvm rules folloed coz of interface (no connect)
monitor-scb uvm rules followed (connect)
########################
verilog:
########################
TB_TOP
Test/TB
DUT
#########################
System_Verilog
#########################
TB_TOP
Test
Env
Scb
Gen
Tx
Bfm
MOn
Interface
Dut
#########################
UVM
#########################
TB_Top
Test
Seq
Sequence_item
Env
Scb
Agnt
SQR
DRV
MON
Interface
Dut
//print
paddr
pwdata
prdata
pwrite
pselx
pready
pslaveerror
penable
..
100000
//code-1(System verilog)
//$display("%d",paddr);
$display("%x",pwdata);
$display("%d",prdata);
$display("%d",pwrite);
$display("%d",pselx);
$display("%d",penable);
$display("%d",pslaveerror);
$display("%d",pready);
//code-2:(uvm)
tx.print();
---------------------------------------------------
copy
tx1 and tx2
tx2.addr=tx1.addr
tx2.wd=tx1.addr
tx2.addr=tx1.addr
tx2.addr=tx1.addr
tx2.addr=tx1.addr
tx2.addr=tx1.addr
//sv
//$display("%d",paddr);
//$display("%d",pwdata);
$display("%d",prdata);
$display("%d",pwrite);
$display("%d",pselx);
$display("%d",penable);
$display("%d",pslaveerror);
$display("%d",pready);
//uvm
tx.print();
class
Property(Data Type Declartion)
Method (Data Type Usage)
//Method (legal)
function add();
c=a+b;
#2 c=a+b;(illegal coz we cannot have delay in function)
endfunction
task add();
c=a+b;(legal)
wait(a)
#2 c=a+b;
endtask
Note:
Inside function :only non delay can come ,delay statment cannot come
Inside Task :Both delay and non delay statment can come
endclass
class abc;
int a;
function new();
endfunction
endclass
abc a1;
a1=new();
abc a1;
a1=new();
//code-2
class abc;
//function new defination is user written->Explicit constructor
function new();
endfunction
endclass
abc a1;
a1=new();
//function defination
function add(int a,int b);
c=a+b;
endfunction
//function calling
add(2,3)
class abc;
endclass
float(c)==real(v)
int a1;
real a1;
bit a1;
abc a1;
class student;
int roll_no;
string student_name;
endclass
int a1;
class abc;
int a;
bit b;
//#################HIDDEN Constructor###############################
//function new();
//1)create a blank memory
//2)Extract the variable of the class
//3)Assigned the defualt value
//4)Assign the handle to the memory
//endfunction
//#################HIDDEN Constructor###############################
endclass
abc a1;
a1=new();
class abc;
//Property
int a=10;
bit b=0;
//method
function hello();
$display("%d %b",a,b);
endfunction
endclass
abc a1;
a1=new();
//accessing the Property
a1.a=40;
a1.b=1;
Implicit constructor :
class abc;
//#################HIDDEN Constructor###############################
//function new();
//1)create a blank memory
//2)Extract the variable of the class
//3)Assigned the defualt value
//4)Assign the handle to the memory
//endfunction
//#################HIDDEN Constructor###############################
endclass
abc a1;
a1=new();
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
$$$$$$$$$$$$$
Explicit constructor :
class abc;
int a;
int b;
endclass
abc a1;
a1=new(10,20)
Explicit constructor:
//function new();
//1)create a blank memory
//2)Extract the variable of the class
//3)Assigned the userdefined value
//4)Assign the handle to the memory
//endfunction
UVM_VOID
|
UVM_OBJECT
|
UVM_REPORT_OBJECT
|
UVM_COMPONENT
|
UVM_TEST
class uvm_void;
endclass
###################################################################################
#######
class uvm_void;
endclass
function new();
super.new();
endfunction
endclass
uvm_test t1;
t1=new();
Note:For every class we need to create a memory
class abc;
abc a1;
a1=new();
endclass
class abc;
endclass
class def;
abc a1;
a1=new();
endclass
class abc;
//property
int a;
//method
function hello();
endfunction
endclass
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//Non_Heriachy
class abc;
endclass
class def;
abc a1;//instance
a1=new();//object creation in sv
or
a1=abc::type_id::create("a1",this);//object creation in uvm
endclass
--------------------------------------------------------------
//Heirachy
class abc;
endclass
function new();
super.new();
endfunction
endclass
uvm_void
|
uvm_object
|
uvm_report_object
|
uvm_component
|
uvm_test uvm_env uvm_agent uvm_scoreboard uvm_seqeuncer
uvm_driver uvm_monitor
| | | | | |
|
apb_test apb_env apb_agent apb_scoreboard apb_seqeuncer
apb_driver apb_monitor
test
env
sb
agent
sqr
drv
mon
run_test->test->env->agent,scb->sqr,drv,mon->respective_uvm_parent->uvm_component-
>uvm_report_object->uvm_object->uvm_void
class
uvm_test,uvm_env,uvm_agent,uvm_scoreboard,uvm_sequencer,uvm_driver,uvm_monitor
extends uvm_component;
function new();
super.new();
endfunction
endclass
-----------------------------------------------------------------------------------
-------Till above those coding are part of lib
class apb_test extends uvm_test;
//apb_test-uvm_test
function new();
super.new()
endfunction
//apb_test-apb_env
apb_env apb_env_h;
apb_env_h=new();//sv-no need
or
apb_env_h=apb_env::type_id::create("apb_env_h",this);//uvm
endclass
//apb_env-apb_agent,apb_scoreboard
apb_agent apb_agent_h;
apb_scoreboard apb_scoreboard_h;
//uvm code
apb_scoreboard_h=apb_scoreboard::type_id::create("apb_scoreboard_h",this)
apb_agent_h =apb_agent ::type_id::create("apb_agent_h",this)
endclass
function new();
super.new()
endfunction
endclass
//apb_agent-apb_seqeuncer,apb_driver,apb_monitor
apb_sequencer apb_sequencer_h;
apb_driver apb_driver_h;
apb_monitor apb_monitor_h;
//sv -this lines are not needed as it as uvm code ,for sv we go for this code
apb_sequencer_h=new();
apb_driver_h =new();
apb_monitor_h =new();
//uvm
apb_sequencer_h=apb_sequencer::type_id::create("apb_sequencer_h",this)
apb_driver_h =apb_driver ::type_id::create("apb_driver_h" ,this)
apb_monitor_h =apb_monitor ::type_id::create("apb_monitor_h" ,this)
endclass
//sv
class abc;
endclass
class def;
abc a1;
a1=new();//sv
a1=abc::type_id::create("a1")//uvm
create=new+factory_override
endclass
//uvm
class abc;
endclass
class def;
abc a1;
a1=abc::type_id::create("a1")
endclass
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04/08/2023
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#################
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#################
0)create a text format file
tb_top.sv
test.sv
seq.sv
seq_item.sv
env.sv
scb.sv
agent.sv
sqr.sv
drv.sv
mon.sv
interface.sv
dut.sv
1)Factory Registration test,env,scb,agent,sqr,drv,mon,seq,sequence_item
2)Constructor code test,env,scb,agent,sqr,drv,mon,seq,Sequence_item
3)instance test,env,scb,agent,sqr,drv,mon,seq,Sequence_item
4)create/new done i.e build_phase
class abc;
function new(string name);
endfunction
endclass
class def;
abc a1;
a1=new("a1",this);
a1=abc::type_id::create("a1")
endclass
add(2,3,4)