L7981

3 A step-down switching regulator

Datasheet - production data

 Industrial:
– PLD, PLA, FPGA, chargers
 Networking: XDSL, modems, DC-DC modules
 Computer:
VFQFPN8 3 x 3 HSOP8 exposed pad
– Optical storage, hard disk drive, printers,
audio/graphic cards
Features  Suitable for LED driving

 3 A DC output current
Description
 4.5 V to 28 V input voltage
The L7981 device is a step-down switching
 Output voltage adjustable from 0.6 V
regulator with a 3.7 A (minimum) current limited
 250 kHz switching frequency, programmable embedded Power MOSFET, so it is able to deliver
up to 1 MHz up to 3 A current to the load depending on the
 Internal soft-start and enable application conditions.
 Low dropout operation: 100% duty cycle The input voltage can range from 4.5 V to 28 V,
 Voltage feed-forward while the output voltage can be set starting from
0.6 V to VIN.
 Zero load current operation
Requiring a minimum set of external components,
 Overcurrent and thermal protection
the device includes an internal 250 kHz switching
 VFQFPN 3 x 3 - 8L and HSOP8 package frequency oscillator that can be externally
adjusted up to 1 MHz.
Applications The QFN and the HSOP packages with exposed
pad allow reducing the RthJA down to 60°C/W and
 Consumer:
40°C/W respectively.
– STB, DVD, DVD recorder, car audio, LCD
TV and monitors

Figure 1. Application circuit

May 2014 DocID15182 Rev 5 1/42

This is information on a product in full production. www.st.com
Contents L7981

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Application informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2 Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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L7981 Contents

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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Pin settings L7981

1 Pin settings

1.1 Pin connection

Figure 2. Pin connection (top view)

OUT VCC
SYNCH GND
EN FSW
COMP FB

1.2 Pin description

Table 1. Pin description
No. Type Description

1 OUT Regulator output

Master/slave synchronization. When it is left floating, a signal with
a phase shift of half a period respect to the power turn on is present at
the pin. When connected to an external signal at a frequency higher than
the internal one, then the device is synchronized by the external signal,
2 SYNCH
with zero phase shift.
Connecting together the SYNCH pin of two devices, the one with higher
frequency works as master and the other one as slave; so the two
powers turn on have a phase shift of half a period.
A logical signal (active high) enable the device. With EN higher than
3 EN
1.2 V the device is ON and with EN is lower than 0.3 V the device is OFF.
4 COMP Error amplifier output to be used for loop frequency compensation
Feedback input. Connecting the output voltage directly to this pin the
5 FB output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from Vout to the FB pin.
The switching frequency can be increased connecting an external
6 FSW resistor from the FSW pin and ground. If this pin is left floating the device
works at its free-running frequency of 250 kHz.
7 GND Ground
8 VCC Unregulated DC input voltage

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L7981 Maximum ratings

2 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

Vcc Input voltage 30

OUT Output DC voltage -0.3 to VCC
FSW, COMP, SYNCH Analog pin -0.3 to 4 V
EN Enable pin -0.3 to VCC
FB Feedback voltage -0.3 to 1.5

Power dissipation VFQFPN 1.5.

PTOT W
at TA < 60 °C HSOP 2
TJ Junction temperature range -40 to 150 °C
Tstg Storage temperature range -55 to 150 °C

3 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

Maximum thermal resistance VFQFPN 60

RthJA °C/W
junction ambient(1) HSOP 40
1. Package mounted on demonstration board.

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Electrical characteristics L7981

4 Electrical characteristics

TJ = 25 °C, VCC = 12 V, unless otherwise specified.

Table 4. Electrical characteristics

Values
Symbol Parameter Test condition Unit
Min. Typ. Max.

VCC (1)
Operating input voltage range 4.5 28
(1)
VCCON Turn on VCC threshold 4.4 V
VCCHYS (1)
VCC UVLO hysteresis 0.12 0.35
160 180
RDSON Mosfet on resistance m
(1)
160 250
ILIM Maximum limiting current 3.7 4.2 4.7 A

Oscillator

225 250 275

FSW Switching frequency KHz
(1)
220 275
VFSW FSW pin voltage 1.254 V
D Duty cycle 0 100 %
FADJ Adjustable switching frequency RFSW = 33 k 1000 KHz

Dynamic characteristics

VFB Feedback voltage 4.5 V < VCC < 28 V(1) 0.593 0.6 0.607 V

DC characteristics

IQ Quiescent current Duty cycle = 0, VFB = 0.8 V 2.4 mA

IQST-BY Total standby quiescent current 20 30 A

Enable

Device OFF level 0.3

EN threshold voltage V
Device ON level 1.2
EN current EN = VCC 7.5 10 A

Soft-start

FSW pin floating 7.4 8.2 9.1

TSS Soft-start duration FSW = 1 MHz, ms
2
RFSW = 33 k

Error amplifier

VCH High level output voltage VFB < 0.6 V 3

V
VCL Low level output voltage VFB > 0.6 V 0.1
IO SOURCE Source COMP pin VFB = 0.5 V, VCOMP = 1 V 17 mA

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L7981 Electrical characteristics

Table 4. Electrical characteristics (continued)

Values
Symbol Parameter Test condition Unit
Min. Typ. Max.

IO SINK Sink COMP pin VFB = 0.7 V, VCOMP = 1 V 25 mA

GV (2)
Open loop voltage gain 100 dB

Synchronization function

High input voltage 2 3.3

V
Low input voltage 1
Slave sink current VSYNCH = 2.9 V 0.7 0.9 mA
Master output amplitude ISOURCE = 4.5 mA 2.0 V
Output pulse width SYNCH floating 110
ns
Input pulse width 70

Protection

Thermal shutdown 150

TSHDN °C
Hysteresis 30
1. Specification referred to TJ from -40 to +125 °C. Specification in the -40 to +125 °C temperature range are assured by
design, characterization and statistical correlation.
2. Guaranteed by design.

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Functional description L7981

5 Functional description

The L7981 device is based on a “voltage mode”, constant frequency control. The output
voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V)
providing an error signal that, compared to a fixed frequency sawtooth, controls the on and
off time of the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
 A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed forward are implemented.
 The soft-start circuitry to limit inrush current during the start-up phase.
 The voltage mode error amplifier
 The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch.
 The high-side driver for embedded P-channel Power MOSFET switch.
 The peak current limit sensing block, to handle overload and short-circuit conditions.
 A voltage regulator and internal reference. It supplies internal circuitry and provides
a fixed internal reference.
 A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
 A thermal shutdown block, to prevent thermal runaway.

Figure 3. Block diagram

VCC

REGULATOR
TRIMMING UVLO
&
EN EN
BANDGAP
PEAK
1.254V 3.3V CURRENT
LIMIT
0.6V
SOFT- THERMAL
START SHUTDOWN
COMP DRIVER

E/A S Q
PWM
R

OUT
SYNCH
&
OSCILLATOR PHASE SHIFT

FB FSW GND SYNCH

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L7981 Functional description

5.1 Oscillator and synchronization

Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides
a constant frequency clock. Its frequency depends on the resistor externally connected to
the FSW pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be
increased as shown in Figure 6 by external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feed forward is implemented (Figure 5.b) in order
to keep the PWM gain constant versus the switching frequency (see Section 6.4 on page 18
for PWM gain expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with
higher oscillator frequency works as the master, so the slave device switches at the
frequency of the master but with a delay of half a period. This minimizes the RMS current
flowing through the input capacitor (see the L5988D datasheet).

Figure 4. Oscillator circuit block diagram

Clock

FSW Clock
Synchronization SYNCH
Generator

Ramp
Sawtooth
Generator

The device can be synchronized to work at higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This changing has to be taken into account when the loop stability is studied.
To minimize the change of the PWM gain, the free running frequency should be set (with
a resistor on the FSW pin) only slightly lower than the external clock frequency. This pre-
adjusting of the frequency will change the sawtooth slope in order to get negligible the
truncation of sawtooth, due to the external synchronization.

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Functional description L7981

Figure 5. Sawtooth: voltage and frequency feed forward; external synchronization

Figure 6. Oscillator frequency versus FSW pin resistor

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L7981 Functional description

5.2 Soft-start
The soft-start is essential to assure a correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increases monothonically.
The soft-start is performed by a staircase ramp on the non inverting input (VREF) of the error
amplifier. So the output voltage slew rate is:

Equation 1
R1
SR OUT = SR VREF   1 + --------
 R2

where SRVREF is the slew rate of the non inverting input, while R1and R2 is the resistor
divider to regulate the output voltage (see Figure 7). The soft-start stair case consists of
64 steps of 9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock
cycles. So the soft-start time and then the output voltage slew rate depend on the switching
frequency.

Figure 7. Soft-start scheme

Soft-start time results:

Equation 2
32  64
SS TIME = -----------------
Fsw

For example with a switching frequency of 250 kHz the SSTIME is 8 ms.

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Functional description L7981

5.3 Error amplifier and compensation

The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:

Table 5. Uncompensated error amplifier characteristics

Parameter Value

Low frequency gain 100 dB

GBWP 4.5 MHz
Slew rate 7 V/s
Output voltage swing 0 to 3.3 V
Maximum source/sink current 17 mA/25 mA

In continuous conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter a type II compensation network can be used. Otherwise, a type
III compensation network has to be used (see Section 6.4 on page 18 for details about the
compensation network selection).
Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe
phase margin.

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L7981 Functional description

5.4 Overcurrent protection

The L7981 implements the overcurrent protection sensing current flowing through the
Power MOSFET. Due to the noise created by the switching activity of the Power MOSFET,
the current sensing is disabled during the initial phase of the conduction time. This avoids
an erroneous detection of a fault condition. This interval is generally known as “masking
time” or “blanking time”. The masking time is about 200 ns.
When the overcurrent is detected, two different behaviors are possible depending on the
operating condition.
1. Output voltage in regulation. When the overcurrent is sensed, the Power MOSFET is
switched off and the internal reference (VREF), that biases the non inverting input of the
error amplifier, is set to zero and kept in this condition for a soft-start time (TSS, 2048
clock cycles). After this time, a new soft-start phase takes place and the internal
reference begins ramping (see Figure 8.a).
2. Soft-start phase. If the overcurrent limit is reached the Power MOSFET is turned off
implementing the pulse by pulse overcurrent protection. During the soft-start phase,
under overcurrent condition, the device can skip pulses in order to keep the output
current constant and equal to the current limit. If at the end of the “masking time” the
current is higher than the overcurrent threshold, the Power MOSFET is turned off and it
will skip one pulse. If, at the next switching on at the end of the “masking time” the
current is still higher than the threshold, the device will skip two pulses. This
mechanism is repeated and the device can skip up to seven pulses. While, if at the end
of the “masking time” the current is lower than the overcurrent threshold, the number of
skipped cycles is decreased of one unit. At the end of soft-start phase the output
voltage is in regulation and if the overcurrent persists the behavior explained above
takes place (see Figure 8.b).
So the overcurrent protection can be summarized as an “hiccup” intervention when the
output is in regulation and a constant current during the soft-start phase. If the output is
shorted to ground when the output voltage is on regulation, the overcurrent is triggered and
the device starts cycling with a period of 2048 clock cycles between “hiccup” (Power
MOSFET off and no current to the load) and “constant current” with very short on-time and
with reduced switching frequency (up to one eighth of normal switching frequency). See
Figure 32 on page 33 for short-circuit behavior.

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Functional description L7981

Figure 8. Overcurrent protection strategy

5.5 Enable function

The enable feature allows to put in standby mode the device. With the EN pin lower than
0.3 V the device is disabled and the power consumption is reduced to less than 30 µA. With
the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal
pull down ensures that the voltage at the pin reaches the inhibit threshold and the device is
disabled. The pin is also VCC compatible.

5.6 Hysteretic thermal shutdown

The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, so ensuring an accurate and fast temperature detection.

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L7981 Application informations

6 Application informations

6.1 Input capacitor selection

The capacitor connected to the input has to be capable to support the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 3
2 2
2D D
I RMS = I O  D – --------------- + ------2-
 

Where IO is the maximum DC output current, D is the duty cycle, is the efficiency.
Considering , this function has a maximum at D = 0.5 and it is equal to IO/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:

Equation 4
V OUT + V F
D MAX = -------------------------------------
V INMIN – V SW

and

Equation 5
V OUT + V F
D MIN = --------------------------------------
V INMAX – V SW

Where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across
the internal PDMOS.
The peak to peak voltage across the input capacitor can be calculated as:

Equation 6
IO D D
V PP = -------------------------   1 – ----  D + ----   1 – D  + ESR  I O
C IN  F SW   

where ESR is the equivalent series resistance of the capacitor.

Given the physical dimension, ceramic capacitors can meet well the requirements of the
input filter sustaining a higher input RMS current than electrolytic / tantalum types.

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Application informations L7981

In this case the equation of CIN as a function of the target VPP can be written as follows:

Equation 7
IO D D
C IN = ---------------------------   1 – ----  D + ----   1 – D 
V PP  F SW   

neglecting the small ESR of ceramic capacitors.

Considering = 1, this function has its maximum in D = 0.5, thus, given the maximum peak
to peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is:

Equation 8
IO
C IN_MIN = ------------------------------------------------
2  V PP_MAX  F SW

Typically CIN is dimensioned to keep the maximum peak-peak voltage in the order of 1% of
VINMAX
In Table 6 some multi layer ceramic capacitors suitable for this device are reported.

Table 6. Input MLCC capacitors

Manufacture Series Cap value (F) Rated voltage (V)

UMK325BJ106MM-T 10 50
Taiyo Yuden
GMK325BJ106MN-T 10 35
Murata GRM32ER71H475K 4.7 50

A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that
additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability
on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to
1 µF.

6.2 Inductor selection

The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple has to be selected.
The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.
In the continuous current mode (CCM), the inductance value can be calculated by Equation
9:

Equation 9
V IN – V OUT V OUT + V F
I L = ------------------------------  T ON = ----------------------------  T OFF
L L

Where TON is the conduction time of the internal high-side switch and TOFF is the
conduction time of the external diode [in CCM, FSW = 1 / (TON + TOFF)]. The maximum
current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle
(see Section 6.1 to calculate minimum duty).

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L7981 Application informations

So fixing IL = 20% to 30% of the maximum output current, the minimum inductance value
can be calculated:

Equation 10
V OUT + V F 1 – D MIN
L MIN = ----------------------------  -----------------------
I MAX F SW

where FSW is the switching frequency, 1 / (TON + TOFF).

For example for VOUT = 5 V, VIN = 24 V, IO = 3 A and FSW = 250 kHz the minimum
inductance value to have IL = 30% of IO is about 18 H.
The peak current through the inductor is given by:

Equation 11
I L
I L PK = I O + --------
2

So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In Table 7 some inductor part numbers are listed.

Table 7. Inductors
Manufacturer Series Inductor value (H) Saturation current (A)

MSS1038 3.8 to 10 3.9 to 6.5

Coilcraft
MSS1048 12 to 22 3.84 to 5.34
PD Type L 8.2 to 15 3.75 to 6.25
Wurth
PD Type M 2.2 to 4.7 4 to 6
CDRH6D226/HP 1.5 to 3.3 3.6 to 5.2
SUMIDA
CDR10D48MN 6.6 to 12 4.1 to 5.7

6.3 Output capacitor selection

The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge or discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor has to be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.

Equation 12
I MAX
V OUT = ESR  I MAX + -------------------------------------
8  C OUT  f SW

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Application informations L7981

Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Section 6.4 it will be illustrated how to consider its effect in the
system stability.
For example with VOUT = 5 V, VIN = 24 V, IL = 0.9 A (resulting by the inductor value), in
order to have a VOUT = 0.01 · VOUT, if the multi layer ceramic capacitor are adopted, 10 F
are needed and the ESR effect on the output voltage ripple can be neglected. In case of not
negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value. So in case of 330 µF with ESR = 30 m, the resistive component of
the drop dominates and the voltage ripple is 28 mV
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application the output capacitor and system bandwidth
have to be chosen in order to sustain the load transient.
In Table 8 some capacitor series are listed.

Table 8. Output capacitors

Manufacturer Series Cap value (F) Rated voltage (V) ESR (m)

GRM32 22 to 100 6.3 to 25 <5

MURATA
GRM31 10 to 47 6.3 to 25 <5
ECJ 10 to 22 6.3 <5
PANASONIC
EEFCD 10 to 68 6.3 15 to 55
SANYO TPA/B/C 100 to 470 4 to 16 40 to 80
TDK C3225 22 to 100 6.3 <5

6.4 Compensation network

The compensation network has to assure stability and good dynamic performance. The loop
of the L7981 is based on the voltage mode control. The error amplifier is a voltage
operational amplifier with high bandwidth. So selecting the compensation network the E/A
will be considered as ideal, that is, its bandwidth is much larger than the system one.
The transfer functions of PWM modulator and the output LC filter are studied (see
Figure 10). The transfer function of the PWM modulator, from the error amplifier output
(COMP pin) to the OUT pin, results:

Equation 13
V IN
G PW0 = ---------
Vs

where VS is the sawtooth amplitude.

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L7981 Application informations

As seen in Section 5.1 on page 9, the voltage feed forward generates a sawtooth amplitude
directly proportional to the input voltage, that is:

Equation 14
V S = K  V IN

In this way the PWM modulator gain results constant and equals to:

Equation 15
V IN 1
G PW0 = --------- = ---- = 13
Vs K

The synchronization of the device with an external clock provided trough the SYNCH pin
can modify the PWM modulator gain (see Section 5.1 to understand how this gain changes
and how to keep it constant in spite of the external synchronization).

Figure 9. The error amplifier, the PWM modulation and the LC output filter

VCC

VS
VREF
PWM
L
E/A OUT
FB COMP
ESR

GPW0 GLC COUT

The transfer function on the LC filter is given by:

Equation 16
s
1 + --------------------------
2  f zESR
G LC  s  = ------------------------------------------------------------------------2-
s s
1 + ---------------------------- +  -------------------
2  Q  f LC  2  f LC

where:

Equation 17
1 1
f LC = ------------------------------------------------------------------------ f zESR = --------------------------------------------
ESR 2  ESR  C OUT
2  L  C OUT  1 + ---------------
R OUT

DocID15182 Rev 5 19/42

42
Application informations L7981

Equation 18
R OUT  L  C OUT   R OUT + ESR  V OUT
Q = ------------------------------------------------------------------------------------------ , R OUT = --------------
L + C OUT  R OUT  E SR I OUT

As seen in Section 5.3 on page 12 two different kind of network can compensate the loop. In
the two following paragraph the guidelines to select the Type II and Type III compensation
network are illustrated.

6.4.1 Type III compensation network

The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with
a frequency higher than the desired bandwidth (that is: 2ESR COUT < 1 / BW), the type
III compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low
ESR (< 1 m), with very high frequency zero, so type III network is adopted to compensate
the loop.
In Figure 10 the type III compensation network is shown. This network introduces two zeros
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:

Equation 19
1 1
f Z1 = ------------------------------------------------ f Z2 = ------------------------------
2  C 3   R 1 + R 3  2  R 4  C 4

Equation 20
1 1
f P0 = 0 f P1 = ------------------------------ f P2 = --------------------------------------------
2  R 3  C 3 C4  C5
2  R 4  --------------------
C4 + C5

Figure 10. Type III compensation network

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L7981 Application informations

In Figure 11 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)]
and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)] are drawn.

Figure 11. Open loop gain: module Bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:
1. Choose a value for R1, usually between 1 k and 5 k.
2. Choose a gain (R4 / R1) in order to have the required bandwidth (BW), that means:

Equation 21
BW
R 4 = ----------  K  R 1
f LC

where K is the feed forward constant and 1 / K is equals to 13.

3. Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC):

Equation 22
1
C 4 = ---------------------------
  R 4  f LC

4. Calculate C5 by placing the second pole at four times the system bandwidth (BW):

Equation 23
C4
C 5 = --------------------------------------------------------------
2  R 4  C 4  4  BW – 1

5. Set also the first pole at four times the system bandwidth and also the second zero at
the output filter double pole:

Equation 24
R1 1
R 3 = --------------------------- C 3 = -----------------------------------------
4  BW 2  R 3  4  BW
----------------- – 1
f LC

DocID15182 Rev 5 21/42

42
Application informations L7981

The suggested maximum system bandwidth is equals to the switching frequency divided by
3.5 (FSW / 3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz.
For example with VOUT = 5 V, VIN = 24 V, IO = 3 A, L = 18 H, COUT = 22 F, ESR < 1 m,
the type III compensation network is:

Equation 25

R 1 = 4.99k R 2 = 680 R 3 = 200 R 4 = 3.3k C 3 = 3.3nF C 4 = 22nF C 5 = 220pF

In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about
58 kHz and the phase margin is 50°.

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L7981 Application informations

Figure 12. Open loop gain bode diagram with ceramic output capacitor

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42
Application informations L7981

6.4.2 Type II compensation network

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with
a frequency lower than the desired bandwidth (that is: 2ESR COUT > 1 / BW), this zero
helps stabilize the loop. Electrolytic capacitors show not negligible ESR (> 30 m), so with
this kind of output capacitor the type II network combined with the zero of the ESR allows
stabilizing the loop.
In Figure 13 the type II network is shown.

Figure 13. Type II compensation network

The singularities of the network are:

Equation 26
1 1
f Z1 = ------------------------------ f P0 = 0 f P1 = --------------------------------------------
2  R 4  C 4 C4  C5
2  R 4  --------------------
C4 + C5

In Figure 14 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)]
and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)] are drawn.

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L7981 Application informations

Figure 14. Open loop gain: module bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:
1. Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R4 / R1) in order to have the required bandwidth (BW), that means:

Equation 27
f ESR 2 BW V S
R 4 =  ------------  ------------  ---------  R 1
 f LC  f ESR V IN

Where fESR is the ESR zero:

Equation 28
1
f ESR = --------------------------------------------
2  ESR  C OUT

and VS is the saw-tooth amplitude. The voltage feed forward keeps the ratio VS/VIN
constant.
3. Calculate C4 by placing the zero one decade below the output filter double pole:

Equation 29
10
C 4 = -------------------------------
2  R 4  f LC

4. Then calculate C3 in order to place the second pole at four times the system bandwidth
(BW):

Equation 30
C4
C 5 = --------------------------------------------------------------
2  R 4  C 4  4  BW – 1

DocID15182 Rev 5 25/42

42
Application informations L7981

For example with VOUT = 5 V, VIN = 24 V, IO = 3 A, L = 18 H, COUT = 330 F, ESR = 35 m
the type II compensation network is:

Equation 31
R 1 = 1.1k R 2 = 150 R 4 = 4.99k C 4 = 82nF C 5 = 68pF

In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about
21 kHz and the phase margin is 45°.

Figure 15. Open loop gain bode diagram with electrolytic/tantalum output capacitor

26/42 DocID15182 Rev 5

L7981 Application informations

6.5 Thermal considerations

The thermal design is important to prevent the thermal shutdown of the device if junction
temperature goes above 150 °C. The three different sources of losses within the device are:
a) conduction losses due to the not negligible RDSon of the power switch; these are
equal to:

Equation 32
2
P ON = R DSON   I OUT   D

Where D is the duty cycle of the application and the maximum RDSon overtemperature is
220 m. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN,
but actually it is quite higher to compensate the losses of the regulator. So the conduction
losses increases compared with the ideal case.
b) switching losses due to Power MOSFET turn ON and OFF; these can be
calculated as:

Equation 33

 T RISE + T FALL 
P SW = V IN  I OUT  -------------------------------------------  Fsw = V IN  I OUT  T SW  F SW
2

Where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS)
and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16.
TSW is the equivalent switching time. For this device the typical value for the equivalent
switching time is 30 ns.
c) Quiescent current losses, calculated as:

Equation 34
P Q = V IN  I Q

where IQ is the quiescent current (IQ = 2.4 mA).

The junction temperature TJ can be calculated as:

Equation 35
T J = T A + Rth JA  P TOT

Where TA is the ambient temperature and PTOT is the sum of the power losses just seen.
RthJA is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The RthJA measured on the demonstration board described in the following
paragraph is about 60 °C/W for the VFQFPN package and about 40 °C/W for the HSOP
package.

DocID15182 Rev 5 27/42

42
Application informations L7981

Figure 16. Switching losses

6.6 Layout considerations

The PC board layout of switching DC/DC regulator is very important to minimize the noise
injected in high impedance nodes and interferences generated by the high switching current
loops.
In a step-down converter the input loop (including the input capacitor, the Power MOSFET
and the free wheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current are flowing through it. In order to minimize the EMI, this loop has to be
as short as possible.
The feedback pin (FB) connection to external resistor divider is a high impedance node, so
the interferences can be minimized placing the routing of feedback node as far as possible
from the high current paths. To reduce the pick up noise the resistor divider has to be placed
very close to the device.
To filter the high frequency noise, a small bypass capacitor (220 nF - 1 µF) can be added as
close as possible to the input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.

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L7981 Application informations

In Figure 17 a layout example is shown.

Figure 17. Layout example

DocID15182 Rev 5 29/42

42
Application informations L7981

6.7 Application circuit

In Figure 18 the demonstration board application circuit is shown.

Figure 18. Demonstration board application circuit (rev 1.0)

Table 9. Component list (rev 1.0)

Reference Part number Description Manufacturer

C1 UMK325BJ106MM-T 10 F, 50 V Taiyo Yuden

C2 GRM32ER61E226KE15 22 F, 25 V Murata
C3 2.2 nF, 50 V
C4 22 nF, 50 V
C5 470 pF, 50 V
C6 470 nF, 50 V
R1 4.99 k, 1%, 0.1 W 0603
R2 1.1 k, 1%, 0.1 W 0603
R3 249 , 1%, 0.1 W 0603
R4 1.5 k, 1%, 0.1 W 0603
R5 220 k1%, 0.1 W 0603
D1 STPS3L40 3A DC, 40 V STMicroelectronics
10 H, 30%, 3.9 A,
L1 MSS1038-103NL Coilcraft
DCRMAX = 35 m

30/42 DocID15182 Rev 5

L7981 Application informations

Figure 19. PCB layout: L7981 and L7981A (component side)

Figure 20. PCB layout: L7981 and L7981A (bottom side)

Figure 21. PCB layout: L7981 and L7981A (front side)

DocID15182 Rev 5 31/42

42
Application informations L7981

Figure 22. Junction temperature vs. output Figure 23. Junction temperature vs. output
current - VIN = 12 V current - VIN = 5 V

Figure 24. Junction temperature vs. output Figure 25. Efficiency vs. output current
current - VIN = 24 V - VOUT = 5 V
92 V IN =12V

VIN =18V

87

VIN =24V
Eff [%]

82

77

VOUT=5.0 V
fsw=250 kHz

72
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Io [A]

Figure 26. Efficiency vs.output current Figure 27. Efficiency vs. output current
- VOUT = 3.3 V - VOUT = 1.8 V
95
85

VIN =5V
90 VIN =5V
80

VIN =12V
85 75
VIN =12V

70
Eff [%]

Eff [%]

80 VIN =24V V IN =24V

65

75
60

70 VOUT=3.3 V VOUT=1.8 V
55
fsw=250 kHz fsw=250 kHz

65 50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0

Io [A] Io [A]

32/42 DocID15182 Rev 5

L7981 Application informations

Figure 28. Load regulation Figure 29. Line regulation

1.6
0.1

1.4 Vcc=5V
Vcc=12V 0.0

1.2 Vcc=24V
-0.1
1
 VFB /VF B [%]

 V FB /V FB [%]
-0.2
0.8
-0.3
0.6
-0.4
0.4 Io=1A
-0.5 Io=2A
0.2 Io=3A

-0.6
0 5 10 15 20 25
0 0.5 1 1.5 2 2.5 3 VCC [V]

Io [A]

Figure 30. Load transient: from 0.4 A to 3 A Figure 31. Soft-start

IL 1A/div
VOUT
VOUT 0.5V/div
1V/div
200mV/div
AC coupled

VIN=24V
VOUT=3.3V
COUT=47uF
L=10uH
IL 1A/div FSW=520k

Time base 1ms/div

Time base 200us/div

Figure 32. Short-circuit behavior

OUT 10V/div

VOUT 1V/div
SHORTED OUTPUT

IL 1A/div

Time base 5ms/div

DocID15182 Rev 5 33/42

42
Application ideas L7981

7 Application ideas

7.1 Positive buck-boost

The L7981 device can implement the step-up/down converter with a positive output voltage.
Figure 33 shows the schematic: one Power MOSFET and one Schottky diode are added to
the standard buck topology to provide 12 V output voltage with input voltage from 4.5 V to
28 V.

Figure 33. Positive buck-boost regulator

The relationship between input and output voltage is:

Equation 36
D
V OUT = V IN  -------------
1–D

So the duty cycle is:

Equation 37
V OUT
D = ------------------------------
V OUT + V IN

The output voltage isn’t limited by the maximum operating voltage of the device (28 V),
because the output voltage is sensed only through the resistor divider. The external Power
MOSFET maximum drain to source voltage must be higher than output voltage; the
maximum gate to source voltage must be higher than the input voltage (in Figure 33, if VIN is
higher than 16 V, the gate must be protected through the Zener diode and resistor)
The current flowing through the internal Power MOSFET is transferred to the load only
during the OFF time, so according to the maximum DC switch current (3.0 A), the maximum
output current for the buck boost topology can be calculated from Equation 38.

Equation 38
I OUT
I SW = -------------  3 A
1–D

where ISW is the average current in the embedded Power MOSFET in the on time.

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L7981 Application ideas

To chose the right value of the inductor and to manage transient output current, that for short
time can exceed the maximum output current calculated by Equation 38, also the peak
current in the Power MOSFET has to be calculated. The peak current, showed in Equation
39, must be lower than the minimum current limit (3.7 A).

Equation 39
I OUT r
I SW,PK = -------------  1 + ---  3.7A
1–D 2

V OUT 2
r = ------------------------------------   1 – D 
I OUT  L  F SW

Where r is defined as the ratio between the inductor current ripple and the inductor DC
current:
So in the buck boost topology the maximum output current depends on the application
conditions (firstly input and output voltage, secondly switching frequency and inductor
value).
In Figure 34 the maximum output current for the above configuration is depicted varying the
input voltage from 4.5 V to 28 V.
The dashed line considers a more accurate estimation of the duty cycles given by Equation
40, where power losses across diodes, external Power MOSFET, internal Power MOSFET
are taken into account.

Figure 34. Maximum output current according to max DC switch current (3.0 A):
VO = 12 V

Equation 40
V OUT + 2  V D
D = --------------------------------------------------------------------------------------------
V IN – V SW – V SWE + V OUT + 2  V D

where VD is the voltage drop across diodes, VSW and VSWE across the internal and external
Power MOSFET.

DocID15182 Rev 5 35/42

42
Application ideas L7981

7.2 Inverting buck-boost

The L7981 device can implement the step-up/down converter with a negative output
voltage.
Figure 33 shows the schematic to regulate -5 V: no further external components are added
to the standard buck topology.
The relationship between input and output voltage is:

Equation 41
D
V OUT = – V IN  -------------
1–D

So the duty cycle is:

Equation 42
V OUT
D = ------------------------------
V OUT – V IN

As in the positive one, in the inverting buck-boost the current flowing through the Power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (3.0 A), the maximum output current can be calculated from the Equation
38, where the duty cycle is given by Equation 42.

Figure 35. Inverting buck-boost regulator

The GND pin of the device is connected to the output voltage so, given the output voltage,
input voltage range is limited by the maximum voltage the device can withstand across VCC
and GND (28 V). Thus if the output is -5 V the input voltage can range from 4.5 V to 23 V.
As in the positive buck-boost, the maximum output current according to application
conditions is shown in Figure 36. The dashed line considers a more accurate estimation of
the duty cycles given by Equation 43, where power losses across diodes and internal Power
MOSFET are taken into account.

Equation 43
V OUT – V D
D = -----------------------------------------------------------------
– V IN – V SW + V OUT – V D

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L7981 Application ideas

Figure 36. Maximum output current according to switch max peak current (3.0 A):
VO = -5 V

DocID15182 Rev 5 37/42

42
Package information L7981

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

Figure 37. VFQFPN8 (3 x 3 x 1.08 mm) package outline

38/42 DocID15182 Rev 5

L7981 Package information

Table 10. VFQFPN8 (3 x 3 x 1.08 mm) package mechanical data

Dimensions

Symbol mm inch

Min. Typ. Max. Min. Typ. Max.

A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0.02 0.05 0.0008 0.0020

A2 0.70 0.0276
A3 0.20 0.0079

b 0.18 0.23 0.30 0.0071 0.0091 0.0118

D 2.95 3.00 3.05 0.1161 0.1181 0.1200
D2 2.23 2.38 2.48 0.0878 0.0937 0.0976

E 2.95 3.00 3.05 0.1161 0.1181 0.1200

E2 1.65 1.70 1.75 0.0649 0.0669 0.0689
e 0.50 0.0197
L 0.35 0.40 0.45 0.0137 0.0157 0.0177
ddd 0.08 0.0031

DocID15182 Rev 5 39/42

42
Package information L7981

Figure 38. HSOP8 package outline

Table 11. HSOP8 package mechanical data

Dimensions

Symbol mm inch

Min. Typ. Max. Min. Typ. Max.

A 1.70 0.0669
A1 0.00 0.15 0.00 0.0059
A2 1.25 0.0492
b 0.31 0.51 0.0122 0.0201
c 0.17 0.25 0.0067 0.0098
D 4.80 4.90 5.00 0.1890 0.1929 0.1969
E 5.80 6.00 6.20 0.2283 0.2441
E1 3.80 3.90 4.00 0.1496 0.1575
e 1.27
h 0.25 0.50 0.0098 0.0197
L 0.40 1.27 0.0157 0.0500
k 0 8 0.3150
ccc 0.10 0.0039

40/42 DocID15182 Rev 5

L7981 Order codes

9 Order codes

Table 12. Order codes

Order codes Package Packaging

L7981A HSOP8 Tube

L7981TR VFQFPN8 Tape and reel
L7981ATR HSOP8 Tape and reel

10 Revision history

Table 13. Document revision history

Date Revision Changes

19-Nov-2008 1 Initial release.

17-Mar-2009 2 Content reworked to improve readability, no technical changes.
01-Jul-2010 3 Added application information.
Updated Table 5 on page 12 (added header).
Updated text below Equation 21 on page 21 (replaced ”K” value: “9”
by “13”).
Numbered Equation 25 on page 22, Equation 26 on page 24 and
Equation 31 on page 26 .
Updated titles of Figure 22 on page 32 to Figure 27 on page 32
21-Mar-2014 4
(added “VIN”and “VOUT” with values).
Updated Section 8: Package information on page 38 (reversed order
of Figure 36 and Table 10, Figure 38 and Table 11, minor
modifications).
Updated cross-references throughout document.
Minor modifications throughout document.
Updated Table 12: Order codes (removed the L7981 order code
05-May-2014 5 related to the VFQFPN8 in tube).
Minor modifications throughout document.

DocID15182 Rev 5 41/42

42
 L7981

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42/42 DocID15182 Rev 5

Mouser Electronics

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