Um3083 stm32g0 Series Iec 60730 Selftest Library User Guide Stmicroelectronics
Um3083 stm32g0 Series Iec 60730 Selftest Library User Guide Stmicroelectronics
User manual
Introduction
This document applies to the X-CUBE-CLASSB self-test library set for the STM32G0 Series microcontrollers that include an
Arm® Cortex®-M0+ core. Order code X-CUBE-CLASSB-G0.
Safety has an essential role in electronic applications. The level of safety requirements for components is steadily increasing
and, manufacturers of electronic devices include many new technical solutions in their designs. Techniques for improving safety
are continuously evolving, and are regularly incorporated into updated versions of the safety standards.
The current safety recommendations and requirements are specified in worldwide standards issued by various authorities.
These include: the international electro-technical commission (IEC), Underwriters laboratories (UL), and the Canadian standards
association (CSA) authorities.
Compliance, verification, and certification are the focus of the certification institutes. These include: the German TUV and VDE
(mostly operating in Europe), and the UL and the CSA (targeting mainly the USA and Canadian markets).
Standards related to safety requirements have a very wide scope. These safety standards cover many areas such as:
classification, methodology, materials, mechanics, labeling, hardware, and software testing. Here, the target is just compliance
with the software requirements when testing programmable electronic components, which form a specific part of the safety
standards. These requirements are exceptionally subject of any change when a new upgrade of the standard is released.
Also, there is significant similarity across commonly oriented safety standards that concern the testing of generic parts of
microcontrollers, such as the CPU or memories.
The library presented in this document is based on a partial subset of testing modules developed and applied by ST to satisfy
the stringent IEC 61508 industrial safety standard requirements. These modules are adapted to fulfill the IEC 60730 standard
targeting household safety. That is why this new library adopts a different delivery format to that was used for previous releases.
This format is derived from the industrial safety library, which is currently delivered as a black box pre-compiled object with no
sources but with a clear outer interface definition. The advantage of this immutable solution is that it is compilation tool-chain
agnostic. It is also independent of any other firmware such as HAL, LL, or CMSIS layer. This solution prevents unexpected
compilation results when source code files previously verified on older versions of the library are re-compiled later by any newer
compiler version or combined with the latest firmware drivers. This is generally a common practice.
X-CUBE-CLASSB X-CUBE-CLASSB-G0
1 General information
Note: Arm is a registered trademark of Arm limited (or its subsidiaries) in the US and/or elsewhere.
The version of the application-independent software test library, self-test library, available in the X-CUBE-
CLASSB-G0 expansion package (and associated to this manual), STL_Lib.a file, is V4.0.0.
2 STM32Cube overview
3 STL overview
The STL is an application-independent software test library released by ST. The aim is to provide the
implementation of a relevant subset of safety mechanisms required by the "Class B" related safety standards
applicable to STM32G0 Series microcontrollers. The STL is an HAL / LL independent library, dedicated to
STM32G0 Series microcontrollers. The STL is a compilation tool chain-agnostic, so any standard C-compiler can
compile it.
The STL is an autonomous software. It executes, on application-demand, selected tests to detect hardware
issues, and reports the outcomes to the application.
The STL is delivered partly in object code (for the library itself) and partly in source code for the user interface
definitions and the user parameter settings.
User application
STL
Function return value
User
Test result value
APIs
STL User
HAL/LL
STL scheduler parameters
STM32 microcontroller
Legend:
DT67412V1
STL
User
4 STL description
This section describes basic information on the functionality and performance of the STL. The section also
summarizes restrictions and mandatory actions to be followed by the end user.
The user application repeatedly applies the call scheme illustrated in the following figure to program a sequence
of API function calls and so handle the order of the test modules execution.
User application
STL
STL scheduler
Legend: DT49038V2
STL
User
Principles
The flash test concerns the embedded flash memory of STM32G0 Series.
The following structures must be respected to provide correct configuration of the flash memory test.
• Block: a contiguous area of 4 bytes (FLASH_BLOCK_SIZE), hard coded by STL.
• Section: a contiguous area of 1024 bytes (FLASH_SECTION_SIZE), hard coded by the STL. This has no
link with the flash memory physical sector. The flash memory is partitioned in sections. The first section
starts at the first address of the flash memory, and the following sections are contiguous with each other.
The user must ensure proper calculation and placement of the CRC checksum for each section that is to
be checked during the flash memory integrity test.
• Binary (named 'user program' in Figure 4): a contiguous area of code provided by the compiler. It starts at
the beginning of a section. It usually ends with an incomplete section when the binary area size is not a
multiple of the section size. In all cases, the binary must be 32-bit aligned (see ST CRC tool information
below).
• Subset: a contiguous area of sections defined by the user. The user application can define one subset or
several subsets. A subset has to be defined within a binary area. Its start address has to be aligned with
the beginning of a section. It can only include sections with the corresponding precalculated CRC values.
When the last section of a subset is the last part of the binary, the section may be incomplete. The user
application has to align the end of the subset with the end address of the binary area. If a set of complete
sections is tested exclusively, the subset end address has to be aligned with the end of the last-tested
section.
The subset is calculated as follows:
Subset size = K * FLASH_SECTION_SIZE + L * FLASH_BLOCK_SIZE
where:
– K is an integer greater than 0.
– 0 ≤ L < (FLASH_SECTION_SIZE / FLASH_BLOCK_SIZE) when L > 0 the last section of a binary is
incomplete.
The user application defines the subset.
Note: It is possible to define several subsets.
The STL implements a test of the flash memory with the following principles (based on actual content of the user
configuration structures):
• Tests are performed on sections of one or more subsets defined by the user application.
• Tests are performed either in a row (one shot) or partially in a single atomic step for a number of sections
defined by the user application.
• Test results are based on a CRC comparison between the computed CRC value (calculated during test
execution) and an expected CRC value (calculated before software binary flashing).
The mandatory steps (for the user application) to perform flash memory tests are:
• Test initialization
• Configuration of one or more subsets
• Execution of the test.
Once all subsets are tested, the user needs to reset the flash-memory test module to perform the test again.
In the case of an STL_ERROR / STL_FAILED test result, the test module is stuck at the failed memory subset. In
this case, deinitalize, initialize and reconfigure the flash prior running the test again.
Program area
...
Section 3
Section 2
Section 1
CRC area
DT49041V2
Flash memory section (1 Kbyte)
Figure 4. Flash memory test: CRC use cases versus program areas
Example Example Example Example
1 3 CRCs_2@ = CRC_START@ + (((User
2 4
ROM_END@ Program 2 start @ - ROM_START@)/
CRCs_3
CRC area CRCs
CRCs CRCs_2 (section size))*4 bytes)
CRCs CRCs
CRCs
CRCs_1
CRC_START@
Flash section
User
program
3 Color legend
User program
User
program
1
ROM_START@
DT49603V2
User programs always start
at the beginning of a section
Principles
The RAM test concerns the embedded SRAM memories of STM32G0 Series.
The following structures must be respected to provide correct configuration of the RAM test.
• Block: a contiguous area of 16 bytes (RAM_BLOCK_SIZE), hard coded by the STL (no link with the
memory physical sectors).
• Section: a contiguous area of 128 bytes (RAM_SECTION_SIZE), hard coded by the STL.
• Subset: a contiguous area, with the size being a multiple of two blocks and with a 32-bit aligned start
address. A subset size is not necessarily a multiple of the section size, because the last part of a subset
can be less than one section.
• Subset size = N * RAM_SECTION_SIZE + 2 * M * RAM_BLOCK_SIZE,
where:
– N is an integer ≥ 0
– M is an integer 0 ≤ M < 4, when M > 0, the size of the last partial subset not aligned with section size.
The user application defines the subset.
Note: It is possible to define several subsets.
The STL implements a RAM memory test with the following principles (based on actual content of the user
configuration structures):
• RAM tests are performed on RAM blocks defined by the user application
• RAM tests are performed either in a row (one shot), or partially in a single atomic step for a number of
sections defined by the user application
• The test implementation is based on the March C- algorithm
The mandatory steps (for the user application) to perform RAM tests are:
• Initialization of RAM test
• Configuration of one or more RAM subsets
• Execution of the RAM test
Once all subsets are tested, the application must reset the RAM test module in order to perform the test again.
In the case of an STL_ERROR / STL_FAILED test result, the test module is stuck in the failed memory subset. In
this case, deinitialize, initialize and reconfigure the RAM prior to running the test again.
RAM_END@
DT49050V1
RAM_START@
Tested
Conditions Result in μs
module
stl_user_param_template.o - 5 44
stl_user_param_template.o - 5 44
1. When the software CRC calculation is applied, there are less code / functions compiled (the CRC hardware initialization is
missing), consequently the object code size is reduced compared to the hardware CRC.
Duration (max)
Tested module Comments
in μs
1. Number of RAM blocks (multiple of two RAM_BLOCK_SIZE is required) involved with each RAM test execution depends on
content of user structures (size of defined subset(s) versus atomic step – see Section 4.1.4 RAM tests)
4.3.1 Privileged-level
The CPU TM7 and the RAM TM must be executed with privileged-level, in order to be able to modify certain core
registers (for example the PRIMASK register).
When the STL disables STM32 interrupts, and Cortex® exceptions with configurable priority, remember that an
Arm® Cortex® escalation to HardFault might occur. In this case, the HardFault handler is called instead of the fault
handler.
By default, the STM32 interrupts and Cortex® exceptions with configurable priority are masked during the CPU
TM7 except if the user application activates STL_ENABLE_IT (see Section 5.5.2 Steps to build an application
from scratch).
If the STL_ENABLE_IT flag is activated, the correct STL CPU TM7 behavior is not guaranteed. This could lead
the STL to generate false test error reporting or not to detect hardware failures.
By default, the STM32 interrupts and Cortex® exceptions with configurable priority are masked during the RAM
March C- tests, except if the user application activates STL_ENABLE_IT (see Section 5.5.2 Steps to build an
application from scratch).
If the STL_ENABLE_IT flag is activated:
• The correct STL RAM test behavior is not guaranteed, as the application may overwrite the STL-tested
RAM content during its interrupt treatment. This could lead the STL to generate false RAM test error
reporting.
• The behavior of the user application software can be compromised. Wrong data may be read or used from
RAM locations that are being modified by the STL March C- test.
4.3.6 DMA
The application must manage the DMA to avoid unwanted accesses to the RAM bank during the STL March C-
test. In this case:
• DMA writes can disturb the STL test causing false error reporting
• DMA reads can return wrong data due to STL overwrites to DMA dedicated RAM sections.
.rodata :
{
……
} >ROM
Note: Usually the default configuration locates “read only” data in flash memory.
5 Package description
This section details the X-CUBE-CLASSB-G0 expansion package content and its correct use.
5.2 Architecture
The components of the X-CUBE-CLASSB-G0 expansion package are illustrated in Figure 6.
Drivers
DT49051V1
Legend:
STL
User
5.2.3 STL
A significant part of the STL, available at middleware level, is a black box that manages the software-based
diagnostic test. It is independent from the HAL, BSP, and CMSIS, even if the STL integration example relies on
some HAL drivers.
STL integration
example
MS70112V1
5.4 APIs
5.4.1 Compliance
Interface compliance
The library part of the STL is not delivered in source code. This library has been compiled with IAR Embedded
Workbench® for Arm v9.20.1. The compilation is done with --aeabi and --guard_calls compilation options to
fulfill AEABI compliance as described in “AEABI compliance” of the EWARM help section.
To comply with the IEC 61508 functional safety standard, the industrial version of the STL certified by TUV was
compiled by safety certified EWARMFS version of the IAR™ compiler exclusively. Sources of this STL are based
on the industrial version of the library and have been adapted to comply with the IEC 60730-1 standard and
recompiled by the latest available version of the EWARM compiler. This library can be compiled by whatever
standard version of the EWARM compiler not specifically safety certified.
Safety guidelines
To fulfill the safety guidelines compliance as described in the IAR Embedded Workbench® safety guide (advice
2.1-1, 2.2-5, 2.4-1a and 5.4-3) and the Keil® safety manual (§4.9.2), the compliance is done with --strict,
--remarks, --require_prototypes and -- no_unaligned_access compilation options.
Library compliance
The library part of the STL (not delivered in source code) is compliant with C standard library ISO C99.
It has been compiled with the IAR™ option. Language C dialect = C99.
5.4.2 Dependency
The STL library calls the memset standard C library function.
Furthermore, the IAR™ EWARM toolchain compiler is used to compile the STL library. This compiler may,
under some circumstances, call the following standard C library functions: memcpy, memset, and memclr. This
behavior is intrinsic to the IAR™ EWARM toolchain compiler. It is not possible to disable or avoid it.
As a result, when linking the STL library the user must ensure that these standard C library functions are defined.
The user can use either the functions provided by the toolchain or the user ones.
5.4.3 Details
Detailed technical information about the available APIs can be found in Section 7.2 User APIs, where the
functions and parameters are described.
Note: The codes definitions are given in the stl_user_api.h file, in the case of a defensive programing failure, the
DEF_PROG_OFFSET is added to the module code.
DT61663V1
Figure 9. CRC tool command line
typedef enum
{
STL_PASSED = STL_PASSED_DEF, /* Test passed. For Flash/RAM, test is passed and end of
configuration is also reached */
STL_PARTIAL_PASSED = STL_PARTIAL_PASSED_DEF, /* Used only for RAM and Flash testing.
Test passed, But end of Flash/RAM
configuration not yet reached */
STL_FAILED = STL_FAILED_DEF, /* Hardware error detection by Test Module */
STL_NOT_TESTED = STL_NOT_TESTED_DEF, /* Initial value after a SW init, SW config,
SW reset, SW de-init or value when Test Module
not executed */
STL_ERROR = STL_ERROR_DEF /* Test Module unsuccessfully executed (defensive programing
check failed) */
} STL_TmStatus_t; /* Type for the result of a Test Module */
typedef enum
{
STL_CPU_TM1L_IDX = 0U, /* CPU Arm Core Test Module 1L index */
STL_CPU_TM7_IDX, /* CPU Arm Core Test Module 7 index */
STL_CPU_TMCB_IDX, /* CPU Arm Core Test Module Class B index */
STL_CPU_TM_MAX /* Number of CPU Arm Core Test Modules */
} STL_CpuTmxIndex_t; /* Type for index of CPU Arm Core Test
Modules */
typedef struct
{
STL_MemSubset_t *pSubset; /* Pointer to the Flash or RAM subsets to test */
uint32_t NumSectionsAtomic; /* Number of Flash or RAM sections to be tested
during an atomic test */
} STL_MemConfig_t; /* Type used to fully define Flash or RAM test configuration */
typedef struct
{
STL_TmStatus_t aCpuTmStatus[STL_CPU_TM_MAX]; /* Array of forced status value
for CPU Test Modules */
STL_TmStatus_t FlashTmStatus; /* Forced status value for Flash Test Module */
STL_TmStatus_t RamTmStatus; /* Forced status value for RAM Test Module */
} STL_ArtifFailingConfig_t; /* Type used to force Test Modules status to a specific
value for each STL Test Module */
7.2.1.1 STL_SCH_Init
Description: initializes the scheduler. It can be used at any time to reinitialize the scheduler (it resets all tests).
Declaration: STL_Status_t STL_SCH_Init(void).
Additional information: there is no specific CPU initialization function for CPU test modules.
Note: This function uses hardware CRC as explained in Section 4.3.3 CRC resources.
7.2.2.1 STL_SCH_RunCpuTMx
Description: runs one of the CPU test modules.
Declaration: STL_Status_t STL_SCH_RunCpuTMx(STL_TmStatus_t *pSingleTmStatus) where TMx
can be one of TM1L, TM7 or TMCB.
Parameters
Allowed states
Value Comments
STL_PASSED -
STL_FAILED -
Source of defensive
programming error:
• STL internal data
STL_OK Function successfully executed corrupted CPU_TMx_CONFIGURED
• Software is not
STL_ERROR executed with
privileged level for CPU
TM7
• Software is not
executed in thread
mode for CPU TM7
Possible source of defensive
programming error:
STL_KO Not relevant Value must not be used No state change
• pSingleTmStatus = NULL
• STL internal data corrupted
7.2.3.1 STL_SCH_InitFlash
Description: initializes flash memory test.
Declaration: STL_Status_t STL_SCH_InitFlash(STL_TmStatus_t *pSingleTmStatus)
Parameters
Allowed states
Value Comments
FLASH_IDLE
FLASH_INIT *pSingleTmStatus Caution
FLASH_CONFIGURED
7.2.3.2 STL_SCH_ConfigureFlash
Description: configures the flash memory test.
Declaration: STL_Status_t STL_SCH_ConfigureFlash(STL_TmStatus_t *pSingleTmStatus,
STL_MemConfig_t *pFlashConfig)
Parameter
Allowed states
Value Comments
STL_NOT_TESTED - FLASH_CONFIGURED
Possible source of
defensive programming
error:
STL_OK Function successfully executed • State not allowed
STL_ERROR No state change
• Wrong configuration
detected
• STL internal data
corrupted
Possible source of defensive
programming error:
STL_KO • pSingleTmStatus = NULL Not relevant Value must not be used No state change
• pFlashConfig = NULL
• STL internal data corrupted
Additional information: in the case of a return value set to STL_KO or *pSingleTmStatus set to STL_ERROR,
the flash memory configuration is not applied.
7.2.3.3 STL_SCH_RunFlashTM
Description: runs flash memory test.
Declaration: STL_Status_t STL_SCH_RunFlashTM(STL_TmStatus_t *pSingleTmStatus)
Parameters
Allowed states
Value Comments
STL_PASSED - FLASH_CONFIGURED
STL_PARTIAL_PASSED - FLASH_CONFIGURED
STL_FAILED - FLASH_CONFIGURED
All subsets are already
STL_NOT_TESTED FLASH_CONFIGURED
tested
STL_OK Function successfully executed Possible source of
defensive programming
error:
• State not allowed
STL_ERROR No state change
• Configuration
corrupted
• STL internal data
corrupted
Possible source of defensive
programming error:
STL_KO • pSingleTmStatus = Not relevant Value must not be used No state change
NULL
• STL internal data corrupted
7.2.3.4 STL_SCH_ResetFlash
Description: resets flash memory test.
Declaration: STL_Status_t STL_SCH_ResetFlash(STL_TmStatus_t *pSingleTmStatus)
Parameters
Allowed states
Value Comments
Configuration successfully
STL_NOT_TESTED FLASH_CONFIGURED
applied
Possible source of
defensive programming
error:
STL_OK Function successfully executed
• State not allowed
STL_ERROR No state change
• Configuration
corrupted
• STL internal data
corrupted
Possible source of defensive
programming error:
STL_KO Not relevant Value must not be used No state change
• pSingleTmStatus = NULL
• STL internal data corrupted
Additional information
• Once all subsets are tested, the user needs to reset the test module to perform the flash memory test
again.
• In the case of a return value set to STL_KO or *pSingleTmStatus set to STL_ERROR, the flash
memory reset is not applied.
7.2.3.5 STL_SCH_DeInitFlash
Description: deinitializes flash memory test – used only for single test.
Declaration: STL_Status_t STL_SCH_DeInitFlash(STL_TmStatus_t *pSingleTmStatus)
Parameters
Allowed states
Value Comments
FLASH_IDLE
FLASH_INIT *pSingleTmStatus See Caution
FLASH_CONFIGURED
7.2.4.1 STL_SCH_InitRam
Description: initializes the RAM test.
Declaration: STL_Status_t STL_SCH_InitRam(STL_TmStatus_t *pSingleTmStatus).
Parameters
Allowed states
Value Comments
RAM_IDLE
RAM_INIT *pSingleTmStatus See Caution
RAM_CONFIGURED
Parameter
Allowed states
Value Comments
STL_NOT_TESTED - RAM_CONFIGURED
Possible source
of defensive
programming error:
• State not
STL_OK Function successfully executed allowed
STL_ERROR No state change
• Wrong
configuration
detected
• STL internal
data corrupted
Possible source of defensive
programming error:
Value must not be
STL_KO • pSingleTmStatus = NULL Not relevant No state change
used
• pRamConfig = NULL
• STL internal data corrupted
Additional information: in the case of a return value set to STL_KO or *pSingleTmStatus set to STL_ERROR,
the RAM configuration is not applied.
7.2.4.3 STL_SCH_RunRamTM
Description: runs the RAM test.
Declaration: STL_Status_t STL_SCH_RunRamTM(STL_TmStatus_t *pSingleTmStatus)
Parameters
Allowed states
Value Comments
STL_PASSED - RAM_CONFIGURED
STL_PARTIAL_PASS
- RAM_CONFIGURED
ED
STL_FAILED - RAM_CONFIGURED
All subsets are
STL_NOT_TESTED RAM_CONFIGURED
already tested
STL_OK Function successfully executed Possible source
of defensive
programming error:
• State not
STL_ERROR allowed No state change
• Configuration
corrupted
• STL internal
data corrupted
Possible source of defensive
programming error: Value must not be
STL_KO Not relevant No state change
• pSingleTmStatus = NULL used
• STL internal data corrupted
Parameters
Allowed states
Value Comments
Configuration
STL_NOT_TESTED RAM_CONFIGURED
successfully applied
Possible source
of defensive
programming error:
STL_OK Function successfully executed • State not
STL_ERROR allowed No state change
• Configuration
corrupted
• STL internal
data corrupted
Possible source of defensive
programming error: Value must not be
STL_KO Not relevant No state change
• pSingleTmStatus = NULL used
• STL internal data corrupted
Additional information
• Once all subsets are tested, the user needs to reset the test module to perform the RAM test again.
• In the case of a return value set to STL_KO or *pSingleTmStatus set to STL_ERROR, the RAM reset is
not applied.
7.2.4.5 STL_SCH_DeInitRam
Description: deinitializes the RAM test.
Declaration: STL_Status_t STL_SCH_DeInitRam(STL_TmStatus_t *pSingleTmStatus)
Parameters
Allowed states
Value Comments
RAM_IDLE
RAM_INIT *pSingleTmStatus See Caution
RAM_CONFIGURED
7.2.5.1 STL_SCH_StartArtifFailing
Description: sets artificial-failing configuration and starts artificial-failing feature.
Declaration: STL_Status_t STL_SCH_StartArtifFailing(const STL_ArtifFailingConfig_t
*pArtifFailingConfig)
Parameters
Allowed states
Value Comments
CPU TMx:
• CPU_TMx_CONFIGURED
Flash TM:
• FLASH_IDLE
• FLASH_INIT *pArtifFailingConfig No state change
• FLASH_CONFIGURED
RAM TM
• RAM_IDLE
• RAM_INIT
• RAM_CONFIGURED
STL_Status_t
Comments Output Comments
return value
Additional information: All the following API calls are executed normally except if the STL_Status_t return value is
set to STL_OK, the test module status (*pSingleTmStatus, *pTmListStatus) is forced to a configured value.
7.2.5.2 STL_SCH_StopArtifFailing
Description: stops the artificial-failing feature.
Declaration: STL_Status_t STL_SCH_StopArtifFailing(void)
Parameters
Allowed states
Value Comments
CPU TMx:
• CPU_TMx_CONFIGURED
Flash TM:
• FLASH_IDLE
• FLASH_INIT
No input parameter No state change
• FLASH_CONFIGURED
RAM TM
• RAM_IDLE
• RAM_INIT
• RAM_CONFIGURED
STL_SCH_Init()
SCH_IDLE
STL_SCH_Init()
CPU_TMx_C
ONFIGURED
SW reset
Return of STL_SCH_RunCpuTMx()
STL_SCH_RunCpuTMx()
CPU_TMx_
RUNNING
DT69947V1
STL_SCH_InitFlash()
FLASH_IDLE STL_SCH_ConfigureFlash()
STL_SCH_Init() FLASH_INIT
STL_SCH_DeInitFlash()
STL_SCH_InitFlash()
SCH_IDLE
STL_SCH_ResetFlash()(1)
STL_SCH_DeInitFlash() FLASH_
CONFIGURED
STL_SCH_Init()
Return of STL_SCH_RunFlashTM()
SW reset
STL_SCH_RunFlashTM()
FLASH_R
UNNING
DT69948V1
Note (1): Once all subsets are tested, the user needs to reset the flash memory test module to perform the test again.
STL_SCH_DeInitRam()
STL_SCH_Init() STL_SCH_InitRam()
STL_SCH_Init()
STL_SCH_InitRam()
RAM_IDLE STL_SCH_ConfigureRam()
STL_SCH_Init() RAM_INIT
STL_SCH_DeInitRam()
STL_SCH_InitRam()
SCH_IDLE
STL_SCH_DeInitRam() RAM_
CONFIGURED
STL_SCH_Init()
STL_SCH_ResetRam()(1)
Return of STL_SCH_RunRamTM()
SW reset
STL_SCH_RunRamTM()
RAM_
RUNNING
DT69949V1
Note (1): Once all subsets are tested, the user needs to reset the RAM test module to perform the test again.
Later, at run time, the order of the tests can be changed and executed in more relaxed way. The memory regions
under tests can be reduced. The test process can even be dynamically modified with prior focus on those areas
where just safety related code and data are stored. This is especially the case while considering other factors,
focusing on those areas where just safety related code and data is stored especially:
• available application process safety time
• system overall performance
• concrete status of the application
• and so on.
The customization depends upon the STM32 product and the user choice.
/* TM RAM Backup Buffer configuration */
…..
/* User shall locate the buffer in RAM */
/* The RAM backup buffer is placed in "backup_buffer_section". */
/* "backup_buffer_section" section is defined in scatter file */
User STL_SCH
STL_SCH_Init
STL_OK
STL_SCH_InitFlash (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_NOT_TESTED
STL_SCH_InitRam (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_NOT_TESTED
STL_SCH_ConfigureFlash (*p_SingleTmStatus, *pFlashConfig)
*pFlashConfig: Flash memory subsets tested in one shot
STL_OK
pSingleTmStatus =
STL_NOT_TESTED
STL_SCH_ConfigureRam (*p_SingleTmStatus, *pRamConfig)
*pRamConfig: RAMsubsets tested in two shots
STL_OK
pSingleTmStatus =
STL_NOT_TESTED
STL_SCH_RunCpuTM1L (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_ PASSED
STL_SCH_RunCpuTMCB (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_ PASSED
STL_RunFlashTM (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_PASSED
STL_SCH_RunRamTM (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_PARTIAL_PASSED
STL_SCH_RunRamTM (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_PASSED
STL_SCH_InitFlash (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_NOT_TESTED
STL_SCH_InitRam (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_NOT_TESTED
STL_SCH_DeInitFlash (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_NOT_TESTED
STL_SCH_DeInitRam (*p_SingleTmStatus)
STL_OK
pSingleTmStatus =
STL_NOT_TESTED
DT70600V1
Legend:
Test status
STL
User
7.7.3
Init STL
STL_SCH_RunFlashTM
(*pSingleTmStatus)
Main scheduler
...
STL_SCH_RunFlashTM
*pSingleTmStatus =
(*pSingleTmStatus)
Test example figures
STL_PARTIAL_PASSED
Main scheduler
...
...
STL_SCH_RunFlashTM
First subset
*pSingleTmStatus =
K sections (*pSingleTmStatus)
STL_PARTIAL_PASSED
Main scheduler
Flash tests module
STL_OK
...
Main scheduler
...
STL_SCH_RunFlashTM
*pSingleTmStatus =
(*pSingleTmStatus)
Main scheduler
STL_PARTIAL_PASSED
K sections
Flash tests module
...
Main scheduler STL_OK
K sections
Last subset
...
K sections STL_SCH_RunFlashTM
*pSingleTmStatus =
(*pSingleTmStatus)
Main scheduler
STL_PARTIAL_PASSED
...
STL_SCH_RunFlashTM
= STL_PASSED
(*pSingleTmStatus)
*pSingleTmStatus
Main scheduler
STL_SCH_ResetFlash
(*pSingleTmStatus)
*pSingleTmStatus =
STL_NOT_TESTED
Main scheduler
STL_SCH_RunFlashTM
(*pSingleTmStatus)
Legend:
Main scheduler
*pSingleTmStatus =
STL_NOT_TESTED
Test status
UM3083
page 47/61 UM3083 - Rev 1
STL
User
Init STL
STL_SCH_RunRamTM
(*pSingleTmStatus)
Main scheduler
STL_SCH_RunRamTM
*pSingleTmStatus =
(*pSingleTmStatus)
STL_PARTIAL_PASSED
Main scheduler
...
...
STL_SCH_RunRamTM
First subset
*pSingleTmStatus =
N sections (*pSingleTmStatus)
STL_PARTIAL_PASSED
Main scheduler
RAM tests module
STL_OK
...
Main scheduler
...
STL_SCH_RunRamTM
*pSingleTmStatus =
(*pSingleTmStatus)
Main scheduler
STL_PARTIAL_PASSED
N sections
... RAM tests module
N sections
Last subset
...
N sections STL_SCH_RunRamTM
*pSingleTmStatus =
(*pSingleTmStatus)
Main scheduler
STL_PARTIAL_PASSED
STL_SCH_RunRamTM
= STL_PASSED
(*pSingleTmStatus)
*pSingleTmStatus
Main scheduler
STL_SCH_ResetRam
(*pSingleTmStatus)
*pSingleTmStatus =
STL_NOT_TESTED
Main scheduler
STL_SCH_RunRamTM
Legend:
(*pSingleTmStatus)
Test status
Main scheduler
*pSingleTmStatus =
STL_NOT_TESTED
UM3083
UM3083
STL: execution timing details
STL_SCH_InitFlash() 9 9 -
STL_SCH_ConfigureFlash() 13 13 -
STL_SCH_InitRam() 9 9 -
STL_SCH_ConfigureRam() 13 13 -
STL_SCH_RunCpuTM1L() 87 87 -
STL_SCH_RunCpuTM7()(2) 34 34 -
STL_SCH_RunCpuTMCB() 12 12 -
1. Test duration increased because of the CRC algorithm (see Section 4.1.1 Scheduler principle).
2. Default configuration: STL_ENABLE_IT and STL_DISABLE_RAM_BCKUP_BUF are not enabled.
The user must focus on all the remaining required tests covering application specific MCU parts not included in
the ST firmware library:
• Test of analog parts (ADC/DAC, multiplexer)
• Test of digital I/O
• External addressing
• External communication
• Timing and interrupts
• System clock frequency measurement.
Note: The clock frequency measurement is not an integrated part of the STL package. The clock testing module
is provided as open source within STL integration example to demonstrate the capability of implementing
additional user defined testing modules which can be included at the STL flow. For more details refer to
Section 9.5 Extension capabilities STL library.
A valid solution for these components is strongly dependent on application and device-peripheral capability. The
application must follow as precisely as possible the suggested testing principles from the very early stages of its
design.
Very often this method leads to redundancy at both hardware and software levels.
Hardware methods can be based on:
• Multiplication of inputs and/or outputs
• Reference point measurement
• Loop-back read control at analog or digital outputs such as DAC, PWM, GPIO
• Configuration protection.
Software methods can be based on:
• Repetition in time, multiple acquisitions, multiple checks, decisions, or calculations made at different times
or performed by different methods
• Data redundancy (data copies, parity check, error correction/detection codes, checksum, protocol)
• Plausibility check (valid range, valid combination, expected change, or trend)
• Periodicity and occurrence checks (flow and occurrence in time controls)
• Periodic checks of correct configuration (for example, read back the configuration registers).
Internal reference voltage and temperature sensor (VBAT for some devices)
• Ratio between these signals can be verified within the allowed ranges.
• Additional testing can be performed where the VDD voltage is known.
ADC clock
Measurement of the ADC conversion time (by timers) can be used to test the independent ADC clock
functionality.
Comparator functionality
Comparison between known voltage and DAC output or internal reference voltage can be used for testing
comparator output on another comparator input.
Analog signal disconnection can be tested by pull-down or pull-up activation on a tested pin and comparing this
signal with the DAC voltage as reference on another comparator input.
Operational amplifier
Functionality can be tested forcing (or measuring) a known analog signal to the operational amplifier (OPAMP)
input pin, and internally measuring the output voltage with the ADC. The input signal to the OPAMP can be also
measured by ADC (on another channel).
9.3 Interrupts
Occurrence in time and periodicity of events must be checked. Different methods can be used; one of them
uses a set of incremental counters where every interrupt event increments a specific counter. The values in the
counters are then cross-checked periodically with other independent time bases. The number of events occurred
within the last period depends upon the application requirements.
The configuration lock feature can be used to secure the timer register settings with three levels controlled by the
TIMx_BDTR register. Unused interrupt vectors must be diverted into a common error handler. Polling is preferable
for nonsafety relevant tasks if possible to simplify an application interrupt scheme.
9.4 Communication
Data exchange during communication sessions must be checked while including redundant information in the
data packets. Parity, sync signals, CRC check sums, block repetition, or protocol numbering can be used for this
purpose. Robust application software protocol stacks like TCP/IP give higher level of protection, if necessary.
Periodicity and occurrence in time of the communication events together with protocol error signals has to be
checked permanently.
The user can find more information and methods in product-dedicated safety manuals.
The parameter that is passed during this function call acts as a pointer to the clock module measurement status,
and the function itself provides a STL_KO vs STL_OK return status as well as do the regular STL modules if
defensive programing fails. If the clock measurement hardware is active and the new period value updated by the
last measurement cycle (set to 8 consecutive LSI periods) is found at the expected interval (defined by macros
CLK_LimitLow and CLK_LimitHigh), the module measurement status value is changed into STL_PASSED.
If not it is set to STL_FAILED as per the regular API modules. This is also the case when artificial failing of the
module is invoked.
In a similar way, the user can integrate the following modules. For example, checking of stack pointer validity or
implementing watchdog testing and servicing is no longer included at this new package by default. The source
code of these tests is available in older versions of this library see Section 1.2 Reference documents. Refer
to Section 1.2 Reference documents for additional information about the commonly recognized safety methods
that are not specifically required by the household standard. They may be useful to improve the user application
robustness.
The pivotal IEC standards are IEC 60730-1 and IEC 60335-1, harmonized with UL/CSA 60730-1 and UL/CSA
60335-1 starting from the 4th edition. Previous UL/CSA editions use references to the UL1998 standard in
addition.
The standards are updated at regular intervals. The range of overall regulations collected in the standards is
very large; the sections that concerns the requirements for software self-tests of generic parts of microcontrollers
is very specific. In most cases, the provided updates don't impact these specific parts of the standard at all.
Therefore, an obsolete certification can still comply and stay valid for newer editions of the standard.
The relevant detailed conditions required are defined in:
• Annexes Q and R of the IEC 60335-1 norm
• Annex H of the IEC 60730-1 norm.
Three classes are defined by the IEC 60730-1:2010 H.2.22 they are:
• Class A: control functions that are not intended to be relied upon for the safety of the application.
• Class B: control functions that are intended to prevent an unsafe state of the controlled equipment. Failure
of the control function does not directly lead to a hazardous situation.
• Class C: control functions that are intended to prevent special hazards such as explosion or which failure
could directly cause a hazard in the appliance.
For a programmable electronic component applying a safety protection function, the IEC 60335-1 standard
requires incorporation of software measures to control fault and error conditions specified in tables R.1 and R.2:
• Table R.1 summarizes general conditions comparable with requirements given for Class B level
• Table R.2 summarizes specific conditions comparable with requirements given for Class C level.
Requirements for Class B level software, which is the subject of this user manual, are defined to prevent hazards
if another fault occurs elsewhere in the appliance. In this case, the self-test software is run on the appliance
after a failure. An accidental software fault occurring during a safety-critical routine execution does not necessarily
result in a hazard due to another applied redundant software procedure or hardware protection function required
at this level.
There is no such hardware protection required in Class C level counting that whatever fault at safety-critical
software can result in a potential hazard. To comply with this level, more robust testing is required than the one
usually applicable to standard industrial microcontrollers like the STM32. An acceptable solution usually leads to
the implementation of specific hardware redundancy at system level, like dual channel structures.
For more information on more stringent test methods, refer to the industrial documentation [1].
IEC 60730-1 defines the set of applicable architectures acceptable for the design of Class B control functions:
• Single channel with functional test. A single CPU executes the software control functions as required. A
functional test is performed as the software starts. It guarantees that all critical features work properly.
• Single channel with periodic self-test. A single CPU executes the software control functions. Embedded
periodic tests check the various critical functions of the system without impacting the performance of the
planned control tasks.
• Dual channel (homogeneous or diverse) with comparison. The software is designed to execute control
functions (identically or differently) on two independent CPUs. Both CPUs compare internal signals for fault
detection when executing any safety-critical task.
Note: This structure is recognized to comply with Class C level also. A common principle is that whatever
method compliesy with Class C automatically complies with Class B.
An overview of the methods applied by STL and their references to the standards are listed on the table below.
The STL is focused on generic components of the microcontroller reused at all applications. The test of the
other parts is under the end-user responsibility as their testing is mostly application specific and can be achieved
effectively at the planning stage of the system design. Refer to Section 9 Application-specific tests not included in
ST firmware self-test library for more information on how to handle these application-specific tests.
Table 35. IEC 60335-1 components covered by the X-CUBE-CLASSB library by methods recognized by IEC-60730-1
References to
Component of Table R.1 (IEC Safety method applied at
Class B IEC 60730-1: Fault/error Note
60335-1: Annex R) X-CUBE-CLASSB
Annex H)
1.2 Instruction
decoding and N/A Not required for Class B
execution
1. CPU
N/A Logical and time slot
1.3 Program H.2.18.10.2
X Stuck at End-user responsibility program sequence monitoring,
counter H.2.18.10.4
implementation of watchdogs
1.4 Addressing N/A Not required for Class B
1.5 Data
path instruction N/A Not required for Class B
decoding
Handshake of results is
No interrupt
H.2.18.10.4 applied at the interrupt End-user responsibility for the
or too
2. Interrupt handling and execution X associated with a clock other interrupts implemented at
H2.18.18 frequent
cross-check measurement application
interrupts
module
Periodic run of clock
cross-check module.
Clock cross-check
Added at open source
H.2.18.10.1 Wrong measurement done between
3. Clock X format as a user
H.2.18.10.4 frequency two independent clock sources
specific test module within
(system clock and LSI)
the firmware integration
example
H.2.19.3.1
4.1 Invariable All single bit Periodic execution of the ECC-enable under end-user
X H.2.19.3.2
memory faults STL FlashTM test module responsibility
H.2.19.8.2
4.2. Variable H.2.19.6 Periodic execution of the ECC-enable under end-user
X DC fault
4. Memory memory H.2.19.8.2 STL RamTM test module responsibility
4.3 Addressing
(relevant for Tested indirectly by execution
X H.2.19.8.2 Stuck at -
variable and of the applied memory test
invariable memory) modules
5.1 Data X H.2.19.8.2 Stuck at - ECC-enable under end-user
5. Internal
Wrong responsibility
data path 5.2 Addressing X H.2.19.8.2 -
address
N/A
6. External communication X - - End-user responsibility -
N/A
7. I/O periphery X - - End-user responsibility -
Revision history
Table 36. Document revision history
Glossary
AEABI Arm® embedded application binary interface SDK software development kit
Class B
middle level of regulations targeting safety for home
appliances (UL/CSA/IEC 60730-1/60335-1)
LL low layer
Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Purpose and scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 STM32Cube overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 What is STM32Cube?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 How does this software complement STM32Cube? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 STL overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.1 Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Supported products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 STL description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.1 STL functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1.1 Scheduler principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1.2 CPU Arm® core tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.3 Flash memory tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.4 RAM tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 STL performance data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.1 STL execution timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.2 STL code and data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.3 STL stack usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.4 STL heap usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.5 STL interrupt masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 STL user constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.1 Privileged-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.2 RCC resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.3 CRC resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.4 Interrupt management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3.5 How STL masks the interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.6 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.7 RAM backup buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.8 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.9 Processor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 End-user integration tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4.1 Test 1: correct STL execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4.2 Test 2: correct STL error-message processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 Package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
List of tables
Table 1. Applicable product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STL return information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. STL execution timings, clock at 56 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. STL code size and data size (in bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. STL maximum interrupt masking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. STL_SCH_Init input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. STL_SCH_Init output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. STL_SCH_RunCpuTMx input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. STL_SCH_RunCpuTMx output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. STL_SCH_InitFlash input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. STL_SCH_InitFlash output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. STL_SCH_ConfigureFlash input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. STL_SCH_ConfigureFlash output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. STL_SCH_RunFlashTM input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. STL_SCH_RunFlashTM output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. STL_SCH_ResetFlash input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. STL_SCH_ResetFlash output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 18. STL_SCH_DeInitFlash input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. STL_SCH_DeInitFlash output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. STL_SCH_InitRam input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 21. STL_SCH_InitRam output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. STL_SCH_ConfigureRam input information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23. STL_SCH_ConfigureRam output information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. STL_SCH_RunRamTM input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 25. STL_SCH_RunRamTM output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 26. STL_SCH_ResetRam input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 27. STL_SCH_ResetRam output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 28. STL_SCH_DeInitRam input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 29. STL_SCH_DeInitRam output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 30. STL_SCH_StartArtifFailing input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 31. STL_SCH_StartArtifFailing output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 32. STL_SCH_StopArtifFailing input information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 33. STL_SCH_StopArtifFailing output information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 34. Integration tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 35. IEC 60335-1 components covered by the X-CUBE-CLASSB library by methods recognized by IEC-60730-1 . . . . 53
Table 36. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
List of figures
Figure 1. STL architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Single test mode architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Flash memory test: CRC principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Flash memory test: CRC use cases versus program areas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. RAM test: usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Software architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Project file structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. IAR™ post-build actions screenshot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. CRC tool command line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. STM32 Nucleo board example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. State machine diagram - CPU test APIs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 12. State machine diagram - Flash memory test APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. State machine diagram - RAM test APIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 14. Single testing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 15. Flash memory single test example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16. RAM single test example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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