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AD8016

The AD8016 is a low power, high output current xDSL line driver that features full ADSL CO performance from ±12V supplies. It provides 12.5mA of total supply current and a reduced 4.5mA keep-alive current. The device has a high output voltage and current capability of 600mA and 40V peak-to-peak. It offers low distortion down to -75dBc at 1MHz and high speed operation with a 78MHz bandwidth.

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0% found this document useful (0 votes)
60 views20 pages

AD8016

The AD8016 is a low power, high output current xDSL line driver that features full ADSL CO performance from ±12V supplies. It provides 12.5mA of total supply current and a reduced 4.5mA keep-alive current. The device has a high output voltage and current capability of 600mA and 40V peak-to-peak. It offers low distortion down to -75dBc at 1MHz and high speed operation with a 78MHz bandwidth.

Uploaded by

Telo Godhog
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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a Low Power, High Output Current

xDSL Line Driver


AD8016
FEATURES PIN CONFIGURATION
xDSL Line Driver that Features Full ADSL CO (Central 20-Lead PSOP3 24-Lead Batwing
Office) Performance on ⴞ12 V Supplies (RP-20) (RB-24)
Low Power Operation +V2 +V1 1 24 +V2
+V1 1 20
ⴞ5 V to ⴞ12 V Voltage Supply VOUT1 2 19 VOUT2 VOUT1 2 23 VOUT2
12.5 mA/Amp (Typ) Total Supply Current VINN1 3 18 VINN2 VINN1 3 22 VINN2
Power-Reduced Keep-Alive Current of 4.5 mA/Amp VINP1 4 17 VINP2 VINP1 4 21 VINP2
High Output Voltage and Current Drive NC 5 16 NC AGND 5 20 AGND
AD8016
IOUT = 600 mA NC 6 15 NC AGND 6
AD8016 19 AGND
40 V p-p Differential Output Voltage RL = 50 ⍀, NC 7 14 NC AGND 7 18 AGND
V S = ⴞ12 V PWDN0 8 13 PWDN1 AGND 8 17 AGND
Low Single Tone Distortion DGND 9 12 BIAS PWDN0 9 16
PWDN1
–75 dBc @ 1 MHz SFDR, RL = 100 ⍀, VO = 2 V p-p –V1 10 11 –V2 DGND 10 15
BIAS

MTPR = –75 dBc, 26 kHz to 1.1 MHz, ZLINE = 100 ⍀, –V1 11 14


NC = NO CONNECT –V2
NC 12 13 NC
PLINE = 20.4 dBm
High Speed NC = NO CONNECT

78 MHz Bandwidth (–3 dB), G = +5 28-Lead HTSSOP


40 MHz Gain Flatness (RE-28)
1000 V/␮s Slew Rates
NC 1 28 NC
NC 2 27 NC
NC 3 26 NC

PRODUCT DESCRIPTION +VIN2 4 25 NC


–VIN2 5 24 PWDN1
The AD8016 high output current dual amplifier is designed
VOUT2 6 23 BIAS
for the line drive interface in Digital Subscriber Line systems
+V2 7 22 –V2
such as ADSL, HDSL2, and proprietary xDSL systems. The AD8016ARE
+V1 8 21 –V1
drivers are capable, in full-bias operation, of providing 24.4 dBm VOUT1 9 20 DGND
output power into low resistance loads, enough to power a –VIN1 10 19 NC
20.4 dBm line, including hybrid insertion loss. +VIN1 11 18 PWDN0
NC 12 17 NC
NC 13 16 NC
NC 14 15 NC

NC = NO CONNECT

–75dBc
The AD8016 is available in a low cost 24-lead SOIC, a ther-
10dB/DIV

mally enhanced 20-lead PSOP, and a 28-lead HTSSOP with


an exposed leadframe (ePAD). Operating from ±12 V supplies,
the AD8016 requires only 1.5 W of total power dissipation
(refer to the Power Dissipation section for details) while driving
20.4 dBm of power downstream using the xDSL hybrid in Figure
33a and Figure 33b. Two digital bits (PWDN0, PWDN1) allow
the driver to be capable of full performance, an output “keep-alive
state,” or two intermediate bias states. The “keep-alive” state
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY – kHz
biases the output transistors enough to provide a low imped-
ance at the amplifier outputs for back termination.
Figure 1. Multitone Power Ratio; VS = ± 12 V, 20.4 dBm
Output Power into 100 Ω, Downstream The low power dissipation, high output current, high output voltage
swing, flexible power-down, and robust thermal packaging enable
the AD8016 to be used as the Central Office (CO) terminal driver
in ADSL, HDSL2, VDSL, and proprietary xDSL systems.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000
(@ 25ⴗC, VS = ⴞ12 V, RL = 100 ⍀, PWDN0, PWDN1 = (1, 1), TMIN = –40ⴗC,
AD8016–SPECIFICATIONS T MAX = +85ⴗC, unless otherwise noted)

Parameter Conditions Min Typ Max Unit


DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p 380 MHz
G = +5, RF = 499 Ω, VOUT < 0.5 V p-p 69 78 MHz
Bandwidth for 0.1 dB Flatness G = +5, RF = 499 Ω, VOUT = 0.2 V p-p 16 38 MHz
Large Signal Bandwidth VOUT = 4 V p-p 90 MHz
Peaking VOUT = 0.2 V p-p < 50 MHz 0.1 dB
Slew Rate VOUT = 4 V p-p, G = +2 1000 V/µs
Rise and Fall Time VOUT = 2 V p-p 2 ns
Settling Time 0.1%, VOUT = 2 V p-p 23 ns
Input Overdrive Recovery Time VOUT = 12.5 V p-p 350 ns
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended VOUT = 2 V p-p, G = +5, RF = 499 Ω
2nd Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω –75/–62 –77/–64 dBc
3rd Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω –88/–74 –93/–76 dBc
Multitone Power Ratio1 26 kHz to 1.1 MHz, ZLINE = 100 Ω,
PLINE = 20.4 dBm –75 dBc
IMD 500 kHz, ∆f = 10 kHz, RL = 100 Ω/25 Ω –84/–80 –88/–85 dBc
IP3 500 kHz, RL = 100 Ω/25 Ω 42/40 43/41 dBm
Voltage Noise (RTI) f = 10 kHz 2.6 4.5 nV/√Hz
Input Current Noise f = 10 kHz 18 21 pA√Hz
INPUT CHARACTERISTICS
RTI Offset Voltage –3.0 1.0 +3.0 mV
+Input Bias Current –45 +45 µA
–Input Bias Current –75 4 +75 µA
Input Resistance 400 kΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range –10 +10 V
Common-Mode Rejection Ratio 58 64 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Single-Ended, RL = 100 Ω –11 +11 V
Linear Output Current G = 5, RL = 10 Ω, f1 = 100 kHz,
–60 dBc SFDR 400 600 mA
Short Circuit Current 2000 mA
Capacitive Load Drive 80 pF
POWER SUPPLY
Operating Range ±3 ± 13 V
Quiescent Current PWDN1, PWDN0 = (1, 1) 12.5 13.2 mA/Amp
PWDN1, PWDN0 = (1, 0) 8 10 mA/Amp
PWDN1, PWDN0 = (0, 1) 5 8 mA/Amp
PWDN1, PWDN0 = (0, 0) 4 6 mA/Amp
Recovery Time To 95% of IQ 25 µs
Shutdown Current 250 µA Out of Bias Pin 1.5 4.0 mA/Amp
Power Supply Rejection Ratio ∆VS = ± 1 V 63 75 dB
OPERATING TEMPERATURE RANGE –40 +85 °C
NOTES
1
See Figure 43, R20, R21 = 0 Ω, R1 = open.
Specifications subject to change without notice.

–2– REV. A
(@ 25ⴗC, VS = ⴞ6 V, RL = 100 ⍀, PWDN0, PWDN1 = (1, 1), TMIN = –40ⴗC, AD8016
SPECIFICATIONS TMAX = +85ⴗC, unless otherwise noted)
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p 320 MHz
G = +5, RF = 499 Ω, VOUT < 0.5 V p-p 70 71 MHz
Bandwidth for 0.1 dB Flatness G = +5, RF = 499 Ω, VOUT = 0.2 V p-p 10 15 MHz
Large Signal Bandwidth VOUT = 1 V rms 80 MHz
Peaking VOUT = 0.2 V p-p < 50 MHz 0.7 1.0 dB
Slew Rate VOUT = 4 V p-p, G = +2 300 V/µs
Rise and Fall Time VOUT = 2 V p-p 2 ns
Settling Time 0.1%, VOUT = 2 V p-p 39 ns
Input Overdrive Recovery Time VOUT = 6.5 V p-p 350 ns
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended G = +5, VOUT = 2 V p-p, RF = 499 Ω
2nd Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω –73/61 –75/–63 dBc
3rd Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω –80/–68 –82/–70 dBc
Multitone Power Ratio1 26 kHz to 138 kHz, ZLINE = 100 Ω,
PLINE = 13 dBm –68 dBc
IMD 500 kHz, ∆f = 110 kHz, RL = 100 Ω/25 Ω –87/–82 –88/–83 dBc
IP3 500 kHz 42/39 42/39 dBm
Voltage Noise (RTI) f = 10 kHz 4 5 nV/√Hz
Input Current Noise f = 10 kHz 17 20 pA√Hz
INPUT CHARACTERISTICS
RTI Offset Voltage –3.0 0.2 +3.0 mV
+Input Bias Current –25 10 +25 µA
–Input Bias Current –30 10 +30 µA
Input Resistance 400 kΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range –4 +4 V
Common-Mode Rejection Ratio 60 66 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Single-Ended, RL = 100 Ω –5 +5 V
Linear Output Current G = 5, RL = 5 Ω, f = 100 kHz,
–60 dBc SFDR 300 420 mA
Short Circuit Current 830 mA
Capacitive Load Drive RS = 10 Ω 50 pF
POWER SUPPLY
Quiescent Current PWDN1, PWDN0 = (1, 1) 8 9.7 mA/Amp
PWDN1, PWDN0 = (1, 0) 6 6.9 mA/Amp
PWDN1, PWDN0 = (0, 1) 4 5.0 mA/Amp
PWDN1, PWDN0 = (0, 0) 3 4.1 mA/Amp
Recovery Time To 95% of IQ 23 µs
Shutdown Current 250 µA Out of Bias Pin 1.0 2.0 mA/Amp
Power Supply Rejection Ratio ∆VS = ± 1 V 63 80 dB
OPERATING TEMPERATURE RANGE –40 +85 °C
NOTES
1
See Figure 43, R20, R21 = 0 Ω, R1 = open.
Specifications subject to change without notice.

LOGIC INPUTS (CMOS-Compatible Logic) (PWDN0, PWDN1, V CC = ⴞ12 V or ⴞ6 V; Full Temperature Range)
Parameter Min Typ Max Unit
Logic “1” Voltage 2.2 +VCC V
Logic “0” Voltage 0 0.8 V

REV. A –3–
AD8016
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V The maximum power that can be safely dissipated by the AD8016
Internal Power Dissipation is limited by the associated rise in junction temperature. The
PSOP3 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 W maximum safe junction temperature for plastic encapsulated
Batwing Package3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W device is determined by the glass transition temperature of the
EPAD Package4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W plastic, approximately 150°C. Temporarily exceeding this limit
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ± VS may cause a shift in parametric performance due to a change in
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ± VS the stresses exerted on the die by the package.
Output Short Circuit Duration The output stage of the AD8016 is designed for maximum load
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves current capability. As a result, shorting the output to common
Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C can cause the AD8016 to source or sink 2000 mA. To ensure
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C proper operation, it is necessary to observe the maximum power
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C derating curves. Direct connection of the output to either power
NOTES supply rail can destroy the device.
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
8
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating

MAXIMUM POWER DISSIPATION – Watts


7
conditions for extended periods may affect device reliability.
2
Specification is for device on a four-layer board with 10 inches 2 of 1 oz. copper at
6
85°C 20-lead PSOP3 package: θJA = 18°C/W.
3
Specification is for device on a four-layer board with 10 inches 2 of 1 oz. copper at PSOP3
5
85°C 24-lead Batwing package: θJA = 28°C/W.
4
Specification is for device on a four-layer board with 9 inches 2 of 1 oz. copper at
4
85°C 28-lead (EPAD) package: θJA = 29°C/W. BATWING

3
EPAD
2

0
0 10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ⴗC

Figure 2. Plot of Maximum Power Dissipation vs.


Temperature for AD8016 for TJ = 125°C

ORDERING GUIDE

Temperature Package Package


Model Range Description Option
AD8016ARP –40°C to +85°C 20-Lead PSOP3 RP-20
AD8016ARP-Reel –40°C to +85°C 20-Lead PSOP3 ARP-Reel
AD8016ARP-EVAL –40°C to +85°C Evaluation Board ARP-EVAL
AD8016ARB –40°C to +85°C 24-Lead Batwing RB-24
AD8016ARB-Reel –40°C to +85°C 24-Lead Batwing ARB-Reel
AD8016ARB-EVAL –40°C to +85°C Evaluation Board ARB-EVAL
AD8016ARE –40°C to +85°C 28-Lead HTSSOP RE-28
AD8016ARE-Reel –40°C to +85°C 28-Lead HTSSOP ARE-Reel
AD8016ARE-EVAL –40°C to +85°C Evaluation Board ARE-EVAL

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD8016 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. A
Typical Performance Characteristics– AD8016

10␮F
+VS
124⍀ 499⍀ +
VOUT 0.1␮F
RL
+VIN
49.9⍀ +VO
VIN
499⍀
49.9⍀
+VS
111⍀ 499⍀ RL
+
0.1␮F 10␮F

–VO
+ –VIN 0.1␮F
0.1␮F 10␮F
49.9⍀
–VS 10␮F
+
–VS

Figure 3. Single-Ended Test Circuit; G = +5 Figure 6. Differential Test Circuit; G = +10

VOUT = 100mV VOUT = 100mV

VOLTS
VOLTS

VIN = 20mV VIN = 20mV

TIME – 100ns/DIV TIME – 100ns/DIV

Figure 4. 100 mV Step Response; G = +5, VS = ± 6 V, Figure 7. 100 mV Step Response; G = +5, VS = ± 12 V,
RL = 25 Ω, Single-Ended RL = 25 Ω, Single-Ended

VOUT = 5V VOUT = 4V
VOLTS
VOLTS

VIN = 800mV VIN = 800mV

TIME – 100ns/DIV TIME – 100ns/DIV

Figure 5. 4 V Step Response; G = +5, VS = ± 6 V, Figure 8. 4 V Step Response; G = +5, VS = ± 12 V,


RL = 25 Ω, Single-Ended RL = 25 Ω, Single-Ended

REV. A –5–
AD8016
–30 –30
(0,0)
(0,0) RF = 499⍀
RF = 499⍀
–40 –40 G = +10
G = +10
VO = 4V p-p VO = 4V p-p (0,1)
–50 (0,1) –50

DISTORTION – dBc
DISTORTION – dBc

(1,0)
–60 –60 (1,0)

–70 –70
PWDN 1,0 = (1,1)
–80 –80
PWDN 1,0 = (1,1)
–90 –90

–100 –100

–110 –110
0.01 0.1 1 10 20 0.01 0.1 1 10 20
FREQUENCY – MHz FREQUENCY – MHz

Figure 9. Distortion vs. Frequency; Second Harmonic, Figure 12. Distortion vs. Frequency; Third Harmonic,
VS = ± 12 V, RL = 50 Ω, Differential VS = ± 12 V, RL = 50 Ω, Differential

–30 –30
(0,0)
RF = 499⍀ RF = 499⍀
–40 G = +10 (0,1) –40 G = +10
VO = 4V p-p (0,0)
VO = 4V p-p
–50 –50
(1,0) (0,1) (1,0)
DISTORTION – dBc

DISTORTION – dBc

–60 –60

–70 –70
PWDN 1,0 = (1,1)
–80 PWDN 1,0 = (1,1) –80

–90 –90

–100 –100

–110 –110
0.01 0.1 1 10 20 0.01 0.1 1 10 20
FREQUENCY – MHz FREQUENCY – MHz

Figure 10. Distortion vs. Frequency; Second Harmonic, Figure 13. Distortion vs. Frequency; Third Harmonic,
VS = ± 6 V, RL = 50 Ω, Different VS = ± 6 V, RL = 50 Ω, Differential

–30 –30
RF = 499⍀ RF = 499⍀
–35
G = +5 G = +5
–40
–40
(1,0)
–45 (0,0)
DISTORTION – dBc

DISTORTION – dBc

–50
–50
(0,1)
–55 –60
(0,0) (0,1) (1,0)
–60
–70
–65

–70
–80
–75 PWDN 1,0 = (1,1) PWDN
1,0 = (1,1)
–80 –90
0 100 200 300 400 500 600 700 800 0 100 200 300 400 500 600 700
PEAK OUTPUT CURRENT – mA PEAK OUTPUT CURRENT – mA

Figure 11. Distortion vs. Peak Output Current; Second Figure 14. Distortion vs. Peak Output Current, Third
Harmonic, VS = ± 12 V, RL = 10 Ω, f = 100 kHz, Single-Ended Harmonic; VS = ± 12 V, RL = 10 Ω, G = +5, f = 100 kHz,
Single-Ended

–6– REV. A
AD8016
–30 –30
RF = 499⍀
–35 –35
G = +5
–40 –40

–45 –45

DISTORTION – dBc
DISTORTION – dBc

(0,0)
–50 –50
(0,1) (0,0)
–55 –55
(1,0) (0,1)
–60 –60
(1,0)
–65 –65

–70 –70

–75 –75 PWDN 1,0 = (1,1)


PWDN 1,0 = (1,1)
–80 –80
0 100 200 300 400 500 600 0 100 200 300 400 500 600
PEAK OUTPUT CURRENT – mA PEAK OUTPUT CURRENT – mA

Figure 15. Distortion vs. Peak Output Current; Second Figure 18. Distortion vs. Peak Output Current; Third
Harmonic, VS = ± 6 V, RL = 5 Ω, f = 100 kHz, Single-Ended Harmonic, VS = ± 6 V, G = +5, RL = 5 Ω, f = 100 kHz,
Single-Ended

–30 –30

–40 –40

(0,0)
–50 –50
DISTORTION – dBc

DISTORTION – dBc

(0,0) (0,1)
–60 –60

(1,0)
–70 (0,1) –70
(1,0)

–80 –80
PWDN 1,0 = (1,1) PWDN 1,0 = (1,1)
–90 –90

–100 –100
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
DIFFERENTIAL OUTPUT – V p-p DIFFERENTIAL OUTPUT – V p-p

Figure 16. Distortion vs. Output Voltage; Second Figure 19. Distortion vs. Output Voltage; Third
Harmonic, VS = ± 12 V, G = +10, f = 1 MHz, RL = 50 Ω, Harmonic, VS = ± 12 V, G = +10, f = 1 MHz, RL = 50 Ω,
Differential Differential

–30 –30

–40 –40
(0,0)
DISTORTION – dBc

DISTORTION – dBc

–50 –50

(0,1)
–60 –60
(0,0) (1,0)
(0,1)
–70 –70
(1,0)

–80 –80 PWDN 1,0 = (1,1)


PWDN 1,0 = (1,1)

–90 –90
0 5 10 15 20 0 5 10 15 20
DIFFERENTIAL OUTPUT – V p-p DIFFERENTIAL OUTPUT – V p-p

Figure 17. Distortion vs. Output Voltage; Second Figure 20. Distortion vs. Output Voltage, Third Harmonic,
Harmonic, VS = ± 6 V, G = +10, f = 1 MHz, RL = 50 Ω, VS = ± 6 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential
Differential

REV. A –7–
AD8016
3 6

NORMALIZED FREQUENCY RESPONSE – dB


NORMALIZED FREQUENCY RESPONSE – dB

0 3

–3 0
1,1 1,1
–6 VIN = 40mV p-p –3
G = +5
–9 RL = 100⍀ 1,0 –6 VIN = 40mV p-p
G = +5
–12 –9 RL = 100⍀ 1,0
0,1
–15 –12
0,1
–18 0,0 –15

–21 –18 0,0

–24 –21

–27 –24
1 10 100 500 1 10 100 500
FREQUENCY – MHz FREQUENCY – MHz

Figure 21. Frequency Response; VS = ± 12 V, Figure 24. Frequency Response; VS = ± 6 V,


@ PWDN1, PWDN0 Codes @ PWDN1, PWDN0 Codes

11 11
G = +5 G = +5
8 RL = 100⍀ 8 RL = 100⍀
RF = 499⍀ RF = 499⍀
5 5
OUTPUT VOLTAGE – dBV

2 2

–1 –1
PSRR – dB

–4 –4

–7 –7

–10 –10

–13 –13

–16 –16

–19 –19
1 10 100 500 1 10 100 500
FREQUENCY – MHz FREQUENCY – MHz

Figure 22. Output Voltage vs. Frequency; VS = ± 12 V Figure 25. PSRR vs. Frequency; VS = ± 6 V

20 –10
RF = 499⍀
10 VIN = 2V rms –20
RF = 602⍀ 1,1
0 1,0
–30
–10 +PSRR

–20 –40
CMRR – dB

PSRR – dB

–30 0,1 –50


–PSRR
–40
–60
0,0
–50
–70
–60
–80
–70

–80 –90
0.03 0.1 1 10 100 500 0.01 0.1 1 10 100 500
FREQUENCY – MHz FREQUENCY – MHz

Figure 23. CMRR vs. Frequency; VS = ± 12 V Figure 26. PSRR vs. Frequency; VS = ± 12 V
@ PWDN1, PWDN0 Codes

–8– REV. A
AD8016
180 90 1000000 360

160 80 100000 320


+ INPUT CURRENT NOISE – pA/ Hz

INPUT VOLTAGE NOISE – nV/ Hz


140 70 10000 280

TRANSIMPEDANCE – k⍀
120 60 1000 PHASE 240

PHASE – Degrees
100 50 100 200

80 40 10 TRANSIMPEDANCE 160

60 30 1 120
+I NOISE
40 VIN NOISE 20 0.1 80

20 10 0.01 40

0 0 0 0
10 100 1k 10k 100k 1M 10M 0.0001 0.001 0.01 0.1 1 10 100 1000 10000
FREQUENCY – MHz FREQUENCY – MHz

Figure 27. Noise vs. Frequency Figure 30. Open-Loop Transimpedance and Phase
vs. Frequency

OUTPUT VOLTAGE ERROR – 2mV/DIV (0.1%/DIV)


OUTPUT VOLTAGE ERROR – 2mV/DIV (0.1%/DIV)

G = +2 G = +2
RF = 1k⍀ RF = 1k⍀
VOUT = 2VSTEP VOUT = 2VSTEP
RL = 100⍀ RL = 100⍀

+2mV
(–0.1%) +2mV
(–0.1%)
0
0
–2mV VIN
(–0.1%) –2mV
(–0.1%)

VIN VOUT –VIN VOUT VOUT –VIN

VOUT

–5 0 5 10 15 20 25 30 35 40 45 –5 0 5 10 15 20 25 30 35 40 45
TIME – ns TIME – ns

Figure 28. Settling Time 0.1%; VS = ± 12 V Figure 31. Settling Time 0.1%; VS = ± 6 V

–20 1000

VOUT = 2V p-p
–30 RF = 499⍀
100
G = +5
OUTPUT IMPEDANCE – ⍀

RL = 100⍀
–40 0,0
CROSSTALK – dB

10 0,1
–50

1,0
–60
1
1,1
–70
0.1
–80

–90 0.01
0.03 0.1 1 10 100 500 0.03 0.1 1 10 100 500
FREQUENCY – MHz FREQUENCY – MHz

Figure 29. Output Crosstalk vs. Frequency Figure 32. Output Impedance vs. Frequency
@ PWDN1, PWDN0 Codes

REV. A –9–
AD8016
18
VIN = 2V/DIV
16
VOUT = 5V/DIV
PWDN 1,0 = [1.1]
VOUT
14

12
[1,0]

IQ – mA
10
0V
8 [0,1]
VIN

6
[0,0]
4

0V
2

0
–100 0 100 200 300 400 500 600 700 800 900 0 50 100 150 200
TIME – ns IBIAS – ␮A

a. Overload Recovery; VS = ± 12 V, G = +5, RL = 100 Ω Figure 35. IQ vs. IBIAS Pin Current; VS = ± 6 V

12
+VOUT, VS = ⴞ12V
VIN = 2V/DIV
VOUT = 5V/DIV 8
+VOUT, VS = ⴞ6V
0V
VOUT OUTPUT SWING – Volts 4

0V
VIN –4

–VOUT, VS = ⴞ6V
–8

–VOUT, VS = ⴞ12V
–12
–100 0 100 200 300 400 500 600 700 800 900 10 100 1k 10k
TIME – ns RLOAD –

b. Overload Recovery; VS = ± 12 V, G = +5, RL = 100 Ω Figure 36. Output Voltage vs. RLOAD
Figure 33.

25

PWDN 1,0 = [1,1]


20

15 [1,0]
IQ – mA

[0,1]
10

[0,0]
5

0
0 50 100 150 200
IBIAS – ␮A

Figure 34. IQ vs. IBIAS Pin Current; VS = ± 12 V

–10– REV. A
AD8016
THEORY OF OPERATION FEEDBACK RESISTOR SELECTION
The AD8016 is a current feedback amplifier with high (500 mA) In current feedback amplifiers, selection of feedback and gain
output current capability. With a current feedback amplifier the resistors will have an impact on the MTPR performance, band-
current into the inverting input is the feedback signal and the width and gain flatness. Care should be exercised in the selec-
open-loop behavior is that of a transimpedance, dVo/dIin or TZ. tion of these resistors so that optimum performance is achieved.
The open-loop transimpedance is analogous to the open-loop The table below shows the recommended resistor values for use
voltage gain of a voltage feedback amplifier. Figure 37 shows a in a variety of gain settings. These values are suggested as a
simplified model of a current feedback amplifier. Since RIN is good starting point when designing for any application.
proportional to 1/gm, the equivalent voltage gain is just TZ × gm,
where gm is the transconductance of the input stage. Basic Table I. Resistor Selection Guide
analysis of the follower with gain circuit yields:
Gain RF (⍀) RG (⍀)
VO
=G×
TZ ( S ) +1 1k ∞
VIN TZ ( S ) + G × RIN + RF –1 500 500
+2 650 650
where: +5 750 187
RF +10 1k 111
G =1+
RG BIAS PIN AND PWDN FEATURES
1 The AD8016 is designed to cover both CO (Central Office) and
RIN = ≈ 25 Ω CPE (Customer Premise Equipment) ends of an xDSL applica-
gm tion. It offers full versatility in setting quiescent bias levels for
the particular application from full ON to reduced bias (in three
Recognizing that G × RIN << RF for low gains, the familiar
steps) to full OFF (via BIAS pin). This versatility gives the
result of constant bandwidth with gain for current feedback
modem designer the flexibility to maximize efficiency while
amplifiers is evident, the 3 dB point being set when |TZ| = RF.
maintaining reasonable levels of Multitone Power Ratio (MTPR)
Of course, for a real amplifier there are additional poles that
performance. Optimizing driver efficiency while delivering the
contribute excess phase and there will be a value for RF below
required DMT power is accomplished with the AD8016 through
which the amplifier is unstable. Tolerance for peaking and desired
the use of on-chip power management features. Two digitally
flatness will determine the optimum RF in each application.
programmable logic pins, PWDN1 and PWDN0, may be used
RF
to select four different bias levels; 100%, 60%, 40%, and 25%
RG

of full quiescent power (see Table II).
RIN Table II. PWDN Code Selection Guide
+
IIN TZ VOUT

RN
PWDN1 PWDN0
+
Code Code Quiescent Bias Level
VIN
1 1 100% (Full ON)
1 0 60%
Figure 37. Simplified Block Diagram
0 1 40%
The AD8016 is the first current feedback amplifier capable of
0 0 25% (Low ZOUT but Not OFF)
delivering 400 mA of output current while swinging to within
2 V of either power supply rail. This enables full CO ADSL X X Full OFF (High ZOUT via 250 µA
performance on only 12 V rails, an immediate 20% power saving. Pulled Out of BIAS Pin)
The AD8016 is also unique in that it has a power management
The bias level can be controlled with TTL logic levels (HI = 1)
system included on-chip. It features four user programmable
applied to PWDN1 and PWDN0 pins alone or in combination
power levels (all of which provide a low output impedance of the
with BIAS control pin. The DGND or digital ground pin is the
driver), as well as the provision for complete shutdown (high
logic ground reference for PWDN1 and PWDN0 pins. In typical
impedance state). Also featured is a thermal shutdown with
ADSL applications where ± 12 V or ± 6 V supplies (also single
alarm signal.
supplies) are used, the DGND pin is connected to analog ground.
POWER SUPPLY AND DECOUPLING The BIAS control pin by itself is a means to continuously adjust
The AD8016 should be powered with a good quality (i.e., low the AD8016 internal biasing and thus quiescent current IQ. By
noise) dual supply of ± 12 V for the best distortion and Multi- pulling out a current of 0 µA (or open) to approximately 200 µA,
tone Power Ratio (MTPR) performance. Careful attention must the quiescent current can be adjusted from 100% (full ON) to a
be paid to decoupling the power supply pins. A 10 µF capacitor full OFF condition. The full OFF condition yields a high output
located in near proximity to the AD8016 is required to provide impedance. Because of on-chip resistor variation of up to ± 20%
good decoupling for lower frequency signals. In addition, 0.1 µF the actual amount of current required to fully shut down the
decoupling capacitors should be located as close to each of the AD8016 can vary. To institute a full chip shutdown, a pull-
four power supply pins as is physically possible. All ground pins down current of 250 µA is recommended. See Figure 38 for
should be connected to a common low impedance ground logic drive circuit for complete amplifier shutdown. Figures 34
plane. and 35 show the relationship between current pulled out of

REV. A –11–
AD8016
BIAS pin (IBIAS) and the supply current (IQ). A typical shut- APPLICATIONS
down IQ is less than 1 mA total. Alternatively, an external pull- The AD8016ARP and AD8016ARB dual xDSL line driver
down resistor to ground or a current sink attached to the BIAS amplifiers are the most efficient xDSL line drivers available to
pin can be used to set IQ to lower levels (see Figure 39). The the market today. The AD8016 may be applied in driving modu-
BIAS pin may be used in combination with the PWDN1 and lated signals including Discrete Multitone (DMT) in either
PWDN0 pins; however, diminished MTPR performance may direction; upstream from Customer Premise Equipment (CPE)
result when IQ is lowered too much. Current pulled away from to the Central Office (CO) and downstream from CO to CPE.
the BIAS pin will shunt away a portion of the internal bias cur- The most significant thermal management challenge lies in
rent. Setting PWDN1 or PWDN0 to Logic 0 also shunts away a driving downstream information from CO sites to the CPE.
portion of the internal bias current. The reduction of quiescent Driving xDSL information downstream suggests the need to
bias levels due to the use of PWDN1 and PWDN0 is consistent locate many xDSL modems in a single CO site. The implication
with the percentages established in Table II. When PWDN0 alone is that several modems will be placed onto a single printed cir-
is set to Logic 0, and no other means of reducing the internal cuit board residing in a card cage located in a variety of ambient
bias currents is used, full-rate ADSL signals may be driven while conditions. Environmental conditioners such as fans or air con-
maintaining reasonable levels of MTPR. ditioning may or may not be available, depending on the density
of modems and the facilities contained at the CO site. To achieve
3.3V LOGIC
R2
R1* long-term reliability and consistent modem performance, designers
BIAS
50k⍀
2N3904
of CO solutions must consider the wide array of ambient condi-
tions that exist within various CO sites.
*R1 = 47k⍀ FOR ⴞ12VS OR +12VS,
R1 = 22k⍀ FOR ⴞ6VS. MULTITONE POWER RATIO OR MTPR
ADSL systems rely on Discrete Multitone (or DMT) modulation
Figure 38. Logic Drive of BIAS Pin for Complete Amplifier
to carry digital data over phone lines. DMT modulation appears
Shutdown
in the frequency domain as power contained in several individual
THERMAL SHUTDOWN frequency subbands, sometimes referred to as tones or bins, each
The AD8016ARB and ARP have been designed to incorporate of which is uniformly separated in frequency. (See Figure 1 for
shutdown protection against accidental thermal overload. In the example of downstream DMT signals used in evaluating MTPR
event of thermal overload, the AD8016 was designed to shut performance.) A uniquely encoded, Quadrature Amplitude Modu-
down at a junction temperature of 165°C and return to normal lation (QAM) signal occurs at the center frequency of each
operation at a junction temperature 140°C The AD8016 will subband or tone. Difficulties will exist when decoding these
continue to operate, cycling on and off, as long as the thermal subbands if a QAM signal from one subband is corrupted by the
overload condition remains. The frequency of the protection QAM signal(s) from other subbands, regardless of whether the
cycle depends on the ambient environment, severity of the ther- corruption comes from an adjacent subband or harmonics of
mal overload condition, the power being dissipated and the ther- other subbands. Conventional methods of expressing the output
mal mass of the PCB beneath the AD8016. When the AD8016 signal integrity of line drivers, such as spurious free dynamic range
begins to cycle due to thermal stress, the internal shutdown (SFDR), single-tone harmonic distortion or THD, two-tone
circuitry draws current out of the node connected in common Intermodulation Distortion (IMD) and 3rd order intercept (IP3)
with the BIAS pin, while the voltage at the BIAS pin goes to the become significantly less meaningful when amplifiers are required
negative rail. When the junction temperature returns to 140°C, to drive DMT and other heavily modulated waveforms. A typical
current is no longer drawn from this node and the BIAS pin xDSL downstream DMT signal may contain as many as 256
voltage returns to the positive rail. Under these circumstances, carriers (subbands or tones) of QAM signals. Multitone Power
the BIAS pin can be used to trip an alarm indicating the pres- Ratio (MTPR) is the relative difference between the measured
ence of a thermal overload condition. power in a typical subband (at one tone or carrier) versus the
power at another subband specifically selected to contain no QAM
Figure 39 also shows three circuits for converting this signal to a data. In other words, a selected subband (or tone) remains open
standard logic level. or void of intentional power (without a QAM signal) yielding an
empty frequency bin. MTPR, sometimes referred to as the “empty
VCC
AD8016
bin test,” is typically expressed in dBc, similar to expressing the
relative difference between single-tone fundamentals and 2nd or
200␮A V = VCC –0.2V
10k⍀ 3rd harmonic distortion components.
BIAS
SHUT- OR 0–200␮A See Figure 1 for a sample of the ADSL downstream spectrum
DOWN
BIAS
showing MTPR results while driving 20.4 dBm of power onto a
VEE
100 Ω line. Measurements of MTPR are typically made at the
+5V
PWDN0 PWDN1 output (line side) of ADSL hybrid circuits. (See Figure 46a for
VCC 10k⍀ an example of Analog Devices’ hybrid schematic.) MTPR can
+5V ALARM
10k⍀ 1M⍀
be affected by the components contained in the hybrid circuit,
BIAS ALARM OR BIAS including the quality of the capacitor dielectrics, voltage ratings
MIN ␤ 350
100k⍀
and the turns ratio of the selected transformers. Other compo-
1/4 HCF 40109B
SGS - THOMSON
nents aside, an ADSL driver hybrid containing the AD8016 can be
optimized for the best MTPR performance by selecting the turns
Figure 39. Shutdown and Alarm Circuit ratio of the transformers. The voltage and current demands from
the differential driver changes, depending on the transformer
–12– REV. A
AD8016
turns ratio. The point on the curve indicating maximum dynamic GENERATING DMT
headroom is achieved when the differential driver delivers both At this time, DMT-modulated waveforms are not typically menu-
the maximum voltage and current while maintaining the lowest selectable items contained within arbitrary waveform generators.
possible distortion. Below this point the driver has reserve cur- Even using (AWG) software to generate DMT signals, AWGs
rent-driving capability and experiences voltage clipping while that are available today may not deliver DMT signals sufficient
above this point the amplifier runs out of current drive capabil- in performance with regard to MTPR due to limitations in the
ity before the maximum voltage drive capability is reached. D/A converters and output drivers used by AWG manufactur-
Since a transformer reflects the secondary load impedance back ers. Similar to evaluating single-tone distortion performance of
to the primary side by the square of the turns ratio, varying the an amplifier, MTPR evaluation requires a DMT signal generator
turns ratio changes the load across the differential driver. In the capable of delivering MTPR performance better than that of the
transformer configuration of Figure 46a and 46b, the turns ratio driver under evaluation. Generating DMT signals can be accom-
of the selected transformer is effectively doubled due to the plished using a Tektronics AWG 2021 equipped with opt 4,
parallel wiring of the transformer primaries within this ADSL (12/24-Bit, TTL Digital Data Out), digitally coupled to Analog
driver hybrid. The following equation may be used to calculate Devices AD9754, a 14-bit TxDAC, buffered by an AD8002
the load impedance across the output of the differential driver, amplifier configured as a differential driver. See Figure 45 for
reflected by the transformers, from the line side of the xDSL schematics of a circuit used to generate DMT signals that can
driver hybrid. Z' is the primary side impedance as seen by the achieve down to –80 dBc of MTPR performance, sufficient for
differential driver; Z2 is the line impedance and N is the trans- use in evaluating xDSL drivers. Note that the DMT waveforms
former turns ratio. available with the AD8016ARP-EVAL and AD8016ARB-EVAL
boards or similar WFM files are needed to produce the neces-
Z2 sary digital data required to drive the TxDAC from the optional
Z' ≡
(2 × N )
2
TTL Digital Data output of the TEK AWG2021. Copies of
these WFM files can be obtained through the Analog Devices
Figure 40 shows the dynamic headroom in each subband of a website. http://www.analog.com/.
downstream DMT waveform versus turns ratio running at 100%
and 60% of the quiescent power while maintaining –65 dBc of EVALUATION BOARDS
MTPR at VS = ± 12 V. The AD8016ARP-EVAL, AD8016ARB-EVAL, AD8016ARE-EVAL
boards available through Analog Device provide a platform for
4 evaluating the AD8016 in an ADSL differential line driver
VS = ⴞ12V
PWDN1,0 = (1,1)
circuit. The board is laid out to accommodate Analog Devices
3 two transformer line driver hybrid circuit (see Figures 46a and
VS = ⴞ11.4V 46b) including line matching network, an RJ11 jack for interfac-
DYNAMIC HEADROOM – dB

PWDN1,0 = (1,1)
2
ing to line simulators, transformer coupled input for single-to-
differential input conversion and accommodations for the receiver
VS = ⴞ12V function. Schematics and layout information are available for both
1 PWDN1,0 = (1,0)
versions of the EVAL board. Also included in the package are
WFM files for use in generating 14-bit DMT waveforms.
0 Upstream data is contained in the ...24.wfm files and down-
VS = ⴞ11.4V
PWDN1,0 = (1,0) stream data in the ...128.wfm files.
–1
These DMT modulated signals are used to evaluate xDSL
products for Multitone Power Ratio or MTPR performance.
–2
1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 The data files are used in pairs (adslu24.wfm and adsll24.wfm
DOWNSTREAM TURNS RATIO go together, etc.) and are loaded into Tektronics AWG2021
Figure 40. Dynamic Headroom vs. XFMR Turns Ratio, arbitrary waveform generator. The adslu24.wfm is loaded via
VS = ± 12 V the TEK AWG2021 floppy drive into Channel 1, while the
adsll24.wfm is simultaneously loaded into Channel 2. The num-
Once an optimum turns ratio is determined, the amplifier will ber in the file name, prefixed with “u,” goes into CH1 or upper
have an MTPR performance for each setting of the power-down channel and the “l” goes into CH2 or the lower channel. 12 bits
pins. The table below demonstrates the effects of reducing the from CH1 are combined with 2 bits from CH2 to achieve 14-
total power dissipated by using the PWDN pins on MTPR bit digital data at the digital outputs of the TEK 2021. The
performance when driving 20.4 dBm downstream onto the line resulting waveforms produced at the AD9754-EB outputs are
with a transformer turns ratio of 1:1.4. then buffered and amplified by the AD8002 differential driver to
achieve 14-bit performance from this DMT signal source.
Table III. Dynamic Power Dissipation for Downstream
Transmission POWER DISSIPATION
In order to properly size the heat sinking area for your applica-
PWDN1 PWDN0 PD (W) MTPR
tion, it is important to consider the total power dissipation of
1 1 1.454 –78 dBc the AD8016. The dc power dissipation for VIN = 0 is IQ (VCC –
1 0 1.262 –75.3 dBc VEE), or 2 × IQ × VS.
0 1 1.142 –57.2 dBc
For the AD8016 powered on +12 V and –12 V supplies (± VS),
0* 0 0.120 N/A
the number is 0.6 W. In a differential driver circuit (Figure 6),
*This mode is quiescent power dissipation.

REV. A –13–
AD8016
we can use symmetry to simplify the computation for a dc input of the die, allowing more drivers/square-inch within the CO
signal. design. The AD8016, whether in a PSOP3 (ARP) or batwing
(ARB) package, can be designed to operate in the CO solution
VO
PD = 2 × IQ × VS + 4 × (VS – VO ) using prudent measures to manage the power dissipation through
RL careful PCB design. The PSOP3 package is available for use in
where designing the highest density CO solutions. Maximum heat trans-
VO is the peak output voltage of an amplifier. fer to the PCB can be accomplished using the PSOP3 package
when the thermal slug is soldered to an exposed copper pad
This formula is slightly pessimistic due to the fact that some of directly beneath the AD8016. Optimum thermal performance
the quiescent supply current is commutated during sourcing or can be achieved in the ARE package only when the back of the
sinking current into the load. For a sine wave source, integration package is soldered to a PCB designed for maximum thermal
over a half cycle yields: capacity (see Figure 44). Thermal experiments with the PS0P3
4 V V package were conducted without soldering the heat slug to the
V 
2
PD = 2 × IQ × VS + 2  O S
− O  PCB. Heat transfer was through physical contact only. The
 π RL RL  following offers some insight into the AD8016 power dissipation

and relative junction temperature, the effects of PCB size and
The situation is more complicated with a complex modulated composition on the junction-to-air thermal resistance or θJA.
signal. In the case of a DMT signal, taking the equivalent sine
wave power overestimates the power dissipation by ~23%. For THERMAL TESTING
example: A wind tunnel study was conducted to determine the relationship
POUT = 23.4 dBm = 220 mW between thermal capacity (i.e., printed circuit board copper area),
VOUT @ 50 Ω = 3.31 V rms air flow and junction temperature. Junction-to-ambient ther-
VO = 2.354 V mal resistance, θJA, was also calculated for the AD8016ARP,
AD8016ARE, and AD8016ARB packages. The AD8016 was
at each amplifier output, which yields a PD of 1.81 W. operated in a noninverting differential driver configuration, typical
Through measurement, a DMT signal of 23.4 dBm requires of an xDSL application yet isolated from any other modem
1.47 W of power to be dissipated by the AD8016. Figure 41 components. Testing was conducted using a 1 ounce copper
shows the results of calculation and actual measurements board in an ambient temperature of ~24°C over air flows of
detailing the relationship between the power dissipated by the 200, 150, 100, and 50 (0.200 and 400 for AD8016ARE) linear
AD8016 versus the total output power delivered to the back feet per minute (LFM) and for ARP and ARB packages as well
termination resistors and the load combined. A 1:2 transformer as in still air. The four-layer PCB was designed to maximize the
turns ratio was used in the calculations and measurements. area of copper on the outer two layers of the board while the
inner layers were used to configure the AD8016 in a differential
2.5
driver circuit. The PCB measured 3 × 4 inches in the beginning
of the study and was progressively reduced in size to approxi-
2.0 mately 2 × 2 inches. The testing was performed in a wind tunnel to
CALCULATED control air flow in units of LFM. The tunnel is approximately
POWER DISSIPATION

11 inches in diameter.
1.5
MEASURED
SINE AIR FLOW TEST CONDITIONS
1.0 MEASURED
DUT Power: Typical DSL DMT signal produces about 1.5 W
DMT of power dissipation in the AD8016 package. The fully biased
(PWDN0 and PWDN1 = Logic 1) quiescent current of the
0.5 AD8016 is ~25 mA. A 1 MHz differential sine wave at an ampli-
tude of 8 V p-p/amplifier into an RLOAD of 100 Ω differential
(50 Ω per side) will produce the 1.5 W of power typical in the
0
0 100 200 300 AD8016 device. (See the Power Dissipation section for details.)
OUTPUT POWER – mW
Thermal Resistance: The junction-to-case thermal resistance
Figure 41. Power Dissipation vs. Output Power (Including (θ JC) of the AD8016ARB or batwing package is 8.6°C/W,
Back Terminations). See Figure 7 for Test Circuit AD8016ARE is 5.6°C/W, and the AD8016ARP or PSOP3
package is 0.86°C/W. These package specifications were used in
THERMAL ENHANCEMENTS AND PCB LAYOUT
this study to determine junction temperature based on the mea-
There are several ways to enhance the thermal capacity of the
sured case temperature.
CO solution. Additional thermal capacity can be created using
enhanced PCB layout techniques such as interlacing (sometimes PCB Dimensions of a Differential Driver Circuit: Several
referred to as stitching or interconnection) of the layers immedi- components are required to support the AD8016 in a differential
ately beneath the line driver. This technique serves to increase driver circuit. The PCB area necessary for these components (i.e.,
the thermal mass or capacity of the PCB immediately beneath feedback and gain resistors, ac coupling and decoupling capaci-
the driver. (See AD8016-EVAL boards for an example of this tors, termination and load resistors) dictated the area of the
method of thermal enhancement.) A cooling fan that draws smallest PCB in this study, 4.7 square inches. Further reduction
moving air over the PCB and xDSL drivers, while not always in PCB area, although possible, will have consequences in terms
required, may be useful in reducing the operating temperature of the maximum operating junction temperature.

–14– REV. A
AD8016
EXPERIMENTAL RESULTS 35
The experimental data suggests that for both packages, and a ARB 0 LFM
PCB as small as 4.7 square inches, reasonable junction tempera- ARB 50 LFM
30
tures can be maintained even in the absence of air flow. The graph ARB 100 LFM
in Figure 42 shows junction temperature versus air flow for various
dimensions of 1 ounce copper PCBs at an ambient temperature 25

␪JA – ⴗC/W
of 24°C in both the ARB and ARP packages. For the worst case
ARB 150 LFM
package, the AD8016ARB and the worst case PCB at 4.7 square ARP 0 LFM ARB 200 LFM
inches, the extrapolated junction temperature for an ambient 20 ARP 50 LFM
ARP 100 LFM
environment of 85°C would be approximately 132°C with 0 LFM
of air flow. If the target maximum junction temperature of the
15
AD8016ARB is 125°C, a 4-layer PCB with 1 oz. copper covering
the outer layers and measuring 9 square inches is required ARP 150 LFM
ARP 200 LFM
with 0 LFM of air flow. 10
4 7 10
Note that the AD8016ARE is targeted at xDSL applications PCB AREA – SQ-IN

other than full-rate CO ADSL. The AD8016ARE is targeted at Figure 43. Junction-to-Ambient Thermal Resistance vs.
g.lite and other xDSL applications where reduced power dissi- PCB Area
pation can be achieved through a reduction in output power.
Extreme temperatures associated with full-rate ADSL using the
AD8016ARE should be avoided whenever possible. 50

75 45
ARB 4.7 SQ-IN +24ⴗC AMBIENT
ARB 6 SQ-IN 40
70
JUNCTION TEMPERATURE – ⴗC

35 ARE 0 LFM
␪JA – ⴗC/W
65
30
ARB 7.125 SQ-IN ARE 200 LFM
60
ARB 9 SQ-IN
25
ARP 4.7 SQ-IN ARE 400 LFM
55
ARP 6 SQ-IN 20

50 15

45 ARP 9 SQ-IN 10
0 1 2 3 4 5 6 7 8 9 10
ARP 12 SQ-IN PCB AREA – SQ-IN
40
0 50 100 150 200
AIR FLOW – LFM Figure 44. Junction-to-Ambient Thermal Resistance vs.
PCB Area
Figure 42. Junction Temperature vs. Air Flow

REV. A –15–
AD8016
DVDD DGND AVDD AGND AVEE AVCC
B1 B2 B3 B4 B5 B6
TP19
TP3 TP2 TP4 TP6 TP7
TP18

TP5 TP1 CLK


J1
C3 C4 A C5 A C6 A JP1
10␮F 10␮F 10␮F 10␮F A B
EXTCLK
R15 1 2 3
DVDD DVDD 49.9⍀
R1 R5 R3 R7
16 PINDIP
1 1 1 1 U1 AVDD TP8
RES PK
C7 C8 C9
P1
AD9754 1␮F 0.1␮F 0.1␮F
2 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 C19 1 16 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 1 28
DB13 CLOCK A
4 3 C1 2 15 2 27
DB12 DVDD
6 5 C2 3 14 3 26
DB11 DCOM
8 7 C25 4 13 4 25
DB10 NC
10 9 C26 5 12 5 24
DB9 AVDD AVDD
12 11 C27 6 11 6 23
DB8 COMP2 OUT1
14 13 C28 7 10 7 22
TO TEK DB7 IOUTA OUT2
16 AWG 15 C29 8 9 8 21
DB6 IOUTB
18 2021 17 9 20
DB5 ACOM
20 19 10 19
DB4 COMP1
22 21 11 18
DB3 FS ADJ
24 23 16 PINDIP 12 17
25 RES PK DB2 REFIO TP13
26 13 16
DB1 REFLO
28 27 14 15
29 DB0 SLEEP TP11 TP10 TP9
30 C30 1 16
32 31 A
C31 2 15 R16
34 33 CT1 AVDD
C32 3 14 2k⍀
36 35 C33 4 13
38 37 A R
C34 5 12

–16–
40 39 20k⍀
C35 6 11 C11 C10
C36 7 10 0.1␮F 0.1␮F
1 TP14

10 9 8 7 6 5 4 3 2 10 9 8 7 6 5 4 3 2 10 9 8 7 6 5 4 3 2 10 9 8 7 6 5 4 3 2 2
PDIN JP4
TP12 J2
JP2 3
1 1 1 1
A A A
AVDD
R2 R6 R4 R8 R17
DVDD DVDD 49.9⍀

Figure 45. DMT Signal Generator Schematic


AVCC

0.1␮F
J3
1␮F
OUT1
A
249⍀
C12
22pF 49.9⍀
AD8002
10k⍀

A A A 750⍀ A

226⍀
750⍀ DIFFERENTIAL
DMT OUTPUTS

J4 249⍀
1␮F AD8002
OUT2
0.1␮F
C13 A
22pF 49.9⍀ 10k⍀
A

A A A AVEE

REV. A
AD8016
TP10 TP5
+VT
AGND3,4,5 C8 1 TP6 TP7 PR1 TP13 TP15
R9 4 T2
S5 +V R20 C11 1
C4 R2
2 10
R11 R13 R24 U1
3
–V 2 8
AD8016
2 11 3 9 C6 C7 R4
–VT TP14
1 A B 3
C5 R3
4 7
JP6 R18 1
R1 NC = 5, 6
6 T3 1 TP1 TP16
5 WATT
R17 2 T1
P4 1 2 1 10 1
1:1 R23 R19
4 3 2
P4 2 P1
2 8 3
NC = 5 –VT C9
3 9 4
P4 3 JP5 R25 14 PR2
22 5
–V
23 R21 C12 4 7 6
AGND3,4,5 U1
R14 21 NC = 5, 6
S6 +V AD8016
R16 24 TP8 7 8
R15 C10 TP9 TP2
+VT
+VR;8
TP17 –VR;4
TP11 TP4 3
1
S3 U2
2
AD8022
P3 3
R6
P3 2
R5
R7
P3 1
TP18 AD8022 6
7
S4 U2
5
+VR;8
–VR;4

Figure 46a. Schematic AD8016ARB-EVAL

TP19 TP3
L5
TB1 1 +VT S2
BEAD + C14 R9
10␮F C17 C15 C26
25V 0.1␮F 0.1␮F 0.1␮F
R10 CW
TB1 2
+ C1 C19 C16 C25

13
R22

12
10␮F
L1 0.1␮F 0.1␮F 0.1␮F +VL
25V 15

NC
NC
TB1 3 –VT BIAS
BEAD R12 10
DGND U1
TP20 AD8016
9
P2 3 PDN0
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
TP21 16
L4 P2 1 PDN1
TB2 1 +VR
P2 2 JP1 JP2
20
8
17

19
5
6
7

18

BEAD + C13
10␮F C21 C23
25V 0.1␮F 0.1␮F
TB2 2
+ C3 C24 C22 JP3
10␮F
L3 0.1␮F 0.1␮F +VT +VR
25V
TB2 3 –VR
BEAD JP4
TP22 –VT –VR

TP12
L2
TB3 1 +VL TP24 TP23 TP25 TP26 TP27 TP28 TP29 TP30
BEAD + C2
10␮F C20 C18
25V 0.1␮F 0.1␮F
TB3 2

Figure 46b. Schematic AD8016ARB-EVAL

REV. A –17–
AD8016
LAYOUT AD8016ARB-EVAL

Figure 47. Assembly Figure 50. Layer 1

Figure 48. Layer 1 Figure 51. Silkscreen Bottom

Figure 49. Power/Ground Plane


–18– REV. A
AD8016
ALP – EVALUATION BOARD – BILL OF MATERIALS

Qty. Description Vendor Ref Desc.


5 10 µF 25 V Size Tantalum Chip Capacitor ADS# 4-7-2 C1–3, 13, 14
10 0.1 µF 50 V 1206 Size Ceramic Chip Capacitor ADS# 4-5-18 C15–21, 24–26
2 49.9 Ω 1% 1/8 W 1206 Size Chip Resistor ADS# 3-14-26 R11, 15
2 100 Ω 1% 1/8 W 1206 Size Chip Resistor ADS# 3-18-40 R8, 14
1 100 Ω 5% 3.0 W Metal Film Power Resistor ADS# 3-24-1 R1
3 1.00 kΩ 1% 1/6 W 1206 Size Chip Resistor ADS# 3-18-11 R17–R19
2 10.0 kΩ 1% 1/6 W 1206 Size Chip Resistor ADS# 3-18-119 R13 and 16
1 Test Point (Black) [GND] ADS# 12-18-44 GND
2 Test Point (Brown) ADS# 12-18-59 TP10, 11
4 Test Point (Red) ADS# 12-18-43 TP17–19, 21
2 Test Point (Orange) ADS# 12-18-60 TP3, 15, 16
1 Test Point (Yellow) ADS# 12-18-32 TP12
2 Test Point (Green) ADS# 12-18-61 TP7, 9
2 Test Point (Blue) ADS# 12-18-62 TP20, 22
2 Test Point (Violet) ADS# 12-18-63 TP4, 5
4 Test Point (Grey) ADS# 12-18-64 TP1, 2, 13, 14
2 Test Point (White) ADS# 12-18-42 TP6, 8
2 3 Green Terminal Block. ONSHORE# EDZ250/3 ADS# 12-19-14 TB1, TB2
1 2 Green Terminal Block. ONSHORE# EDZ250/2 ADS# 12-19-13 TB3
5 1 Inch Center Shunt Berg# 65474-001 ADS# 11-2-38 J1–J5
5 Male Header. 1 Inch Center. Berg #69157-102 ADS# 11-2-37 J1–J5
5 Conn. BNC Vert. MT Telegartner # J01001A1944 ADS# 12-6-22 S2–S6
1 AMP# 555154-1 MOD. JACK (SHIELDED) 6 6 D–K# A 9024 P1
1 3-Pin Gold Male Header Waldom #WM 2723-ND D–K# WM 2723-ND JP6
3 3-Pin Gold Male Locking Header Waldom #WM 2701-ND D–K# WM 2701-ND P2–4
1 AD8016 ARB ADS# AD 8016 XRP D.U.T.
1 AD8016 SOIC Rev. A Evaluation PC Board SIERRA/PROTO EXPRESS Eval. PC Board
4 # 4 –40 × 1/4" Panhead SS Machine Screw ADS# 30-1-1
4 # 4 –40 × 1/2" Threaded Alum. Standoffs ADS# 30-16-2
OPTION
2 1:1.4 Turns Ratio RF Transformer from CoEv C1374 Rev. 2 T1, T2

REV. A –19–
AD8016
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

20-Lead PSOP3
(RP-20A)

0.0433 (1.10) MAX ⴛ 45ⴗ 0.5118 (13.00)

C01019a–1–8/00 (rev. A)
0.3543 (9.00)

10 1
PIN 1
0.4370 (11.10) 0.5709 (14.50)
0.2441 (6.20)
0.4331 (11.00) 0.5591 (14.20)
0.2283 (5.80)
0.4252 (10.80) TOP VIEW 0.5472 (13.90) BOTTOM VIEW

11 20

DETAIL A
0.6299 (16.00) 0.0433 0.0039 (0.10)
0.1142 (2.90) MAX 0.1299 (3.30)
0.6260 (15.90) (1.10) MAX 0.0020 (0.05)
2 PLACES 2 PLACES DETAIL A 0.1240 (3.15)
0.6220 (15.80) 0.0000 (0.00)
0.1417 (3.60) 0.1181 (3.00)
SIDE VIEW
0.1319 (3.35) 0.0394 (1.00)
0.1220 (3.10) 0.0354 (0.90)
8° END VIEW 0.1118 (0.30) 0.0126 (0.32)
0.0315 (0.80)
SEATING 0.0500 0.0209 (0.53) 0° 0.0079 (0.20) 0.0090 (0.23)
PLANE (1.27) 0.0157 (0.40) 0.0433 (1.10)
0.0039 (0.10)
BSC 0.0315 (0.80)

24-Lead Batwing
(RB-24)
0.6141 (15.60)
0.5985 (15.20)

24 13
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
1 0.3937 (10.00)
12

PIN 1 0.1043 (2.65) 0.0291 (0.74)


ⴛ 45°
0.0926 (2.35) 0.0098 (0.25)


0.0118 (0.30) 0.0500 0.0201 (0.51) 0° 0.0500 (1.27)
(1.27) SEATING 0.0125 (0.32)
0.0040 (0.10) 0.0130 (0.33) PLANE 0.0157 (0.40)
BSC 0.0091 (0.23)

28-Lead HTSSOP
(RE-28)
0.386 (9.80)
0.382 (9.70)
0.378 (9.60)

28
EXPOSED PAD
15 PRINTED IN U.S.A.
ON BOTTOM
0.059 0.177 (4.50) 0.252
(1.50) 0.173 (4.40) (6.40)
MIN 0.169 (4.30) BSC
0.130 (3.30)
1 MIN 14

PIN 1
0.0256 (0.65) 0.041 (1.05)
0.047
BSC 0.039 (1.00)
(1.20)
MAX 0.031 (0.80)

8ⴗ
0.006 (0.15) 0.0118 (0.30) 0ⴗ 0.030 (0.75)
SEATING 0.0079 (0.20)
0.000 (0.00) 0.0075 (0.19) PLANE 0.024 (0.60)
0.0035 (0.09)
0.177 (0.45)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm)

–20– REV. A

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