MPMC Unit 1

Microprocessors & Microcontrollers (EC501PC)
UNIT -I: (13 Concepts)

8086 Architecture:
 8086 Architecture-Functional diagram,
 Register Organization,
 Memory Segmentation,
 Programming Model,
 Memory addresses,
 Physical Memory Organization,
 Signal descriptions of 8086,
 interrupts of 8086.
Instruction Set and Assembly Language Programming of 8086:
 Instruction formats,
 Addressing modes,
 Assembler Directives and Macros
 Instruction Set,
 Simple Programs involving Logical, Branch and Call Instructions, Sorting,
String Manipulations.
Introduction to Microprocessors
• Intel introduced it’s 4 bit microprocessor 4004 in
1971 and it’s 8 bit microprocessor 8008 in 1972
• These microprocessors could not survive as
general purpose microprocessors because of
their design and performance limitations.
• Then the launch of a first general purpose 8 bit
microprocessor 8080 in 1974 by Intel is
considered to be the first major stepping stone
towards the development of advanced
microprocessors.
Introduction to Microprocessors cntd…
• The microprocessor 8085 followed by 8080, with a few
more added features to it’s architecture, which
resulted in a functionally complete microprocessor.
• The main limitations of 8-bit microprocessor were
– Low speed,
– Low memory addressing capability
– Limited number of general purpose registers
– Less powerful instruction set
• All these limitations lead to the launching of 8086
microprocessor.
• In the family of 16 bit microprocessors, Intel’s 8086 was
the first one to be launched in 1978.
Introduction to Microprocessors cntd…
• The 8086 microprocessor has a much more
powerful instruction set along with the
architectural developments which imparts
substantial programming flexibility and
improvement in speed over the 8-bit
microprocessor.
• The peripheral chips designed earlier for 8085
were compatible with microprocessor 8086
with slight or no modifications.
Architecture of 8086
• The architecture of 8086 supports a 16 bit ALU, a set of
16 bit registers and provides the segmented memory
addressing capability, a rich instruction set, powerful
interrupt structure, fetched instruction queue for
overlapped fetching and execution etc.
• The internal block diagram, shown in Figure, describes
the overall organization of different units inside the
chip.
• The complete architecture of 8086 can be divided into
two parts.
– Bus interface unit
– Execution Unit
Architecture of 8086 cntd…
• The bus interface unit contains the circuit for
physical address calculations and a pre-
decoding instruction byte queue (6 bytes long)
• The bus interface unit makes the system’s bus
signals available for external interfacing of the
devices.
• In other words, this unit is responsible for
establishing communications with external
devices and peripherals including memory via
the bus.
• As already stated, the 8086 addresses a
segmented memory. The complete physical
address which is 20 bits long is generated
using segment and offset registers, each 16 bit
long.
• For generating a physical address from
contents of these two registers, the content of
a segment register also called as segment
address is shifted left bit-wise four times and
to this result, content of an offset register also
called as offset address is added, to produce a
20 bit physical address.
• For example, if the segment address is 1005H and
the offset is 5555H, then the physical address is
calculated as below
segment address  1005H
offset address  5555H
Physical address = 1005 * 10 + 5555 = 155A5H
• Thus, the segment addressed by the segment
value 1005H can have offset values from 0000H
to FFFFH within it ie maximum 64 K locations may
be accommodated in the segment.
• Thus, the segment register indicates the base
address of a particular segment, while the offset
indicates the distance of the required memory
location in the segment from the base address.
• Since the offset is a 16-bit number, each segment
can have a maximum of 64k locations.
• The bus interface unit has a separate adder to
perform this procedure for obtaining a physical
address while addressing a memory
• The segment address value is to be taken from an
appropriate segment register depending upon whether
code, data or stack are to be accessed, while the offset
may be the content of IP, BX, SI, DI, SP, BP or an
immediate 16-bit value, depending upon the
addressing mode.
• In case of 8085, once the op-code is fetched and
decoded, the external bus remains free for some time,
while processor internally executes the instruction.
• The time slot is utilized in 8086 to achieve the
overlapped fetch and execution cycles.
• While the fetched instruction is executed
internally, the external bus is used to fetch the
machine code of the next instruction and
arrange it in a queue known as pre-decoded
instruction byte queue. It is a 6 byte long,
first-in first-out structure.
• The instructions from the queue are taken for
decoding sequentially.
• Once a byte is decoded, the queue is
rearranged by pushing it out and the queue
status is checked for the possibility of the next
op-code fetch cycle.
• While the op-code is fetched by the interface
unit (BIU), the execution unit (EU) executes
the previously decoded instruction
concurrently.
• The BIU along with EU thus forms a pipeline.
• The bus interface unit, thus manages the
complete interface of execution unit with
memory and I/O devices, of-course, under the
control of the timing and control unit.
• The execution unit contains the register set of
8086 except segment register and IP.
• It has a 16-bit ALU, able to perform arithmetic
and logical operation.
• The 16-bit flag register reflects the results of
execution by the ALU.
• The decoding unit decodes the op-code bytes
issued from the instruction byte queue.
• The timing and control unit derives the necessary
control signals to execute the instruction op-code
received from the queue, depending upon the
information made available by the decoding
circuit.
• The execution unit may pass the results to bus
interface unit for storing them in memory.
8086 Features
 16-bit Arithmetic Logic Unit
 16-bit data bus
 20-bit address bus – 1,048,576 = 1 MB
 16 I/O lines so it can access 64K I/O ports
 16 bit flag
 It has 14 -16 bit registers
 Clock frequency range is 5-10 MHZ
 Designed by Intel
 Rich set of instructions
 40 Pin DIP, Operates in two modes
Register organization of 8086
• 8086 has a powerful set of registers known as
general purpose registers and special purpose
registers.
• All of them are 16 bit registers.
• The general purpose registers can be used as
either 8 bit registers or 16 bit registers.
• They may be either used for holding data,
variables and intermediate results temporarily or
other purposes like a counter or for storing offset
address for some particular addressing modes
etc.
Register organization of 8086 cntd…
• The special purpose registers are used as
segment registers, pointers, index registers or as
offset storage registers for particular addressing
modes.
• The register set is categorized into four groups, as
follows:
– General data registers
– Segment registers
– Pointers and index registers
– Flag register
General data registers:
• Figure 1.1 shows the register organization of
8086.
• The registers AX, BX, CX and DX are the general
purpose 16 bit registers.
• AX is used as 16 bit accumulator  AH, AL
• AL can be used as an 8 bit accumulator for 8 bit
operations. This is the most important general
purpose register having multiple functions.
• Usually L and H specify the lower and higher
bytes of a particular register.
• AX – accumulator,
BX – offset storage,
CX – counter,
DX – to store data
Segment Registers:
• Unlike 8085, the 8086 addresses segmented
memory.
• The complete 1 megabyte memory, which the
8086 addresses, is divided into 16 logical
segments.
• Each segment thus contains 64 k bytes of
memory.
• There are 4 segment registers, viz,
Code segment register (CS)  Code,
Data segment register (DS)  Data,
Extra segment register (ES)  Data,
Stack segment register (SS)  Stack related
data
• The CPU uses the stack for temporarily storing
important data.
• While addressing any location in the memory
bank, the physical address is calculated from
two parts, the first is segment address and the
second is offset.
• The segment registers contain 16 bit segment
base addresses, related to different segments
• Any of the pointers and index registers or BX
may contain the offset of the location to be
addressed
• The advantage of this scheme is that instead
of maintaining a 20 bit register for a physical
address, the processor just maintains two 16
bit registers which are within the word length
capacity of the machine.
• It may be noted that all these segments are
logical segments
Pointers and Index registers:
• The pointers contain offset within the particular
segments.
• The pointers IP, BP and SP usually contain offsets
with in the code (IP), and stack (BP & SP)
segments.
• The index registers are used as general purpose
registers as well as for offset storage in case of
indexed, based indexed and relative based
indexed addressing modes
• The register SI is generally used to store the
offset of the source data in data segment
while the register DI is used to store the offset
of the destination in data or extra segment.
• The index registers are particularly useful for
string manipulations.
Flag Register:
• The 8086 flag register contents indicate the results of
computations in the ALU. It also contains some flag bits to
control the CPU operation.
Memory Segmentation
• The memory in an 8086 based system is
organized as segmented memory.
• In this scheme, the complete physically available
memory may be divided into a number of logical
segments.
• Each segment is 64 Kbytes in size and is
addressed by one of the segment register.
• The 16 bit contents of the segment register
actually point to the starting location of a
particular segment.
Memory Segmentation cntd…
• To address a specific memory location within a
segment, we need an offset address.
• The offset address is also 16 bit long so that the
maximum offset value can be FFFFH, and the maximum
size of any segment is thus 64 K locations.
• To emphasize this segmented memory concept, we will
consider an example of a housing colony containing
say, 100 houses
– Numbering the houses sequentially
– Numbering the houses matrix wise (rows X columns)
10 X 10
• In the second scheme, the efforts required for
finding the same house will be too less.
• This second scheme in our example is analogous
to the segmented memory scheme, where the
addresses are specified in terms of segment
addresses analogous to rows and offset
addresses analogous to columns
• The CPU 8086 is able to address 1 Mbytes of
physical memory.
• The complete 1 Mbytes memory can be divided
into 16 segments, each of 64 Kbytes size.
• In the second scheme, the efforts required for
finding the same house will be too less.
• This second scheme in our example is analogous
to the segmented memory scheme, where the
addresses are specified in terms of segment
addresses analogous to rows and offset
addresses analogous to columns
• The CPU 8086 is able to address 1 Mbytes of
physical memory.
• The complete 1 Mbytes memory can be divided
into 16 segments, each of 64 Kbytes size.
• The offset address values are from 0000H and
FFFFH so that the physical addresses range
from 00000H to FFFFFH.
• In the above said case, the segments are
called non-overlapping segments which are
shown in Figure (a).
• In some cases, however, the segments are
overlapping.
• Suppose a segment starts at a particular
address and its maximum size can be 64
Kbytes
• But, if another segment starts before this 64
kbytes locations of the first segment, the two
segments are said to be overlapping segments
• The area of memory from the start of the
second segment to the possible end of the
first segment is called an overlapped segment
area
• The Figure (b) explains the phenomenon
more clearly.
The main advantages of the segmented memory scheme are
as follows
– Allows the memory capacity to be 1 Mbytes although
the actual addresses to be handled are of 16 bit size.
– Allows the placing of the code, data, and stack portions of

the same program in different parts of memory for data
and code protection.
– Permits a program and/or its data to be put into different
areas of memory each time the program is executed ie
provision for relocation is done.
Programming Model
•An assembly language program model of 8086 is as follows
ASSUME DS:DATA,CS:CODE
DATA SEGMENT
. (Declaration of data variables, constants etc)
.
DATA ENDS
CODE SEGMENT
START:
MOV AX,DATA
MOV DS,AX
.
.
CODE ENDS
END START
END
Memory Addresses
• As 8086 has got 20 address lines, it’s
addressing capability is 1 M Byte memory
locations.
• The physical address is calculated from
segment address and offset address as given
below
Physical address=10*segment addr + offset addr
Physical Memory Organization
• In 8086, 1Mbyte memory is physically organized as an
odd bank and even bank, each of 512 Kbytes.
• Data byte with an even address is transferred on D7 – D0
while the data byte with an odd address is transferred
on D15 – D8 bus lines.
• If instructions are fetched from memory as words,
different possibilities of these words are
– Both the bytes may be data operands
– Both the bytes may contain op-code bits
– one of the bytes may be op-code while other may be data
Physical Memory Organization cntd..
• The above possibilities are taken care by
internal decoder which creates signals and
sends those to Timing & Control Unit.
• This Timing and Control Unit generates the
signals which executes the instructions.
• While referring to word data, BIU requires one
or two memory cycles
– Starting byte at even address ------- One cycle
– Starting byte at odd address ------- two cycles
• Hence while initializing the stack, it should be
initialized at an even address for efficient
operation.
• A map of an 8086 memory system starts at
00000H and ends at FFFFFH.
• For accessing 16 bit data, both banks are to be
accessed where as to access only 8 bit data,
only one bank is accessed.
• Selection of memory banks depends on BHE
and A0.
BHE A0 Indication
0 0 Whole word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None
Signal Descriptions of 8086
• The microprocessor 8086 is a 16 bit CPU
available in 3 clock rates 5, 8 and 10 MHz,
packed in a 40 pin CERDIP or plastic package.
• The 8086 operates in single processor or
multiprocessor configurations to achieve high
performance.
• The pin configuration is shown in Figure
Signal Descriptions of 8086 cntd…
• Some of the pins serve a particular function in
minimum mode (single processor mode) and
others function in maximum mode (multi
processor mode) configuration
• The 8086 signals can be categorized in three
groups.
– Signals having common functions in minimum as well
as maximum mode
– Signals which have special functions for minimum
mode
– Signals which have special functions for maximum
mode.
• The following signal descriptions are common for
both the minimum and maximum modes.
AD15 – AD0:
• These are the time multiplexed memory I/O
address and data lines
• Address remains on lines during T1 state, while
the data is available on the data bus during T2,
T3, Tw and T4.
• Here T1, T2, T3, T4 and Tw are the clock states of
a machine cycle.
• Tw is a wait state.
• These lines are active high and float to a tri-
state during interrupt acknowledge and local
bus hold acknowledge cycles.
A19/S6, A18/S5, A17/S4, A16/S3:
• These are the time multiplexed address and
status lines.
• During T1, these are the most significant
address lines for memory operations.
• During I/O operations, these lines are low.
• During memory or I/O operations, status information
is available on those lines for T2, T3, Tw and T4.
• The status of the interrupt enable flag bit (displayed
on S5) is updated at the beginning of each clock cycle.
• The S4 and S3 together indicate which segment
register is presently being used for memory accesses,
as shown in Table. S4 S3 Indications
0 0 Alternate data
0 1 Stack
1 0 Code or none
1 1 data
Signal Descriptions of 8086 cntd..
• These lines float to tri-state off (tri-stated)
during the local bus hold acknowledge
• The status line S6 is always low (logical).
• The address bits are separated from the status
bits using latches controlled by the ALE signal
BHE/S7 – Bus High Enable/Status:
• The bus high enable signal is used to indicate the transfer of data
over the higher order (D15 – D8) data bus as shown in Table
• It goes low for the data transfers over D15 – D8 and is used to
derive chip selects of odd address memory bank or peripherals.
• BHE is low during T1 for read, write and interrupt acknowledge
cycles, whenever a byte is to be transferred on the higher byte of
the data bus. BHE A0 Indication
0 0 Whole word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None
• The status information is available during T2,
T3 and T4.
• The signal is active low and is tri-stated during
“Hold”.
• It is low during T1 for the first pulse of the
interrupt acknowledge cycle. S7 is not
currently used.
RD – READ
• Read signal, when low, indicates the
peripherals that the processor is performing a
memory or I/O read operation.
• RD is active low and shows the state for T2,
T3, Tw of any read cycle.
• The signal remains tri-stated during the ‘HOLD
Acknowledge’
READY
• This is the acknowledgement from the slow devices or
memory that they have completed the data transfer.
• This is an input signal to the 8086.
• This signal is active high.
INTR – Interrupt request
• This is a level triggered input
• This is sampled during the last clock cycle of each
instruction to determine the availability of the request
• If any interrupt request is pending the processor enters
the interrupt acknowledge cycle.
• This can be internally masked by resetting the
interrupt enable flag.
• This signal is active high.
TEST
• This input is examined by a ‘wait’ instruction.
• If the TEST input goes low, execution will
continue, else, the processor remains in an
idle state.
NMI – Non-maskable Interrupt.
• This is an edge triggered input which causes a
type 2 interrupt.
• The NMI is not maskable internally by
software.
• A transition from low to high initiates the
interrupt response at the end of the current
instruction.
RESET
• This input causes the processor to terminate the
current activity and start execution from FFFF0H
• The signal is active high and must be active for at least
four clock cycles.
CLK – Clock Input
• The clock input provides the basic timing for processor
operation and bus control activity.
• It’s an asymmetric square wave with 33% duty cycle.
• The range of frequency for different 8086 versions is
from 5 MHz to 10 MHz.
Vcc
• 8086 requires +5V power supply for the
operation of the internal circuit.
GND
• This is the ground for the internal circuit.
MN/MX.
• The logic level at this pin decides whether the
processor is to operate in either minimum (Single
processor) or maximum (multi processor) mode.
The following pin functions are for the minimum
mode operation of 8086.
M/I/O – Memory/IO
• This is a status line logically equivalent to S2 in the
maximum mode.
• Low – I/O operation
High – Memory operation.
• This line becomes active in the previous T4 and
remains active till final T4 of the current cycle.
• It is tri-stated during local bus “hold acknowledge”
INTA – Interrupt acknowledge
• This signal is used as a read strobe for interrupt
acknowledge cycles
• In other words, when it goes low, it means that the
processor has accepted the interrupt.
• It is active low during T2,T3 and Tw of each interrupt
acknowledge cycle.
ALE – Address Latch Enable
• This output signal indicates that availability of the valid
address on the address / data lines, and is connected to
latch enable input of latches
• This signal is active high and is never tri-stated.
DT/R – Data Transmit / Receive
• This output is used to decide the direction of data
flow through the transreceivers (bidirectional
buffers).
• Data transmission – signal is high.
data receiving – signal is low.
• Logically, this is equivalent to S1 in maximum
mode.
• It’s timing is the same as M/I/O.
• This is tri-stated during ‘hold acknowledge’
DEN – Data Enable
• This signal indicates the availability of valid data
over the address / data lines.
• It is used to enable the transreceivers to separate
the data from the multiplexed address / data
signal.
• It is active from the middle of T2 until the middle
of T4.
• DEN is tri-stated during hold acknowledge cycle
HOLD, HLDA – Hold, Hold Acknowledge
• When the HOLD line goes high, it indicates to the
processor that another master is requesting the bus
access.
• The processor, after receiving the HOLD request, issues
the HOLD acknowledge signal on HLDA pin, in the
middle of the next clock cycle after completing the
current bus cycle. At the same time, the processor
floats the local bus and control lines.
• When the processor detects the HOLD line low, it
lowers the HLDA signal.
The following pin functions are applicable for maximum mode
operation of 8086.
S2, S1, S0 – status lines
• These are the status lines which indicate the type of
operation, being carried out by the processor.
• These become active during T4 of the previous cycle and
remain active during T1 and T2 of the current bus cycle.
• The status lines return to passive state during T3 of the
current bus cycle so that they may again become active for
the next bus cycle during T4.
• The various operations indicated by these status lines are
given in the table 1.3.
Table 1.3
S2 S1 S0 Indication
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
LOCK
• This output pin indicates that other system bus masters
will be prevented from gaining the system bus, while
LOCK signal is low.
• The LOCK signal is activated by the ‘LOCK’ prefix
instruction and remains active until the completion of
the next instruction.
• This floats to tri-state off during ‘hold acknowledge’
• When CPU is executing a critical instruction which
requires the system bus, the LOCK prefix instruction
ensure that other processors connected in the system
will not gain the control of the bus.
QS1, QS0 – Queue Status
• These lines give information about the status
of the code-prefetch queue.
• These are active during the CLK cycle after
which the queue operation is performed
• These lines indicate various operations as
indicated in the table 1.4.
Table 1.4
QS1 QS0 Indication
0 0 No Operation
0 1 First byte of opcode from the queue
1 0 Empty queue
1 1 Subsequent byte from the queue
• This simultaneous fetching and executing of

instructions is called pipe-lining. This results in
faster execution.
RQ/GT0, RQ/GT1 – REQUEST/GRANT
• These pins are used by other local bus masters in
maximum mode, to force the processor to
release local bus at the end of processor’s current
bus cycle.
• Each of the pins is bidirectional with RQ/GT0
having the higher priority than RQ/GT1.
• The request and grant pulses are active low.
• RQ/GT pins have internal pull up resistors and
may be left unconnected.
8086 Interrupts
Interrupt is the method of creating a temporary halt during
program execution and allows peripheral devices to access the
microprocessor. The microprocessor responds to that interrupt
with an ISR (Interrupt Service Routine), which is a short
program to instruct the microprocessor on how to handle the
interrupt.
Hardware Interrupts
 Hardware interrupt is caused by any peripheral device by sending a
signal through a specified pin to the microprocessor.
 The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a
non-maskable interrupt and INTR is a maskable interrupt having lower
priority. One more interrupt pin associated is INTA called interrupt
acknowledge.
NMI
 It is a single non-maskable interrupt pin (NMI) having higher priority
than the maskable interrupt request pin (INTR)and it is of type 2
interrupt.
INTR
• The INTR is a maskable interrupt because the microprocessor will be
interrupted only if interrupts are enabled using set interrupt flag
instruction. It should not be enabled using clear interrupt Flag
instruction.
Software Interrupts
• Some instructions are inserted at the desired position into the

program to create interrupts.
• These interrupt instructions can be used to test the working of
various interrupt handlers.
• INT- Interrupt instruction with type number It is 2-byte

instruction. First byte provides the op-code and the second
byte provides the interrupt type number. There are 256
interrupt types under this group.
• The starting address for type0 interrupt is 000000H, for type1

interrupt is 00004H similarly for type2 is 00008H and ……so on.
The first five pointers are dedicated interrupt pointers. i.e. −
TYPE 0 interrupt represents division by zero situation.
TYPE 1 interrupt represents single-step execution during the

debugging of a program.
TYPE 2 interrupt represents non-maskable NMI interrupt.
TYPE 3 interrupt represents break-point interrupt.
TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other

advanced microprocessors, and interrupts from 32 to Type 255
are available for hardware and software interrupts.

MPMC Unit 1

Uploaded by

Document Informationclick to expand document information

Copyright:

Available Formats

MPMC Unit 1

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MPMC Unit 1

Uploaded by

Copyright:

Available Formats

Microprocessors & Microcontrollers (EC501PC)

UNIT -I: (13 Concepts)

– Allows the placing of the code, data, and stack portions of

• This simultaneous fetching and executing of

• Some instructions are inserted at the desired position into the

• INT- Interrupt instruction with type number It is 2-byte

• The starting address for type0 interrupt is 000000H, for type1

TYPE 0 interrupt represents division by zero situation.

TYPE 1 interrupt represents single-step execution during the

TYPE 2 interrupt represents non-maskable NMI interrupt.

TYPE 3 interrupt represents break-point interrupt.

TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other

You might also like