Alliance College of Engineering Design

Department of Computer Science

and Engineering.
&
Information Technology

Lab Manual

Digital System Design

Class: B Tech CSE and IT

Semester: IV
Lab: LT 202
 Alliance College of Engineering and Design

Digital System Design Laboratory Certificate

This is to certify that Mr/Ms._________________________________________ __has

satisfactorily completed the course of experiments in practical Digital System Design

Prescribed by Department of Computer Science and Engineering, Alliance College of

Engineering and Design, Alliance University in the Laboratory of this college in the

year ______

Signature of the Faculty in charge

Signature of the HoD

Date:
 CONTENTS
Digital Trainer Kit

1. Design and implementation of Logic Gates

2. Design and implementation of SOP and POS terms
3. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and voice versa
(ii) Binary to gray and vice-versa
4. Design and implementation of 4 bit binary Adder/ subtractor and BCD adder using
IC 7483
5. Design and implementation of Multiplexer and De-multiplexer using logic gates and
study of IC74150 and IC 74154
6. Design and implementation of encoder and decoder using logic gates and study of
IC7445 and IC74147
7. Recognition and verification of different Flipflop and latches
8. Construction and verification of 4 bit ripple counter and Mod-10 / Mod 12 Ripple
counters
9. Design and implementation of 3-bit synchronous up/down counter
10.Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops.
11.Write and execute Assembly language program using different addressing modes
and copying a set of data from source memory location to destination for 8086
Processor.
12.Write and execute Assembly language program to perform different I/O
operations using 8051 Microcontroller.
EXP NO. :
DATE :

DESIGN AND IMPLEMENTATION OF LOGIC GATES

Aim:-
Introduction to digital electronics lab - nomenclature of digital ICs,
specifications, study of the data sheet, concept of Vcc and ground, verification of
the truth tables of logic gates using TTL ICs.
Apparatus Required:-
Digital lab kit, single strand wires, breadboard, TTL IC’s

Gates IC NO.

AND 7408

OR 7432

NAND 7400

NOR 7402

NOT 7404

XOR 74136

Theory:-
Logic gates are idealized or physical devices implementing a Boolean function,
which it performs a logical operation on one or more logical inputs and produce
a single output. Depending on the context, the term may refer to an ideal logic
gate, one that has for instance zero rise time and unlimited fan out or it may refer
to anon-ideal physical device.

The main hierarchy is as follows:-

1. Basic Gates

2. Universal Gates

3. Advanced Gates

Basic Gates
1. AND gate: - Function of AND gate is to give the output true when both the inputs are
true. In all the other remaining cases output becomes false. Following table justifies the
statement:-

Input A Input B Output

1 1 1
 1 0 0

0 1 0

0 0 0

IC 7408

2. OR gate: - Function of OR gate is to give output true when one of the either inputs are
true .In the remaining case output becomes false. Following table justify the statement:-

Outpu
Input A Input B
t
0 0 0

0 1 1

1 0 1

1 1 1
 IC 7432

3. NOT gate: -Function of NOR gate is to reverse the nature of the input .It converts
true input to false and vice versa. Following table justifies the statement :-

Input Output

1 0

0 1

IC 7404
Universal Gates
1. NAND gate: -Function of NAND gate is to give true output when one of the two
provided input are false. In the remaining output is true case .Following table justifies
the statement :-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 1

IC 7400

2. NOR gate: - NOR gate gives the output true when both the two provided input are
false. In all the other cases output remains false. Following table justifies the statement

Input A Input B Output

1 1 0

1 0 0

0 1 0

0 0 1
Advanced Gates IC 7402

1. XOR gate: - The function of XOR gate is to give output true only when both the
inputs are true. Following table explain this:-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 0

IC 74136
Exclusive NOR Gate: IC 74266

Symbol Truth Table

B A Q

0 0 1

0 1 0

1 0 0
2-input Ex-NOR Gate
1 1 1

Read if A AND B the SAME

Boolean Expression Q = A ⊕ B
gives Q
Procedure:-
• Place the breadboard gently on the observation table.
• Fix the IC which is under observation between the half shadow line of
breadboard, so there is no shortage of voltage.
• Connect the wire to the main voltage source (Vcc) whose other end is connected to
last pin of the IC (14 place from the notch).
• Connect the ground of IC (7th place from the notch) to the ground terminal
provided on the digital lab kit.
• Give the input at any one of the gate of the ICs i.e. 1st, 2nd, 3rd, 4th gate by using
connecting wires.(In accordance to IC provided).

• Connect output pins to the led on digital lab kit.

• Switch on the power supply.

• If led glows red then output is true, if it glows green output is false, which is
numerically denoted as 1 and 0 respectively. The Color can change based on the IC
manufacturer it’s just verification of the Truth Table not the color change.

Result:-
All gates are verified. Observed output matches theoretical concepts.
EXP NO. :
DATE :

DESIGN AND IMPLEMENTATION SOP AND POS

Aim:-Implement of the given Boolean function using logic gates in both SOP and
POS forms
Two input SOP - A.B + A’.B’
Two input POS: - (A+B) (B+C) (A+C’)

Apparatus required:-Digital Lab Kit, Single Strand Wires, ICs, breadboards, Connecting
Wires.
Theory:-
a) SOP: - It is the Sum of product form in which the terms are taken as 1. It is denoted in
the K-map expression by sigma (∑)

A.B. + A’B’

Logic Circuit Of this expression:-

Truth Table for this SOP expression

A B A’ B’ A.B A’.B’ Y= AB’ + AB’

0 0 1 1 0 1 1
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 1 0 0 1 0 1
 b) POS: - It is the product of the sums form in which the terms are taken as 0. It is denoted in the K-
Map expression by the Sign pie (π)

(A+B) (B+ C) (A + C’)

Circuit Diagram

Y B OR

AND AND

C OR

CNOT

NOT OR

Truth Table foe POS expression

A B C A+B B+C A+C’ Y= (A+B)(B+C)(A+C’)

0 0 0 0 0 1 0
0 0 1 0 1 0 0
0 1 0 1 1 1 1
0 1 1 1 1 0 0
1 0 0 1 0 1 0
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1
Procedure: -
For SOP form: - A.B + A’.B’

1. Place the Digital lab kit at one place.

2. Take the one AND gate ICs i.e. IC no.7408, one NOT gate IC i.e. IC no. 7404 and one OR gate IC i.e. IC
no. 7432.
3. Place these 3 ICs in the breadboard one by one.
4. Now, connect the AND gate with the inputs of A and B and other AND gate in the same IC is given by the
complement input of the A and B i.e. A’ and B’ by using NOT gate with the help of connecting wires.
5. Give the output voltage Vcc and GROUND to all the ICs separately.
6. When whole configuration is read, gently on the switch and note there output of different values of A and
B i.e. either 0 or 1.
 For POS form :- (A+B)(B+C)(A+C’)

1. Place the Digital lab kit at one place.

2. Take the 1 OR, 1 AND, 1 NOT gates IC
3. Place these 3 ICs in the breadboard one by one.
4. Now, connect the OR gate of Input A or B, B or C and last one is A or C’ (i.e. complement of C using NOT
gate. Inputs are connected with the help of connecting wires.
5. When whole circuit is complete, on the switch and note down the output with different values of A, B and
C.

Result:-Hence, given Boolean Expression is implemented by the Logic Gates.

i.e. (i) A.B + A’.B’

(ii) (A+B) (B+C) (A+C’)

EXP NO. :
DATE :

DESIGN AND IMPLEMENTATION OF CODE CONVERTORS

AIM:
To design and implement 4-bit.
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter.
(iv) Excess-3 to BCD code converter
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. XOR Gate IC 7486 1
2. AND Gate IC 7408 1
3. OR Gate IC 7432 1
4. NOT Gate IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
Code is a symbolic representation of discrete information. Codes are of different types.
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes
for same information. Thus, code converter is a circuit that makes the
two systems compatible even though each uses different binary code.
Gray Code is one of the most important codes. It is a non-weighted code
which belongs to a class of codes called minimum change codes. In this codes
while traversing from one step to another step, only one bit in the code group
changes. In case of Gray Code two adjacent code numbers differs from each
other by only one bit.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as G3, G2, G1, G0. From the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output
variable. A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the k - map.
BINARY TO GRAY CODE CONVERTER:

TRUTH TABLE:

Binary Input Gray code output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR
K-Map for G3:

G3 = B3

K-Map for G2:

K-Map for G1:

 K-Map for G0:

Gray Code to Binary Code Converter:

TRUTH TABLE:

Gray code input Binary output

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

B3 = G3
K-Map for B2:

K-Map for B1:

K-Map for B0:

BCD to Excess-3 Code Converter:

TRUTH TABLE:

BCD input Excess - 3 output

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR
K-Map for E3:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

K-Map for E1:

K-Map for E0:

Excess – 3 to BCD Code Converter:
TRUTH TABLE:

Excess - 3 input BCD output

X4 X3 X2 X1 A B C D

0 0 0 0 x x x x
0 0 0 1 x x x x
0 0 1 0 x x x x
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1
 K-Map for B:

K-Map for C:

K-Map for D:
PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs are given through switches as per truth table

(iii) Logical output values are observed in the LED outputs and verified with the truth

tables.

RESULT:

Thus the code convertors circuits were designed using logic gates and their truth table were
verified.
EXP NO. : DESIGN OF 4-BIT ADDER AND SUBTRACTOR
DATE :

AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.
It can be constructed with full adders connected in cascade, with the output carry from
each full adder connected to the input carry of next full adder in chain. The augends
bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to
left, with subscript 0 denoting the least significant bits. The carries are connected in
chain through the full adder. The input carry to the adder is C0 and it ripples through
the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between
each data input ‘B’ and the corresponding input of full adder. The input carry C0 must
be equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one common
binary adder. The mode input M controls the operation. When M=0, the circuit is adder
circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be
greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must
be represented in BCD and should appear in the form listed in the columns.
An BCD adder that adds 2 BCD digits and produce a sum digit in BCD format. The
2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce
the binary sum.
PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
LOGIC DIAGRAM: 4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR

Function table:

Input Data A Input Data B Addition Subtraction LOGIC

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 1 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0

1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 0 1

1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 1
DIAGRAM: BCD ADDER
TRUTH TABLE FOR SUM GREATER THAN 9:

BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
K MAP :

Y = S4 (S3 + S2)
PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
RESULT:

Thus the 4 bit binary adder, 4 bit binary subtractor and BCD adder
were designed using logic gates and their truth table was verified.
EXP NO. :
DATE :

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DEMULTIPLEXER

AIM:
To design and implement 4-to-1 multiplexer and 1-to-4 demultiplexer using logic gates.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational
circuit that selects binary information from one of many input lines and directs
it to a single output line. The selection of a particular input line is controlled
by a set of selection lines. Normally there are 2n input line and n selection lines
whose bit combination determine which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also
be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates.
The data select lines enable only one gate at a time and the data on the data
input line will pass through the selected gate to the associated data output line.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:
PIN DIAGRAM OF IC7411:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:

TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74150: 16-to-1 Multiplexer

\
PIN DIAGRAM FOR IC 74154: 1-to-16 Demultiplexer

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus the multiplexer and de-multiplexer circuit was designed using logic gates and their
truth table was verified.
EXP NO. : DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER
DATE :

AIM:
To design and implement encoder and decoder using logic gates.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P NAND GATE IC 7411 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY: ENCODER
An encoder is a digital circuit that performs inverse operation of a decoder. An encoder
has 2n input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three output that generate the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero
outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code
word i.e., there is one to one mapping can be expressed in truth table. In the block diagram of
decoder circuit the encoded information is present as n input producing 2n possible outputs.
2n output values are from 0 through out 2n – 1.
TRUTH TABLE: OCTAL TO BINARY ENCODER
INPUT (OCTAL) OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
LOGIC DIAGRAM FOR ENCODER:
TRUTH TABLE: 2 TO 4 DECODER WITH ENABLE

INPUT OUTPUT
EN A B D0 D1 D2 D3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

LOGIC DIAGRAM: 2 TO 4 DECODER

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus the encoder and decoder circuit was designed using logic gates and their truth
table was verified.
EXP NO. :

DATE :
RECOGNITION AND VERIFICATION OF FLIPFLOP

Aim: -Verification of state tables of

1. R-S flip-flop
2. J - K flip-flop
3. T Flip-Flop
4. D Flip-Flop

Using NAND and NOR gates.

Apparatus:- IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7408 (AND Gate).

Theory: -In case of sequential circuits the effect of all previous inputs on the
outputs is represented by a state of the circuit. Thus, the output of the circuit at any time
depends upon its current state and the input. These also determine the next state
of the circuit. The relationship that exists among the inputs, outputs, present states
and next states can be specified by either the state table or the state diagram.
State Table: -The state table representation of a sequential circuit consists of three
sections labelledpresent state next stateand output. T he p r e sen t s t a t e
d e s i gn a t e s t h e s t a t e o f f l i p - f l op s be f o re t h e occurrence of a clock pulse.
The next state shows the states of flip-flops after the clock pulse, and the output
section lists the value of the output variables during the present state.

Flip-Flop:-The basic one bit digital memory circuit is known as flip-flop.It can store either
0or 1. Flip-flops are classifieds according to the number of inputs.

R-S Flip-Flop:- The circuit is similar to SR latch except enable signal is replaced by clock
pulse.
Logic Diagram

Characteristic table for S-R flip flop

D Flip-Flop:-The modified clocked SR flip-flop is known as D-flip-flop. From the truth

table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable state
when the inputs are same and high. In many practical applications, these input conditions
are not required. These input conditions can be avoided by making then complement of
each other.
Logic Diagram

Characteristic table for D flip flop

J-K Flip-Flop:- In a RS flip-flop the input R=S=1 leads to an indeterminate output. The
RSflip-flop circuit may be re-joined if both inputs are 1 than also the outputs are
complement of each other.

Logic Diagram

Characteristic table for J-K flip flop

 T Flip-Flop:-T flip-flop is known as toggle flip-flop. The T flip-flop is modification of
the J-K f l i p - f l op . Bot h t h e J K i np ut s of t h e J K f l i p - f l o p a r e h e l d a t
l o gic 1 an d t h e c l oc k s i gn a l continuous to change.

Logic Diagram

Characteristic table for T flip flop

Procedure:-
1. Co nn e c t i o n s a r e m a d e as p er ci rc ui t di a gr a m.

2. Verify truth-tables for various combinations of input.

RESULT: -Study and verified truth-tables of various flip-flops.

EXP NO. :

DATE :
CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 10/MOD 12
RIPPLE COUNTER

AIM: To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. A specified sequence of states appears as counter
output. This is the main difference between a register and a counter. There are two types of counter,
synchronous and asynchronous. In synchronous common clock is given to all flip flop and in asynchronous
first flip flop is clocked by external pulse and then each successive flip flop is clocked by Q or Q output
of previous stage. A soon the clock of second stage is triggered by output of first stage. Because of inherent
propagation delay time all flip flops are not activated at same time which results in asynchronous
operation.
PIN DIAGRAM FOR IC 7476:
Equivalent Diagram:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

 TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1

LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:
QA QB QC QD
CLK
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

 TRUTH TABLE:
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the 4 bit ripple counter (Modulus 16), mod -10 ripple counter and mod- 12 ripple counter
circuits were designed using JK flip-flops and their output was verified.
 EXP NO. :
DATE :
DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP / DOWN COUNTER
AIM: To design and implement 3 bit synchronous up / down counter using JK flip-flops and logic
gates.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. In synchronous counters, the clock inputs
of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-
flops change state simultaneously (in parallel). An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down
counter is also called bidirectional counter. Usually up/down operation of the counter is controlled
by up/down signal. When this signal is high counter goes through up sequence and when up/down
signal is low counter follows reverse sequence.
PIN DIAGRAM FOR IC 7476:
LOGIC DIAGRAM: 3 – BIT SYNCHRONOUS UP / DOWN COUNTER
 TRUTH TABLE:
Up Counter Down Counter
CLK QA QB QC QA QB QC
0 0 0 0 1 1 1
1 0 0 1 1 1 0
2 0 1 0 1 0 1
3 0 1 1 1 0 0
4 1 0 0 0 1 1
5 1 0 1 0 1 0
6 1 1 0 0 0 1
7 1 1 1 0 0 0
8 0 0 0 1 1 1

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus Up counter and Down counter was designed successfully using IC 7476 and its truth table
was verified successfully.
EXP NO. :
DATE :

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM: To design and implement the following types of shift registers using D flip-flops.
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions is known as shift
register. The logical configuration of shift register consist of a D-Flip flop cascaded with output
of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses
which causes the shift in the output of the flip flop. The simplest possible shift register is one that
uses only flip flop. The output of a given flip flop is connected to the input of next flip flop of the
register. Each clock pulse shifts the content of register one bit position to right.

PIN DIAGRAM: IC7474 Dual D Flip-flop with Preset and Clear

 EQUIVALENT DIAGRAM: IC7474 Dual D Flip-flop

LOGIC DIAGRAM: SERIAL IN SERIAL OUT

TRUTH TABLE:

CLK Serial in Serial out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
LOGIC DIAGRAM: SERIAL IN PARALLEL OUT
 TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGIC DIAGRAM: PARALLEL IN SERIAL OUT

TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
 LOGIC DIAGRAM: PARALLEL IN PARALLEL OUT

TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:

Thus the various shift registers were designed successfully using flip-flops and their truth tables
were verified successfully.
Expt. No:
Date:
Aim: To write and execute Assembly language program using different addressing modes
and copying a set of data from source memory location to destination for 8086 Processor.
Components:

8086 Microprocessor, Power supply unit.

Source Memory location: 4100H

Destination Memory Location: 4500H

Data Input:

Memory location Operand

4100 01

4101 02

4102 03

4103 04

4104 05

4105 06

4106 07

4107 08

4108 09

4109 10

Program: Without overlapping the memory location

 Instruction Register Operand

MOV SI 4100

MOV DI 4500

MOV CX 0A

MOV AL [SI]

MOV [DI] AL

INC SI

INC DI

DEC CX

JNZ 41009

INT 03

Data Output

Memory location Operand

4500 01

4501 02

4502 03

4503 04

4504 05

4505 06

4506 07

4507 08

4508 09

4509 10
Program: By overlapping the memory location

Data Input:

Memory location Operand

4100 01

4101 02

4102 03

4103 04

4104 05

4105 06

4106 07

4107 08

4108 09

4109 10

program: Without overlapping the memory location

Instruction Register Operand

MOV SI 4101

MOV DI 450C

MOV CX 0A

MOV AX [SI]

MOV [DI] AX

DEC SI

DEC DI

DEC CX

JNZ NEXT

INT 03
Data Output

Memory location Operand

4103 01

4104 02

4105 03

4106 04

4107 05

4108 06

4109 07

410A 08

410B 09

410C 10

Result:

The results are verified by verifying the memory locations.

EXPT No:
Date:
Aim: Write and execute an Assembly language program to perform different I/O
operations using 8051 Microcontroller (To write an assembly program to make the
stepper motor run in forward and reverse).

Components: 8051 Microcontroller, stepper motor, Power supply

Program:
Algorithm:
1. Fix the DPTR with the Latch Chip address FFC0
2. Move the values of register A one by one with some delay based on the 2-
Phase switching Scheme and repeat the loop.
3. For Anti Clockwise direction repeat the step 3 by reversing the value
sequence.
4. End the Program

Memory Label Opco Mnemonics Comments

Location de
4100 90 FF MOV DPTR, #FFC0
C0
4103 74 09 MOV A, #09

4105 F0 MOVX @DPTR, A

4106 12 45 LCALL DELAY

00
4109 74 05 MOV A, #05

410B F0 MOVX @DPTR, A

410C 12 45 LCALL DELAY

00
410F 74 06 MOV A, #06

4111 F0 MOVX @DPTR, A

4112 12 45 LCALL DELAY

00
4115 74 0A MOV A, #0A

4117 F0 MOVX @DPTR, A

4118 12 45 LCALL DELAY
00
 411B 80 E3 SJMP 4100

4500 DELA 78 55 MOV R0, #55

Y:
4502 L2 79 FF MOV R1, #FF

4504 L1 D9 DJNZ R1, L1

FE
4506 D8 DJNZ R0, L2
FA
4508 22 RET

Result:
The direction of rotation of the stepper motor changes as the data bit in the port changes