VLSI Design Automation

Introduction

http://sist.shanghaitech.edu.cn/faculty/zhoupq/Teaching/Spr16/eda.html
 Logistics
 Course page:
http://sist.shanghaitech.edu.cn/faculty/zhoupq/Teaching/Spr16/eda.html
 Time: Monday/Thursday, 3:00-4:40pm
 Location: H2-315

 Instructor: Pingqiang Zhou

 Email: [email protected]
 Office hour: Thursday, 5:00 – 6:00 pm, or by appointment
 Venue: H2-213.
 TA
 Still looking for …

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 Textbook for Reference (Not Required)
 “Electronic Design Automation: Synthesis,
Verification, and Test (Systems on Silicon),” by
Laung-TerngWang,Yao-Wen Chang, and Kwang-
Ting Cheng, Morgan Kaufmann Publishing, 2009.

 “Logic Synthesis and Verification Algorithms,” by

Gary Hachtel and Fabio Somenzi, Springer
Publishing,1996.
 “VLSI Physical Design Automation,” by Sadiq Sait
and Habib Youssef, World Scientific Publishing,
1999.

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 Grading
 Composition (tentative)
 5 written assignments: 20%
 2 programming assignments: 30%
 2 paper reviews: 20%
 Final exam or project: 30%

 Questions about the grading?

 Must contact the instructor within one week after receiving the
item.

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 Rules
 Each written assignment must be turned in before class on each
due date.
 Each programming assignment (PA) must be turned in by 11:59
pm on the due date to be accepted for full credit.
 However, we still allow you to submit your PA within 3 days after the
due date, but there is a late penalty.
Hours Late Scaling Factor
(0, 24] 80 %
(24, 48] 60 %
(48, 72] 40 %
 No PA will be accepted if it is more than 3 days late!
 You can discuss homework with your classmates. BUT what you
submit must be your own work.
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 Suggestions
 Read the lecture notes before & after the lecture

 Taking notes in class is a good idea.

 Start your programming assignment early!

 Back up your code frequently in case your computer crashes.

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 What Background Do You Need?
 Computer science  Mathematics
 Basic programming skills  Discrete mathematics: basic
(C/C++) sets, Boolean logic,
 Data structures and algorithms combinatorics
 Exposure to graph theory is
nice but not essential
 Computer engineering
 Continuous: basic calculus,
 Basic digital design (gates, flip
linear algebra, matrix
flops, Boolean algebra)
 Combinational and sequential
logic design  Basic VLSI knowledge
 Some chip layout exposure is
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nice, but not essential
 What’s this Course About?
 Computer-aided design (CAD) tools for very large scale
integrated (VLSI) circuits.
 Indeed, we focus on the algorithms.
 CAD is also known as electronic design automation (EDA).

VLSI CAD tools

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 What is The Class NOT About?
 It is NOT a circuit class – although we will mention circuits
many times
 Not a digital design or VLSI design class, in the sense that we
design a system or a chip

 Instead, we design software for CAD tools

 But it is not just a hacking class: there is some nontrivial math to
explain what our CAD tools are doing

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 You should be taking this course if
 you are interested in building VLSI design tools;

 you are interested in designing VLSI chips, and you want to know
why the tools do what they do;

 you just like cool algorithms, that work on big cool problems that
involve bits, and gates, and geometry, and graphs, and matrices,
and time, and...

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 IC Design Steps
High-Level Register-Transfer-
Specifications Level Description
Description

SystemC Verilog
SystemVerilog VHDL

module mux( input a,

input b, input sel,
output z, output zbar);
assign z = sel ? b : a;
assign zbar = z;
endmodule
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 IC Design Steps
High-Level Register-Transfer-
Specifications Level Description
Description

Fabrication Physical Design Gate Level Design

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 Two Major Components of this Course

High-Level Register-Transfer-
Specifications Level Description
Description

Logic Synthesis
Layout Synthesis

Fabrication Physical Design Gate Level Design

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 The Focus of Our Course
 Start with some Boolean / logic
Logic Synthesis design description …
 …end with gates+wires, located at
Logic Verification (x,y) coordinates on chip

Layout Synthesis  Big goals

 Explain the critical algorithms, data
Timing Verification structures, and modeling assumptions
used in each of these big steps

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 Course Topics (Tentative)
 Basic algorithms and complexity theory
 Logic Synthesis
 Computational Boolean Algebra
 Binary Decision Diagram (BDD)
 Boolean Satisfiability
 Two-Level Logic Synthesis
 Multi-Level Logic Synthesis
 Technology Mapping
 Layout Synthesis
 Placement
 Routing
 Timing Analysis
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 References and Copyright
 Slides used (Modified when necessary)
 Rob Rutenbar, University of Illinois at Urbana-Champaign
 Kia Bazargan, University of Minnesota
 Hai Zhou, Northwestern University

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 Reading Assignment
 Chapter 1 of

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 Questions?

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