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Digital Integrated Circuits

A Design Perspective

Manufacturing Process

53

A Modern CMOS Process

gate-oxide

TiSi2 AlCu

SiO2
Tungsten

poly
p-well n-well SiO2
n+ p-epi p+

p+

Dual-Well Trench-Isolated CMOS Process

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Transistor Layout

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Circuit Under Design

VDD VDD

M2
M4

Vin Vout Vout2

M1 M3

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Its Layout View

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Photo-Lithographic Process

optical
mask
oxidation

photoresist photoresist coating

removal (ashing)
stepper exposure

Typical operations in a single

photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process spin, rinse, dry
step

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Patterning of SiO2

Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2 (d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2

(b) After oxidation and deposition Hardened resist

of negative photoresist SiO
2
Si-substrate
UV-light
Patterned (e) After etching
optical mask

Exposed resist
SiO
2

Si-substrate Si-substrate

(f) Final result after removal of resist

(c) Stepper exposure

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CMOS Process at a Glance

Define active areas

Etch and fill trenches

Implant well regions

Deposit and pattern

polysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windows

Deposit and pattern metal layers

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Fabrication Procedure Flow: Basic Steps

 Each Processing steps in the fabrication procedure requires to define certain area on the chip. This is
known as Masks.
 Chips are specified with set of masks
 Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
 Feature size l = distance between source and drain
 Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design rules
 The ICs are viewed as a set of pattern layers of doped Silicon, Polysilicon, Metal and Insulating Silicon
Dioxide.
 A layer must be Patterned before the next layer of material is applied on the chip

61

Inverter Cross-section
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors

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Inverter Cross-section with Well and Substrate taps

 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors
 Substrate must be tied to GND and n-well to VDD
 Metal to lightly-doped semiconductor forms poor connection called Shottky Diode
 Use heavily doped well and substrate contacts / taps

63

Inverter Mask Set

 Transistors and wires are defined by masks
 Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

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Detailed Mask Views

 Six masks
 n-well
 Polysilicon
 n+ Diffusion
 p+ Diffusion
 Contact
 Metal

65

Fabrication
 Chips are built in huge factories called fabs
 Contain clean rooms as large as football fields

Courtesy of International Business Machines Corporation.

Unauthorized use not permitted.

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Fabrication Steps
 Start with blank wafer
 Build inverter from the bottom up
 First step will be to form the n-well
 Cover wafer with protective layer of SiO2 (oxide)
 Remove layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer
 Strip off SiO2

p substrate

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Oxidation
 Grow SiO2 on top of Si wafer
 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

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Photolithography

photoresist coating

Exposure Processes

69

Photoresist
 Used for lithography .
 Lithography is a process used to transfer a pattern to layer on the chip. Similar to printing process.
 Spin on photoresist (about 1 mm thickness)
 Photoresist is a light-sensitive organic polymer
 Positive Photoresist: Softens where exposed to light
 Negative Photoresist: Harden where exposed to light, Not used in practice generally

Photoresist
SiO2

p substrate

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Lithography
 Expose photoresist through n-well mask
 Strip off exposed photoresist

Photoresist
SiO2

p substrate

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Etch
 Etch oxide with hydrofluoric acid (HF)
 Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

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Strip Photoresist
 Strip off remaining photoresist
 Use mixture of acids called piranah etch
 Necessary, so resist doesn’t melt in next step

SiO2

p substrate

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n-well
 n-well is formed with diffusion or ion implantation
 Diffusion
 Place wafer in furnace with arsenic gas
 Heat until As atoms diffuse into exposed Si
 Ion Implantation
 Blast wafer with beam of As ions
 Ions blocked by SiO2, only enter exposed Si

SiO2

n well

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Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps

n well
p substrate

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Polysilicon
 Deposit very thin layer of gate oxide
 < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
 Place wafer in furnace with Silane gas (SiH4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor

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Polysilicon Patterning
 Use same lithography process to pattern polysilicon

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Self-Aligned Process
 Use oxide and masking to expose where n+ dopants should be diffused or implanted
 N-diffusion forms nMOS source, drain, and n-well contact

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N-diffusion
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion
 Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later
processing

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N-diffusion cont.
 Historically dopants were diffused
 Usually, ion implantation today
 But regions are still called diffusion

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N-diffusion cont.
 Strip off oxide to complete patterning step

81

P-Diffusion
 Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate
contact

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Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed

Contact

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Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires

M e ta l

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Advanced Metallization

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From Sand to Semiconductor

86

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Digital Integrated Circuits

A Design Perspective

Design Rules

87

3D Perspective

Polysilicon Aluminum

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Design Rules
• Interface between designer and process engineer
• Guidelines for constructing process masks
• Unit dimension: Minimum line width
• scalable design rules: lambda parameter
• absolute dimensions (micron rules)

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CMOS Process Layers

Layer Color Representation

Well (p,n) Yellow

Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black

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Layers in 0.25 mm CMOS process

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Intra-Layer Design Rules

Same Potential Different Potential

9 2
0
Well or Polysilicon
6
10 2
3 3
Active Metal1
Contact
or Via 2
3 Hole 3
2 2 4
Metal2
Select

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Transistor Layout

Transistor
1

3 2

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Vias and Contacts

2
4
Via
1 1
5
Metal to
Metal to 1 Poly Contact
Active Contact 3 2

2
2

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Select Layer
2
Select
3
2

1
3 3

2 5

Well
Substrate

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CMOS Inverter Layout

GND In VD D

A A’

Out

(a) Layout

A A’
n
p-substrate Field
n+ p+ Oxide
(b) Cross-Section along A-A’

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Layout Editor

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Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

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Sticks Diagram

V DD 3

In Out
 Dimensionless layout entities
 Only topology is important
 Final layout generated by
1 “compaction” program

GND

Stick diagram of inverter

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Digital Integrated Circuits

A Design Perspective

Packaging

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Packaging Requirements

Mechanical:
Reliable and
Thermal: robust
Efficient
Economical: heat removal
Cheap
Electrical:
Low
parasitic

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Bonding Techniques

Wire Bonding

Substrate

Die

Pad

Lead Frame

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Tape-Automated Bonding (TAB)

Sprocket
hole

Film + Pattern Solder Bump

Die
Test
pads
Lead
frame Substrate

(b) Die attachment using solder bumps.

Polymer film

(a) Polymer Tape with imprinted

wiring pattern.

103

Flip-Chip Bonding

Die

Solder bumps
Interconnect
layers

Substrate

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Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

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Package Types

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Package Parameters

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Multi-Chip Modules

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Thank you

109

Digital Integrated Circuits

A Design Perspective

The Inverter

110

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Outlines
Static Ccs
 Voltage Transfer Characteristic
 Noise Margin
Dynamic Ccs
 Propagation Delay
 Power Dissipations

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Digital Integrated Circuits

A Design Perspective

Voltage Transfer Characteristic

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DC Response
DC Response: Vout vs. Vin for a gate
Ex: Inverter
When Vin = 0 Vout = VDD VDD
When Vin = VDD Vout = 0
In between, Vout depends on transistor size and current
By KCL, must settle such that Idsp
 Idsn = |Idsp| Vin Vout
We could solve equations
But graphical solution gives more insight
Idsn

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Transistor Operation
 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
Cutoff?
Linear?
Saturation?

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nMOS Operation

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

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pMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

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I-V Characteristics
 Make pMOS is wider than nMOS such that bn = bp

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PMOS Load Lines

IDn
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp

V out

IDp IDn IDn

Vin=0 Vin=0

V in=1.5 Vin=1.5

V DSp V DSp Vout

VGSp=-1

VGSp=-2.5
Vin = V DD+VGSp Vout = V DD+VDSp
IDn = - IDp

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Load Line Analysis

 For a given Vin:
VDD
 Plot Idsn, Idsp vs. Vout
 Vout must be where |currents| are equal in Vin
Idsp
Vout
Idsn

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

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Load Line Analysis

VDD
 Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD Idsp
Vin Vout
Vin0 Idsn
Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp| Vin1 Vin4

Vin2 Vin3
Vin2 Vin3
Vin3 Vin2
Vin3 Vin2
Vin4 Vin1
Vin4 Vin0
in1
VDD
Vout VDD
Vout

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DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

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Operating Regions
Revisit transistor operating regions

Region nMOS pMOS

A Cutoff Linear
VDD
B Saturation Linear A B

C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

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Switching Threshold as a function of Transistor Ratio

 The switching threshold, VM, is defined as the point where Vin = Vout (both PMOS
and NMOS are always saturated).
 An analytical expression for VM is obtained by equating the currents through the
transistor.

For VDD >>

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Switching threshold Example

In our generic 0.25-µm CMOS process, using the process parameters a VDD = 2.5V, and a
minimum size NMOS device ((W/L)n of 1.5)

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Switching threshold Example

 VM is relativity insensitive to variation in device ratio
 Setting the ratio to 3, 2.5, and 2 gives VM’s of 1.22V, 1.18V, and 1.13V
 Increase the width of the PMOS moves VM towards VDD
 Increase the width of the NMOS moves VM towards GND

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