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Unit 1: IC Fabrication

Lecture 1.2: CMOS Process

Dr. Ganesh Samudra, Dr. Shajith Ali & Dr. R.

Ramaprabha
Department of EEE
SSN College of Engineering, Chennai

IIYear / 4th Sem: UEE2402– Analog Electronic Circuits (AEC)

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Learning Objective

To discuss the CMOS process steps

Outline of the Lecture

• MOSFET basic structure and layout

• Modifications as the channel length shrinks

• Full CMOS process flow with realistic process conditions

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NMOS Physical structure

Physical structure What layout layers will be needed?

Circuit
CVD oxide
Poly gate Metal 1Layout representation Schematic
representation
Source Ldrawn Drain Ldrawn G

S D
n+ n+ Wdrawn
Leffective
B
Gate oxide

p-substrate (bulk)
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NMOS Physical structure

NMOS layout representation:

NMOS physical structure:
Implicit layers:
– p-substrate
» oxide layers
– n+ source/drain
» substrate (bulk)
– gate oxide (SiO2)
Drawn layers:
– polysilicon gate
» n+ regions
– CVD oxide
» polysilicon gate
– metal 1
» oxide contact cuts,
– Leff< Ldrawn (lateral
doping effects) » metal layers
Note that the areas outside the
MOSFET area shown by
rectangle is filled with isolation
oxide.
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PMOS Physical structure

Physical structure What changes to NMOS layers will be needed?

CVD oxide Circuit Schematic
Poly gate Metal 1 Layout representation
representation
Source Ldrawn Drain G
Ldrawn

p+ p+ S D
Wdrawn
Leffective
B
Gate oxide
n-well (bulk) n-well

p-substrate
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PMOS Physical structure
PMOS layout representation:
Implicit layers:
PMOS physical structure: » oxide layers
– p-substrate Drawn layers:
– n-well (bulk) » n-well (bulk)
– p+ source/drain » p+ regions
– gate oxide (SiO2) » polysilicon gate,
– polysilicon gate » oxide contact cuts,
– CVD oxide, metal 1 » metal layers
Note that the areas outside the
MOSFET area shown by
rectangle is filled with isolation
oxide.
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Modifications to the structure as
the channel length scales
• CMOS technology has evolved to 5nm technology. This poses
tremendous challenges. What do you think they will be?
• A single well or substrate is not sufficient.
• Multiple doping levels are needed to meet different performance
specifications.
• Both n- and p-well are needed to meet reliability specifications.
• The threshold adjust implant is needed to get desired threshold
voltage.
• The punch thru implant is required to ensure that Source-Drain
are not shorted to lead to device breakdown due to lateral
diffusion and device phenomena.
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Modifications as the channel
length shrinks
• Polysilicon replaces metal gate and should mimic metal. Hence
very high doping is required to reduce poly resistance as it
increases number of carriers reducing resistivity.
• A single gate polysilicon (poly) doping is not sufficient to achieve
correct threshold voltages for both NMOS and PMOS. NMOS poly
is doped heavily n-type and PMOS poly doped heavily p-type.
• Extremely shallow (<10nm junction depth) Source-Drain region is
required to ensure that Source-Drain are not shorted due to lateral
diffusion and device phenomena. (Why?)
• If all S/D regions are shallow, S/D resistance increases beyond
specifications due to reduced cross-sectional area. (How?)
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Modifications as the channel
length shrinks
• Hence Lightly Doped Drain(LDD) ( above 90nm) or heavily doped
Source Drain Extension (SDE) (below 90nm) regions are
innovatively added for a very short distance near S/D.
• Innovative solutions such as spacers, general self-alignment,
salicide, planarization, Cu metallization, etc are needed for
processes at short channel.
• These will be explained in the process flow.
• Advanced solutions such as strained silicon, modified masks such
as phase shift mask or optical proximity corrections or annular
illumination, Silicon-on-oxide substrate(below 65nm), non-planar
MOSFETs like FinFETs(below 18nm), etc are needed. We will
cover these in the last module in this unit.
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Short Channel CMOS

Process Flow
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INITIAL OXIDE & NITRIDE DEP

Initial ox:
o 20-50nm, dry oxidation
• Oxide strip : (Why this step is done?)
• Pad/stress release ox :
▪ 10-30nm
▪ oxidation at 820ºC
• Nitride :
▪ 200-250nm

200nm Nitride
10nm PAD Oxide
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NITRIDE ETCH
• Shallow Trench Isolation (STI) MASK
• Plasma Etch Nitride/oxide after patterning using mask
• Plasma resist strip by O2 (PRS)
• Chemical resist strip (using sulfuric acid) (CRS)

mask
200nm Nitride
10nm PAD Oxide
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STI ETCH
• STI etch: shallow trench (300-370nm depth) - RIE etcher.
Selectivity. Very good control on Angle and Depth. Selectivity?

• Trench Liner Oxide Clean for growth of oxide layer on trench.

185nm Nitride
10nm PAD Oxide
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HDP DEPOSITION
• Liner ox:
▪ 25-35nm, dry oxidation (purpose?)

• High Density Plasma Oxide Deposition for Gap Fill

▪ 600-700nm
mask

630nm HDP

185nm Nitride
10nm PAD Oxide

25nm Liner Oxide

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CMP
• Oxide Etch MASK ( Previous Slide)
• Oxide etch back outside STI region as oxide much thicker.
Later Chemical Mechanical Polishing (CMP) is done to
remove oxide. If masked oxide etch is not done before
CMP, dishing due to polishing in the STI region will be
more.
• PRS & CRS
• Now do oxide CMP for STI with low dishing.
Dishing < 30nm
140nm Nitride
10nm PAD Oxide
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NITRIDE REMOVAL
• Nitride removal:
▪ HF + H3PO4 at 150ºC
• Sacrificial oxidation:
▪ 20nm, dry oxidation at 850ºC

20nm SAC Oxide

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N-WELL
• N-well MASK
o Implant:
▪ Well: Phosphorus dose 1013cm-2 order / energy 400-600keV
▪ Punch-thru: (What is Punch-thru?) Phosphorus dose 1013cm-2
order / energy 100-150keV
▪ Resist and STI oxide block p-well areas. Self-aligned/robust?
• PRS & CRS
mask

N-pthru

N-Well
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P-WELL
• P-well MASK
• Implant: Self alignment and robustness in many steps.
▪ Well: Boron dose 1013cm-2 order / energy 300-400keV
▪ Anneal / drive-in
▪ Punch-thru: Boron dose 1013cm-2 order / energy 50-100keV
▪ Post Implant Anneal
N
• PRS & CRS

mask

P-pthru
N-Well
N-Well P-Well
P-Well
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PMOS-Vt Adjust
• Vt adjust MASK
o Implant (Why combination not possible?):
▪ Phosphorus dose 1012cm-2 order / energy 20-60keV.
▪ Post implant anneal
• PRS & CRS

mask
N-VT
N-pthru

N-Well P-Well
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NMOS-Vt Adjust
• Vt Adjust Mask
o Implant:
▪ BF2 dose 1012cm-2 order / energy 10-30keV
PRS & CRS
▪ Post Implant Anneal
▪ Substrate representation simplified after this slide but
all 3 substrate engineered regions are there.
• Usually, boron p-type processing always later. Why?

mask
P-VT
P-pthru

N-Well P-Well
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GATE OX
• Gate Oxidation
• Rapid Thermal Oxidation (RTO) to grow 3nm oxide,
950-1050ºC.
• Now on, all substrate implants together will be shown
as wells.
6.5nm
3nm thick
thin gate
gate oxide
oxide 3nm thin gate oxide
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POLY
• Poly Deposition:
▪ 150-300nm at 600ºC
• Poly MASK for protecting P+ poly gate areas
N-Poly Implant: Poly doped N+ here. Only small area
for p-channel gate is not included here as it will
have boron implant. Done with PMOS S/D implant.
▪ Phosphorus, dose 1015cm-2 order/ energy 20-40keV
Will the mask be larger or equal to the gate size?
• PRS & CRS P Implant
mask

250nm Poly
gate oxide

N-Well P-Well
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POLY
• Poly Anneal
o Distributes dopants uniformly
o Densification : 800-850ºC
o Design Rule: Line/Space = 0.18 µm/0.25 µm
• Gate MASK - Nikon Deep Ultra-Violet (DUV)
• Poly etch
• PRS & CRS
• HF Etch to remove oxide.
• Poly Re_Oxidation
o 800-850ºC in O2
mask

Oxide
N-Well P-Well
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NLDD
• NLDD MASK [N MOS]
o Implant:
▪ Boron, pocket implant, dose 1013cm-2 order / energy 5-15keV.
Usually at an angle to prevent punch-through.
▪ As Ldd implant, dose 1013cm-2 order / energy 1-10keV.
Self alignment.
• PRS & CRS

mask

N N

N-Well P-Well
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PLDD
• PLDD MASK [P MOS]
• Implant:
▪ Pocket implant, As dose 1013cm-2 order/energy 60-120keV
▪ Ldd implant, BF2 dose 1014cm-2 order / energy 1-5keV
• PRS & CRS
• Oxide Liner 20nm. Liner not shown later and is
merged in final spacer.
mask
15nm oxide liner

P P N N

N-Well P-Well
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NITRIDE SPACER

• 60-90nm nitride deposition. 20nm liner

not shown below nitride.

>70nm
70nm Nitride
P P N N

N-Well P-Well
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NITRIDE SPACER
• Nitride spacer etch. The spacer width can
be as low as 20nm. Yellow region below
spacer is 20 nm liner, simplified here and
shown same as the gate oxide
• What is the principle?

Nitride Spacer

P P N N

N-Well P-Well
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N+ & P+
• N+
o N+ MASK (NMOS)
o S/D Implant, As dose 1015cm-2 order / energy 50-80keV
o PRS & CRS
• P+
o P+ MASK (PMOS)
o S/D Implant, Boron dose 1015cm-2 order / energy 1-7keV. Why?
o PRS & CRS
o P+ RTA Anneal, dopant activation at 1000-1050ºC. Typically, 20-40s.
High ramp rate spike anneal, laser anneal, explored currently.

N+ mask P+ mask

P+ P+ N+ N+

N-Well P-Well
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Co SALICIDE
• Co/Ti cap deposition
• 1st RTA : 500-550ºC 3060s N2
• Why this step is needed? Self alignment.
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Co SALICIDE
• Salicide EtchBack: . SPM: H2SO4/H2O2
• 2nd RTA : 840-880ºC 30-50s N2
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Salicide Transistor TEM

CoSi2
ILD Nitride

Si3N4
Spacer

Liner TEOS
Poly Gate

30A gate oxide

NMOS PMOS
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INTERLAYER DIELECTRIC
• Nitride Liner deposition
• 350nm 5% B x 5%P BPSG (P/B doped oxide)
• Use?
• Densification at 880ºC
• 1000nm PETEOS (Oxide with TEOS method) deposition
• Oxide CMP for Inter Layer Dielectric (ILD)

1000nm PETEOS

50nm Nitride
350nm SABPSG

P+ P+ N+ N+

N-Well P-Well
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CONTACT ETCH
• Contact MASK
• Contact etch
• 0.21um bottom CD
• PRS + CRS

P+ P+ N+ N+

N-Well P-Well
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W-PLUG
• Barrier for W-plug
25nm Ti/ 30nm TiN
• Annealing at 685ºC
• 330nm W CVD
• W CMP for Inter Metal Dielectric

W Ti/TiN

P+ P+ N+ N+

N-Well P-Well
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METAL1 DEPOSITION
• 25-30nm Ti / 20-30nm TiN / 450-500nm
AlCu / 5-10nm Ti / 20-25nm TiN

5-10nm Ti / 20-
25nm TiN

Met 1 450nm AlCu

25-30nm Ti / 20-
30nm TiN
W Ti/TiN

P+ P+ N+ N+

N-Well P-Well
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METAL1 ETCH
• Metal 1 MASK
• Metal etch
• (Line/Spacing) = 0.20/0.20. Metal slope: vertical.
• Post metal Etch polymer clean, no W plug corrosion

Met 1

P+ P+ N+ N+

N-Well P-Well
 Metal Layer Stack and Dimensions 37

SiN 300nm

HDP 800nm

690nm Met 6
IMD5 900nm

540nm Met 5
IMD4 900nm

540nm Met 4
IMD3 900nm

540nm Met 3
IMD2 900nm

540nm Met 2
IMD1 900nm

540nm Met 1
ILD 650nm CoSi 40nm

Poly 200nm
SiN 50nm

0.11µm 0.32µm 0.10µm

Gox 3.8nm (El.)
 Bonding Pads 38

Over glass and pad openings

• A protective layer is added over the surface. The
protective layer consists of:
• A layer of SiO2
• Followed by a layer of silicon nitride
• The SiN layer acts as a diffusion barrier against
contaminants (passivation)
• Finally, contact cuts are etched, over top metal layer, on
the passivation to allow for wire bonding.
Bonding Pads 39
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Sample Questions

• With the help of cross-section diagrams, explain salicide

formation after S/D formation in CMOS process and how self
alignment is achieved.

• Explain what is self alignment and robustness in a process

and give an example of a part of CMOS process which is self
aligned. Provide detailed explanations.

• Although CMOS Technology uses MOS structure, the gate is

not a metal gate in this process. Explain why.

• Draw a cross-section of short channel NMOSFET and explain

different regions clearly with justification for one of the added
feature to standard long channel MOSFET.
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Summary

• The complete CMOS process has been discussed in this

lecture

References

1. D. Roy Choudhury, Shail B. Jain, ‘Linear Integrated Circuits’,

II edition, New Age, 2003.
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Outcome of the module

✓The students are able to understand and justify
the steps involved in CMOS process.