DIGITAL LOGIC DESIGN AND COMPUTER ORGANIZATION

(Effective from the Academic Year 2022 - 2023)

SEMESTER - III
Course Code 21CS32 CIA Marks 50
Number of Contact Hours/Week (L: T: P: S) 3:0:2:0 SEE Marks 50
Total Hours of Pedagogy 40L + 20P Exam Hours 03
CREDITS – 4
COURSE PREREQUISITES:
 Basic logic design principles and various function of digital computer.
COURSE OBJECTIVES:

This course will enable students to:

 Illustrate combinational digital circuits.

 Demonstrate the use of flipflops and apply for registers and counters.
 Explain the basic sub systems of a computer, their organization, structure and operation.
 Describe memory hierarchy and concept of cache memory.
 Describe arithmetic and logical operations with integer operands.
 Demonstrate different ways of communicating with I/O devices and standard I/O interfaces.
 Illustrate organization of a simple processor and other computing systems using instruction level
parallelism.
TEACHING - LEARNING STRATEGY:
Following are some sample strategies that can be incorporate for the Course Delivery
● Chalk and Talk Method/Blended Mode Method

● Power Point Presentation

● Expert Talk/Webinar/Seminar

● Video Streaming/Self-Study/Simulations

● Peer-to-Peer Activities

● Activity/Problem Based Learning

● Case Studies

● MOOC/NPTEL Courses

● Any other innovative initiatives with respect to the Course contents

COURSE CONTENTS
MODULE - I
Combinational Logic design: Karnaugh Map, Minimization of complete and incomplete Boolean 8 Hours
expressions using K-Map, Multiplexers, Three state buffers, Decoders and Encoders, Programmable Logic
devices.

(Text book 1:Part B: Chapter 5 ( Sections 5.1 to 5.4),Chapter 9 (Sections 9.1 to 9.6))
MODULE - II
Sequential Logic Design: Flip-Flops and its Applications: Master Slave Flip-Flops, Edge-Triggered Flip- 8 Hours
Flops, Registers, Counters, Design of Synchronous Counters.
Text book 1:Part B: Chapter 11 (Sections 11), Chapter 12(Sections 12)
MODULE - III
Basic Structure of Computers: Basic Operational Concepts, Bus Structures, Performance – Processor 8 Hours
Clock, Basic Performance Equation, Clock Rate, Performance Measurement.

Memory System: Basic Concepts, Semiconductor RAM Memories, Read Only Memories, Speed, Size, and
Cost, Cache Memories – Mapping Functions, Replacement Algorithms, Performance Considerations.

(Text book 2: Chapter1 – 1.3, 1.4, 1.6 (1.6.1-1.6.4, 1.6.7), Chapter5 – 5.1 to 5.4, 5.5 (5.5.1, 5.5.2), 5.6 )
MODULE - IV
Arithmetic: Numbers, Arithmetic Operations and Characters, Addition and Subtraction of Signed Numbers, 8 Hours
Design of Fast Adders, Multiplication of Positive Numbers.

Input/Output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Direct Memory
Access, Buses, Interface Circuits.

(Textbook 2: Chapter2-2.1, Chapter6 – 6.1 to 6.3 Chapter4 – 4.1, 4.2, 4.4, 4.5, 4.6)
MODULE - V
Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete Instruction, Hard-wired 8 Hours
Control, Micro programmed Control.

Machine Instructions and Addressing Modes: Memory Location and Addresses, Instructions and
Instruction Sequencing, Addressing Modes

(Textbook 2: Chapter7 – 7.1, 7.2,7.4, 7.5 Chapter2 – 2.2 to 2.5)

COURSE OUTCOMES
Upon completion of this course, the students will be able to:
Bloom’s
CO
No.
Course Outcome Description Taxonomy
Level
Utilize the concepts of combinational logic design principles for the given problem
CO1 CL4
statement and design digital circuits
Utilize the understanding/concepts of sequential logic design principles for the given problem
CO2 CL4
statement and design digital circuits
CO3 Understanding the concepts of computer modules and construct memory subsystem CL4
CO4 Create the model of ALU and gain the basic knowledge on I/O CL4
CO5 Explain the functions of basic processing unit and the instructions associated with it. CL3
LABORATORY COMPONENTS
Bloom’s
Exp. CO
Experiment Description Taxonomy
No. No.
Level
Design and implement Half adder, Half subtractor, Full adder and Full Subtractor using
1. CO1 CL4
basic gates.
Given a 4-variable logic expression, simplify it using appropriate technique and realize
2. CO1 CL4
the simplified logic expression using 8:1 multiplexer IC.
3. Design and implement code converter I) Binary to Gray (II) Gray to Binary Code. CO1 CL4
Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs
4. CO2 CL4
and demonstrate its working.
5. Design and implement an asynchronous counter using decade counter IC to count up CO2 CL4
 from 0 to n (n<=9) and demonstrate on 7-segment display.
6. Synthesis of Combinational Multipliers to multiply two 4-bit binary numbers. CO3 CL4

7. Design and simulate Booth's Multiplier to multiply two signed integers. CO4 CL4

8. Design and realization of 16-bit ALU (Arithmetic Logic Unit). CO4 CL4

9. Design and simulate 4x4 RAM. CO5 CL4

CO-PO-PSO MAPPING
Programme
CO Programme Outcomes (PO) Specific
No. Outcome (PSO)
1 2 3 4 5 6 7 8 9 10 11 12 1 2
CO1 3 3 3 2 2 1 1
CO2 3 3 3 2 2 1 1
CO3 3 3 2 1 2 1 1
CO4 3 3 2 1 2 1 1
CO5 3 3 2 1 2 1 1
3: Substantial (High) 2: Moderate (Medium) 1: Poor (Low)

ASSESSMENT STRATEGY

Assessment will be both CIA and SEE. Students learning will be assessed using Direct and Indirect methods:
Sl. No. Assessment Description Weightage (%) Max. Marks
1 Continuous Internal Assessment (CIA) 100 % 50
Continuous Internal Evaluation (CIE) 60 % 30
Practical Session (Laboratory Component) 40 % 20
2 Semester End Examination (SEE) 100 % 50
CO - ASSESSMENT MAPPING
Continuous Internal Assessment (CIA) (50%) Semester End Exam (SEE) (50%)
Continuous Internal Practical Sessions
Course Outcomes Evaluation (CIE) (60%) (40%)
I II III
Syllabus Coverage Syllabus Coverage Syllabus Coverage
40% 30% 30% 100% 100%
CO1 x x x
CO2 x x x x
CO3 x x x
CO4 x x x
CO5 x x x
NOTE

● Assessment will be both CIA and SEE.

● The practical sessions of the IPCC shall be for CIE only.

● The Theory component of the IPCC shall be for both CIA and SEE respectively.

● The questions from the practical sessions shall be included in Theory SEE.
Note: For Examinations (both CIE and SEE), the question papers shall contain the questions mapped to the
appropriate Bloom’s Level. Any COs mapped with higher cognitive Bloom’s Level may also be assessed through
the assignments.
SEE QUESTION PAPER PATTERN:
● The question paper will have TEN full questions from FIVE Modules

● There will be 2 full questions from each module. Every question will carry a maximum of 20 marks.

● Each full question may have a maximum of four sub-questions covering all the topics under a module.

● The students will have to answer FIVE full questions, selecting one full question from each module.
TEXT BOOKS:
1. Charles H Roth and Larry L Kinney, Analog and Digital Electronics, Cengage Learning,2019. (Chapters: 5, 9,
11, 12)

2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization, 5th Edition, Tata McGraw Hill, 2002.
(Chapters: 1, 2, 4, 5, 6, 7)
REFERENCE BOOKS:
1. Digital Principles and Design, Donald D. Givone, 1st Edition, 2002, Tata McGraw-Hill Publishers.
2. Computer Organization And Architecture Designing For Performance, William Stallings 11th Edition, 2019,
Pearson.
3. Logic and Computer Design Fundamentals, M. Morris Mano Charles Kime, 4th Edition 2014, Pearson.
4. David A. Bell, Electronic Devices and Circuits, 5th Edition, Oxford University Press, 2008
5. Digital Design and Computer Architecture, David M Harris, Sarah L Harris, 2nd Edition, 2013, Elsevier Morgan
Kaufmann Publishers.
REFERENCE WEB LINKS AND VIDEO LECTURES (E - RESOURCES):

1. https://nptel.ac.in/courses/108/105/108105132/

2. https://nptel.ac.in/courses/106/103/106103068/

3. https://nptel.ac.in/content/storage2/courses/106103068/pdf/coa.pdf

4. https://nptel.ac.in/courses/106/105/106105163/

5. https://nptel.ac.in/courses/106/106/106106092/

6. https://nptel.ac.in/courses/106/106/106106166/

7. http://www.nptelvideos.in/2012/11/computer-organization.html

8. http://vlabs.iitkgp.ac.in/coa/index.html

9. http://vlabs.iitkgp.ac.in/dec