Circuit Theory (Phy301)

PHY 301
LECTURE 40
PRALLEL CLIPPER:
z The parallel configuration is defined as while the parallel variety has the diode in a branch parallel to the
load.

EXAMPLE: Determine the output voltage for the network shown in the fig.

SOLUTION: Diode will be on for the –ve half cycle .So the effective circuit is shown in the fig.

Apply I = 0, V =0 to get transition voltage so that

d d
V – I R – 4V =0
i d
V – 0R – 4V =0
i
V = 4V is transition voltage.
i

176

© Copyright Virtual University of Pakistan

Circuit Theory (Phy301)

hence for the positive half cycle so that

V =V
L 0
V = 16 Volts.
L

EXAMPLE: Consider in previous example the diode is silicon diode and draw its output.

SOLUTION:
The diode will be on for the negative half cycle. Apply I =0 ,V = 0.7 to get transition voltage
d d
V + V – V =0
i T
V =V–V
i T
= 4 – 0.7
= 3.3 V

3.3 is the transition voltage will be 4V, hence for positive half cycle
V =V
L 0
V = 16V
0

177

© Copyright Virtual University of Pakistan

Circuit Theory (Phy301)

CLAMPERS:
These are the circuits which clamp the input signal to a different level depending upon the configuration of
the clamper circuit. For carrying out analysis following points to be remember
(1) The total swing of the output is equal to the total swing of the input signal.
(2) Start the analysis by considering that part of the input which will forward bias the diode.
(3) During the period, the diode is ‘ON’, assume that the capacitor will charge up instantaneously to a
level determined by the network.
(4) During the period for which the diode id ‘OFF’ assume that capacitor will hold its charge.
(5) Throughout the analysis keep complete awareness of the polarity for V , So that the proper value of V
0 o
is determined.
EXAMPLE: Determine v for the network shown in the fig.
0

SOLUTION:
Our analysis will begin at time t to t .our circuit will behave as shown in the fig. Applying KVL to input loop
1 2
-20 + V – 5 = 0
c
Vc = 25V

The capacitor will therefore charge up to 25V. In this case the resistor will not be shorted by the diode, but a
Thevenin’s equivalent circuit for that portion of the network which includes the battery and resistor will result
in R = 0, with E = V = 5V.
th th

For the period t to t the circuit is shown in the fig.

2 3

KVL across the outer loop

10 + 25 – V = 0
o
And
V = 35V
o

178

© Copyright Virtual University of Pakistan

Circuit Theory (Phy301)

The time constant of the discharging network of fig. is determined by the product of RC and has
magnitude
T = RC
= 0.01S
The output wave form will get the shape as

EXAMPLE: Repeat the previous example using silicon diode with V = 0.7V
T

SOLUTION:
For the short circuit state the network now takes the appearance of the fig. and V can be determined by
0
KVL in the output section

+5 – 0.7 – V = 0
0
V = 4.3V
0
For the input section KVL will result in
-20 +V + 0.7 – 5 =0
c
V = 25 – 0.7
c
=24.3V
For the period t to t the network will now appear as in fig. By KVL
2 3
10 + 24.3 – V = 0
0
V = 34.3V
0

179

© Copyright Virtual University of Pakistan