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DLD Lab 12

1) The document describes a lab assignment to design a special shift register that can perform different types of shifting operations on an FPGA board. 2) Students are tasked with implementing a shift register using suitable flip-flops like D flip-flops, and adding circuitry to display results on a Nexys2 board. 3) The shift register is designed to perform operations like serial-in parallel-out, serial-in serial-out, parallel-in serial-out, and parallel-in parallel-out shifts, as well as act as a universal shift register.

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212 views13 pages

DLD Lab 12

1) The document describes a lab assignment to design a special shift register that can perform different types of shifting operations on an FPGA board. 2) Students are tasked with implementing a shift register using suitable flip-flops like D flip-flops, and adding circuitry to display results on a Nexys2 board. 3) The shift register is designed to perform operations like serial-in parallel-out, serial-in serial-out, parallel-in serial-out, and parallel-in parallel-out shifts, as well as act as a universal shift register.

Uploaded by

abdullahakhtarkhan55
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LAB #12: Implementation of a Special Shift Register on FPGA

COMSATS UNIVERSITY ISLAMABAD


Lab Assignment 12

DEPARTMENT OF COMPUTER SCIENCE (BSSE)

Reg No: FA21-BSE-070


Submitted By: Mujeeb Munsab
Submitted to: Madam Shafia Hussain
Class: FA21 2021- BSE – IIIB
Subject: Digital Logic Design (DLD)

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COMSATS University Islamabad Page 1


LAB #12: Implementation of a Special Shift Register on FPGA

LAB #12: Design a Special Shift Register.


Objective:

In this open-ended lab, students need to implement a special shift register which can perform
different shifting operations including universal shift register options. The students need to
explore:

• Which flip flop more suits to design a shift register

• Different types of shifting

• Multiple shifting

• Additional circuitry required to show the result on Nexys2 board

• Comparative analysis of a special shift register implementation in Structural Level


and Behavioral Model.

Pre-Lab:

Register
A register is a digital circuit, which can store data. An 𝑛 − 𝑏𝑖𝑡 register consists of 𝑛 −flip
flops capable of storing 𝑛 − 𝑏𝑖𝑡𝑠 of binary information. The two common features of
registers are:

 Data storage
 Data movement

Shift Register
A shift register is a group of flip-flops set up in a linear fashion with their inputs and outputs
connected in such a way that the data is shifted from one flip flop to another when the circuit
is active.

Universal Shift Register


A universal shift register (USR) is an integrated logic circuit that can transfer data in three
different modes. Like a parallel register: it can load and transmit data in parallel. Like a shift
register: it can load and transmit data in serial fashions, through left shifts or right shifts. In
addition, the universal shift register can combine the capabilities of both parallel and shift
registers to accomplish tasks that neither basic type of register can perform on its own. For
instance, on a particular job a universal register can load data in series (e.g., through a
sequence of left/right shifts) and then transmit/output data in parallel.

COMSATS University Islamabad Page 2


LAB #12: Implementation of a Special Shift Register on FPGA

Depending on the signal values on the select lines of the multiplexers, the
register can retain its current state, shift right, shift left or be loaded in parallel.
Each operation is the result of an active edge on the clock line.

To operate USR in a specific mode, it must first select the mode. To accomplish
mode selection the universal register uses a set of two selector switches, S1 and
S0. As shown in Table 12.1, each permutation of the switches corresponds to a
loading/input mode.

Table 12.1: Operating mode of USR

Operating S1 S0
Mode
No Change 0 0
Shift-Right 0 1
Shift-Left 1 0
Parallel Load 1 1

Different types of shift registers:


1. SISO Shift Register:
LAB #12: Implementation of a Special Shift Register on FPGA

2. SIPO Shift Register:

3. PISO Shift Register:

4. PIPO Shift Register:


LAB #12: Implementation of a Special Shift Register on FPGA

5. Special shift Registers:

In Lab Task:
SHIFT REGISTER USING MUX4_1 AND D FLIP FLOP:

Verilog code of MUX4_1:


LAB #12: Implementation of a Special Shift Register on FPGA

Verilog code of D flip flop:

VERILOG CODE OF SHIFT REGISTER:


LAB #12: Implementation of a Special Shift Register on FPGA

TEST BENCH OF SHIFT REGISTER:


LAB #12: Implementation of a Special Shift Register on FPGA

Simulation:
LAB #12: Implementation of a Special Shift Register on FPGA

INLAB TASK 2:
Special Shift Register:
VERILOG CODE FOR SHIFT REGISTER:

TEST BENCH OF SHIFT REGISTER:


LAB #12: Implementation of a Special Shift Register on FPGA

SIMULATION:
LAB #12: Implementation of a Special Shift Register on FPGA

POST LAB TASK


Using Behavioral model 𝑛 − 𝑏𝑖𝑡 special shift REGISTER
VERILOG CODE FOR 𝑛 − 𝑏𝑖𝑡 special shift REGISTER:

TEST BENCH 𝑛 − 𝑏𝑖𝑡 special shift REGISTER:


LAB #12: Implementation of a Special Shift Register on FPGA

SIMULATION:
LAB #12: Implementation of a Special Shift Register on FPGA

Conclusion/Critical Analysis:
 In this lab we write a Verilog code of special shift register which can perform different
shifting operations including universal shift register, used the suitable flipflop
 Block diagrams of these different shifting operations are also attached in this report.
 We also did comparative analysis of a special shift register using D flipflop and
Behavioral Model.
 We also write Verilog code for 𝑛 − 𝑏𝑖𝑡 special shift REGISTER.
 We also write their test cases and simulate it for verification.
 All results supported my observations.

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