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    Architecture of ARM Processor Family: Seminar On Architectures and Design Methods

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    Sree Harsha Vemulapalli
    This document summarizes an seminar presentation on the architecture of ARM processors. It discusses the history and development of ARM processors, their core features and organization, pipeline design, instruction sets, register files, modes and exceptions. It also provides details on various ARM processor families such as ARM7, ARM9, ARM10 and ARM11 in terms of their characteristics, applications and supported instructions.

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    Architecture of ARM Processor Family: Seminar On Architectures and Design Methods

    Uploaded by

    Sree Harsha Vemulapalli
    12K views27 pages
    This document summarizes an seminar presentation on the architecture of ARM processors. It discusses the history and development of ARM processors, their core features and organization, pipeline design, instruction sets, register files, modes and exceptions. It also provides details on various ARM processor families such as ARM7, ARM9, ARM10 and ARM11 in terms of their characteristics, applications and supported instructions.

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    This document summarizes an seminar presentation on the architecture of ARM processors. It discusses the history and development of ARM processors, their core features and organization, pipeline design, instruction sets, register files, modes and exceptions. It also provides details on various ARM processor families such as ARM7, ARM9, ARM10 and ARM11 in terms of their characteristics, applications and supported instructions.

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    12K views27 pages

    Architecture of ARM Processor Family: Seminar On Architectures and Design Methods

    Uploaded by

    Sree Harsha Vemulapalli
    This document summarizes an seminar presentation on the architecture of ARM processors. It discusses the history and development of ARM processors, their core features and organization, pipeline design, instruction sets, register files, modes and exceptions. It also provides details on various ARM processor families such as ARM7, ARM9, ARM10 and ARM11 in terms of their characteristics, applications and supported instructions.

    Copyright:

    Attribution Non-Commercial (BY-NC)
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    of 27

    Seminar on Architectures and Design Methods for Embedded Systems

    Seminar Topic

    Architecture of ARM Processor Family


    Presented by Sambhavi Parajuli INFOTECH II semester, University of Stuttgart Supervisor Dominik Lcke 03.07.2006

    Overview
    1. History of development of the ARM processor. 2. Features of the ARM processor architecture and oganisation of the ARM components. 3. The ARM pipelines, modes and structure of the ARM components. 4. Development of wide range of the ARM processor families. 5. Instructions supported by the ARM processors.

    History of the ARM Processor


    Developed the first ARM Processor (Acorn RISC Machine) in 1985 at Acorn Computers Limited. Established a new company named Advanced RISC Machine Limited and developed ARM6. Continuation of the architecture enhancements from the original architecture.

    Features of the ARM Processor


    Incorporate features of Berkeley RISC design -a large register file -a load/store architecture -uniform and fixed length instruction field -simple addressing mode Other ARM architecture features -Arithmetic Logic Unit and barrel shifter Source: www.wikipedia.com -auto increment and decrement addressing mode -conditional execution of instructions Based on Von Neumaan Architecture or Harvard Architecture
    4

    Internal Organisation of the ARM Processor

    Source: Shuqiang Zhang

    ARM Pipelines
    Pipeline mechanism to increase execution speed. The pipeline design of each processor family is different.

    ARM Processor Modes


    ARM architecture supports seven operating modes: one unprivileged mode and six privileged modes. Unprivileged mode User mode Privileged mode Abort mode Fast Interrupt Request mode Interrupt Request mode Supervisor mode System mode Undefined mode
    7

    Register Files
    The ARM Registers-37 registers: one program counter, six program status registers, 30 general purpose registers. The Banked Registers: 20 registers when the processor is in a particular privileged mode
    R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 cpsr Spsr_fiq Spsr_irq Spsr_svc Spsr_undef Spsr_abt R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R13_irq R14_irq R13_svc R14_svc R13_undef R14_undef R13_abt R14_abt

    Register Organisation

    user and system

    fast interrupt request

    interrupt request

    supervisor

    undefined

    abort

    Program Status Register


    Current Program Status Register
    Flags 31 30 29 28 27 N Z C V Q 24 J Status Extension 7 I Interrupt Mask Control 6 5 4 F T Mode Processor mode 0

    Jazelle (optional) Condition flags DSP

    Fast Interrupt Thumb State Mask

    N=Negative, Z=Zero, C=Carry, V= oVerflow

    Representation of Processor modes in cpsr


    Processor Mode Abort Fast Interrupt Request Interrupt Request Supervisor System Undefined User Abbreviation abt fiq irq svc sys und usr Mode[4:0] 10111 10001 10010 10011 11111 11011 10000

    Saved Program Status Register

    Instruction Set Design


    ARM, Thumb and Jazelle ARM instruction set 32-bit instructions,support load-store architecture,conditionally execution,use 3-address format Example : ADDS r0,r1,#1 Thumb instruction set 16-bit instructions, support load-store architecture, unconditionally execution (branch instructions), use 2-address format Example : ADD r1,#1 Jazelle instruction set 8-bit instructions, Javabyte code execution

    10

    Interrupt and Exceptions


    When an exception occurs, the processor stops normal execution and enters one of the exception modes.
    Table1: The Interrupt Vector Table Exception/Interrupt Reset Undefined instruction Software interrupt Prefetch abort Data abort Reserved Interrupt request Fast Interrupt request Abbreviation RESET UNDEF SWI PABT DABT IRQ FIQ Address 0x00000000 0x00000004 0x00000008 0x0000000c 0x00000010 0x00000014 0x00000018 0x0000001c High Address 0xffff0000 0xffff0004 0xffff0008 0xffff000c 0xffff0010 0xffff0014 0xffff0018 0xffff001c

    Exception when processor in the Thumb mode


    ARM THUMB ARM THUMB ARM

    Reset

    BCX Exceptions End of exceptions

    BX

    Source: Trevor Martin

    11

    The ARM Processor Families (I)


    The ARM7 Family 32-bit RISC Processor. Support three-stage pipeline
    Fetch Decode Execute

    Uses Von Neumann Architecture.

    12
    Source: www.arm.com

    ARM7TDMI Processor

    ARM7EJ-S Processor

    Characteristics of ARM7 family


    Cache size(Inst/ Data ARM720T ARM7EJ-S ARM7TDMI ARM7TDMI-S
    Source: www.arm.com

    Tightly Coupled Memory -

    Memory Mgmt

    Thumb

    DSP

    Jazelle

    8k unified -

    MMU -

    Yes Yes Yes Yes

    No Yes No No

    No Yes No No

    Widely used in many applications such as palmtop computers, portable instruments, smart card.

    13

    The ARM Processor Families (II)


    The ARM9 Family 32-bit RISC Processor with ARM and Thumb instruction sets Supports five-stage pipeline.
    Fetch Decode Execute Memory Write

    Uses Harvard architecture

    ARM920T Processor
    Source: www.arm.com

    ARM946E-S Processor

    14

    Characteristics of ARM9 Thumb Family


    Cache size(Inst/Data) ARM920T ARM922T 16k/16k 8k/8k Tightly Coupled Memory Memory Mgmt MMU MMU Thumb DSP Jazelle

    Yes Yes

    No No

    No No

    Characteristics of ARM9E Family


    Cache size(Inst/ Data) ARM926EJ-S ARM946E-S ARM966E-S ARM968E-S ARM996H-S
    Source: www.arm.com

    Tightly Coupled Memory Yes Yes Yes Yes

    Memory Mgmt MMU MPU DMA MPU

    Thumb

    DSP

    Jazelle

    Variable Variable N/a

    Yes Yes Yes Yes Yes

    Yes Yes Yes Yes Yes

    Yes No No No No

    Widely used in mobile phones, PDAs,digital cameras, automotive systems, industrial control systems.

    15

    The ARM Processor Families (III)


    The ARM10 Family 32-bit RISC processor with ARM, Thumb and DSP instruction sets. Supports six-stage Pipelines.
    Fetch Issue Decode Execute Memory Write

    Uses Harvard Architecture

    ARM1020E Processor

    Source: www.arm.com

    16

    Characteristics of ARM10 family


    Cache size(Inst /Data) ARM1020E ARM1022E ARM1026EJ-S 32k/32k 16k/16k Variable Tightly Coupled Memory Yes Memory Mgmt MMU MMU MMU or MPU Thumb DSP Jazelle

    Yes Yes Yes

    Yes Yes Yes

    No No Yes

    Widely used in videophone, PDAs, set-top boxes, game console, digital video cameras,automotive and industrial control systems

    17

    The ARM Processor Families (IV)


    The ARM11 Family 32-bit RISC processor with ARM, Thumb and DSP instruction sets. Uses Harvard Architecture. Supports eight-stage Pipelines except ARM1156T2 uses ninestage pipeline. Widely used in automotive and industrial control systems, 3D graphics, security critical applications. Characteristics of ARM11 family
    Cache size(Inst /Data) ARM11 MPCore ARM1136J(F)-S ARM1156T2(F)-S ARM1176JZ(F)-S
    Source: www.arm.com

    Tightly Coupled Memory Yes Yes Yes Yes

    Memory Mgmt

    Thumb

    DSP

    Jazelle

    Variable Variable Variable Varaible

    MMU+cache MMU MPU MMU+TrustZone

    Yes Yes Yes Yes

    Yes Yes Yes Yes

    Yes Yes No Yes 18

    Instructions supported by the ARM Processors


    ARM Instruction Set: standard 32-bit instruction set Thumb Instruction Set: 16-bit instruction set Jazelle Instruction Set: 8-bit instruction set ARM Instruction Set supports six different types of instructions Data Processing Instructions Branch Instructions Load/Store Instructions Software Interrupt Instruction Program Status Register Instructions Coprocessor Instructions
    19

    Data Processing Instructions


    used to manipulate data in general-purpose registers, employ a 3-address format, support barrel shifter. Arithmetic Instructions: ADD, ADC, SUB, SBC, RSB, RSC Move Instructions: MOV, MVN Bit-Wise Logical Instructions: AND, EOR, ORR, BIC Comparison Instructions: TST, TEQ, CMP, CMN Multiply Instructions: MUL, MLA

    20

    Examples of Data Processing Instructions


    ADD operation without barrel shifter Pre r0 = 0x00000000 r1 = 0x00000002 r2 = 0x00000001 ADD r0, r1, r2 Post r0 = 0x00000003 ADD operation with barrel shifter Pre r0 = 0x00000000 r1 = 0x00000005 ADD r0, r1, r1, LSL #1 Post r0 = 0x0000000f r1 =0x00000005

    Barrel Shifter operations


    Mnemonic LSL LSR ASR ROR RRX Description Logical shift left Logical shift right Arithmetic right shift Rotate right Rotote right extended
    21

    Branch Instructions
    Change the flow of sequencial execution of instructions and force to modify the program counter. Branch (B) jumps in a range of +/- 32 MB. Branch with link(BL) suitable for subroutine call by storing the address of next instructions after BL into the link register and restore the program counter from the link register while returning from subroutine. Branch Exchange and Branch Exchange Link for switching the processor state from Thumb to ARM and vice versa
    ARM Thumb
    22

    Load/Store Instructions
    Transfer data between memory and registers Single Register Transfer Instructions used to move a single data item in and out of register (signed, unsigned, 16-bit half words and 32-bit word) supports register indirect, base-plus-offset and stack addressing mode LDR, STR, LDRB, STRB, LDRH, STRH, LDRSB Multiple Register Transfer Instructions any subset or all the 16 registers loaded from or stored to memory but increase interrupt latency. addressing modes- IA, IB,DA, DB stack operations- FA, FD, EA, ED LDM, STM Swap Instructions swap the contect of memory with the content of registers. SWP, SWPB

    23

    Software Interrupt Instruction


    Used to call the SWI exception handler (operating system functions). Forces processor into supervisor mode. SWI Used to transfer the content of program status registers to/from a general-purpose register. MRS (copy program status register to a general purpose register), MSR(move a general-purpose register to a program status register) Used to extend the instruction set, to control on-chips functions (caches and memory management) and for additional computations. CDP (data processing), MRC/MCR (register transfer), LDC/STC (memory transfer).

    Program Status Register Instructions

    Coprocessor Instructions

    24

    Systems with ARM Processor

    25

    Conclusion
    Continuous evolution of the ARM processors. Use of various design techniques such as RISC architectures, pipelines, DSP extension and Jazelle technology. High performance, lower power consumption and system cost, low silicon area and time-to-market. Provide benefits in the wide area of technology design and developments such as embedded real time applications, automotive control systems, portable applications and secure applications.

    26

    Thank you very much for your attention. Any questions?

    27

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